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Fri, 04 Sep 2026 15:11:11 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:46 -0500 Subject: [PATCH v2 01/10] iio: adc: ti-ads112c14: add DRDY interrupt support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-1-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6047; i=dlechner@baylibre.com; h=from:subject:message-id; bh=NDSDpivYarXePwTSDpiVgkViP53hrWoSMytekojHNS0=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBqm0G3M+uBhqsEPf5gJgli+9VzwuNxMeOriZst5 X025WDRUWeJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaptBtwAKCRDCzCAB/wGP wBGAB/4msLmdoxHeNkgTAbnuYoIAdb817nGdND14bB7D4VccDAJpcnLVZ5eiD8BIFcDB/hABGeA v/8lTz/NV/yN+JI2rrTtHC0yQLLEk4PuPas7e5AkQj+LkOVcYUbQqFIDemKFoRN6XvYTpN+U+PT uPg7ij3j0G7xqtA7AWZbIsWlj9R33CrM9mZCJBjyCexmE6h+EM82TxPsLEAhtNupqOdizRAOOI5 oTmlqTOMeWfr0ypaAQ1qsKCmqADqgzHn0ljIed+BlWKK94t8Axmz2y8Hj3tNyoENu+dIYq1CxE/ 9acUC3nvKLWDYx7IXuC0Wm8eBeX5RjRn7wGTx930vet3nT4u X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add handling for the DRDY interrupt to wait for data ready events rather than polling (only when it is wired up). Signed-off-by: David Lechner (TI) --- Small note: the hard-coded 100 ms timeout will be replaced in a future series with a dynamic value, so I didn't bother with a macro or comments to explain why the value was chosen. And passing indio_dev instead of data to irq is intentional as it will be used in the next patch. --- drivers/iio/adc/ti-ads112c14.c | 100 ++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 90 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ti-ads112c14.c b/drivers/iio/adc/ti-ads112c14.c index 60eab4852ba2..63b819339788 100644 --- a/drivers/iio/adc/ti-ads112c14.c +++ b/drivers/iio/adc/ti-ads112c14.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -117,9 +119,15 @@ #define ADS112C14_GPIO_CFG_GPIO2_CFG GENMASK(5, 4) #define ADS112C14_GPIO_CFG_GPIO1_CFG GENMASK(3, 2) #define ADS112C14_GPIO_CFG_GPIO0_CFG GENMASK(1, 0) +#define ADS112C14_GPIO_CFG_GPIO_CFG_DISABLED 0 +#define ADS112C14_GPIO_CFG_GPIO_CFG_INPUT 1 +#define ADS112C14_GPIO_CFG_GPIO_CFG_OUTPUT_PUSH_PULL 2 +#define ADS112C14_GPIO_CFG_GPIO_CFG_OUTPUT_OPEN_DRAIN 3 =20 #define ADS112C14_REG_GPIO_DATA_OUTPUT 0x0C #define ADS112C14_GPIO_DATA_OUTPUT_GPIO3_SRC BIT(7) +#define ADS112C14_GPIO_DATA_OUTPUT_GPIO3_SRC_DAT_OUT 0 +#define ADS112C14_GPIO_DATA_OUTPUT_GPIO3_SRC_DRDY 1 #define ADS112C14_GPIO_DATA_OUTPUT_GPIO2_SRC BIT(6) #define ADS112C14_GPIO_DATA_OUTPUT_GPIO3_DAT_OUT BIT(3) #define ADS112C14_GPIO_DATA_OUTPUT_GPIO2_DAT_OUT BIT(2) @@ -251,6 +259,8 @@ struct ads112c14_data { struct regmap *regmap; /* Synchronizes access to register value fields. */ struct mutex lock; + int drdy_irq; + struct completion drdy_completion; bool i2c_crc_enabled; u32 avdd_uV; u32 ext_ref_uV; @@ -265,6 +275,16 @@ struct ads112c14_data { ARRAY_SIZE(ads112c14_sys_mon_channels)); }; =20 +static irqreturn_t ads112c14_drdy_irq_handler(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + struct ads112c14_data *data =3D iio_priv(indio_dev); + + complete(&data->drdy_completion); + + return IRQ_HANDLED; +} + static bool ads112c14_writeable_reg(struct device *dev, unsigned int reg) { switch (reg) { @@ -581,12 +601,45 @@ static int ads112c14_prepare_sys_mon_channel(struct a= ds112c14_data *data, return 0; } =20 +static int ads112c14_wait_for_conversion_irq(struct ads112c14_data *data) +{ + unsigned long remaining; + int ret; + + reinit_completion(&data->drdy_completion); + + ret =3D regmap_write(data->regmap, ADS112C14_REG_CONVERSION_CTRL, + ADS112C14_CONVERSION_CTRL_START); + if (ret) + return ret; + + remaining =3D wait_for_completion_timeout(&data->drdy_completion, + msecs_to_jiffies(100)); + + return remaining ? 0 : -ETIMEDOUT; +} + +static int ads112c14_wait_for_conversion_poll(struct ads112c14_data *data) +{ + u32 reg_val; + int ret; + + ret =3D regmap_write(data->regmap, ADS112C14_REG_CONVERSION_CTRL, + ADS112C14_CONVERSION_CTRL_START); + if (ret) + return ret; + + return regmap_read_poll_timeout(data->regmap, + ADS112C14_REG_STATUS_MSB, reg_val, + FIELD_GET(ADS112C14_STATUS_MSB_DRDY, reg_val), + 1 * USEC_PER_MSEC, 100 * USEC_PER_MSEC); +} + static int ads112c14_single_conversion(struct ads112c14_data *data, const struct iio_chan_spec *chan, u8 *buf, bool for_scan) { struct i2c_client *client =3D to_i2c_client(regmap_get_device(data->regma= p)); - u32 reg_val; int ret; =20 guard(mutex)(&data->lock); @@ -601,15 +654,10 @@ static int ads112c14_single_conversion(struct ads112c= 14_data *data, return ret; } =20 - ret =3D regmap_write(data->regmap, ADS112C14_REG_CONVERSION_CTRL, - ADS112C14_CONVERSION_CTRL_START); - if (ret) - return ret; - - ret =3D regmap_read_poll_timeout(data->regmap, - ADS112C14_REG_STATUS_MSB, reg_val, - FIELD_GET(ADS112C14_STATUS_MSB_DRDY, reg_val), - 1 * USEC_PER_MSEC, 100 * USEC_PER_MSEC); + if (data->drdy_irq) + ret =3D ads112c14_wait_for_conversion_irq(data); + else + ret =3D ads112c14_wait_for_conversion_poll(data); if (ret) return ret; =20 @@ -1391,6 +1439,38 @@ static int ads112c14_probe(struct i2c_client *client) if (ret) return ret; =20 + if (device_property_present(dev, "interrupt-names")) { + data->drdy_irq =3D fwnode_irq_get_byname(dev_fwnode(dev), "drdy"); + if (data->drdy_irq < 0) + return dev_err_probe(dev, data->drdy_irq, + "failed to get drdy interrupt\n"); + + /* + * REVISIT: would probably need to implement a pin controller in + * order to support open drain option here. + */ + ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_GPIO_CFG, + ADS112C14_GPIO_CFG_GPIO3_CFG, + FIELD_PREP(ADS112C14_GPIO_CFG_GPIO3_CFG, + ADS112C14_GPIO_CFG_GPIO_CFG_OUTPUT_PUSH_PULL)); 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Fri, 04 Sep 2026 15:11:13 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:500:4324:3ccf:e2bf:d545]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4b970d1ff95sm3187113b6e.6.2026.09.04.15.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 15:11:13 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:47 -0500 Subject: [PATCH v2 02/10] iio: adc: ti-ads112c14: create data read helper functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-2-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2657; i=dlechner@baylibre.com; h=from:subject:message-id; bh=0jleKfSV4x8zSuizbp6O6ni4ujngh47YqjL22y19AbA=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBqm0G+ncKbLAltqxDm3KwBMxwEmv5L7xt+NEwPP hm0vKE0HWaJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaptBvgAKCRDCzCAB/wGP wKtHB/9lhh+sMAjNSzNihwUyAb9ZCOTVvJicjbzhuEClzuyeeer3Ys2JKgOUF+pVcE7q6MucRPp NCcGra1aWi3a5qxRr0BdOdB/EhNgihlAExslS3GLSYgt9nKAl7uDawQD3i5XZ2AZBexBVS6UfIb gQlXFbruTs1rWpIqCe9D3+8L7gnFxMMFmwzYd3Fj7hq6djaetTz1QhHIubrUkkcv8LdOHlMmbB7 jEReskh7EJZchTf7rltywUYMNNfway4LFO+05OhEyTnovw42GKNIL+1lZ8wwKr1t51Ksfd8ht0Q 9//egdNS/S8YxozxeA+RRQyfu2te2QOztRXFhbIw5a3cANmn X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Refactor a few bits of code into helper functions. These will be reused when continuous mode support is added in a later patch. Signed-off-by: David Lechner (TI) --- drivers/iio/adc/ti-ads112c14.c | 51 +++++++++++++++++++++++++-------------= ---- 1 file changed, 31 insertions(+), 20 deletions(-) diff --git a/drivers/iio/adc/ti-ads112c14.c b/drivers/iio/adc/ti-ads112c14.c index 63b819339788..23f15be303fb 100644 --- a/drivers/iio/adc/ti-ads112c14.c +++ b/drivers/iio/adc/ti-ads112c14.c @@ -601,6 +601,32 @@ static int ads112c14_prepare_sys_mon_channel(struct ad= s112c14_data *data, return 0; } =20 +static int ads112c14_prepare_channel(struct ads112c14_data *data, + const struct iio_chan_spec *chan) +{ + if (chan->channel < ADS112C14_SYS_MON_CHANNEL_BASE) + return ads112c14_prepare_measurement_channel(data, chan); + + return ads112c14_prepare_sys_mon_channel(data, chan); +} + +static int ads112c14_scan_read(struct ads112c14_data *data, u8 *buf) +{ + struct i2c_client *client =3D to_i2c_client(regmap_get_device(data->regma= p)); + int ret; + u8 len; + + len =3D BITS_TO_BYTES(data->chip_info->resolution_bits); + if (data->i2c_crc_enabled) + len +=3D 1; + + ret =3D i2c_smbus_read_i2c_block_data(client, ADS112C14_CMD_RDATA, len, b= uf); + if (ret < 0) + return ret; + + return 0; +} + static int ads112c14_wait_for_conversion_irq(struct ads112c14_data *data) { unsigned long remaining; @@ -644,15 +670,9 @@ static int ads112c14_single_conversion(struct ads112c1= 4_data *data, =20 guard(mutex)(&data->lock); =20 - if (chan->channel < ADS112C14_SYS_MON_CHANNEL_BASE) { - ret =3D ads112c14_prepare_measurement_channel(data, chan); - if (ret) - return ret; - } else { - ret =3D ads112c14_prepare_sys_mon_channel(data, chan); - if (ret) - return ret; - } + ret =3D ads112c14_prepare_channel(data, chan); + if (ret) + return ret; =20 if (data->drdy_irq) ret =3D ads112c14_wait_for_conversion_irq(data); @@ -667,17 +687,8 @@ static int ads112c14_single_conversion(struct ads112c1= 4_data *data, * with CRC errors, but rather leave it to userspace to decide what to * do. */ - if (for_scan) { - u8 len =3D BITS_TO_BYTES(data->chip_info->resolution_bits) + - (data->i2c_crc_enabled ? 1 : 0); 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Fri, 04 Sep 2026 15:11:16 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:500:4324:3ccf:e2bf:d545]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4b970d1ff95sm3187113b6e.6.2026.09.04.15.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 15:11:15 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:48 -0500 Subject: [PATCH v2 03/10] iio: adc: ti-ads112c14: add continuous mode support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-3-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; 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In this mode the ADC itself is starting each conversion, so we add a trigger based on the DRDY interrupt to read each sample. This mode is also limited in that only one channel can be enabled at a time since the chip does not have a sequencer or simultaneous sampling capability. Continuous mode will only be used when this new trigger is the current trigger. Signed-off-by: David Lechner (TI) --- drivers/iio/adc/ti-ads112c14.c | 153 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 151 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ti-ads112c14.c b/drivers/iio/adc/ti-ads112c14.c index 23f15be303fb..06b962fbde5e 100644 --- a/drivers/iio/adc/ti-ads112c14.c +++ b/drivers/iio/adc/ti-ads112c14.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -257,10 +259,12 @@ struct ads112c14_measurement { struct ads112c14_data { const struct ads112c14_chip_info *chip_info; struct regmap *regmap; + struct iio_trigger *drdy_trig; /* Synchronizes access to register value fields. */ struct mutex lock; int drdy_irq; struct completion drdy_completion; + bool continuous_mode; bool i2c_crc_enabled; u32 avdd_uV; u32 ext_ref_uV; @@ -280,11 +284,18 @@ static irqreturn_t ads112c14_drdy_irq_handler(int irq= , void *private) struct iio_dev *indio_dev =3D private; struct ads112c14_data *data =3D iio_priv(indio_dev); =20 - complete(&data->drdy_completion); + if (READ_ONCE(data->continuous_mode)) + iio_trigger_poll(data->drdy_trig); + else + complete(&data->drdy_completion); =20 return IRQ_HANDLED; } =20 +static const struct iio_trigger_ops ads112c14_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, +}; + static bool ads112c14_writeable_reg(struct device *dev, unsigned int reg) { switch (reg) { @@ -695,6 +706,13 @@ static int ads112c14_single_conversion(struct ads112c1= 4_data *data, data->i2c_crc_enabled); } =20 +static bool ads112c14_using_drdy_trigger(struct iio_dev *indio_dev) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + + return data->drdy_trig && indio_dev->trig =3D=3D data->drdy_trig; +} + static int ads112c14_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -898,6 +916,19 @@ static int ads112c14_write_raw_get_fmt(struct iio_dev = *indio_dev, } } =20 +static int ads112c14_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + /* Only continuous mode is limited to a single channel. */ + if (!ads112c14_using_drdy_trigger(indio_dev)) + return 0; + + if (!iio_validate_scan_mask_onehot(indio_dev, scan_mask)) + return -EINVAL; + + return 0; +} + static int ads112c14_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, @@ -952,6 +983,19 @@ static int ads112c14_read_label(struct iio_dev *indio_= dev, return sysfs_emit(label, "%s\n", label_source); } =20 +static const struct iio_chan_spec * +ads112c14_first_active_channel(struct iio_dev *indio_dev) +{ + unsigned int scan_mask_len =3D iio_get_masklength(indio_dev); + unsigned int i; + + i =3D find_first_bit(indio_dev->active_scan_mask, scan_mask_len); + if (i =3D=3D scan_mask_len) + return NULL; + + return &indio_dev->channels[i]; +} + static irqreturn_t ads112c14_trigger_handler(int irq, void *private) { struct iio_poll_func *pf =3D private; @@ -961,6 +1005,26 @@ static irqreturn_t ads112c14_trigger_handler(int irq,= void *private) u32 i; int ret; =20 + if (ads112c14_using_drdy_trigger(indio_dev)) { + const struct iio_chan_spec *chan; + + chan =3D ads112c14_first_active_channel(indio_dev); + if (!chan) + goto out; + + ret =3D ads112c14_scan_read(data, (u8 *)&data->scan[0]); + if (ret) { + dev_err_once(indio_dev->dev.parent, + "failed to read channel %d: %pe; additional errors will be suppre= ssed\n", + chan->channel, ERR_PTR(ret)); + goto out; + } + + iio_push_to_buffers_with_ts(indio_dev, data->scan, + sizeof(data->scan), pf->timestamp); + goto out; + } + iio_for_each_active_channel(indio_dev, i) { const struct iio_chan_spec *chan =3D &indio_dev->channels[i]; =20 @@ -988,10 +1052,81 @@ static const struct iio_info ads112c14_info =3D { .read_avail =3D ads112c14_read_avail, .write_raw =3D ads112c14_write_raw, .write_raw_get_fmt =3D ads112c14_write_raw_get_fmt, + .update_scan_mode =3D ads112c14_update_scan_mode, .debugfs_reg_access =3D ads112c14_debugfs_reg_access, .read_label =3D ads112c14_read_label, }; =20 +static int ads112c14_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + const struct iio_chan_spec *chan; + int ret; + + if (!ads112c14_using_drdy_trigger(indio_dev)) + return 0; + + chan =3D ads112c14_first_active_channel(indio_dev); + if (!chan) + return -EINVAL; + + guard(mutex)(&data->lock); + + ret =3D ads112c14_prepare_channel(data, chan); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DEVICE_CFG, + ADS112C14_DEVICE_CFG_CONV_MODE, + FIELD_PREP(ADS112C14_DEVICE_CFG_CONV_MODE, + ADS112C14_DEVICE_CFG_CONV_MODE_CONTINUOUS)); + if (ret) + return ret; + + WRITE_ONCE(data->continuous_mode, true); + + ret =3D regmap_write(data->regmap, ADS112C14_REG_CONVERSION_CTRL, + ADS112C14_CONVERSION_CTRL_START); + if (ret) { + WRITE_ONCE(data->continuous_mode, false); + regmap_update_bits(data->regmap, ADS112C14_REG_DEVICE_CFG, + ADS112C14_DEVICE_CFG_CONV_MODE, + FIELD_PREP(ADS112C14_DEVICE_CFG_CONV_MODE, + ADS112C14_DEVICE_CFG_CONV_MODE_SINGLE_SHOT)); + return ret; + } + + return 0; +} + +static int ads112c14_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + int ret; + + if (!ads112c14_using_drdy_trigger(indio_dev)) + return 0; + + guard(mutex)(&data->lock); + + WRITE_ONCE(data->continuous_mode, false); + + ret =3D regmap_write(data->regmap, ADS112C14_REG_CONVERSION_CTRL, + ADS112C14_CONVERSION_CTRL_STOP); + if (ret) + return ret; + + return regmap_update_bits(data->regmap, ADS112C14_REG_DEVICE_CFG, + ADS112C14_DEVICE_CFG_CONV_MODE, + FIELD_PREP(ADS112C14_DEVICE_CFG_CONV_MODE, + ADS112C14_DEVICE_CFG_CONV_MODE_SINGLE_SHOT)); +} + +static const struct iio_buffer_setup_ops ads112c14_buffer_setup_ops =3D { + .postenable =3D ads112c14_buffer_postenable, + .predisable =3D ads112c14_buffer_predisable, +}; + static int ads112c14_populate_idac_mag(u32 current_nA, u8 *idac_mag) { u32 current_uA =3D current_nA / (NANO / MICRO); @@ -1480,6 +1615,19 @@ static int ads112c14_probe(struct i2c_client *client) 0, dev_name(dev), indio_dev); if (ret) return ret; + + data->drdy_trig =3D devm_iio_trigger_alloc(dev, "%s-dev%d-drdy", + info->name, + iio_device_id(indio_dev)); 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Fri, 04 Sep 2026 15:11:18 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:500:4324:3ccf:e2bf:d545]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4b970d1ff95sm3187113b6e.6.2026.09.04.15.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 15:11:17 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:49 -0500 Subject: [PATCH v2 04/10] iio: adc: ti-ads112c14: add burnout current support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-4-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=8219; i=dlechner@baylibre.com; h=from:subject:message-id; bh=Deeaer94Jcor75gpy0lfZKp/okGWx/opCeDuktVE8UE=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBqm0HLI/LcF2uFgi749qeP4XAV2xYp7pM+IL06m ltn56+eUyuJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaptBywAKCRDCzCAB/wGP wNCXB/4kmgkZ2SJO9DpFYZJFLGhp5F1aWWkv/W80bs4CftaqCZePRqw6lv565QMYQ7IZN4z58n7 FbKlDkJ+igL6/1kUhrSi8W/bP1ZTXOYKTvwbew9ow6wsUlInSnIzvaxidp7P9GiUdDch67taS+M x4eamqR5D/ZhA79lQTHIZB3zRNipSVK+yHabX27ufWbpUA+1BjW7KiyNMp0mtiEUx6J9C45u7bX r057J0D7dlNeCZuQvgEWIIwY/SPPclATdBxhXGVju9oU7rqvmqtl8YSzSCY8aaWKrrbBrJx3oh4 aI/pNNcM+LuE+sUViOtXJlFCy04eknaVuCAFgNz3Ck0YDTAb X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add a custom attribute via ext_info when a channel has a burnout current specified in the devicetree. This adds an in_{voltageY,resistanceY, voltageY-voltageX}_burnoutraw sysfs attribute for the channel that performs a single conversion (same as _raw attribute) except that it enables the burnout current. The chip also has a restriction that input chopping cannot be enabled when burnout current is enabled, so we also disable input chopping when burnout current is active. Signed-off-by: David Lechner (TI) --- drivers/iio/adc/ti-ads112c14.c | 125 +++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 116 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ti-ads112c14.c b/drivers/iio/adc/ti-ads112c14.c index 06b962fbde5e..c03789c3d95e 100644 --- a/drivers/iio/adc/ti-ads112c14.c +++ b/drivers/iio/adc/ti-ads112c14.c @@ -76,6 +76,11 @@ #define ADS112C14_DEVICE_CFG_PWDN BIT(7) #define ADS112C14_DEVICE_CFG_STBY_MODE BIT(6) #define ADS112C14_DEVICE_CFG_BOCS GENMASK(5, 4) +#define ADS112C14_DEVICE_CFG_BOCS_DISABLED 0 +#define ADS112C14_DEVICE_CFG_BOCS_200_nA 1 +#define ADS112C14_DEVICE_CFG_BOCS_1_uA 2 +#define ADS112C14_DEVICE_CFG_BOCS_10_uA 3 + #define ADS112C14_DEVICE_CFG_CLK_SEL BIT(3) #define ADS112C14_DEVICE_CFG_CONV_MODE BIT(2) #define ADS112C14_DEVICE_CFG_CONV_MODE_CONTINUOUS 0 @@ -251,6 +256,7 @@ struct ads112c14_measurement { u8 idac2_mux; u8 iadc_count; u8 gain_val; + u8 burnout; bool global_chop; bool bipolar; int scale_available[ARRAY_SIZE(ads112c14_pga_gains_x10)][2]; @@ -461,7 +467,8 @@ static const struct regmap_config ads112c14_regmap_conf= ig =3D { }; =20 static int ads112c14_prepare_measurement_channel(struct ads112c14_data *da= ta, - const struct iio_chan_spec *chan) + const struct iio_chan_spec *chan, + bool en_burnout) { struct ads112c14_measurement *measurement =3D &data->measurements[chan->s= can_index]; u32 refp_buf_en, refn_buf_en, ref_val, ref_sel; @@ -515,7 +522,8 @@ static int ads112c14_prepare_measurement_channel(struct= ads112c14_data *data, ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DATA_RATE_CFG, ADS112C14_DATA_RATE_CFG_GC_EN, FIELD_PREP(ADS112C14_DATA_RATE_CFG_GC_EN, - measurement->global_chop)); + (measurement->global_chop && + !en_burnout) ? 1 : 0)); if (ret) return ret; =20 @@ -613,10 +621,11 @@ static int ads112c14_prepare_sys_mon_channel(struct a= ds112c14_data *data, } =20 static int ads112c14_prepare_channel(struct ads112c14_data *data, - const struct iio_chan_spec *chan) + const struct iio_chan_spec *chan, + bool en_burnout) { if (chan->channel < ADS112C14_SYS_MON_CHANNEL_BASE) - return ads112c14_prepare_measurement_channel(data, chan); + return ads112c14_prepare_measurement_channel(data, chan, en_burnout); =20 return ads112c14_prepare_sys_mon_channel(data, chan); } @@ -674,14 +683,14 @@ static int ads112c14_wait_for_conversion_poll(struct = ads112c14_data *data) =20 static int ads112c14_single_conversion(struct ads112c14_data *data, const struct iio_chan_spec *chan, - u8 *buf, bool for_scan) + u8 *buf, bool en_burnout, bool for_scan) { struct i2c_client *client =3D to_i2c_client(regmap_get_device(data->regma= p)); int ret; =20 guard(mutex)(&data->lock); =20 - ret =3D ads112c14_prepare_channel(data, chan); + ret =3D ads112c14_prepare_channel(data, chan, en_burnout); if (ret) return ret; =20 @@ -742,7 +751,7 @@ static int ads112c14_read_raw(struct iio_dev *indio_dev, if (IIO_DEV_ACQUIRE_FAILED(claim)) return -EBUSY; =20 - ret =3D ads112c14_single_conversion(data, chan, buf, false); + ret =3D ads112c14_single_conversion(data, chan, buf, false, false); if (ret) return ret; =20 @@ -1030,7 +1039,7 @@ static irqreturn_t ads112c14_trigger_handler(int irq,= void *private) =20 ret =3D ads112c14_single_conversion(data, chan, (u8 *)&data->scan[offset++], - true); + false, true); if (ret) { dev_err_once(indio_dev->dev.parent, "failed to read channel %d: %pe; additional errors will be suppre= ssed\n", @@ -1072,7 +1081,7 @@ static int ads112c14_buffer_postenable(struct iio_dev= *indio_dev) =20 guard(mutex)(&data->lock); =20 - ret =3D ads112c14_prepare_channel(data, chan); + ret =3D ads112c14_prepare_channel(data, chan, false); if (ret) return ret; =20 @@ -1127,6 +1136,74 @@ static const struct iio_buffer_setup_ops ads112c14_b= uffer_setup_ops =3D { .predisable =3D ads112c14_buffer_predisable, }; =20 +static ssize_t ads112c14_read_burnout_raw(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + char *buf) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + struct ads112c14_measurement *measurement; + int ret, ret2, val; + u8 raw_buf[3]; + + if (chan->channel >=3D ADS112C14_SYS_MON_CHANNEL_BASE) + return -EINVAL; + + measurement =3D &data->measurements[chan->scan_index]; + if (!measurement->burnout) + return -EINVAL; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DEVICE_CFG, + ADS112C14_DEVICE_CFG_BOCS, + FIELD_PREP(ADS112C14_DEVICE_CFG_BOCS, + measurement->burnout)); + if (ret) + return ret; + + ret =3D ads112c14_single_conversion(data, chan, raw_buf, true, false); + + /* + * Important to always turn off burnout current even if the conversion + * fails so that it does not affect subsequent measurements. + */ + ret2 =3D regmap_update_bits(data->regmap, ADS112C14_REG_DEVICE_CFG, + ADS112C14_DEVICE_CFG_BOCS, + FIELD_PREP(ADS112C14_DEVICE_CFG_BOCS, + ADS112C14_DEVICE_CFG_BOCS_DISABLED)); + if (ret < 0) + return ret; + if (ret2) + return ret2; + + switch (data->chip_info->resolution_bits) { + case 16: + val =3D get_unaligned_be16(raw_buf); + break; + case 24: + val =3D get_unaligned_be24(raw_buf); + break; + default: + return -EINVAL; + } + + if (measurement->bipolar) + val =3D sign_extend32(val, data->chip_info->resolution_bits - 1); + + return sysfs_emit(buf, "%d\n", val); +} + +static const struct iio_chan_spec_ext_info ads112c14_ext_info_burnout[] = =3D { + { + .name =3D "burnoutraw", + .read =3D ads112c14_read_burnout_raw, + }, + { } +}; + static int ads112c14_populate_idac_mag(u32 current_nA, u8 *idac_mag) { u32 current_uA =3D current_nA / (NANO / MICRO); @@ -1172,6 +1249,7 @@ static int ads112c14_parse_channels(struct iio_dev *i= ndio_dev, device_for_each_named_child_node_scoped(dev, child, "channel") { struct ads112c14_measurement *measurement =3D &data->measurements[i]; struct iio_chan_spec *spec =3D &channels[i]; + const char *propname; =20 spec->indexed =3D 1; spec->scan_index =3D i; @@ -1295,6 +1373,35 @@ static int ads112c14_parse_channels(struct iio_dev *= indio_dev, measurement->global_chop =3D fwnode_property_read_bool(child, "input-chopping"); =20 + propname =3D "burn-out-current-nanoamp"; + if (fwnode_property_present(child, propname)) { + u32 burnout_nA; + + ret =3D fwnode_property_read_u32(child, propname, &burnout_nA); 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Fri, 04 Sep 2026 15:11:20 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:500:4324:3ccf:e2bf:d545]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4b970d1ff95sm3187113b6e.6.2026.09.04.15.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 15:11:19 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:50 -0500 Subject: [PATCH v2 05/10] iio: ABI: add sysfs attribute for _burnoutraw Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-5-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; 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This is likely only applicable to ADCs (but is seen on multiple chips and vendors) so it gets its own file instead of being added to the main IIO ABI file. Signed-off-by: David Lechner (TI) --- Documentation/ABI/testing/sysfs-bus-iio-adc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio-adc b/Documentation/AB= I/testing/sysfs-bus-iio-adc new file mode 100644 index 000000000000..e1309b371efb --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-adc @@ -0,0 +1,9 @@ +What: /sys/bus/iio/devices/iio:deviceX/in_resistanceY_burnoutraw +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_burnoutraw +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_burnoutraw +KernelVersion: 7.4 +Contact: linux-iio@vger.kernel.org +Description: + Raw value from channel Y read using a single conversion with + the channel burnout current enabled. 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Fri, 04 Sep 2026 15:11:20 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:51 -0500 Subject: [PATCH v2 06/10] iio: adc: ti-ads112c14: support external clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-6-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3103; i=dlechner@baylibre.com; h=from:subject:message-id; bh=tuKhK0Enx5k//K8I0pTMmNB+pTPJg1C2xYOO+ZfG/4E=; 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The unused fclk_Hz field is added in preparation for filter support. Signed-off-by: David Lechner (TI) --- drivers/iio/adc/ti-ads112c14.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/iio/adc/ti-ads112c14.c b/drivers/iio/adc/ti-ads112c14.c index c03789c3d95e..55462fc57752 100644 --- a/drivers/iio/adc/ti-ads112c14.c +++ b/drivers/iio/adc/ti-ads112c14.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -178,6 +179,8 @@ static const u32 ads112c14_pga_gains_x10[] =3D { 200, 320, 500, 640, 1000, 1280, 2000, 2560, /* 8 - 15 */ }; =20 +#define ADS112C14_INTERNAL_CLK_Hz 4096000 + #define ADS112C14_I2C_CRC8_POLYNOMIAL 0x07 DECLARE_CRC8_TABLE(ads112c14_crc8_table); =20 @@ -268,6 +271,7 @@ struct ads112c14_data { struct iio_trigger *drdy_trig; /* Synchronizes access to register value fields. */ struct mutex lock; + long fclk_Hz; int drdy_irq; struct completion drdy_completion; bool continuous_mode; @@ -1536,6 +1540,7 @@ static int ads112c14_probe(struct i2c_client *client) const struct ads112c14_chip_info *info; struct iio_dev *indio_dev; struct ads112c14_data *data; + struct clk *clk; bool need_avdd_ref, need_ext_ref; u32 refp_uV =3D 0; u32 refn_uV =3D 0; @@ -1628,6 +1633,12 @@ static int ads112c14_probe(struct i2c_client *client) return dev_err_probe(dev, -EINVAL, "external reference measurements require either refp-supply or ti= ,refp-refn-resistor-ohms property\n"); =20 + clk =3D devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to get clk\n"); + + data->fclk_Hz =3D clk ? clk_get_rate(clk) : ADS112C14_INTERNAL_CLK_Hz; + /* It takes some time for the internal reference to stabilize. */ fsleep(10 * USEC_PER_MSEC); =20 @@ -1698,6 +1709,10 @@ static int ads112c14_probe(struct i2c_client *client) return dev_err_probe(dev, data->drdy_irq, "failed to get drdy interrupt\n"); =20 + if (clk) + return dev_err_probe(dev, -EINVAL, + "cannot use both DRDY and CLK - they share the same pin\n"); + /* * REVISIT: would probably need to implement a pin controller in * order to support open drain option here. @@ -1737,6 +1752,20 @@ static int ads112c14_probe(struct i2c_client *client) return ret; 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Fri, 04 Sep 2026 15:11:23 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:500:4324:3ccf:e2bf:d545]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4b970d1ff95sm3187113b6e.6.2026.09.04.15.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 15:11:22 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:52 -0500 Subject: [PATCH v2 07/10] iio: adc: ti-ads112c14: add filter support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-7-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; 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On these chips, these three controls are interdependent and the SPEED_MODE register value has a different meaning depending on the filter type, which makes the interactions a bit complex. As such, the expectation is that the user will set the filter type first, then depending on the filter type, either set the oversampling ratio or the sampling frequency and finally the other of these two. Signed-off-by: David Lechner (TI) --- Note: I intend to sumbit a documentation patch later that explains the "right way" to set these three attributes since it is a bit odd due to the conditional interdependencies. --- drivers/iio/adc/ti-ads112c14.c | 493 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 480 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ti-ads112c14.c b/drivers/iio/adc/ti-ads112c14.c index 55462fc57752..85e926184b6e 100644 --- a/drivers/iio/adc/ti-ads112c14.c +++ b/drivers/iio/adc/ti-ads112c14.c @@ -92,6 +92,14 @@ #define ADS112C14_DATA_RATE_CFG_DELAY GENMASK(7, 4) #define ADS112C14_DATA_RATE_CFG_GC_EN BIT(3) #define ADS112C14_DATA_RATE_CFG_FLTR_OSR GENMASK(2, 0) +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_16 0 +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_32 1 +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_128 2 +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_256 3 +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_512 4 +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_1024 5 +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS 6 +#define ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS 7 =20 #define ADS112C14_REG_MUX_CFG 0x07 #define ADS112C14_MUX_CFG_AINP GENMASK(7, 4) @@ -181,6 +189,43 @@ static const u32 ads112c14_pga_gains_x10[] =3D { =20 #define ADS112C14_INTERNAL_CLK_Hz 4096000 =20 +/* Index corresponds to first 2 ADS112C14_DATA_RATE_CFG_FLTR_OSR values. */ +static const int ads112c14_sinc4_osr_available[] =3D { + 16, 32 +}; + +/* Index corresponds to next 4 ADS112C14_DATA_RATE_CFG_FLTR_OSR values. */ +static const int ads112c14_sinc4_sinc1_osr_available[] =3D { + 128, 256, 512, 1024 +}; + +/* Index corresponds to ADS112C14_DEVICE_CFG_SPEED_MODE value. */ +static const int ads112c14_sinc4_sinc1_pf1_20sps_osr_available[] =3D { + 1600, 12800, 25600, 51200 +}; + +/* Index corresponds to ADS112C14_DEVICE_CFG_SPEED_MODE value. */ +static const int ads112c14_sinc4_sinc1_pf1_25sps_osr_available[] =3D { + 1280, 10240, 20480, 40960 +}; + +/* Index corresponds to ADS112C14_DEVICE_CFG_SPEED_MODE value. */ +static const int ads112c14_fmod_div[] =3D { + 128, 16, 8, 4 +}; + +enum ads112c14_filter_type { + ADS112C14_FILTER_TYPE_SINC4, + ADS112C14_FILTER_TYPE_SINC4_SINC1, + ADS112C14_FILTER_TYPE_SINC4_SINC1_PF1, +}; + +static const char * const ads112c14_filter_type_names[] =3D { + [ADS112C14_FILTER_TYPE_SINC4] =3D "sinc4", + [ADS112C14_FILTER_TYPE_SINC4_SINC1] =3D "sinc4+sinc1", + [ADS112C14_FILTER_TYPE_SINC4_SINC1_PF1] =3D "sinc4+sinc1+pf1", +}; + #define ADS112C14_I2C_CRC8_POLYNOMIAL 0x07 DECLARE_CRC8_TABLE(ads112c14_crc8_table); =20 @@ -202,6 +247,8 @@ enum { ADS112C14_SYS_MON_CHANNEL_SHORT, }; =20 +static const struct iio_chan_spec_ext_info ads112c14_ext_info[]; + static const struct iio_chan_spec ads112c14_sys_mon_channels[] =3D { { .type =3D IIO_TEMP, @@ -210,7 +257,12 @@ static const struct iio_chan_spec ads112c14_sys_mon_ch= annels[] =3D { .address =3D 2, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) - | BIT(IIO_CHAN_INFO_OFFSET), + | BIT(IIO_CHAN_INFO_OFFSET) + | BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info =3D ads112c14_ext_info, }, { .type =3D IIO_VOLTAGE, @@ -218,7 +270,12 @@ static const struct iio_chan_spec ads112c14_sys_mon_ch= annels[] =3D { .channel =3D ADS112C14_SYS_MON_CHANNEL_EXT_REF, .address =3D 3, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) - | BIT(IIO_CHAN_INFO_SCALE), + | BIT(IIO_CHAN_INFO_SCALE) + | BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info =3D ads112c14_ext_info, }, { .type =3D IIO_VOLTAGE, @@ -226,7 +283,12 @@ static const struct iio_chan_spec ads112c14_sys_mon_ch= annels[] =3D { .channel =3D ADS112C14_SYS_MON_CHANNEL_AVDD, .address =3D 4, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) - | BIT(IIO_CHAN_INFO_SCALE), + | BIT(IIO_CHAN_INFO_SCALE) + | BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info =3D ads112c14_ext_info, }, { .type =3D IIO_VOLTAGE, @@ -234,7 +296,12 @@ static const struct iio_chan_spec ads112c14_sys_mon_ch= annels[] =3D { .channel =3D ADS112C14_SYS_MON_CHANNEL_DVDD, .address =3D 5, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) - | BIT(IIO_CHAN_INFO_SCALE), + | BIT(IIO_CHAN_INFO_SCALE) + | BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info =3D ads112c14_ext_info, }, { .type =3D IIO_VOLTAGE, @@ -244,8 +311,13 @@ static const struct iio_chan_spec ads112c14_sys_mon_ch= annels[] =3D { .differential =3D 1, .address =3D 1, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) - | BIT(IIO_CHAN_INFO_SCALE), - .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SCALE), + | BIT(IIO_CHAN_INFO_SCALE) + | BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SCALE) + | BIT(IIO_CHAN_INFO_SAMP_FREQ) + | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info =3D ads112c14_ext_info, }, }; =20 @@ -265,6 +337,11 @@ struct ads112c14_measurement { int scale_available[ARRAY_SIZE(ads112c14_pga_gains_x10)][2]; }; =20 +struct ads112c14_channel_state { + u8 speed_mode; + u8 filter_osr; +}; + struct ads112c14_data { const struct ads112c14_chip_info *chip_info; struct regmap *regmap; @@ -282,9 +359,13 @@ struct ads112c14_data { bool refn_is_gnd; u32 ext_ref_ohms; struct ads112c14_measurement *measurements; + struct ads112c14_channel_state *channel_states; u32 num_measurements; u8 sys_mon_chan_short_gain_val; int sys_mon_chan_short_scale_available[ARRAY_SIZE(ads112c14_pga_gains_x10= )][2]; + int sinc4_sample_rate_available[ARRAY_SIZE(ads112c14_sinc4_osr_available)= ][ARRAY_SIZE(ads112c14_fmod_div)][2]; + int sinc4_sinc1_sample_rate_available[ARRAY_SIZE(ads112c14_sinc4_sinc1_os= r_available)][ARRAY_SIZE(ads112c14_fmod_div)][2]; + int sinc4_sinc1_pf1_sample_rate_available[2][2]; IIO_DECLARE_BUFFER_WITH_TS(__be32, scan, ADS112C14_MAX_MEASUREMENT_CHANNE= LS + ARRAY_SIZE(ads112c14_sys_mon_channels)); }; @@ -470,14 +551,46 @@ static const struct regmap_config ads112c14_regmap_co= nfig =3D { .cache_type =3D REGCACHE_MAPLE, }; =20 +static int ads112c14_get_osr(struct ads112c14_channel_state *channel_state) +{ + u8 i; + + switch (channel_state->filter_osr) { + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_16...ADS112C14_DATA_RATE_CFG_FLTR_O= SR_32: + i =3D channel_state->filter_osr; + return ads112c14_sinc4_osr_available[i]; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_128...ADS112C14_DATA_RATE_CFG_FLTR_= OSR_1024: + i =3D channel_state->filter_osr - ADS112C14_DATA_RATE_CFG_FLTR_OSR_128; + return ads112c14_sinc4_sinc1_osr_available[i]; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS: + i =3D channel_state->speed_mode; + return ads112c14_sinc4_sinc1_pf1_25sps_osr_available[i]; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS: + i =3D channel_state->speed_mode; + return ads112c14_sinc4_sinc1_pf1_20sps_osr_available[i]; + default: + return -EINVAL; + } +} + static int ads112c14_prepare_measurement_channel(struct ads112c14_data *da= ta, const struct iio_chan_spec *chan, bool en_burnout) { struct ads112c14_measurement *measurement =3D &data->measurements[chan->s= can_index]; + struct ads112c14_channel_state *channel_state; u32 refp_buf_en, refn_buf_en, ref_val, ref_sel; int ret; =20 + channel_state =3D &data->channel_states[chan->scan_index]; + + ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DEVICE_CFG, + ADS112C14_DEVICE_CFG_SPEED_MODE, + FIELD_PREP(ADS112C14_DEVICE_CFG_SPEED_MODE, + channel_state->speed_mode)); + if (ret) + return ret; + ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_MUX_CFG, ADS112C14_MUX_CFG_AINP | ADS112C14_MUX_CFG_AINN, FIELD_PREP(ADS112C14_MUX_CFG_AINP, chan->channel) | @@ -524,10 +637,13 @@ static int ads112c14_prepare_measurement_channel(stru= ct ads112c14_data *data, return ret; =20 ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DATA_RATE_CFG, - ADS112C14_DATA_RATE_CFG_GC_EN, + ADS112C14_DATA_RATE_CFG_GC_EN | + ADS112C14_DATA_RATE_CFG_FLTR_OSR, FIELD_PREP(ADS112C14_DATA_RATE_CFG_GC_EN, (measurement->global_chop && - !en_burnout) ? 1 : 0)); + !en_burnout) ? 1 : 0) | + FIELD_PREP(ADS112C14_DATA_RATE_CFG_FLTR_OSR, + channel_state->filter_osr)); if (ret) return ret; =20 @@ -570,9 +686,12 @@ static int ads112c14_prepare_measurement_channel(struc= t ads112c14_data *data, static int ads112c14_prepare_sys_mon_channel(struct ads112c14_data *data, const struct iio_chan_spec *chan) { + struct ads112c14_channel_state *channel_state; u32 gain_val; int ret; =20 + channel_state =3D &data->channel_states[chan->scan_index]; + /* * NB: IDAC registers are left as-is in case they are generating current * needed for the external reference measurement. @@ -599,6 +718,22 @@ static int ads112c14_prepare_sys_mon_channel(struct ad= s112c14_data *data, if (ret) return ret; =20 + ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DEVICE_CFG, + ADS112C14_DEVICE_CFG_SPEED_MODE, + FIELD_PREP(ADS112C14_DEVICE_CFG_SPEED_MODE, + channel_state->speed_mode)); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DATA_RATE_CFG, + ADS112C14_DATA_RATE_CFG_GC_EN | + ADS112C14_DATA_RATE_CFG_FLTR_OSR, + FIELD_PREP(ADS112C14_DATA_RATE_CFG_GC_EN, 0) | + FIELD_PREP(ADS112C14_DATA_RATE_CFG_FLTR_OSR, + channel_state->filter_osr)); + if (ret) + return ret; + /* * REVISIT: if we implement regulator support for the REFOUT pin, we * might need to make this voltage match what is required by that. In @@ -833,6 +968,45 @@ static int ads112c14_read_raw(struct iio_dev *indio_de= v, */ *val =3D div_s64((s64)(25 * 405 - 119500) * BIT(fsr_bits), vref_uV); return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: { + struct ads112c14_channel_state *channel_state; + const int (*available)[2]; + u8 i, j; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + switch (channel_state->filter_osr) { + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_16...ADS112C14_DATA_RATE_CFG_FLTR_= OSR_32: + j =3D channel_state->filter_osr; + available =3D data->sinc4_sample_rate_available[j]; + i =3D channel_state->speed_mode; + break; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_128...ADS112C14_DATA_RATE_CFG_FLTR= _OSR_1024: + j =3D channel_state->filter_osr - ADS112C14_DATA_RATE_CFG_FLTR_OSR_128; + available =3D data->sinc4_sinc1_sample_rate_available[j]; + i =3D channel_state->speed_mode; + break; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS: + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS: + available =3D data->sinc4_sinc1_pf1_sample_rate_available; + i =3D channel_state->filter_osr - ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SP= S; + break; + default: + return -EINVAL; + } + + *val =3D available[i][0]; + *val2 =3D available[i][1]; + return IIO_VAL_INT_PLUS_MICRO; + } + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { + guard(mutex)(&data->lock); + + *val =3D ads112c14_get_osr(&data->channel_states[chan->scan_index]); + return IIO_VAL_INT; + } default: return -EINVAL; } @@ -843,6 +1017,9 @@ static int ads112c14_read_avail(struct iio_dev *indio_= dev, int *type, int *length, long mask) { struct ads112c14_data *data =3D iio_priv(indio_dev); + struct ads112c14_channel_state *channel_state; + + channel_state =3D &data->channel_states[chan->scan_index]; =20 switch (mask) { case IIO_CHAN_INFO_SCALE: @@ -868,6 +1045,58 @@ static int ads112c14_read_avail(struct iio_dev *indio= _dev, } =20 return -EINVAL; + + case IIO_CHAN_INFO_SAMP_FREQ: { + guard(mutex)(&data->lock); + + switch (channel_state->filter_osr) { + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_16...ADS112C14_DATA_RATE_CFG_FLTR_= OSR_32: + *vals =3D (const int *)data->sinc4_sample_rate_available[channel_state-= >filter_osr]; + *length =3D 2 * ARRAY_SIZE(data->sinc4_sample_rate_available[0]); + *type =3D IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_128...ADS112C14_DATA_RATE_CFG_FLTR= _OSR_1024: + *vals =3D (const int *)data->sinc4_sinc1_sample_rate_available[channel_= state->filter_osr - ADS112C14_DATA_RATE_CFG_FLTR_OSR_128]; + *length =3D 2 * ARRAY_SIZE(data->sinc4_sinc1_sample_rate_available[0]); + *type =3D IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS...ADS112C14_DATA_RATE_CFG_FL= TR_OSR_20SPS: + *vals =3D (const int *)data->sinc4_sinc1_pf1_sample_rate_available; + *length =3D 2 * ARRAY_SIZE(data->sinc4_sinc1_pf1_sample_rate_available); + *type =3D IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + } + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { + guard(mutex)(&data->lock); + + switch (channel_state->filter_osr) { + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_16...ADS112C14_DATA_RATE_CFG_FLTR_= OSR_32: + *vals =3D ads112c14_sinc4_osr_available; + *length =3D ARRAY_SIZE(ads112c14_sinc4_osr_available); + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_128...ADS112C14_DATA_RATE_CFG_FLTR= _OSR_1024: + *vals =3D ads112c14_sinc4_sinc1_osr_available; + *length =3D ARRAY_SIZE(ads112c14_sinc4_sinc1_osr_available); + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS: + *vals =3D ads112c14_sinc4_sinc1_pf1_25sps_osr_available; + *length =3D ARRAY_SIZE(ads112c14_sinc4_sinc1_pf1_25sps_osr_available); + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS: + *vals =3D ads112c14_sinc4_sinc1_pf1_20sps_osr_available; + *length =3D ARRAY_SIZE(ads112c14_sinc4_sinc1_pf1_20sps_osr_available); + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + } default: return -EINVAL; } @@ -880,6 +1109,7 @@ static int ads112c14_write_raw(struct iio_dev *indio_d= ev, struct ads112c14_data *data =3D iio_priv(indio_dev); const int (*scale_avail)[2]; u8 *gain_val; + u32 i; =20 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); if (IIO_DEV_ACQUIRE_FAILED(claim)) @@ -912,6 +1142,99 @@ static int ads112c14_write_raw(struct iio_dev *indio_= dev, =20 return -EINVAL; } + case IIO_CHAN_INFO_SAMP_FREQ: { + struct ads112c14_channel_state *channel_state; + const int (*available)[2]; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + switch (channel_state->filter_osr) { + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_16...ADS112C14_DATA_RATE_CFG_FLTR_= OSR_1024: + if (channel_state->filter_osr < ADS112C14_DATA_RATE_CFG_FLTR_OSR_128) { + u8 idx =3D channel_state->filter_osr; + + available =3D data->sinc4_sample_rate_available[idx]; + } else { + u8 idx =3D channel_state->filter_osr - ADS112C14_DATA_RATE_CFG_FLTR_OS= R_128; + + available =3D data->sinc4_sinc1_sample_rate_available[idx]; + } + + for (i =3D 0; i < ARRAY_SIZE(ads112c14_fmod_div); i++) { + if (val =3D=3D available[i][0] && val2 =3D=3D available[i][1]) { + channel_state->speed_mode =3D i; + return 0; + } + } + + return -EINVAL; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS: + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS: { + available =3D data->sinc4_sinc1_pf1_sample_rate_available; + + for (i =3D 0; i < ARRAY_SIZE(data->sinc4_sinc1_pf1_sample_rate_availabl= e); i++) { + if (val =3D=3D available[i][0] && val2 =3D=3D available[i][1]) { + channel_state->filter_osr =3D i + ADS112C14_DATA_RATE_CFG_FLTR_OSR_25= SPS; + return 0; + } + } + + return -EINVAL; + } + default: + return -EINVAL; + } + } + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { + struct ads112c14_channel_state *channel_state; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + switch (channel_state->filter_osr) { + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_16...ADS112C14_DATA_RATE_CFG_FLTR_= OSR_32: + for (i =3D 0; i < ARRAY_SIZE(ads112c14_sinc4_osr_available); i++) { + if (val =3D=3D ads112c14_sinc4_osr_available[i]) { + channel_state->filter_osr =3D i; + return 0; + } + } + + return -EINVAL; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_128...ADS112C14_DATA_RATE_CFG_FLTR= _OSR_1024: + for (i =3D 0; i < ARRAY_SIZE(ads112c14_sinc4_sinc1_osr_available); i++)= { + if (val =3D=3D ads112c14_sinc4_sinc1_osr_available[i]) { + channel_state->filter_osr =3D i + ADS112C14_DATA_RATE_CFG_FLTR_OSR_12= 8; + return 0; + } + } + + return -EINVAL; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS: + for (i =3D 0; i < ARRAY_SIZE(ads112c14_sinc4_sinc1_pf1_25sps_osr_availa= ble); i++) { + if (val =3D=3D ads112c14_sinc4_sinc1_pf1_25sps_osr_available[i]) { + channel_state->speed_mode =3D i; + return 0; + } + } + + return -EINVAL; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS: + for (i =3D 0; i < ARRAY_SIZE(ads112c14_sinc4_sinc1_pf1_20sps_osr_availa= ble); i++) { + if (val =3D=3D ads112c14_sinc4_sinc1_pf1_20sps_osr_available[i]) { + channel_state->speed_mode =3D i; + return 0; + } + } + + return -EINVAL; + default: + return -EINVAL; + } + } default: return -EINVAL; } @@ -1200,11 +1523,98 @@ static ssize_t ads112c14_read_burnout_raw(struct ii= o_dev *indio_dev, return sysfs_emit(buf, "%d\n", val); } =20 +static int ads112c14_get_filter_type_from_state(struct ads112c14_channel_s= tate *channel_state) +{ + switch (channel_state->filter_osr) { + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_16...ADS112C14_DATA_RATE_CFG_FLTR_O= SR_32: + return ADS112C14_FILTER_TYPE_SINC4; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_128...ADS112C14_DATA_RATE_CFG_FLTR_= OSR_1024: + return ADS112C14_FILTER_TYPE_SINC4_SINC1; + case ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS...ADS112C14_DATA_RATE_CFG_FLT= R_OSR_20SPS: + return ADS112C14_FILTER_TYPE_SINC4_SINC1_PF1; + default: + return -EINVAL; + } +} + +static int ads112c14_set_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + unsigned int val) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + struct ads112c14_channel_state *channel_state; + int ret; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + ret =3D ads112c14_get_filter_type_from_state(channel_state); + if (ret < 0) + return ret; + + /* + * channel_state->filter_osr affects multiple attributes, so don't modify + * it if the filter type is already set to the requested value. + */ + if (ret =3D=3D val) + return 0; + + /* Otherwise, pick an arbitrary default for each type. */ + switch (val) { + case ADS112C14_FILTER_TYPE_SINC4: + channel_state->filter_osr =3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_16; + break; + case ADS112C14_FILTER_TYPE_SINC4_SINC1: + channel_state->filter_osr =3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_128; + break; + case ADS112C14_FILTER_TYPE_SINC4_SINC1_PF1: + channel_state->filter_osr =3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ads112c14_get_filter_type(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + struct ads112c14_channel_state *channel_state; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + return ads112c14_get_filter_type_from_state(channel_state); +} + +static const struct iio_enum ads112c14_filter_type_enum =3D { + .items =3D ads112c14_filter_type_names, + .num_items =3D ARRAY_SIZE(ads112c14_filter_type_names), + .set =3D ads112c14_set_filter_type, + .get =3D ads112c14_get_filter_type, +}; + +static const struct iio_chan_spec_ext_info ads112c14_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, &ads112c14_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ads112c14_filter_type_en= um), + { } +}; + static const struct iio_chan_spec_ext_info ads112c14_ext_info_burnout[] = =3D { { .name =3D "burnoutraw", .read =3D ads112c14_read_burnout_raw, }, + IIO_ENUM("filter_type", IIO_SEPARATE, &ads112c14_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ads112c14_filter_type_en= um), { } }; =20 @@ -1230,7 +1640,7 @@ static int ads112c14_parse_channels(struct iio_dev *i= ndio_dev, struct ads112c14_data *data =3D iio_priv(indio_dev); struct device *dev =3D indio_dev->dev.parent; struct iio_chan_spec *channels; - u32 num_child_nodes, i, pair[2]; + u32 num_child_nodes, num_data_chans, i, pair[2]; int ret; =20 *need_avdd_ref =3D false; @@ -1243,8 +1653,15 @@ static int ads112c14_parse_channels(struct iio_dev *= indio_dev, if (!data->measurements) return -ENOMEM; =20 - channels =3D devm_kcalloc(dev, num_child_nodes + - ARRAY_SIZE(ads112c14_sys_mon_channels) + 1, + num_data_chans =3D num_child_nodes + ARRAY_SIZE(ads112c14_sys_mon_channel= s); + + data->channel_states =3D devm_kcalloc(dev, num_data_chans, + sizeof(*data->channel_states), + GFP_KERNEL); + if (!data->channel_states) + return -ENOMEM; + + channels =3D devm_kcalloc(dev, num_data_chans + 1, sizeof(*channels), GFP_KERNEL); if (!channels) return -ENOMEM; @@ -1257,7 +1674,9 @@ static int ads112c14_parse_channels(struct iio_dev *i= ndio_dev, =20 spec->indexed =3D 1; spec->scan_index =3D i; + spec->ext_info =3D ads112c14_ext_info; measurement->gain_val =3D 1; + data->channel_states[i].filter_osr =3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_= 16; =20 if (fwnode_property_present(child, "label")) { ret =3D fwnode_property_read_string(child, "label", &measurement->label= ); @@ -1422,8 +1841,13 @@ static int ads112c14_parse_channels(struct iio_dev *= indio_dev, if (measurement->vref_source =3D=3D ADS112C14_VREF_SOURCE_EXTERNAL) *need_ext_ref =3D true; =20 - spec->info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_= SCALE); - spec->info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SCALE); + spec->info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); + spec->info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); =20 /* * If reference source is resistor rather than voltage supply, @@ -1457,6 +1881,10 @@ static int ads112c14_parse_channels(struct iio_dev *= indio_dev, =20 for (u32 j =3D 0; j < ARRAY_SIZE(ads112c14_sys_mon_channels); j++) { struct iio_chan_spec *spec =3D &channels[i]; + struct ads112c14_channel_state *channel_state; + + channel_state =3D &data->channel_states[i]; + channel_state->filter_osr =3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_16; =20 /* Update the template that was already copied with dynamic values. */ spec->scan_index =3D i; @@ -1495,6 +1923,44 @@ static void ads112c14_populate_scale_available(int (= *scale_avail)[2], } } =20 +static void ads112c14_populate_odr_tables(struct ads112c14_data *data) +{ + int *available; + u32 osr, fmod_Hz; + u64 odr_uHz; + u32 i, j; + + for (i =3D 0; i < ARRAY_SIZE(ads112c14_sinc4_osr_available); i++) { + osr =3D ads112c14_sinc4_osr_available[i]; + + for (j =3D 0; j < ARRAY_SIZE(ads112c14_fmod_div); j++) { + fmod_Hz =3D data->fclk_Hz / ads112c14_fmod_div[j]; + odr_uHz =3D div_u64((u64)fmod_Hz * MICRO, osr); + available =3D data->sinc4_sample_rate_available[i][j]; + available[0] =3D div_u64_rem(odr_uHz, MICRO, &available[1]); + } + } + + for (i =3D 0; i < ARRAY_SIZE(ads112c14_sinc4_sinc1_osr_available); i++) { + osr =3D ads112c14_sinc4_sinc1_osr_available[i]; + + for (j =3D 0; j < ARRAY_SIZE(ads112c14_fmod_div); j++) { + fmod_Hz =3D data->fclk_Hz / ads112c14_fmod_div[j]; + odr_uHz =3D div_u64((u64)fmod_Hz * MICRO, osr); + available =3D data->sinc4_sinc1_sample_rate_available[i][j]; + available[0] =3D div_u64_rem(odr_uHz, MICRO, &available[1]); + } + } + + odr_uHz =3D div_u64((u64)25 * data->fclk_Hz * MICRO, ADS112C14_INTERNAL_C= LK_Hz); + available =3D data->sinc4_sinc1_pf1_sample_rate_available[0]; + available[0] =3D div_u64_rem(odr_uHz, MICRO, &available[1]); + + odr_uHz =3D div_u64((u64)20 * data->fclk_Hz * MICRO, ADS112C14_INTERNAL_C= LK_Hz); + available =3D data->sinc4_sinc1_pf1_sample_rate_available[1]; + available[0] =3D div_u64_rem(odr_uHz, MICRO, &available[1]); +} + static void ads112c14_populate_tables(struct ads112c14_data *data) { u32 full_scale, fsr_bits; @@ -1532,6 +1998,7 @@ static void ads112c14_populate_tables(struct ads112c1= 4_data *data) =20 ads112c14_populate_scale_available(data->sys_mon_chan_short_scale_availab= le, full_scale, fsr_bits); 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Fri, 04 Sep 2026 15:11:23 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:53 -0500 Subject: [PATCH v2 08/10] iio: ABI: add sinc4+sinc1+pf1 filter_type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-8-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=859; i=dlechner@baylibre.com; h=from:subject:message-id; bh=4mIrQseGaDrWXOkGj+VmtS3xT3kzP+fkmkBCoKYUU7I=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBqm0HlQXdNNIv6P1pCGYX3k0ytCkSsrBvRFD/gx 8Xp0vh7buCJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaptB5QAKCRDCzCAB/wGP wOjrB/wP+pIBS0ZXanR7Fag75lIXHQ8UPkpwn3bDpjabLNeuTguY43lX/pl3e5xPSXNgq2n8JmD 7IM5RXzKz/vQupNeKlsz+iAbseCmomlK4hVfkMzus/pUb+wpWpOTAlTQN5v0z//RJmG8ocka2bZ kQjgPg4pKRmrQzpyFYyD1ss42q7k+JKcJTY9bukatphXZKGU7g/pIpPpBkIjPllx9ZZN8MHAP6I H2YevGAlw6t4zFIyP/MOZ6kr5Vy0xtsQJnEoVYbxlyLUYh54wrfCcVf6V7ZFVBws0edtP3zTrcm trxOOshaBjbYzagMhFWzAn8/db8LvuCDK+SGkiVeS1SXnq+b X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Document "sinc4+sinc1+pf1" as a valid value for the filter_type attributes (used by the ti-ads112c14 driver). Signed-off-by: David Lechner (TI) --- Documentation/ABI/testing/sysfs-bus-iio | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index a4f5595722ad..a8e1cb8e7490 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2380,6 +2380,7 @@ Description: * "sinc4+lp" - Sinc4 + Low Pass Filter. * "sinc4+sinc1" - Sinc4 + averaging by 8. Low 1st conversion time. + * "sinc4+sinc1+pf1" - Sinc4 + Sinc1 + device specific Post Filter 1. * "sinc4+rej60" - Sinc4 + 60Hz rejection. * "sinc5" - The digital sinc5 filter. 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Fri, 04 Sep 2026 15:11:26 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:54 -0500 Subject: [PATCH v2 09/10] iio: adc: ti-ads112c14: add settlingtime attribute Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-9-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=16336; i=dlechner@baylibre.com; h=from:subject:message-id; bh=VYcLUR5pyU3cOVIMVhoy1lnfQPR8q3knc32o7bdB9fs=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBqm0Hr/sPTUq+h7VmmT62js2dn0XDJ6y9mB6wrO hZ6JFI1a6KJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaptB6wAKCRDCzCAB/wGP wPI6B/4wwkup6wNc84ISLkPYkZKh6vHnmOrvMQlZnYWJqGPLNLkQToBQ8zFfa0deO63IwEmg8eK k2OcwbHI+IPR6EBkSe+Q37NiBFPQ0hVq1ZU0u6Ec1uGrLM0z4DLhgEX/VDzTh4zrsj5v0Uwn5Cy Zy++Z43NNxZvpgm1wqhflnsFuIYwcUu270KLyTPN6Z16muY6q+uP3FvAa+K1bt8+Ff4z2rvK9N2 Pma/YUmTwwzjR/bhmMo58ETwneM8YMG2tyqQBH5jk2tXpiuR9k7OGtEPgaUGctcHrpjwUf/q5+x OsbAEFrzOXi6/7vlq1v9FQNCvS8WWDOs/QZoxpH/4dVxwqoU X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add per-channel sysfs attributes for settlingtime and settlingtime_available. These allow adjusting the total settling time for each channel. The value consists of a fixed t_latency time (based on the selected filter_type, oversampling_ratio and sampling_frequency) plus a user-configurable t_delay that determines the value to write to the DELAY field in the registers. The allowable values are non-linear integer multiples, so the step size is just the smallest step size. Writing the attribute will match the closest matching value for the DELAY field with a time equal to or greater than the requested settling time (unless the requested time is larger than the maximum allowable settling time). Signed-off-by: David Lechner (TI) --- drivers/iio/adc/ti-ads112c14.c | 337 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 331 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ti-ads112c14.c b/drivers/iio/adc/ti-ads112c14.c index 85e926184b6e..cefbb7afe729 100644 --- a/drivers/iio/adc/ti-ads112c14.c +++ b/drivers/iio/adc/ti-ads112c14.c @@ -214,6 +214,24 @@ static const int ads112c14_fmod_div[] =3D { 128, 16, 8, 4 }; =20 +#define ADS112C14_DELAY_MAX FIELD_MAX(ADS112C14_DATA_RATE_CFG_DELAY) + +/* Table 7-6 latency in t_MOD for OSR [16, 32, 128, 256, 512, 1024]. */ +static const int ads112c14_sinc_latency_tmod[][ARRAY_SIZE(ads112c14_fmod_d= iv)] =3D { + { 80, 88, 88, 104 }, + { 144, 152, 152, 168 }, + { 240, 248, 248, 264 }, + { 368, 376, 376, 392 }, + { 624, 632, 632, 648 }, + { 1136, 1144, 1144, 1160 }, +}; + +/* Table 7-7 latency in t_MOD for output data rates [25SPS, 20SPS]. */ +static const int ads112c14_fir_latency_tmod[][ARRAY_SIZE(ads112c14_fmod_di= v)] =3D { + { 1416, 10384, 20624, 41120 }, + { 1736, 12944, 25744, 51360 }, +}; + enum ads112c14_filter_type { ADS112C14_FILTER_TYPE_SINC4, ADS112C14_FILTER_TYPE_SINC4_SINC1, @@ -340,6 +358,7 @@ struct ads112c14_measurement { struct ads112c14_channel_state { u8 speed_mode; u8 filter_osr; + u8 delay; }; =20 struct ads112c14_data { @@ -366,6 +385,8 @@ struct ads112c14_data { int sinc4_sample_rate_available[ARRAY_SIZE(ads112c14_sinc4_osr_available)= ][ARRAY_SIZE(ads112c14_fmod_div)][2]; int sinc4_sinc1_sample_rate_available[ARRAY_SIZE(ads112c14_sinc4_sinc1_os= r_available)][ARRAY_SIZE(ads112c14_fmod_div)][2]; int sinc4_sinc1_pf1_sample_rate_available[2][2]; + int sinc_settling_time_range_available[ARRAY_SIZE(ads112c14_sinc_latency_= tmod)][ARRAY_SIZE(ads112c14_fmod_div)][3][2]; + int fir_settling_time_range_available[ARRAY_SIZE(ads112c14_fir_latency_tm= od)][ARRAY_SIZE(ads112c14_fmod_div)][3][2]; IIO_DECLARE_BUFFER_WITH_TS(__be32, scan, ADS112C14_MAX_MEASUREMENT_CHANNE= LS + ARRAY_SIZE(ads112c14_sys_mon_channels)); }; @@ -573,6 +594,211 @@ static int ads112c14_get_osr(struct ads112c14_channel= _state *channel_state) } } =20 +static int ads112c14_get_fmod_Hz(struct ads112c14_data *data, + struct ads112c14_channel_state *channel_state) +{ + return data->fclk_Hz / ads112c14_fmod_div[channel_state->speed_mode]; +} + +static int ads112c14_delay_to_tmod(u8 delay) +{ + if (!delay) + return 0; + + return BIT(delay - 1); +} + +static int ads112c14_get_latency_tmod(struct ads112c14_channel_state *chan= nel_state) +{ + u8 speed_mode =3D channel_state->speed_mode; + u8 filter_osr =3D channel_state->filter_osr; + + if (speed_mode >=3D ARRAY_SIZE(ads112c14_fmod_div)) + return -EINVAL; + + if (filter_osr <=3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_1024) + return ads112c14_sinc_latency_tmod[filter_osr][speed_mode]; + + if (filter_osr =3D=3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS) + return ads112c14_fir_latency_tmod[0][speed_mode]; + + if (filter_osr =3D=3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS) + return ads112c14_fir_latency_tmod[1][speed_mode]; + + return -EINVAL; +} + +static int ads112c14_get_settling_time_us(struct ads112c14_data *data, + struct ads112c14_channel_state *channel_state, + u8 delay, u32 *settling_time_us) +{ + int fmod_Hz, latency_tmod; + u64 total_tmod; + + fmod_Hz =3D ads112c14_get_fmod_Hz(data, channel_state); + if (fmod_Hz <=3D 0) + return -EINVAL; + + latency_tmod =3D ads112c14_get_latency_tmod(channel_state); + if (latency_tmod < 0) + return latency_tmod; + + total_tmod =3D latency_tmod + ads112c14_delay_to_tmod(delay); + *settling_time_us =3D div64_u64(total_tmod * USEC_PER_SEC, fmod_Hz); + + return 0; +} + +static int ads112c14_find_delay_for_settling_time_us(struct ads112c14_data= *data, + struct ads112c14_channel_state *channel_state, + s64 settling_time_us, u8 *delay) +{ + u32 fixed_latency_us, delay_us; + u64 delay_tmod_needed; + int ret, fmod_Hz; + u8 i; + + ret =3D ads112c14_get_settling_time_us(data, channel_state, 0, &fixed_lat= ency_us); + if (ret) + return ret; + + if (settling_time_us <=3D fixed_latency_us) { + *delay =3D 0; + return 0; + } + + fmod_Hz =3D ads112c14_get_fmod_Hz(data, channel_state); + if (fmod_Hz <=3D 0) + return -EINVAL; + + delay_us =3D settling_time_us - fixed_latency_us; + delay_tmod_needed =3D DIV_ROUND_UP_ULL((u64)delay_us * fmod_Hz, + USEC_PER_SEC); + + for (i =3D 1; i < ADS112C14_DELAY_MAX; i++) { + if (ads112c14_delay_to_tmod(i) >=3D delay_tmod_needed) + break; + } + + *delay =3D i; + + return 0; +} + +static ssize_t ads112c14_read_settling_time(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + struct ads112c14_channel_state *channel_state; + u32 settling_time_us; + int vals[2]; + int ret; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + ret =3D ads112c14_get_settling_time_us(data, channel_state, + channel_state->delay, + &settling_time_us); + if (ret) + return ret; + + iio_val_s64_decompose(settling_time_us, &vals[0], &vals[1]); + + return iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(vals), v= als); +} + +static ssize_t ads112c14_write_settling_time(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + struct ads112c14_channel_state *channel_state; + s64 settling_time_us; + int integer; + int fract; + u8 delay; + int ret; + + ret =3D iio_str_to_fixpoint(buf, 100000, &integer, &fract); + if (ret) + return ret; + + settling_time_us =3D integer * MICRO + fract; + if (settling_time_us < 0) + return -EINVAL; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + ret =3D ads112c14_find_delay_for_settling_time_us(data, channel_state, + settling_time_us, &delay); + if (ret) + return ret; + + channel_state->delay =3D delay; + + return len; +} + +static ssize_t ads112c14_read_settling_time_available(struct iio_dev *indi= o_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ads112c14_data *data =3D iio_priv(indio_dev); + struct ads112c14_channel_state *channel_state; + u8 filter_osr, speed_mode; + const int (*range)[2]; + size_t len =3D 0; + int i; + + guard(mutex)(&data->lock); + + channel_state =3D &data->channel_states[chan->scan_index]; + + filter_osr =3D channel_state->filter_osr; + speed_mode =3D channel_state->speed_mode; + + if (speed_mode >=3D ARRAY_SIZE(ads112c14_fmod_div)) + return -EINVAL; + + if (filter_osr <=3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_1024) + range =3D data->sinc_settling_time_range_available[filter_osr][speed_mod= e]; + else if (filter_osr =3D=3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_25SPS) + range =3D data->fir_settling_time_range_available[0][speed_mode]; + else if (filter_osr =3D=3D ADS112C14_DATA_RATE_CFG_FLTR_OSR_20SPS) + range =3D data->fir_settling_time_range_available[1][speed_mode]; + else + return -EINVAL; + + len +=3D sysfs_emit_at(buf, len, "["); + for (i =3D 0; i < 3; i++) { + s64 range_val; + s32 int_val, rem; + + range_val =3D iio_val_s64_compose(range[i][0], range[i][1]); + int_val =3D div_s64_rem(range_val, MICRO, &rem); + + if (i) + len +=3D sysfs_emit_at(buf, len, " "); + + len +=3D sysfs_emit_at(buf, len, "%d.%06d", int_val, rem); + } + len +=3D sysfs_emit_at(buf, len, "]\n"); + + return len; +} + static int ads112c14_prepare_measurement_channel(struct ads112c14_data *da= ta, const struct iio_chan_spec *chan, bool en_burnout) @@ -637,8 +863,11 @@ static int ads112c14_prepare_measurement_channel(struc= t ads112c14_data *data, return ret; =20 ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DATA_RATE_CFG, + ADS112C14_DATA_RATE_CFG_DELAY | ADS112C14_DATA_RATE_CFG_GC_EN | ADS112C14_DATA_RATE_CFG_FLTR_OSR, + FIELD_PREP(ADS112C14_DATA_RATE_CFG_DELAY, + channel_state->delay) | FIELD_PREP(ADS112C14_DATA_RATE_CFG_GC_EN, (measurement->global_chop && !en_burnout) ? 1 : 0) | @@ -726,8 +955,11 @@ static int ads112c14_prepare_sys_mon_channel(struct ad= s112c14_data *data, return ret; =20 ret =3D regmap_update_bits(data->regmap, ADS112C14_REG_DATA_RATE_CFG, + ADS112C14_DATA_RATE_CFG_DELAY | ADS112C14_DATA_RATE_CFG_GC_EN | ADS112C14_DATA_RATE_CFG_FLTR_OSR, + FIELD_PREP(ADS112C14_DATA_RATE_CFG_DELAY, + channel_state->delay) | FIELD_PREP(ADS112C14_DATA_RATE_CFG_GC_EN, 0) | FIELD_PREP(ADS112C14_DATA_RATE_CFG_FLTR_OSR, channel_state->filter_osr)); @@ -786,7 +1018,8 @@ static int ads112c14_scan_read(struct ads112c14_data *= data, u8 *buf) return 0; } =20 -static int ads112c14_wait_for_conversion_irq(struct ads112c14_data *data) +static int ads112c14_wait_for_conversion_irq(struct ads112c14_data *data, + u32 settle_time_us) { unsigned long remaining; int ret; @@ -798,13 +1031,16 @@ static int ads112c14_wait_for_conversion_irq(struct = ads112c14_data *data) if (ret) return ret; =20 + /* Give it 1ms more than calculated settling time. */ remaining =3D wait_for_completion_timeout(&data->drdy_completion, - msecs_to_jiffies(100)); + usecs_to_jiffies(settle_time_us + + 1 * USEC_PER_MSEC)); =20 return remaining ? 0 : -ETIMEDOUT; } =20 -static int ads112c14_wait_for_conversion_poll(struct ads112c14_data *data) +static int ads112c14_wait_for_conversion_poll(struct ads112c14_data *data, + u32 settle_time_us) { u32 reg_val; int ret; @@ -814,10 +1050,12 @@ static int ads112c14_wait_for_conversion_poll(struct= ads112c14_data *data) if (ret) return ret; =20 + /* Give it 1ms more than calculated settling time. */ return regmap_read_poll_timeout(data->regmap, ADS112C14_REG_STATUS_MSB, reg_val, FIELD_GET(ADS112C14_STATUS_MSB_DRDY, reg_val), - 1 * USEC_PER_MSEC, 100 * USEC_PER_MSEC); + 1 * USEC_PER_MSEC, settle_time_us + + 1 * USEC_PER_MSEC); } =20 static int ads112c14_single_conversion(struct ads112c14_data *data, @@ -825,6 +1063,8 @@ static int ads112c14_single_conversion(struct ads112c1= 4_data *data, u8 *buf, bool en_burnout, bool for_scan) { struct i2c_client *client =3D to_i2c_client(regmap_get_device(data->regma= p)); + struct ads112c14_channel_state *channel_state; + u32 settle_time_us; int ret; =20 guard(mutex)(&data->lock); @@ -833,10 +1073,26 @@ static int ads112c14_single_conversion(struct ads112= c14_data *data, if (ret) return ret; =20 + channel_state =3D &data->channel_states[chan->scan_index]; + ret =3D ads112c14_get_settling_time_us(data, channel_state, + channel_state->delay, + &settle_time_us); + if (ret) + return ret; + + ret =3D regmap_test_bits(data->regmap, ADS112C14_REG_DATA_RATE_CFG, + ADS112C14_DATA_RATE_CFG_GC_EN); + if (ret < 0) + return ret; + + /* Input chopping doubles the settling time. */ + if (ret) + settle_time_us *=3D 2; + if (data->drdy_irq) - ret =3D ads112c14_wait_for_conversion_irq(data); + ret =3D ads112c14_wait_for_conversion_irq(data, settle_time_us); else - ret =3D ads112c14_wait_for_conversion_poll(data); + ret =3D ads112c14_wait_for_conversion_poll(data, settle_time_us); if (ret) return ret; =20 @@ -1603,6 +1859,17 @@ static const struct iio_enum ads112c14_filter_type_e= num =3D { }; =20 static const struct iio_chan_spec_ext_info ads112c14_ext_info[] =3D { + { + .name =3D "settlingtime", + .read =3D ads112c14_read_settling_time, + .write =3D ads112c14_write_settling_time, + .shared =3D IIO_SEPARATE, + }, + { + .name =3D "settlingtime_available", + .read =3D ads112c14_read_settling_time_available, + .shared =3D IIO_SEPARATE, + }, IIO_ENUM("filter_type", IIO_SEPARATE, &ads112c14_filter_type_enum), IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ads112c14_filter_type_en= um), { } @@ -1613,6 +1880,17 @@ static const struct iio_chan_spec_ext_info ads112c14= _ext_info_burnout[] =3D { .name =3D "burnoutraw", .read =3D ads112c14_read_burnout_raw, }, + { + .name =3D "settlingtime", + .read =3D ads112c14_read_settling_time, + .write =3D ads112c14_write_settling_time, + .shared =3D IIO_SEPARATE, + }, + { + .name =3D "settlingtime_available", + .read =3D ads112c14_read_settling_time_available, + .shared =3D IIO_SEPARATE, + }, IIO_ENUM("filter_type", IIO_SEPARATE, &ads112c14_filter_type_enum), IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ads112c14_filter_type_en= um), { } @@ -1961,6 +2239,52 @@ static void ads112c14_populate_odr_tables(struct ads= 112c14_data *data) available[0] =3D div_u64_rem(odr_uHz, MICRO, &available[1]); } =20 +static void ads112c14_populate_settling_range_tables(struct ads112c14_data= *data) +{ + s32 (*avail)[2]; + u32 i, j; + + for (i =3D 0; i < ARRAY_SIZE(ads112c14_sinc_latency_tmod); i++) { + for (j =3D 0; j < ARRAY_SIZE(ads112c14_fmod_div); j++) { + u64 fmod_Hz =3D data->fclk_Hz / ads112c14_fmod_div[j]; + u64 start_tmod =3D ads112c14_sinc_latency_tmod[i][j]; + u64 step_tmod =3D ads112c14_delay_to_tmod(1); + u64 stop_tmod =3D start_tmod + ads112c14_delay_to_tmod(ADS112C14_DELAY_= MAX); + s64 start_us, step_us, stop_us; + + start_us =3D DIV_ROUND_CLOSEST_ULL(start_tmod * USEC_PER_SEC, fmod_Hz); + step_us =3D DIV_ROUND_CLOSEST_ULL(step_tmod * USEC_PER_SEC, fmod_Hz); + stop_us =3D DIV_ROUND_CLOSEST_ULL(stop_tmod * USEC_PER_SEC, fmod_Hz); + + avail =3D data->sinc_settling_time_range_available[i][j]; + + iio_val_s64_decompose(start_us, &avail[0][0], &avail[0][1]); + iio_val_s64_decompose(step_us, &avail[1][0], &avail[1][1]); + iio_val_s64_decompose(stop_us, &avail[2][0], &avail[2][1]); + } + } + + for (i =3D 0; i < ARRAY_SIZE(ads112c14_fir_latency_tmod); i++) { + for (j =3D 0; j < ARRAY_SIZE(ads112c14_fmod_div); j++) { + u64 fmod_Hz =3D data->fclk_Hz / ads112c14_fmod_div[j]; + u64 start_tmod =3D ads112c14_fir_latency_tmod[i][j]; + u64 step_tmod =3D ads112c14_delay_to_tmod(1); + u64 stop_tmod =3D start_tmod + ads112c14_delay_to_tmod(ADS112C14_DELAY_= MAX); + s64 start_us, step_us, stop_us; + + start_us =3D DIV_ROUND_CLOSEST_ULL(start_tmod * USEC_PER_SEC, fmod_Hz); + step_us =3D DIV_ROUND_CLOSEST_ULL(step_tmod * USEC_PER_SEC, fmod_Hz); + stop_us =3D DIV_ROUND_CLOSEST_ULL(stop_tmod * USEC_PER_SEC, fmod_Hz); + + avail =3D data->fir_settling_time_range_available[i][j]; + + iio_val_s64_decompose(start_us, &avail[0][0], &avail[0][1]); + iio_val_s64_decompose(step_us, &avail[1][0], &avail[1][1]); + iio_val_s64_decompose(stop_us, &avail[2][0], &avail[2][1]); + } + } +} + static void ads112c14_populate_tables(struct ads112c14_data *data) { u32 full_scale, fsr_bits; @@ -1999,6 +2323,7 @@ static void ads112c14_populate_tables(struct ads112c1= 4_data *data) ads112c14_populate_scale_available(data->sys_mon_chan_short_scale_availab= le, full_scale, fsr_bits); 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Fri, 04 Sep 2026 15:11:30 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:500:4324:3ccf:e2bf:d545]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4b970d1ff95sm3187113b6e.6.2026.09.04.15.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 15:11:29 -0700 (PDT) From: "David Lechner (TI)" Date: Fri, 04 Sep 2026 17:09:55 -0500 Subject: [PATCH v2 10/10] iio: ABI: add settlingtime attributes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-iio-adc-ti-ads112c14-filter-support-v2-10-f86592360658@baylibre.com> References: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> In-Reply-To: <20260904-iio-adc-ti-ads112c14-filter-support-v2-0-f86592360658@baylibre.com> To: Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Chris Hall , Patrick Edwards , Kurt Borja , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, "David Lechner (TI)" X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; 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Usually, in IIO the output data rate is 1 / sampling_frequency. There are known devices (generally ones with filtering and oversampling) where the first conversion takes longer than 1 / sampling_frequency to allow the input to settle in order to have a valid conversion result. Then, any subsequent conversions in a continuous sampling mode would be done at the regular interval defined by 1 / sampling_frequency. This attribute is intended to allow controlling that settling time duration. A device that has input chopping enabled would see this settling time on every conversion since the device setting (i.e. the input mux) changes on every conversion. Signed-off-by: David Lechner (TI) --- Documentation/ABI/testing/sysfs-bus-iio | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index a8e1cb8e7490..045589058655 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2402,6 +2402,32 @@ Description: Specifies which filter type apply to the channel. The possible values are given by the filter_type_available attribute. =20 +What: /sys/bus/iio/devices/iio:deviceX/in_resistanceY_settlingtime +What: /sys/bus/iio/devices/iio:deviceX/in_tempY_settlingtime +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_settlingtime +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_settlingtime +KernelVersion: 7.4 +Contact: linux-iio@vger.kernel.org +Description: + Set/read total settling time in seconds for a device to settle + after starting the first conversion after any settings have + changed. The data for the conversion is outputted at the end of + this time. + + Depending on the device and how it is used, this settling time + may apply to more than just the first conversion, e.g. to every + conversion in a single-shot conversion mode or when a device + setting changes after each conversion (input chopping). + +What: /sys/bus/iio/devices/iio:deviceX/in_resistanceY_settlingtime_availa= ble +What: /sys/bus/iio/devices/iio:deviceX/in_tempY_settlingtime_available +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_settlingtime_available +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_settlingtime_= available +KernelVersion: 7.4 +Contact: linux-iio@vger.kernel.org +Description: + Available settlingtime values in IIO range or list format. + What: /sys/.../events/in_proximity_thresh_either_runningperiod KernelVersion: 6.6 Contact: linux-iio@vger.kernel.org --=20 2.43.0