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This stage is fed by its own gate clock and, when that clock is disabled, a controller that starts a DMA transfer can never complete it. Allow a fourth clock entry, named "pipeline", and require it for the amlogic,t7-mmc compatible. The other controllers of this family keep the existing three clocks. Assisted-by: Claude Fable 5 Signed-off-by: Lucas Tanure --- .../bindings/mmc/amlogic,meson-gx-mmc.yaml | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yam= l b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml index 976f36de2091..12342b1d78e5 100644 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml @@ -15,6 +15,23 @@ maintainers: =20 allOf: - $ref: mmc-controller.yaml# + - if: + properties: + compatible: + contains: + const: amlogic,t7-mmc + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 =20 properties: compatible: @@ -38,13 +55,23 @@ properties: - description: card detect =20 clocks: - maxItems: 3 + minItems: 3 + items: + - description: core clock + - description: clock input 0 of the internal mux + - description: clock input 1 of the internal mux + - description: + clock of the pipeline stage inserted in the bus path between + the controller and the DRAM. Without it, the controller cannot + complete DMA transfers. =20 clock-names: + minItems: 3 items: - const: core - const: clkin0 - const: clkin1 + - const: pipeline =20 resets: maxItems: 1 --=20 2.55.0 From nobody Sat Sep 26 06:20:31 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B39F39478B for ; Thu, 3 Sep 2026 22:59:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788476372; cv=none; b=gyIAA1iVbOib5s4JpLwKpdYV1yk0KD+/hz4p/sdYp7EIMPp5dw3jXDKxYjxR6qadBvlWaIfrhn7qpnZf5BcVl2vRYZvL1SCUh8FNDAVBDhePffhZNqVWY7lWxktDIsUZ4rSZoaKuAisWHLtlaYySEfuPBZKy+dMz9INlLXXBFHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788476372; c=relaxed/simple; bh=C6Ad2AD0siK4x4/GE1JAh5GTw84tgnx8SmNQ9vLx5Ok=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Wy4NP35fSDDs8jvngzE61iToW+tESzDt8m9FQeJvg9EBlabSSg+1ZmFMEWl9ANmEbTCzpql/o1t3vSKin+oyMXDNPRRH76An0V7UoTW7KEAdvN+mlz40aqYKHy4M7cDJYbAyMn0rCeAFtBzN5ikbxE++RqycVo9yiO0prz00TxE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.com; spf=pass smtp.mailfrom=gmail.com; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-482e257a23aso298543f8f.0 for ; Thu, 03 Sep 2026 15:59:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788476367; x=1789081167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=/s6nvcJwx7Ifs5qcA8T+nQv2xmeJ2s33utca3H2YozM=; b=nMIwGmN0vL5tyWLK36kuQLq070WL5aT6u/jyn6HzFGB/xWvulTBlp1yOi/kWn3Ba2t ygmWyyzMJQaILEIs8i/DInqHauYdxmsfnFMsW6TQwtmipXfZ1HzAFJM6pR73sEYySKK5 MIXBCKGfadHvK+hXDIsh848ldSbe/N0FklczCMRrv/7V4GWOr4OjtMwkm7bhMgURayZM WsUJC9xTKd1biDBU5CRwxAcgP56AzncUqKFkHBf40HlJaYFVFdDvluFpEeTYzq4KMz5A v6cCfqnzGa1GhG8dfCSTZfmuZSX5gaOG6hQLxRVw3KwhvwPiB4HODbbFzZoLAsBtlFh8 KQYQ== X-Forwarded-Encrypted: i=1; AKwUvBwUMk2nep+KhnJIu8GbHj46v4I9plVNxbUSgqMciX2YIS0YYZDW8TfOxgOrrzrRutK52ucEVf7eFSVd49w=@vger.kernel.org X-Gm-Message-State: AFuF++l+jUiIUYKpZqUWNMR6NyGEBft58PZHEho7kyd6bbse1TN/49fJ jGz+WwTzABs5tKtIdkEVB9pAGzmX58623Nqi22EmBt+uspiTYQVed1cc X-Gm-Gg: AYBFou3cZz+6fSUe/7da/YEw0e4ZHIr9kzRp+6l3V8eRhjXp8YIjL+2LrhNo0lFFUqm Hr+JOpF6N6rZt5iPrPN/cjkDyaKzLR51qmM2PrAkxcbgEzmGiGYF8JmJvupq6ujLU0mMB6s6Zfs Q8GMM/gZbUTA61gRrKd3Mm/jDrInIpSwQz6SqzIE2mIZKx96cBx4++gFcasya9n5G1g9ymn/jyo T17EKjo/RgNkuySuNu9a8qbAKSty759fzvArrFHMKFzyyF+ncYSqdoO/CQwqRRg4dXJIyZKmk0I F+NJiogpYEVESklCQ2MQs3Bjiv7TkD1E7h3mm+3gK4qPKhmewoMd1jhJ/5TTlU+zht1VwifJE3U f55vIPvF4mi8XgKMW9ViJPqJVBLpByUEuuZdBCJMZXkpN04fcLKQPDTk8Xvv/0ybvM7Gk/LdP9n 19MqhaBEL5EPdch2w1F8Kvm3+SHMMaw07HDtcBoSUoCxR4OF5GpMu4lXp6eyz28IDhvyfrBCAlI vwWV/nfVAotPNqmStHTybqnfRnqJQFyNMvi9W0= X-Received: by 2002:a05:6000:2505:b0:485:8ad5:f965 with SMTP id ffacd0b85a97d-4858ad5ff97mr104210f8f.2.1788476366934; Thu, 03 Sep 2026 15:59:26 -0700 (PDT) Received: from threads.localdomain ([84.68.179.181]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485885c5bbdsm1686142f8f.36.2026.09.03.15.59.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2026 15:59:26 -0700 (PDT) From: Lucas Tanure To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Claude Fable 5 Subject: [PATCH 2/4] mmc: meson-gx: enable the bus pipeline clock on T7 Date: Thu, 3 Sep 2026 23:59:19 +0100 Message-ID: <20260903225921.2290441-3-tanure@linux.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260903225921.2290441-1-tanure@linux.com> References: <20260903225921.2290441-1-tanure@linux.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the T7 SoC, the bus path between the SD/eMMC controllers and the NIC_MATRIX fabric goes through a pipeline stage inserted by the hardware design to help timing closure. The stage has its own gate clock and, when that clock is disabled, a controller that starts a DMA transfer can never complete it, hanging the storage devices and, from there, the whole system. Add a dedicated match data for the amlogic,t7-mmc compatible that makes the driver claim and enable the "pipeline" clock for as long as the device is bound. The clock is deliberately not optional: the hardware cannot do DMA without it, and failing the probe with a clear error is preferable to booting and hitting an undiagnosable DMA hang later. Assisted-by: Claude Fable 5 Signed-off-by: Lucas Tanure --- drivers/mmc/host/meson-gx-mmc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mm= c.c index 694bb443d5f3..68566d7eccc7 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -52,6 +52,7 @@ #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) #define CLK_ALWAYS_ON(h) (h->data->always_on) #define CLK_IRQ_SDIO_SLEEP(h) (h->data->irq_sdio_sleep) +#define CLK_PIPELINE(h) (h->data->has_pipeline_clk) =20 #define SD_EMMC_DELAY 0x4 #define SD_EMMC_ADJUST 0x8 @@ -139,6 +140,7 @@ struct meson_mmc_data { unsigned int always_on; unsigned int adjust; unsigned int irq_sdio_sleep; + bool has_pipeline_clk; }; =20 struct sd_emmc_desc { @@ -1204,6 +1206,15 @@ static int meson_mmc_probe(struct platform_device *p= dev) if (IS_ERR(core_clk)) return PTR_ERR(core_clk); =20 + if (CLK_PIPELINE(host)) { + struct clk *pipe_clk; + + pipe_clk =3D devm_clk_get_enabled(&pdev->dev, "pipeline"); + if (IS_ERR(pipe_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(pipe_clk), + "missing pipeline clock\n"); + } + ret =3D meson_mmc_clk_init(host); if (ret) return ret; @@ -1322,12 +1333,22 @@ static const struct meson_mmc_data meson_axg_data = =3D { .irq_sdio_sleep =3D CLK_V3_IRQ_SDIO_SLEEP, }; =20 +static const struct meson_mmc_data meson_t7_data =3D { + .tx_delay_mask =3D CLK_V3_TX_DELAY_MASK, + .rx_delay_mask =3D CLK_V3_RX_DELAY_MASK, + .always_on =3D CLK_V3_ALWAYS_ON, + .adjust =3D SD_EMMC_V3_ADJUST, + .irq_sdio_sleep =3D CLK_V3_IRQ_SDIO_SLEEP, + .has_pipeline_clk =3D true, +}; + static const struct of_device_id meson_mmc_of_match[] =3D { { .compatible =3D "amlogic,meson-gx-mmc", .data =3D &meson_gx_data }, { .compatible =3D "amlogic,meson-gxbb-mmc", .data =3D &meson_gx_data }, { .compatible =3D "amlogic,meson-gxl-mmc", .data =3D &meson_gx_data }, { .compatible =3D "amlogic,meson-gxm-mmc", .data =3D &meson_gx_data }, { .compatible =3D "amlogic,meson-axg-mmc", .data =3D &meson_axg_data }, + { .compatible =3D "amlogic,t7-mmc", .data =3D &meson_t7_data }, {} }; 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Thu, 03 Sep 2026 15:59:27 -0700 (PDT) From: Lucas Tanure To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Claude Fable 5 Subject: [PATCH 3/4] arm64: dts: amlogic: t7: add the pipeline clock to the MMC controllers Date: Thu, 3 Sep 2026 23:59:20 +0100 Message-ID: <20260903225921.2290441-4-tanure@linux.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260903225921.2290441-1-tanure@linux.com> References: <20260903225921.2290441-1-tanure@linux.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SD/eMMC controllers reach the DRAM through a pipeline stage that the hardware design inserts in the bus path to the NIC_MATRIX fabric, clocked by CLKID_SYS_AMPIPE_NAND. When that clock is disabled, a controller that starts a DMA transfer can never complete it. Reference the clock from the three MMC controller nodes so the driver keeps it running, instead of relying on the clock being marked critical in the clock controller. Assisted-by: Claude Fable 5 Signed-off-by: Lucas Tanure --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index 719e111bc3dd..8f3f1c0579a0 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -762,8 +762,9 @@ sd_emmc_a: mmc@88000 { interrupts =3D ; clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_A>, <&clkc_periphs CLKID_SD_EMMC_A>, - <&scmi_clk CLKID_FCLK_DIV2>; - clock-names =3D "core", "clkin0", "clkin1"; + <&scmi_clk CLKID_FCLK_DIV2>, + <&clkc_periphs CLKID_SYS_AMPIPE_NAND>; + clock-names =3D "core", "clkin0", "clkin1", "pipeline"; resets =3D <&reset RESET_SD_EMMC_A>; assigned-clocks =3D <&clkc_periphs CLKID_SD_EMMC_A_SEL>; assigned-clock-parents =3D <&xtal>; @@ -776,8 +777,9 @@ sd_emmc_b: mmc@8a000 { interrupts =3D ; clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_B>, <&clkc_periphs CLKID_SD_EMMC_B>, - <&scmi_clk CLKID_FCLK_DIV2>; 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Thu, 03 Sep 2026 15:59:28 -0700 (PDT) Received: from threads.localdomain ([84.68.179.181]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485885c5bbdsm1686142f8f.36.2026.09.03.15.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2026 15:59:28 -0700 (PDT) From: Lucas Tanure To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Claude Fable 5 Subject: [PATCH 4/4] clk: meson: t7: don't mark sys_ampipe_nand as critical Date: Thu, 3 Sep 2026 23:59:21 +0100 Message-ID: <20260903225921.2290441-5-tanure@linux.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260903225921.2290441-1-tanure@linux.com> References: <20260903225921.2290441-1-tanure@linux.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sys_ampipe_nand clocks the pipeline stage inserted in the bus path between the SD/eMMC controllers and the NIC_MATRIX fabric. It does have identifiable consumers - the three MMC controllers - so marking it critical was the wrong tool: the clock should be referenced from the consumer nodes and claimed by the mmc driver instead. Drop the CLK_IS_CRITICAL flag and update the comment accordingly. sys_am2axi0..2 remain critical as they clock the AXI DMA bus itself and have no single identifiable consumer. This depends on the MMC controllers actually referencing the clock: the dt-bindings, mmc driver and t7 DTS changes adding the "pipeline" clock must land before this one, otherwise the boot hangs and memory corruption this clock caused are reintroduced. Fixes: 43e1705ecab9 ("clk: meson: t7: keep the memory fabric clocks running= ") Assisted-by: Claude Fable 5 Signed-off-by: Lucas Tanure --- drivers/clk/meson/t7-peripherals.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peri= pherals.c index 55d09e78593b..2f429ea86796 100644 --- a/drivers/clk/meson/t7-peripherals.c +++ b/drivers/clk/meson/t7-peripherals.c @@ -945,13 +945,13 @@ static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, = 0); static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); +static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); /* - * NOTE: sys_ampipe_nand and sys_am2axi0..2 provide the clock to the AXI b= us - * used for DMA between the peripherals and the DRAM. After the clocks are - * disabled, a device that starts a transfer cannot complete it. + * NOTE: sys_am2axi0..2 provide the clock to the AXI bus used for DMA betw= een + * the peripherals and the DRAM. After the clocks are disabled, a device t= hat + * starts a transfer cannot complete it. */ -static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, CLK_IS_CRITICAL); -static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL); --=20 2.55.0