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charset="utf-8" During early CPU initialisation, mcheck_cpu_init() invokes __mcheck_cpu_setup_timer(), which initialises the per-CPU mce_timer descriptor via timer_setup(t, mce_timer_fn, TIMER_PINNED). However, __mcheck_cpu_init_timer() is also called at runtime during sysfs reconfiguration (via mce_cpu_restart() and mce_enable_ce()), redundantly re-initialising mce_timer with timer_setup(). This introduces a race condition against asynchronous CMCI interrupts. When mce_restart() runs, it invokes mce_timer_delete_all() before broadcasting an IPI to execute mce_cpu_restart() on all CPUs. If a hardware CMCI interrupt fires on another CPU before the IPI is serviced, the CMCI handler triggers storm tracking and arms mce_timer via mce_timer_kick(true), enqueuing it in the active timer wheel. When mce_cpu_restart() runs subsequently in IPI context, __mcheck_cpu_init_timer() calls timer_setup(), which invokes __init_timer() on the already-queued timer. This clears the timer's internal list pointers (entry.next and entry.pprev) whilst it remains linked in the active timer wheel bucket, causing linked list corruption, softirq lockups, or kernel panics during timer expiration. Fix this by removing the redundant timer_setup() call from __mcheck_cpu_init_timer(). The timer is already initialised once during CPU setup; runtime restart paths only need to arm it via mce_start_timer(). Fixes: 26c3c283c5b0 ("x86: mce: Split timer init") Reported-by: sashiko-bot Cc: stable@vger.kernel.org Signed-off-by: Aaron Tomlin --- arch/x86/kernel/cpu/mce/core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ab469605fc89..765e8103b0d2 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2091,7 +2091,6 @@ static void __mcheck_cpu_init_timer(void) { struct timer_list *t =3D this_cpu_ptr(&mce_timer); =20 - timer_setup(t, mce_timer_fn, TIMER_PINNED); mce_start_timer(t); } =20 --=20 2.55.0 From nobody Sat Sep 26 06:27:47 2026 Received: from LO2P265CU024.outbound.protection.outlook.com (mail-uksouthazon11021132.outbound.protection.outlook.com [52.101.95.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3421950AC0D; Thu, 3 Sep 2026 19:42:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" cmci_storm_begin() and cmci_storm_end() modify the per-CPU bitmap mce_poll_banks using non-atomic __set_bit() and __clear_bit(). While mce_poll_banks is a per-CPU variable, cmci_storm_end() runs in timer softirq context with local hardirqs enabled, whereas cmci_storm_begin() can be invoked from CMCI hardirq context (via intel_threshold_interrupt()). If a CMCI hardirq fires while a timer softirq is midway through a non-atomic read-modify-write operation on mce_poll_banks, the hardirq's bit update will be overwritten and lost when the softirq resumes. If a bank entering storm mode loses its bit in mce_poll_banks, it will neither generate interrupts (as its hardware threshold is bumped to CMCI_STORM_THRESHOLD) nor be polled by mce_timer_fn(). Consequently, the bank remains unpolled and its error telemetry is permanently lost until the next reboot. Fix this by switching to atomic set_bit() and clear_bit() operations in cmci_storm_begin() and cmci_storm_end(). Fixes: 7eae17c4add5 ("x86/mce: Add per-bank CMCI storm mitigation") Cc: stable@vger.kernel.org Signed-off-by: Aaron Tomlin --- arch/x86/kernel/cpu/mce/threshold.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/= threshold.c index 6c370d5af5bd..af8346f06318 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -86,7 +86,7 @@ void cmci_storm_begin(unsigned int bank) { struct mca_storm_desc *storm =3D this_cpu_ptr(&storm_desc); =20 - __set_bit(bank, this_cpu_ptr(mce_poll_banks)); + set_bit(bank, this_cpu_ptr(mce_poll_banks)); storm->banks[bank].in_storm_mode =3D true; =20 /* @@ -102,7 +102,7 @@ void cmci_storm_end(unsigned int bank) struct mca_storm_desc *storm =3D this_cpu_ptr(&storm_desc); =20 if (!mce_flags.amd_threshold) - __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); + clear_bit(bank, this_cpu_ptr(mce_poll_banks)); storm->banks[bank].history =3D 0; storm->banks[bank].in_storm_mode =3D false; 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charset="utf-8" On x86 platforms, the Machine Check Architecture (MCA) subsystem arms a per-CPU, pinned standard timer (mce_timer) to periodically poll hardware banks for "silent" corrected machine check errors. Because mce_timer is pinned to the local CPU via TIMER_PINNED, the timer core cannot migrate its expiration to a housekeeping CPU, causing periodic latency jitter on isolated cores. On Intel systems supporting Corrected Machine Check Interrupt (CMCI), hardware generates an interrupt for banks with CMCI enabled, clearing their respective bits in mce_poll_banks. However, for banks where MCI_CTL2_CMCI_EN does not stick (such as the Power Control Unit bank), Linux historically assumed software polling was required and left the bank flagged in mce_poll_banks. Per the Intel SDM (Vol 3B, Section 18.5 "Corrected Machine Check Error Interrupt"), if bit 30 of IA32_MCi_CTL2 is zero, no CMCI is available for that bank and no corrected or Uncorrected No Action Required (UCNA) errors will be reported on that bank. Therefore, polling such banks is redundant and wasteful. Clear non-CMCI banks from mce_poll_banks in cmci_claim_bank() on CMCI-capable CPUs, and amend should_enable_timer() to: 1. Check bitmap_empty(mce_poll_banks) bounded to the number of implemented banks (this_cpu_read(mce_num_banks)) so that mce_timer is never armed when no banks require polling. 2. Pin the MCE polling timer to a HK_TYPE_TIMER housekeeping CPU, sparing isolated nohz_full cores from periodic wakeups on systems requiring mce_poll_banks polling. On systems requiring software polling such as legacy platforms lacking CMCI or when booted with mce=3Dno_cmci, mce_timer is restricted to housekeeping CPUs. While this intentionally leaves core-private banks (e.g. L1/L2 caches) on isolated cores exempt from periodic polling to guarantee zero timer jitter, housekeeping CPUs continue to harvest telemetry from their own banks as well as shared package-level resources. Synchronous (#MC) exceptions on isolated cores remain entirely unaffected. Suggested-by: Tony Luck Signed-off-by: Aaron Tomlin --- arch/x86/kernel/cpu/mce/core.c | 7 +++++++ arch/x86/kernel/cpu/mce/intel.c | 13 +++++++------ arch/x86/kernel/cpu/mce/internal.h | 2 -- arch/x86/kernel/cpu/mce/threshold.c | 4 ---- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 765e8103b0d2..b01ad1a9b455 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -1759,6 +1760,12 @@ void (*mc_poll_banks)(void) =3D mc_poll_banks_defaul= t; =20 static bool should_enable_timer(unsigned long iv) { + if (bitmap_empty(this_cpu_ptr(mce_poll_banks), this_cpu_read(mce_num_bank= s))) + return false; + + if (!housekeeping_cpu(smp_processor_id(), HK_TYPE_TIMER)) + return false; + return !mca_cfg.ignore_ce && iv; } =20 diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index 4655223ba560..d264ec8688bb 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -229,16 +229,17 @@ static u64 cmci_pick_threshold(u64 val, int *bios_zer= o_thresh) */ static void cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *= bios_wrong_thresh) { - struct mca_storm_desc *storm =3D this_cpu_ptr(&storm_desc); - val |=3D MCI_CTL2_CMCI_EN; wrmsrq(MSR_IA32_MCx_CTL2(bank), val); rdmsrq(MSR_IA32_MCx_CTL2(bank), val); =20 - /* If the enable bit did not stick, this bank should be polled. */ + /* + * If the enable bit did not stick, this bank does not support CMCI + * and no corrected or UCNA errors will be reported on this bank + * (SDM Vol 3B 18.5). No polling is needed. + */ if (!(val & MCI_CTL2_CMCI_EN)) { - WARN_ON(!test_bit(bank, this_cpu_ptr(mce_poll_banks))); - storm->banks[bank].poll_only =3D true; + clear_bit(bank, this_cpu_ptr(mce_poll_banks)); return; } =20 @@ -250,7 +251,7 @@ static void cmci_claim_bank(int bank, u64 val, int bios= _zero_thresh, int *bios_w mce_inherit_storm(bank); cmci_storm_begin(bank); } else { - __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); + clear_bit(bank, this_cpu_ptr(mce_poll_banks)); } =20 /* diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index a31cf984619c..32ae574d2ad5 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -84,13 +84,11 @@ static inline u32 mce_get_apei_thr_limit(void) { retur= n 0; } * * timestamp: Last time (in jiffies) that the bank was polled. * in_storm_mode: Is this bank in storm mode? - * poll_only: Bank does not support CMCI, skip storm tracking. */ struct storm_bank { u64 history; u64 timestamp; bool in_storm_mode; - bool poll_only; }; =20 #define NUM_HISTORY_BITS (sizeof(u64) * BITS_PER_BYTE) diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/= threshold.c index af8346f06318..af8936262613 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -118,10 +118,6 @@ void mce_track_storm(struct mce *mce) unsigned int shift =3D 1; u64 history =3D 0; =20 - /* No tracking needed for banks that do not support CMCI */ - if (storm->banks[mce->bank].poll_only) - return; - /* * When a bank is in storm mode it is polled once per second and * the history mask will record about the last minute of poll results. --=20 2.55.0