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charset="utf-8" dwc3_qcom_resume() disables wakeup interrupts before re-enabling clocks, then re-enables them again once resume completes. If clk_bulk_prepare_enable() fails partway through, the function returns early without re-enabling the interrupts that were just disabled, leaving host-mode wakeup interrupts masked after a failed resume. Jump to a common cleanup path that re-enables the interrupts before returning the error, mirroring the success path. Signed-off-by: Faisal Hassan Acked-by: Thinh Nguyen --- drivers/usb/dwc3/dwc3-qcom.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index ac68b4218b56..49698a31b2f4 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -382,7 +382,7 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, boo= l wakeup) =20 ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); if (ret < 0) - return ret; + goto enable_irq; =20 ret =3D dwc3_qcom_interconnect_enable(qcom); if (ret) @@ -398,6 +398,16 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bo= ol wakeup) qcom->is_suspended =3D false; =20 return 0; + +enable_irq: + /* + * Re-enable interrupts if they were disabled earlier, so a failed + * resume doesn't leave wakeup interrupts masked. + */ + if (dwc3_qcom_is_host(qcom) && wakeup) + dwc3_qcom_enable_interrupts(qcom); + + return ret; } =20 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) --=20 2.34.1 From nobody Sat Sep 26 07:16:27 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54C124E3EC4 for ; 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charset="utf-8" The dwc3_qcom_suspend() and dwc3_qcom_resume() functions handle both system PM and runtime PM paths but cannot differentiate between them, preventing distinct power management strategies. Refactor suspend/resume functions to accept pm_message_t instead of boolean wakeup flags. Use PMSG_IS_AUTO() to identify runtime PM (PMSG_AUTO_SUSPEND/RESUME) versus system PM (PMSG_SUSPEND/RESUME) paths. Preserve existing wakeup behavior: always enable wakeup for runtime suspend, check device_may_wakeup() for system suspend. Follow dwc3/core.c pattern to enable future per-path strategies like differentiated power states. Co-developed-by: Sriram Dash Signed-off-by: Sriram Dash Signed-off-by: Faisal Hassan Acked-by: Thinh Nguyen --- drivers/usb/dwc3/dwc3-qcom.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 49698a31b2f4..6d25f81800a7 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -335,14 +335,24 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_q= com *qcom) dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); } =20 -static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, pm_message_t msg) { u32 val; int i, ret; + bool wakeup; =20 if (qcom->is_suspended) return 0; =20 + /* + * For runtime suspend, always enable wakeup. + * For system suspend, check device wakeup capability. + */ + if (PMSG_IS_AUTO(msg)) + wakeup =3D true; + else + wakeup =3D device_may_wakeup(qcom->dev); + for (i =3D 0; i < qcom->num_ports; i++) { val =3D readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]); if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) @@ -369,14 +379,24 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, = bool wakeup) return 0; } =20 -static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) +static int dwc3_qcom_resume(struct dwc3_qcom *qcom, pm_message_t msg) { int ret; int i; + bool wakeup; =20 if (!qcom->is_suspended) return 0; =20 + /* + * For runtime resume, always assume wakeup was enabled. + * For system resume, check device wakeup capability. + */ + if (PMSG_IS_AUTO(msg)) + wakeup =3D true; + else + wakeup =3D device_may_wakeup(qcom->dev); + if (dwc3_qcom_is_host(qcom) && wakeup) dwc3_qcom_disable_interrupts(qcom); =20 @@ -759,14 +779,13 @@ static int dwc3_qcom_pm_suspend(struct device *dev) { struct dwc3 *dwc =3D dev_get_drvdata(dev); struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); - bool wakeup =3D device_may_wakeup(dev); int ret; =20 ret =3D dwc3_pm_suspend(&qcom->dwc); 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charset="utf-8" On Qualcomm automotive SoC sa8255p, platform resources like clocks, interconnects, resets, regulators and GDSC are abstracted and managed collectively by firmware. Add a new binding file for firmware-managed USB controllers where access to these resources is exposed as two power domains: - Power domain: Controls power supply (GDSC) to the USB controller - Bus domain: Controls clocks and interconnects for data transfer The binding makes power-domains and power-domain-names properties mandatory for firmware-managed platforms, while excluding the clocks property since clocks are managed through the power domains. Co-developed-by: Sriram Dash Signed-off-by: Sriram Dash Signed-off-by: Faisal Hassan --- .../bindings/usb/qcom,sa8255p-dwc3.yaml | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3= .yaml diff --git a/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml b= /Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml new file mode 100644 index 000000000000..c6db7bcf4981 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,sa8255p-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8255P USB3 Controller with Firmware-Managed Resources + +maintainers: + - Wesley Cheng + - Faisal Hassan + +description: + USB controller on Qualcomm SA8255P automotive SoC where platform resourc= es + such as clocks, interconnects, resets, regulators and the GDSC are + abstracted and managed collectively by firmware through SCMI (System + Control and Management Interface). + + Access to these firmware-managed resources is exposed as two power + domains, one gating the power supply (GDSC) to the controller, and one + gating the clocks and interconnects used for data transfer. + +properties: + compatible: + const: qcom,sa8255p-dwc3 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 6 + + interrupt-names: + minItems: 1 + maxItems: 6 + + power-domains: + description: | + Power domains are provided by SCMI (System Control and Management + Interface). See Documentation/devicetree/bindings/firmware/arm,scmi.= yaml + for details. + + Exactly two power domains must be specified: + - "power": controls power supply (GDSC) to the USB controller + - "bus": controls clocks and interconnects used for data transfer + minItems: 2 + maxItems: 2 + + power-domain-names: + description: Names for the power domains specified in the power-domain= s property. + items: + - const: power + - const: bus + + resets: + description: | + Reset provided by SCMI firmware. See + Documentation/devicetree/bindings/firmware/arm,scmi.yaml for details. + maxItems: 1 + + iommus: + maxItems: 1 + + phys: + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + maxItems: 2 + + # Firmware-managed platforms do not use direct clock/interconnect control + clocks: false + clock-names: false + interconnects: false + interconnect-names: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - power-domains + - power-domain-names + - resets + +allOf: + - $ref: snps,dwc3-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + usb@a800000 { + compatible =3D "qcom,sa8255p-dwc3"; + reg =3D <0x0a800000 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 7 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; 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charset="utf-8" When the USB controller loses power during PM suspend (as occurs on targets like SA8255P that fully power off the controller), it generates a Host Controller Error (HCE) on resume requiring full reinitialization. This is handled by the XHCI_RESET_ON_RESUME quirk (introduced upstream in 8b328f8002bc). Read the "xhci-reset-on-resume-quirk" device property to set XHCI_RESET_ON_RESUME. This allows parent drivers (e.g., dwc3) to enable the quirk via software nodes. Co-developed-by: Sriram Dash Signed-off-by: Sriram Dash Signed-off-by: Faisal Hassan --- drivers/usb/host/xhci-plat.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index 074d9c731639..7df2947d13dc 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -277,6 +277,9 @@ int xhci_plat_probe(struct platform_device *pdev, struc= t device *sysdev, const s if (device_property_read_bool(tmpdev, "xhci-skip-phy-init-quirk")) xhci->quirks |=3D XHCI_SKIP_PHY_INIT; =20 + if (device_property_read_bool(tmpdev, "xhci-reset-on-resume-quirk")) + xhci->quirks |=3D XHCI_RESET_ON_RESUME; + device_property_read_u32(tmpdev, "imod-interval-ns", &xhci->imod_interval); device_property_read_u16(tmpdev, "num-hc-interrupters", --=20 2.34.1 From nobody Sat Sep 26 07:16:27 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED32A4EBAD6 for ; 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charset="utf-8" On platforms where the USB controller loses power during system suspend, like SA8255P, resume triggers a Host Controller Error requiring full reinitialization. The xhci driver supports XHCI_RESET_ON_RESUME to handle this, but dwc3 previously lacked platform-specific quirk configuration. Add a device property "xhci-reset-on-resume" that enables this quirk for controllers needing complete reinitialization after power loss during suspend. Let dwc3 manage the quirk for the usb controller using software properties. Co-developed-by: Sriram Dash Signed-off-by: Sriram Dash Signed-off-by: Faisal Hassan --- drivers/usb/dwc3/core.c | 4 ++++ drivers/usb/dwc3/core.h | 5 +++++ drivers/usb/dwc3/host.c | 5 ++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index fd5c2cd36c59..eb6ffd5148a7 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1712,6 +1712,10 @@ static void dwc3_get_software_properties(struct dwc3= *dwc, &gsbuscfg0_reqinfo); if (!ret) dwc->gsbuscfg0_reqinfo =3D gsbuscfg0_reqinfo; + + if (!dwc->xhci_reset_on_resume && + device_property_read_bool(tmpdev, "xhci-reset-on-resume")) + dwc->xhci_reset_on_resume =3D true; } } =20 diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 608daeb7ef10..0ff23eb217bc 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1172,6 +1172,10 @@ struct dwc3_glue_ops { * @suspended: set to track suspend event due to U3/L2. * @susphy_state: state of DWC3_GUSB2PHYCFG_SUSPHY + DWC3_GUSB3PIPECTL_SUS= PHY * before PM suspend. + * @xhci_reset_on_resume: Enable XHCI_RESET_ON_RESUME quirk for the xHCI + * host controller. Set to true for platforms where + * the USB controller loses power during system suspend, + * requiring complete reinitialization on resume. * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. * @max_cfg_eps: current max number of IN eps used across all USB configs. @@ -1420,6 +1424,7 @@ struct dwc3 { unsigned wakeup_configured:1; unsigned suspended:1; unsigned susphy_state:1; + unsigned xhci_reset_on_resume:1; =20 u16 imod_interval; =20 diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index 96b588bd08cd..2170fcafc889 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -129,7 +129,7 @@ static int dwc3_host_get_irq(struct dwc3 *dwc) =20 int dwc3_host_init(struct dwc3 *dwc) { - struct property_entry props[6]; + struct property_entry props[7]; struct platform_device *xhci; int ret, irq; int prop_idx =3D 0; @@ -173,6 +173,9 @@ int dwc3_host_init(struct dwc3 *dwc) if (dwc->usb2_lpm_disable) props[prop_idx++] =3D PROPERTY_ENTRY_BOOL("usb2-lpm-disable"); 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charset="utf-8" During APPS Suspend, the clock controller unit disables all clocks to the CPU and subsystems, causing the controller to enter the Power-On Reset (POR) state. This results in the loss of Qscratch programming. Upon APPS Resume, the USB controller does not have the proper PIPE_UTMI_CLK_SEL or VBUS_VALID. Hence, if only the High-Speed PHY is used for a controller capable of SuperSpeed operations, the controller will assume it should use the USB3 PHY and not the HS PHY as configured before APPS Suspend. This behavior disrupts the normal operation of the USB controller. Similarly, if the controller was operating in device mode prior to APPS suspend, and VBUS_VALID signal is not set after APPS resume, this will cause the PHYs to transition into the suspend state. This behavior disrupts the normal operation of the USB controller. Address the issues by ensuring that the PIPE_UTMI_CLK_SEL and VBUS_VALID are handled properly after the system resumes from APPS Suspend. This is crucial for maintaining the correct operational state of the USB controller and preventing unintended suspensions of the PHYs. Also, as the controller is starting from POR state, make sure the controller Reset is performed. Co-developed-by: Sriram Dash Signed-off-by: Sriram Dash Signed-off-by: Faisal Hassan --- drivers/usb/dwc3/dwc3-qcom.c | 128 +++++++++++++++++++++++++++-------- 1 file changed, 100 insertions(+), 28 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 6d25f81800a7..e58a9ca23b00 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -68,6 +68,10 @@ struct dwc3_qcom_port { enum usb_device_speed usb2_speed; }; =20 +struct dwc3_qcom_priv_data { + bool broken_suspend; +}; + struct dwc3_qcom { struct device *dev; void __iomem *qscratch_base; @@ -85,6 +89,13 @@ struct dwc3_qcom { struct icc_path *icc_path_apps; =20 enum usb_role current_role; + + bool broken_suspend; + bool ignore_pipe_clk; +}; + +static const struct dwc3_qcom_priv_data sa8255p_dwc3_qcom_priv_data =3D { + .broken_suspend =3D true, }; =20 #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc) @@ -335,6 +346,23 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qc= om *qcom) dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); } =20 +static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) +{ + /* Configure dwc3 to use UTMI clock as PIPE clock not present */ + dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, + PIPE_UTMI_CLK_DIS); + + usleep_range(100, 1000); + + dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, + PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); + + usleep_range(100, 1000); + + dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, + PIPE_UTMI_CLK_DIS); +} + static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, pm_message_t msg) { u32 val; @@ -388,6 +416,28 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, pm= _message_t msg) if (!qcom->is_suspended) return 0; =20 + if (qcom->broken_suspend && !PMSG_IS_AUTO(msg)) { + /* + * Only system suspend fully powers off the controller and + * puts it into POR state. Runtime suspend does not, so skip + * the reset on runtime resume to avoid needlessly clobbering + * state that was never lost. + */ + ret =3D reset_control_assert(qcom->resets); + if (ret) { + dev_err(qcom->dev, "failed to assert resets, err=3D%d\n", ret); + return ret; + } + + usleep_range(10, 1000); + + ret =3D reset_control_deassert(qcom->resets); + if (ret) { + dev_err(qcom->dev, "failed to deassert resets, err=3D%d\n", ret); + return ret; + } + } + /* * For runtime resume, always assume wakeup was enabled. * For system resume, check device wakeup capability. @@ -415,6 +465,14 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, pm= _message_t msg) PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); } =20 + if (qcom->broken_suspend) { + if (!wakeup && qcom->ignore_pipe_clk) + dwc3_qcom_select_utmi_clk(qcom); + /* Make sure vbus valid is set for PHYs after PM resume */ + if (!(dwc3_qcom_is_host(qcom) && wakeup)) + dwc3_qcom_vbus_override_enable(qcom, true); + } + qcom->is_suspended =3D false; =20 return 0; @@ -449,23 +507,6 @@ static irqreturn_t qcom_dwc3_resume_irq(int irq, void = *data) return IRQ_HANDLED; } =20 -static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) -{ - /* Configure dwc3 to use UTMI clock as PIPE clock not present */ - dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, - PIPE_UTMI_CLK_DIS); - - usleep_range(100, 1000); - - dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, - PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); - - usleep_range(100, 1000); - - dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, - PIPE_UTMI_CLK_DIS); -} - static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, const char *name) { @@ -637,6 +678,15 @@ static struct dwc3_glue_ops dwc3_qcom_glue_ops =3D { .pre_run_stop =3D dwc3_qcom_run_stop_notifier, }; =20 +static const struct property_entry dwc3_qcom_props_broken_suspend[] =3D { + PROPERTY_ENTRY_BOOL("xhci-reset-on-resume"), + { } +}; + +static const struct software_node dwc3_qcom_swnode_prop_broken_suspend =3D= { + .properties =3D dwc3_qcom_props_broken_suspend, +}; + static int dwc3_qcom_probe(struct platform_device *pdev) { struct dwc3_probe_data probe_data =3D {}; @@ -644,8 +694,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev) struct dwc3_qcom *qcom; struct resource res; struct resource *r; + const struct dwc3_qcom_priv_data *priv_data; int ret; - bool ignore_pipe_clk; bool wakeup_source; =20 qcom =3D devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); @@ -654,21 +704,33 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) =20 qcom->dev =3D &pdev->dev; =20 + priv_data =3D of_device_get_match_data(dev); + if (priv_data && priv_data->broken_suspend) { + ret =3D device_add_software_node(&pdev->dev, + &dwc3_qcom_swnode_prop_broken_suspend); + if (ret) + return ret; + qcom->broken_suspend =3D priv_data->broken_suspend; + } + qcom->resets =3D devm_reset_control_array_get_optional_exclusive(dev); if (IS_ERR(qcom->resets)) { - return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), - "failed to get resets\n"); + ret =3D dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), + "failed to get resets\n"); + goto err_remove_swnode; } =20 ret =3D devm_clk_bulk_get_all(&pdev->dev, &qcom->clks); - if (ret < 0) - return dev_err_probe(dev, ret, "failed to get clocks\n"); + if (ret < 0) { + dev_err_probe(dev, ret, "failed to get clocks\n"); + goto err_remove_swnode; + } qcom->num_clocks =3D ret; =20 ret =3D reset_control_assert(qcom->resets); if (ret) { dev_err(&pdev->dev, "failed to assert resets, err=3D%d\n", ret); - return ret; + goto err_remove_swnode; } =20 usleep_range(10, 1000); @@ -676,12 +738,12 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) ret =3D reset_control_deassert(qcom->resets); if (ret) { dev_err(&pdev->dev, "failed to deassert resets, err=3D%d\n", ret); - return ret; + goto err_remove_swnode; } =20 ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); if (ret < 0) - return ret; + goto err_remove_swnode; =20 r =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!r) { @@ -708,9 +770,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev) * Disable pipe_clk requirement if specified. Used when dwc3 * operates without SSPHY and only HS/FS/LS modes are supported. */ - ignore_pipe_clk =3D device_property_read_bool(dev, - "qcom,select-utmi-as-pipe-clk"); - if (ignore_pipe_clk) + qcom->ignore_pipe_clk =3D device_property_read_bool(dev, + "qcom,select-utmi-as-pipe-clk"); + if (qcom->ignore_pipe_clk) dwc3_qcom_select_utmi_clk(qcom); =20 qcom->mode =3D usb_get_dr_mode(dev); @@ -757,6 +819,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev) clk_disable: clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); =20 +err_remove_swnode: + if (qcom->broken_suspend) + device_remove_software_node(&pdev->dev); return ret; } =20 @@ -773,6 +838,9 @@ static void dwc3_qcom_remove(struct platform_device *pd= ev) dwc3_qcom_interconnect_exit(qcom); =20 pm_runtime_put_noidle(qcom->dev); + + if (qcom->broken_suspend) + device_remove_software_node(&pdev->dev); } =20 static int dwc3_qcom_pm_suspend(struct device *dev) @@ -867,6 +935,10 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = =3D { }; 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charset="utf-8" Add support for firmware-managed resource handling in the Qualcomm DWC3 USB controller driver. On platforms such as SA8255P, controller resources are abstracted and managed collectively by firmware, and are exposed to Linux through SCMI-backed power domains. On SA8255P, resources such as clocks, regulators, resets, TLMM and interconnects are controlled by firmware. The driver communicates with firmware through two power domains: - "power": controls power supply (GDSC) to the USB controller - "bus": controls clocks and interconnects used for data transfer. Register accesses through the controller require the "power" domain to be enabled. The two domains are voted on and off directly from the PM callbacks through dwc3_qcom_domains_get() and dwc3_qcom_domains_put(). Runtime PM usage counting keeps each domain enabled for as long as it is required; the driver does not attempt to track or infer any aggregate device power state, nor does it assume what state firmware or the bootloader left the domains in before probe. Runtime suspend/resume vote only the "bus" domain, since the "power" domain must remain enabled for hardware accesses that can occur while runtime suspended. System suspend/resume vote both domains. The domains are attached with PD_FLAG_NO_DEV_LINK because runtime suspend and system suspend require different supplier states. Runtime suspend releases only the "bus" domain while retaining the "power" domain, whereas system suspend releases both domains. Ordinary device-links would couple both suppliers to the same consumer runtime PM state and therefore cannot express the required policy. The driver consequently manages the runtime PM references for the attached domains explicitly. These votes are taken during probe, remove, suspend and resume, enabling coordinated management of grouped resources according to the controller's operational requirements. Enable firmware-managed resource handling for the "qcom,sa8255p-dwc3" compatible while maintaining backward compatibility with existing platforms that use direct resource control. While here, harden dwc3_qcom_remove() and the probe error-unwind path: disable runtime PM before tearing down so a concurrent PM operation can't race the teardown, assert the controller reset and mark the device runtime-suspended once cleanup completes, and keep going with best-effort cleanup if the initial pm_runtime_resume_and_get() in remove() fails instead of leaking. These paths are shared by every qcom,snps-dwc3 platform, not only the firmware-managed ones added here: the added reset_control_assert() and pm_runtime_set_suspended() calls are unconditional. They are safe for existing platforms because remove() already fully powers the controller down and probe failure already leaves it unclocked, so putting the (shared) reset line into assert and marking the device suspended only makes the visible runtime PM state match reality more precisely than before. Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Co-developed-by: Sriram Dash Signed-off-by: Sriram Dash Signed-off-by: Faisal Hassan --- drivers/usb/dwc3/dwc3-qcom.c | 309 +++++++++++++++++++++++++++++++---- 1 file changed, 281 insertions(+), 28 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index e58a9ca23b00..7139eadbfb1e 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -70,6 +71,7 @@ struct dwc3_qcom_port { =20 struct dwc3_qcom_priv_data { bool broken_suspend; + bool fw_managed; }; =20 struct dwc3_qcom { @@ -92,14 +94,147 @@ struct dwc3_qcom { =20 bool broken_suspend; bool ignore_pipe_clk; + + bool fw_managed; + struct dev_pm_domain_list *pd_list; }; =20 static const struct dwc3_qcom_priv_data sa8255p_dwc3_qcom_priv_data =3D { .broken_suspend =3D true, + .fw_managed =3D true, }; =20 #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc) =20 +/* + * Firmware-managed resource handling + * + * On platforms where clocks, interconnects, resets and the GDSC for the U= SB + * controller are owned and sequenced by firmware, access to those resourc= es + * is exposed to Linux as two power domains: + * - pd_list->pd_devs[0] ("power"): the GDSC supplying the controller + * - pd_list->pd_devs[1] ("bus"): the clocks and interconnects used for da= ta + * transfer, which additionally require "power" to be on for register + * accesses to succeed + * + * Reset signals are controlled separately through the reset control frame= work + * during probe/remove. + * + * The two domains are voted on/off directly from each PM callback that ne= eds + * them; there's no attempt to track or name an aggregate device power sta= te, + * since the actual state lives in firmware and is queried by voting throu= gh + * runtime PM, not by mirroring it in the driver. + */ + +/** + * dwc3_qcom_domain_detach() - Detach power domains + * @qcom: Pointer to the dwc3_qcom structure + * + * Detaches all power domains. + */ +static void dwc3_qcom_domain_detach(struct dwc3_qcom *qcom) +{ + if (qcom->pd_list) + dev_pm_domain_detach_list(qcom->pd_list); +} + +/** + * dwc3_qcom_domain_attach() - Attach power domains + * @qcom: Pointer to the dwc3_qcom structure + * + * Attaches power domains for firmware managed resource handling. + * Returns 0 on success, negative error code on failure. + */ +static int dwc3_qcom_domain_attach(struct dwc3_qcom *qcom) +{ + struct dev_pm_domain_attach_data pd_data =3D { + .pd_flags =3D PD_FLAG_NO_DEV_LINK, + .pd_names =3D (const char*[]) { "power", "bus" }, + .num_pd_names =3D 2, + }; + struct device *dev =3D qcom->dev; + int ret; + + ret =3D dev_pm_domain_attach_list(dev, &pd_data, &qcom->pd_list); + if (ret !=3D pd_data.num_pd_names) { + dev_err(dev, "domain attach failed (%d)\n", ret); + return ret < 0 ? ret : -ENODEV; + } + + return 0; +} + +/** + * dwc3_qcom_domains_get() - Vote the firmware-managed domains on + * @qcom: Pointer to the dwc3_qcom structure + * @bus_only: If true, leave the power domain untouched and only vote bus + * + * Votes runtime PM "on" for the domains this call is responsible for. Each + * call has exactly one matching dwc3_qcom_domains_put() call with the same + * @bus_only value on the corresponding disable path; runtime PM's own usa= ge + * counting is what keeps power on for as long as bus needs it, without the + * driver tracking or assuming any prior domain state itself. + * Returns 0 on success, negative error code on failure. + */ +static int dwc3_qcom_domains_get(struct dwc3_qcom *qcom, bool bus_only) +{ + struct device *power_dev =3D qcom->pd_list->pd_devs[0]; + struct device *bus_dev =3D qcom->pd_list->pd_devs[1]; + int ret; + + if (!bus_only) { + ret =3D pm_runtime_resume_and_get(power_dev); + if (ret) { + dev_err(qcom->dev, "failed to enable power domain: %d\n", ret); + return ret; + } + } + + ret =3D pm_runtime_resume_and_get(bus_dev); + if (ret) { + dev_err(qcom->dev, "failed to enable bus domain: %d\n", ret); + if (!bus_only) + pm_runtime_put_sync(power_dev); + return ret; + } + + return 0; +} + +/** + * dwc3_qcom_domains_put() - Vote the firmware-managed domains off + * @qcom: Pointer to the dwc3_qcom structure + * @bus_only: If true, leave the power domain untouched and only vote bus + * + * Releases the votes taken by the matching dwc3_qcom_domains_get() call. + * Bus is released before power since bus register accesses require power + * to still be on. + * Returns 0 on success, negative error code on failure. + */ +static int dwc3_qcom_domains_put(struct dwc3_qcom *qcom, bool bus_only) +{ + struct device *power_dev =3D qcom->pd_list->pd_devs[0]; + struct device *bus_dev =3D qcom->pd_list->pd_devs[1]; + int ret; + + ret =3D pm_runtime_put_sync(bus_dev); + if (ret < 0) { + dev_err(qcom->dev, "failed to disable bus domain: %d\n", ret); + return ret; + } + + if (bus_only) + return 0; + + ret =3D pm_runtime_put_sync(power_dev); + if (ret < 0) { + dev_err(qcom->dev, "failed to disable power domain: %d\n", ret); + return ret; + } + + return 0; +} + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 v= al) { u32 reg; @@ -386,11 +521,23 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, = pm_message_t msg) if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); } - clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); =20 - ret =3D dwc3_qcom_interconnect_disable(qcom); - if (ret) - dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); + if (!qcom->fw_managed) { + clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); + + ret =3D dwc3_qcom_interconnect_disable(qcom); + if (ret) + dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); + } else { + /* + * Runtime suspend only needs to drop the bus domain; power + * stays voted on so register accesses remain possible for + * whatever briefly resumes it. System suspend drops both. + */ + ret =3D dwc3_qcom_domains_put(qcom, PMSG_IS_AUTO(msg)); + if (ret) + return ret; + } =20 /* * The role is stable during suspend as role switching is done from a @@ -450,13 +597,25 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, p= m_message_t msg) if (dwc3_qcom_is_host(qcom) && wakeup) dwc3_qcom_disable_interrupts(qcom); =20 - ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); - if (ret < 0) - goto enable_irq; + if (!qcom->fw_managed) { + ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); + if (ret < 0) + goto enable_irq; =20 - ret =3D dwc3_qcom_interconnect_enable(qcom); - if (ret) - dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); + ret =3D dwc3_qcom_interconnect_enable(qcom); + if (ret) + dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); + } else { + /* + * Runtime resume only needs to re-vote bus (power was left + * on across runtime suspend). System resume votes both. + */ + ret =3D dwc3_qcom_domains_get(qcom, PMSG_IS_AUTO(msg)); + if (ret) { + dev_err(qcom->dev, "failed to enable power domains: %d\n", ret); + goto enable_irq; + } + } =20 /* Clear existing events from PHY related to L2 in/out */ for (i =3D 0; i < qcom->num_ports; i++) { @@ -713,6 +872,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev) qcom->broken_suspend =3D priv_data->broken_suspend; } =20 + if (priv_data && priv_data->fw_managed) + qcom->fw_managed =3D priv_data->fw_managed; + qcom->resets =3D devm_reset_control_array_get_optional_exclusive(dev); if (IS_ERR(qcom->resets)) { ret =3D dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), @@ -720,12 +882,14 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) goto err_remove_swnode; } =20 - ret =3D devm_clk_bulk_get_all(&pdev->dev, &qcom->clks); - if (ret < 0) { - dev_err_probe(dev, ret, "failed to get clocks\n"); - goto err_remove_swnode; + if (!qcom->fw_managed) { + ret =3D devm_clk_bulk_get_all(&pdev->dev, &qcom->clks); + if (ret < 0) { + dev_err_probe(dev, ret, "failed to get clocks\n"); + goto err_remove_swnode; + } + qcom->num_clocks =3D ret; } - qcom->num_clocks =3D ret; =20 ret =3D reset_control_assert(qcom->resets); if (ret) { @@ -741,9 +905,31 @@ static int dwc3_qcom_probe(struct platform_device *pde= v) goto err_remove_swnode; } =20 - ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); - if (ret < 0) - goto err_remove_swnode; + if (!qcom->fw_managed) { + ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); + if (ret < 0) + goto err_remove_swnode; + } else { + ret =3D dwc3_qcom_domain_attach(qcom); + if (ret) { + dev_err(dev, "Failed to attach domains (%d).\n", ret); + goto err_remove_swnode; + } + + /* + * Vote both domains on for the remainder of probe. This is a + * plain runtime PM get, not an assumption about what state + * firmware or the bootloader left the domains in beforehand; + * pm_runtime_resume_and_get() is correct regardless of that + * prior state. + */ + ret =3D dwc3_qcom_domains_get(qcom, false /* bus_only */); + if (ret) { + dev_err(dev, "Failed to enable power domains (%d)\n", ret); + dwc3_qcom_domain_detach(qcom); + goto err_remove_swnode; + } + } =20 r =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!r) { @@ -803,9 +989,15 @@ static int dwc3_qcom_probe(struct platform_device *pde= v) goto clk_disable; } =20 - ret =3D dwc3_qcom_interconnect_init(qcom); - if (ret) - goto remove_core; + /* + * Initialize interconnect paths only for non-firmware managed resource h= andling. + * In firmware managed resource handling, interconnects are controlled by= power domains. + */ + if (!qcom->fw_managed) { + ret =3D dwc3_qcom_interconnect_init(qcom); + if (ret) + goto remove_core; + } =20 wakeup_source =3D of_property_read_bool(dev->of_node, "wakeup-source"); device_init_wakeup(&pdev->dev, wakeup_source); @@ -817,7 +1009,20 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) remove_core: dwc3_core_remove(&qcom->dwc); clk_disable: - clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); + if (!qcom->fw_managed) { + clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); + } else { + int cleanup_ret; + + cleanup_ret =3D dwc3_qcom_domains_put(qcom, false /* bus_only */); + if (cleanup_ret) + dev_err(dev, "Failed to disable power domains during cleanup: %d\n", + cleanup_ret); + dwc3_qcom_domain_detach(qcom); + } + + /* Assert reset on error */ + reset_control_assert(qcom->resets); =20 err_remove_swnode: if (qcom->broken_suspend) @@ -829,15 +1034,63 @@ static void dwc3_qcom_remove(struct platform_device = *pdev) { struct dwc3 *dwc =3D platform_get_drvdata(pdev); struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); + bool pm_resumed =3D false; + bool domains_suspended =3D true; + int ret; =20 - if (pm_runtime_resume_and_get(qcom->dev) < 0) - return; + ret =3D pm_runtime_resume_and_get(qcom->dev); + if (ret < 0) + dev_warn(qcom->dev, "Failed to resume. Perform critical cleanups only.\n= "); + else + pm_resumed =3D true; =20 - dwc3_core_remove(&qcom->dwc); - clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); - dwc3_qcom_interconnect_exit(qcom); + /* + * Disable runtime PM to prevent any automatic PM operations during remov= al. + * This prevents race conditions where interrupt handlers or other subsys= tems + * might trigger runtime PM operations while the device is being torn dow= n. + */ + pm_runtime_disable(qcom->dev); + + if (pm_resumed) { + /* Only perform operations that require device to be active */ + dwc3_core_remove(&qcom->dwc); + + if (!qcom->fw_managed) { + dwc3_qcom_interconnect_exit(qcom); + clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); + } else { + ret =3D dwc3_qcom_domains_put(qcom, false /* bus_only */); + if (ret) { + dev_err(qcom->dev, "Failed to disable power domains during remove: %d\= n", + ret); + domains_suspended =3D false; + } + } + } =20 - pm_runtime_put_noidle(qcom->dev); + /* + * Critical cleanup operations that must be performed even if + * pm_runtime_resume_and_get failed to prevent resource leaks + * and anomalies during reboot cycles. + */ + if (qcom->fw_managed) { + /* Always detach power domains for firmware-managed case */ + dwc3_qcom_domain_detach(qcom); + } + + /* Always assert reset on remove */ + reset_control_assert(qcom->resets); + + if (pm_resumed) + pm_runtime_put_noidle(qcom->dev); + + /* + * Only report the device as suspended if the domains were actually + * brought down; otherwise leave the runtime PM status untouched so + * it doesn't misreport hardware that may still be powered. + */ + if (domains_suspended) + pm_runtime_set_suspended(qcom->dev); =20 if (qcom->broken_suspend) device_remove_software_node(&pdev->dev); --=20 2.34.1