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Thu, 03 Sep 2026 00:31:46 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v4 1/3] pinctrl: imx: answer OUTPUT_ENABLE/INPUT_ENABLE queries from the pad register Date: Thu, 3 Sep 2026 09:31:41 +0200 Message-ID: <20260903073143.2068494-2-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903073143.2068494-1-mehmet.fide@gmail.com> References: <20260903073143.2068494-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide The mmio pinconf get callback ignores which parameter was requested and returns the raw conf register, so a generic query through pinctrl_gpio_get_config() gets register bits back instead of the packed parameter it asked for. Decode the requested parameter and answer PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_INPUT_ENABLE on SoCs that declare where those bits live in the pad register; Vybrid has OBE at bit 1 and IBE at bit 0. The answer is 0 with the bit value as the argument, which is what the pinctrl_gpio_get_config() users (gpio-by-pinctrl, and gpio-mmio in the next patch) expect. Other parameters and the SCU based SoCs, whose firmware call returns the raw pad value as well, get -ENOTSUPP; a pin the device tree never configured gets -EINVAL, as the raw helper already does, so a caller can tell "no answer for this pin" from "this controller never answers". The only in-tree user of the raw register was the debugfs group dump, which called the callback with an uninitialized config; it now reads the register through its own helper, like the single pin dump already did. The set callback is not touched: the fsl,pins binding hands it the raw pad register value and that stays the only thing it accepts. Nothing in-tree sends generic parameters to it on these SoCs; making it understand them is a separate change. This gives gpio-mmio a way to read back the line direction on chips whose direction lives in the pin controller. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide --- drivers/pinctrl/freescale/pinctrl-imx.c | 54 +++++++++++++++++++++-- drivers/pinctrl/freescale/pinctrl-imx.h | 4 ++ drivers/pinctrl/freescale/pinctrl-vf610.c | 2 + 3 files changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/free= scale/pinctrl-imx.c index 9a45b376d36f..f08ef52bf4f8 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -21,6 +21,7 @@ =20 #include #include +#include #include #include =20 @@ -291,8 +292,8 @@ struct pinmux_ops imx_pmx_ops =3D { .set_mux =3D imx_pmx_set, }; =20 -static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_= id, - unsigned long *config) +static int imx_pinconf_get_raw_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) { struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info =3D ipctl->info; @@ -312,16 +313,61 @@ static int imx_pinconf_get_mmio(struct pinctrl_dev *p= ctldev, unsigned pin_id, return 0; } =20 +static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info =3D ipctl->info; + const struct imx_pin_reg *pin_reg =3D &ipctl->pin_regs[pin_id]; + enum pin_config_param param =3D pinconf_to_config_param(*config); + unsigned int mask; + u32 raw; + + switch (param) { + case PIN_CONFIG_OUTPUT_ENABLE: + mask =3D info->obe_mask; + break; + case PIN_CONFIG_INPUT_ENABLE: + mask =3D info->ibe_mask; + break; + default: + mask =3D 0; + break; + } + + if (!mask) + return -ENOTSUPP; + if (pin_reg->conf_reg =3D=3D -1) + return -EINVAL; + + raw =3D readl(ipctl->base + pin_reg->conf_reg); + *config =3D pinconf_to_config_packed(param, !!(raw & mask)); + + return 0; +} + static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info =3D ipctl->info; =20 + if (info->flags & IMX_USE_SCU) + return -ENOTSUPP; + + return imx_pinconf_get_mmio(pctldev, pin_id, config); +} + +static int imx_pinconf_get_raw(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info =3D ipctl->info; + if (info->flags & IMX_USE_SCU) return info->imx_pinconf_get(pctldev, pin_id, config); else - return imx_pinconf_get_mmio(pctldev, pin_id, config); + return imx_pinconf_get_raw_mmio(pctldev, pin_id, config); } =20 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, @@ -426,7 +472,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_d= ev *pctldev, struct imx_pin *pin =3D &((struct imx_pin *)(grp->data))[i]; =20 name =3D pin_get_name(pctldev, pin->pin); - ret =3D imx_pinconf_get(pctldev, pin->pin, &config); + ret =3D imx_pinconf_get_raw(pctldev, pin->pin, &config); if (ret) return; seq_printf(s, " %s: 0x%lx\n", name, config); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/free= scale/pinctrl-imx.h index f65ff45b4003..8fa7e1e2521d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -91,6 +91,10 @@ struct imx_pinctrl_soc_info { unsigned int mux_mask; u8 mux_shift; =20 + /* OBE/IBE bits in the conf register, 0 if the pad does not have them */ + unsigned int obe_mask; + unsigned int ibe_mask; + int (*gpio_set_direction)(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/fr= eescale/pinctrl-vf610.c index 76a4bc0181a0..77d077618782 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -319,6 +319,8 @@ static const struct imx_pinctrl_soc_info vf610_pinctrl_= info =3D { .gpio_set_direction =3D vf610_pmx_gpio_set_direction, .mux_mask =3D 0x700000, .mux_shift =3D 20, + .obe_mask =3D 0x2, + .ibe_mask =3D 0x1, }; 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Thu, 03 Sep 2026 00:31:47 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v4 2/3] gpiolib: add get_config() and gpiochip_generic_get_config() Date: Thu, 3 Sep 2026 09:31:42 +0200 Message-ID: <20260903073143.2068494-3-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903073143.2068494-1-mehmet.fide@gmail.com> References: <20260903073143.2068494-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide A chip with a pin control backend sets a line's configuration through set_config() and gpiochip_generic_config(), but has no way to read one back. gpio-mmio needs that to learn the direction of a line whose direction lives in the pin controller. Add the optional get_config() callback, taking the packed parameter to query and returning the packed answer the way pinctrl_gpio_get_config() does, and gpiochip_generic_get_config() as the pin control backed implementation, the mirror of gpiochip_generic_config(). Without CONFIG_PINCTRL the pinctrl stub returns 0 and leaves the config alone, so the helper answers -ENOTSUPP there instead. Nothing in gpiolib calls get_config() and there is no consumer API; it is for the chip's own use. Suggested-by: Linus Walleij Signed-off-by: Mehmet Fide --- Documentation/driver-api/gpio/driver.rst | 6 ++++++ drivers/gpio/gpiolib.c | 23 +++++++++++++++++++++++ include/linux/gpio/driver.h | 9 +++++++++ 3 files changed, 38 insertions(+) diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/drive= r-api/gpio/driver.rst index a4f160b95089..5be217815c9b 100644 --- a/Documentation/driver-api/gpio/driver.rst +++ b/Documentation/driver-api/gpio/driver.rst @@ -134,6 +134,12 @@ ending up in the pin control back-end "behind" the GPI= O controller, usually closer to the actual pins. This way the pin controller can manage the below listed GPIO configurations. =20 +The optional .get_config() callback reads a configuration back with the sa= me +packed format: the parameter to query goes in, the packed parameter and +argument come out. gpiochip_generic_get_config() is its pin control backed +counterpart. Nothing in gpiolib calls it; it is for the GPIO driver's own = use, +for example to learn the direction of a line when the pin controller owns = it. + If a pin controller back-end is used, the GPIO controller or hardware description needs to provide "GPIO ranges" mapping the GPIO line offsets t= o pin numbers on the pin controller so they can properly cross-reference each ot= her. diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index ef8ccaf17c9c..44328aed1646 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -2440,6 +2440,29 @@ int gpiochip_generic_config(struct gpio_chip *gc, un= signed int offset, } EXPORT_SYMBOL_GPL(gpiochip_generic_config); =20 +/** + * gpiochip_generic_get_config() - read back the configuration of a pin + * @gc: the gpiochip owning the GPIO + * @offset: the offset of the GPIO to query + * @config: the packed parameter to query, replaced by the packed answer + * + * Returns: + * 0 on success, or negative errno on failure. + */ +int gpiochip_generic_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config) +{ +#ifdef CONFIG_PINCTRL + if (list_empty(&gc->gpiodev->pin_ranges)) + return -ENOTSUPP; + + return pinctrl_gpio_get_config(gc, offset, config); +#else + return -ENOTSUPP; +#endif +} +EXPORT_SYMBOL_GPL(gpiochip_generic_get_config); + #ifdef CONFIG_PINCTRL =20 /** diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 17511434ed07..5c81cce69173 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -359,6 +359,10 @@ struct gpio_irq_chip { * @set_config: optional hook for all kinds of settings. Uses the same * packed config format as generic pinconf. Must return 0 on success and * a negative error number on failure. + * @get_config: optional hook to read back a setting. Uses the same packed + * config format as generic pinconf: the parameter to query goes in, the + * packed parameter and argument come out. Must return 0 on success and a + * negative error number on failure. * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; * implementation may not sleep * @dbg_show: optional routine to show contents in debugfs; default code @@ -434,6 +438,9 @@ struct gpio_chip { int (*set_config)(struct gpio_chip *gc, unsigned int offset, unsigned long config); + int (*get_config)(struct gpio_chip *gc, + unsigned int offset, + unsigned long *config); int (*to_irq)(struct gpio_chip *gc, unsigned int offset); =20 @@ -708,6 +715,8 @@ int gpiochip_generic_request(struct gpio_chip *gc, unsi= gned int offset); void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, unsigned long config); +int gpiochip_generic_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config); =20 /** * struct gpio_pin_range - pin range controlled by a gpio chip --=20 2.54.0 From nobody Sat Sep 26 08:48:14 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 755AD430CF8 for ; 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Thu, 03 Sep 2026 00:31:49 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce551bf7asm69369455e9.2.2026.09.03.00.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2026 00:31:48 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v4 3/3] gpio: mmio: track the direction of chips without direction registers Date: Thu, 3 Sep 2026 09:31:43 +0200 Message-ID: <20260903073143.2068494-4-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903073143.2068494-1-mehmet.fide@gmail.com> References: <20260903073143.2068494-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide A generic chip with GPIO_GENERIC_PINCTRL_BACKEND and no direction registers sets the direction through pinctrl but has no get_direction callback, so every gpiod_get_direction() call trips the WARN in gpiolib and the direction gpiolib reports is whatever it assumed. On a Vybrid Colibri module that is 21 backtraces per boot. Keep the direction of such a chip in the existing shadow: the direction setters update sdir under the chip lock, and get_direction() is the shadow-reading path already used for unreadable direction registers. That keeps the callback usable in atomic context, which it has to be: gpiochip_lock_as_irq() calls it for !can_sleep chips from gpiochip_irq_domain_activate(), under the irq descriptor lock. The pad's actual state is read once, in process context, when a line is requested: gpiolib calls request() right before get_direction() for a new line, so the shadow is seeded there from PIN_CONFIG_OUTPUT_ENABLE through the chip's get_config(), which is gpiochip_generic_get_config() for the pinctrl backend, and the line reports what the pin controller says. Lines pinctrl cannot answer for keep the input default, which is what gpiolib assumed before. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide --- drivers/gpio/gpio-mmio.c | 60 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index 7e4b3e8d609f..0709ffaab4de 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -49,6 +49,7 @@ o ` ~~~~\___/~~~~ ` control= ler in FPGA is ,.` #include #include #include +#include #include #include #include @@ -372,7 +373,17 @@ static int gpio_mmio_dir_in_err(struct gpio_chip *gc, = unsigned int gpio) =20 static int gpio_mmio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) { - return gpio_mmio_dir_return(gc, gpio, false); + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; + + ret =3D gpio_mmio_dir_return(gc, gpio, false); + if (ret) + return ret; + + guard(raw_spinlock_irqsave)(&chip->lock); + chip->sdir &=3D ~gpio_mmio_line2mask(gc, gpio); + + return 0; } =20 static int gpio_mmio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, @@ -384,9 +395,19 @@ static int gpio_mmio_dir_out_err(struct gpio_chip *gc,= unsigned int gpio, static int gpio_mmio_simple_dir_out(struct gpio_chip *gc, unsigned int gpi= o, int val) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; + gc->set(gc, gpio, val); =20 - return gpio_mmio_dir_return(gc, gpio, true); + ret =3D gpio_mmio_dir_return(gc, gpio, true); + if (ret) + return ret; + + guard(raw_spinlock_irqsave)(&chip->lock); + chip->sdir |=3D gpio_mmio_line2mask(gc, gpio); + + return 0; } =20 static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio) @@ -601,20 +622,51 @@ static int gpio_mmio_setup_direction(struct gpio_gene= ric_chip *chip, gc->direction_input =3D gpio_mmio_dir_in_err; else gc->direction_input =3D gpio_mmio_simple_dir_in; + + if (cfg->flags & GPIO_GENERIC_PINCTRL_BACKEND) { + chip->dir_unreadable =3D true; + gc->get_direction =3D gpio_mmio_get_dir; + gc->get_config =3D gpiochip_generic_get_config; + } } =20 return 0; } =20 +static void gpio_mmio_seed_dir_from_pinctrl(struct gpio_chip *gc, + unsigned int gpio) +{ + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + unsigned long config; + + if (!gc->get_config || chip->reg_dir_out || chip->reg_dir_in) + return; + + config =3D pinconf_to_config_packed(PIN_CONFIG_OUTPUT_ENABLE, 0); + if (gc->get_config(gc, gpio, &config)) + return; + + guard(raw_spinlock_irqsave)(&chip->lock); + if (config) + chip->sdir |=3D gpio_mmio_line2mask(gc, gpio); + else + chip->sdir &=3D ~gpio_mmio_line2mask(gc, gpio); +} + static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin) { struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; =20 if (gpio_pin >=3D gc->ngpio) return -EINVAL; =20 - if (chip->pinctrl) - return gpiochip_generic_request(gc, gpio_pin); + if (chip->pinctrl) { + ret =3D gpiochip_generic_request(gc, gpio_pin); + if (ret) + return ret; + gpio_mmio_seed_dir_from_pinctrl(gc, gpio_pin); + } =20 return 0; } --=20 2.54.0