From nobody Sat Sep 26 08:38:28 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A9A14119F3; Thu, 3 Sep 2026 07:29:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420581; cv=none; b=iQHcjsfJaX2WP0IMRE5sqlr9HwTgXD8oE8l94Q+YKYBJlfGGG+WgACAbB/YhZS+5ndVtTZRC1WgHLfI/51DXelLFvOXOCN9fxRolxYFg/Wyas9HypVsMOtJOvBGY069lfZl/rtM7GhgZb4mW3MriT09nJvpaHVWfLBGI9Q34b9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420581; c=relaxed/simple; bh=qKNdar3rw/NxENAjemjeEJBAo/H6LYU7D0n6l4s7FM0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uZfPqyLwPeazTm3CG4yby07lSLlkKMOekcxSUjVwG0vQ8hXah9NzU5qmGSIibm8Cl3EJvOwU9kKDvl7g2UfMCiRONFP40eY7Z1nWY9Iust0+BtWi8sLI+IqZW3Gjhi2h2ynsuX/OZatKLrKXWNWIQcq4FKMPj13VjPTi3Fwidr8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=YaiBl2CU; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="YaiBl2CU" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6837SsxzE3295537, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1788420534; bh=mQq/r51KBnX7DJUQOd04fDEjw2M7VSDiFa2AU4lTGgs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=YaiBl2CUm8KXfl1KRS8lJdxgDA+LtvEhCjN3wC+u6xaHRV3AGHAdaMdBYIhUB+Nlb pmnApzFwrsm5XhbImGfroEpQ4MkV7VFrU2VLsjsOp0cIRj1J1UC3Tk7ayK8zTTZLZS Xt9RhgR7EYsRCvGrjP3Q2aO5jZrT9+idqWsemQI+DpRU8vpqhXT+Sy3ZP6DF0C6R/7 K1inTZwaPyn3qB5i7ynz/wt88oXzXmj2CfxghLzelU3v1tQ/YjtLeALeJ8c/eQlrFm N840T/Jtsb3LV+jZGcDkdpq3g6oBXQcT0vfihBGfwEBu4TvoI7HQGdlUbxIGGe1Bzx lnQHUMOmoKsyg== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 6837SsxzE3295537 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Sep 2026 15:28:54 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Thu, 3 Sep 2026 15:28:53 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:53 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 1/8] r8152: refactor r8156_init Date: Thu, 3 Sep 2026 15:28:45 +0800 Message-ID: <20260903072852.58695-2-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL8157 and RTL8159 have different init sequences from RTL8156. Split r8156_init into per-chip functions: r8156_init (VER_10/11), r8156b_init (VER_12/13/15), r8157_init (VER_16), and r8159_init (VER_17). Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 488 ++++++++++++++++++++++++++++------------ 1 file changed, 349 insertions(+), 139 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 57d04af6368c3..d4289323895e3 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -78,6 +78,7 @@ #define PLA_EEE_TXTWSYS_2P5G 0xe058 #define PLA_EEEP_CR 0xe080 #define PLA_MAC_PWR_CTRL 0xe0c0 +#define PLA_RMT_WAKE 0xe0c8 #define PLA_MAC_PWR_CTRL2 0xe0ca #define PLA_MAC_PWR_CTRL3 0xe0cc #define PLA_MAC_PWR_CTRL4 0xe0ce @@ -371,6 +372,9 @@ #define MCU_CLK_RATIO_MASK 0x0f0f0f0f #define ALDPS_SPDWN_RATIO 0x0f87 =20 +/* PLA_RMT_WAKE */ +#define RMT_WAKE_EN BIT(0) + /* PLA_MAC_PWR_CTRL2 */ #define EEE_SPDWN_RATIO 0x8007 #define MAC_CLK_SPDWN_EN BIT(15) @@ -417,6 +421,7 @@ =20 /* PLA_INDICATE_FALG */ #define UPCOMING_RUNTIME_D3 BIT(0) +#define PREBOOT_OPTION BIT(1) =20 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */ #define DEBUG_OE BIT(0) @@ -542,6 +547,7 @@ #define RX_AGG_DISABLE 0x0010 #define RX_ZERO_EN 0x0080 #define RX_DESC_16B 0x0400 +#define RX_END_TRANSFER_EN BIT(11) =20 /* USB_U2P3_CTRL */ #define U2P3_ENABLE 0x0001 @@ -4200,6 +4206,22 @@ static u16 r8153_phy_status(struct r8152 *tp, u16 de= sired) return data; } =20 +static int wait_autoload_done(struct r8152 *tp) +{ + u16 ocp_data; + int ret; + + ret =3D read_poll_timeout(ocp_read_word, ocp_data, + ocp_data & AUTOLOAD_DONE, 20000, + 10 * USEC_PER_SEC, false, tp, MCU_TYPE_PLA, + PLA_BOOT_CTRL); + + if (ret) + dev_err(&tp->intf->dev, "autoload done timeout\n"); + + return ret; +} + static void r8153b_ups_en(struct r8152 *tp, bool enable) { if (enable) { @@ -4218,16 +4240,8 @@ static void r8153b_ups_en(struct r8152 *tp, bool ena= ble) UPS_FORCE_PWR_DOWN); =20 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { - int i; - - for (i =3D 0; i < 500; i++) { - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) - break; - msleep(20); - } + if (wait_autoload_done(tp)) + return; =20 tp->rtl_ops.hw_phy_cfg(tp); =20 @@ -4255,16 +4269,8 @@ static void r8153c_ups_en(struct r8152 *tp, bool ena= ble) UPS_FORCE_PWR_DOWN); =20 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { - int i; - - for (i =3D 0; i < 500; i++) { - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) - break; - msleep(20); - } + if (wait_autoload_done(tp)) + return; =20 tp->rtl_ops.hw_phy_cfg(tp); =20 @@ -7253,22 +7259,14 @@ static void r8152b_init(struct r8152 *tp) static void r8153_init(struct r8152 *tp) { u32 ocp_data; - int i; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 r8153_u1u2en(tp, false); =20 - for (i =3D 0; i < 500; i++) { - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) - break; - - msleep(20); - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } + if (wait_autoload_done(tp)) + return; =20 r8153_phy_status(tp, 0); =20 @@ -7369,22 +7367,13 @@ static void r8153_init(struct r8152 *tp) =20 static void r8153b_init(struct r8152 *tp) { - int i; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 r8153b_u1u2en(tp, false); =20 - for (i =3D 0; i < 500; i++) { - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) - break; - - msleep(20); - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } + if (wait_autoload_done(tp)) + return; =20 r8153_phy_status(tp, 0); =20 @@ -7439,8 +7428,6 @@ static void r8153b_init(struct r8152 *tp) =20 static void r8153c_init(struct r8152 *tp) { - int i; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 @@ -7453,15 +7440,8 @@ static void r8153c_init(struct r8152 *tp) =20 ocp_word_set_bits(tp, MCU_TYPE_USB, 0xcbf0, BIT(1)); =20 - for (i =3D 0; i < 500; i++) { - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) - break; - - msleep(20); - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } + if (wait_autoload_done(tp)) + return; =20 r8153_phy_status(tp, 0); =20 @@ -8358,90 +8338,132 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) set_bit(PHY_RESET, &tp->flags); } =20 -static int r8159_wait_backup_restore(struct r8152 *tp) +static void r8156_init(struct r8152 *tp) { - u32 ocp_data; + u16 data; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); - if (!(ocp_data & PCUT_STATUS)) - return 0; + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; =20 - return poll_timeout_us(ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_G= PHY_CTRL), - ocp_data & BACKUP_RESTRORE, 200, 20000, false); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); + + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); + + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); + + r8153b_u1u2en(tp, false); + + if (wait_autoload_done(tp)) + return; + + data =3D r8153_phy_status(tp, 0); + if (data =3D=3D PHY_STAT_EXT_INIT) + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); + + r8153_u2p3en(tp, false); + + /* MSC timer =3D 0xfff * 8ms =3D 32760 ms */ + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); + + /* U1/U2/L1 idle timer. 500 us */ + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); + + r8153b_power_cut_en(tp, false); + r8156_ups_en(tp, false); + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, PREBOOT_OPTION); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_RMT_WAKE, RMT_WAKE_EN); + + if (tp->udev->speed >=3D USB_SPEED_SUPER) + r8153b_u1u2en(tp, true); + + usb_enable_lpm(tp->udev); + + r8156_mac_clk_spd(tp, true); + + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); + + if (rtl8152_get_speed(tp) & LINK_STATUS) + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); + else + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, + POLL_LINK_CHG); + + set_bit(GREEN_ETHERNET, &tp->flags); + + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); + + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); + + r8156_mdio_force_mode(tp); + rtl_tally_reset(tp); + + tp->coalesce =3D 15000; /* 15 us */ } =20 -static void r8156_init(struct r8152 *tp) +static void r8156b_u2phy_backup(struct r8152 *tp) +{ + ocp_write_word(tp, MCU_TYPE_USB, 0xd3ce, 0x181b); + ocp_write_dword(tp, MCU_TYPE_USB, 0xd3d0, 0x616ccd99); + ocp_write_dword(tp, MCU_TYPE_USB, 0xd3d4, 0x08fc8101); + ocp_write_dword(tp, MCU_TYPE_USB, 0xd3d8, 0x159b1100); + ocp_write_word(tp, MCU_TYPE_USB, 0xd3dc, 0x0a00); +} + +static void r8156b_init(struct r8152 *tp) { u32 ocp_data; u16 data; - int i; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 - if (tp->version =3D=3D RTL_VER_16 || tp->version =3D=3D RTL_VER_17) { - ocp_byte_set_bits(tp, MCU_TYPE_USB, 0xcffe, BIT(3)); - ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd3ca, BIT(0)); - } - ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); =20 - if (tp->version < RTL_VER_16) - ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); =20 ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); =20 - if (tp->version >=3D RTL_VER_12 && tp->version <=3D RTL_VER_15) - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); =20 r8153b_u1u2en(tp, false); =20 switch (tp->version) { case RTL_VER_13: case RTL_VER_15: - case RTL_VER_16: - case RTL_VER_17: r8156b_wait_loading_flash(tp); break; default: break; } =20 - for (i =3D 0; i < 500; i++) { - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) - break; - - msleep(20); - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } - - if (tp->version =3D=3D RTL_VER_17 && r8159_wait_backup_restore(tp)) { - rtl_set_inaccessible(tp); - dev_err(&tp->intf->dev, "init failed, backup-restore timed out\n"); + if (wait_autoload_done(tp)) return; - } =20 data =3D r8153_phy_status(tp, 0); if (data =3D=3D PHY_STAT_EXT_INIT) { ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); - if (tp->version >=3D RTL_VER_12) - ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); } =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); =20 - if (tp->version >=3D RTL_VER_16) - r8157_u2p3en(tp, false); - else - r8153_u2p3en(tp, false); + r8153_u2p3en(tp, false); + + /* Disable Auto Speed up */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); =20 /* MSC timer =3D 0xfff * 8ms =3D 32760 ms */ ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); @@ -8449,73 +8471,261 @@ static void r8156_init(struct r8152 *tp) /* U1/U2/L1 idle timer. 500 us */ ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); =20 - if (tp->version >=3D RTL_VER_16) - r8157_power_cut_en(tp, false); - else - r8153b_power_cut_en(tp, false); + r8156b_u2phy_backup(tp); =20 + r8153b_power_cut_en(tp, false); r8156_ups_en(tp, false); r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); =20 + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, PREBOOT_OPTION); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_RMT_WAKE, RMT_WAKE_EN); + if (tp->udev->speed >=3D USB_SPEED_SUPER) r8153b_u1u2en(tp, true); =20 usb_enable_lpm(tp->udev); =20 - if (tp->version >=3D RTL_VER_12 && tp->version <=3D RTL_VER_15) { - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); =20 - ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); =20 - /* enable fc timer and set timer to 600 ms. */ - ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, CTRL_TIMER_EN | (600 / 8)= ); + /* enable fc timer and set timer to 600 ms. */ + ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, + CTRL_TIMER_EN | (600 / 8)); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); - if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) - ocp_data |=3D FLOW_CTRL_PATCH_2; - ocp_data &=3D ~AUTO_SPEEDUP; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); + ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); + if (!(ocp_data & DACK_DET_EN)) + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, + FLOW_CTRL_PATCH_2); =20 - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); - } + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); =20 r8156_mac_clk_spd(tp, true); =20 - if (tp->version < RTL_VER_16) - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, PLA_MCU_SPDWN_EN); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); if (rtl8152_get_speed(tp) & LINK_STATUS) - ocp_data |=3D CUR_LINK_OK; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); else - ocp_data &=3D ~CUR_LINK_OK; - ocp_data |=3D POLL_LINK_CHG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK, POLL_LINK_CHG); =20 set_bit(GREEN_ETHERNET, &tp->flags); =20 - /* RX aggregation / 16 bytes RX descriptor - * BIT(11) is specific to RTL8159, with unknown meaning - */ - if (tp->version =3D=3D RTL_VER_17) - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, - RX_AGG_DISABLE | RX_DESC_16B | BIT(11)); - else if (tp->version =3D=3D RTL_VER_16) - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_AGG_DISABLE | RX_DE= SC_16B); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); + + r8156_mdio_force_mode(tp); + rtl_tally_reset(tp); + + tp->coalesce =3D 15000; /* 15 us */ +} + +static void r8157_init(struct r8152 *tp) +{ + u16 data; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + + /* Enable SW reset */ + ocp_byte_set_bits(tp, MCU_TYPE_USB, 0xcffe, BIT(3)); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd3ca, BIT(0)); + + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); + + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); + + r8153b_u1u2en(tp, false); + + if (wait_autoload_done(tp)) + return; + + r8156b_wait_loading_flash(tp); + + data =3D r8153_phy_status(tp, 0); + if (data =3D=3D PHY_STAT_EXT_INIT) { + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + } + + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); + + r8157_u2p3en(tp, false); + + /* Disable Interrupt Mitigation */ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xcf04, + BIT(0) | BIT(1) | BIT(2) | BIT(7)); + + /* Disable Auto Speed up */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); + + /* MSC timer =3D 0xfff * 8ms =3D 32760 ms */ + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); + + /* U1/U2/L1 idle timer. 500 us */ + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); + + r8157_power_cut_en(tp, false); + r8156_ups_en(tp, false); + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, PREBOOT_OPTION); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_RMT_WAKE, RMT_WAKE_EN); + + /* Clear Warm RST / Bus RST event flag */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, 0xcd06, BIT(11)); + + if (tp->udev->speed >=3D USB_SPEED_SUPER) + r8153b_u1u2en(tp, true); + + usb_enable_lpm(tp->udev); + + r8156_mac_clk_spd(tp, true); + + if (rtl8152_get_speed(tp) & LINK_STATUS) + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); else - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_AGG_DISABLE | RX_ZE= RO_EN); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK, POLL_LINK_CHG); =20 - if (tp->version < RTL_VER_12) - ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); + set_bit(GREEN_ETHERNET, &tp->flags); =20 - if (tp->version >=3D RTL_VER_16) { - /* Disable Rx Zero Len */ - rtl_bmu_clr_bits(tp, 0x2300, BIT(3)); - /* TX descriptor Signature */ - ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd4ae, BIT(1)); + /* RX aggregation / 16 bytes RX descriptor / Bulk In End transfer */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_DESC_16B | RX_END_TRANSFER_EN); + + /* Disable Rx Zero Len */ + rtl_bmu_clr_bits(tp, 0x2300, BIT(3)); + + /* TX descriptor Signature */ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd4ae, BIT(1)); + + r8156_mdio_force_mode(tp); + rtl_tally_reset(tp); + + tp->coalesce =3D 15000; /* 15 us */ +} + +static int r8159_wait_backup_restore(struct r8152 *tp) +{ + u32 ocp_data; + + ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); + if (!(ocp_data & PCUT_STATUS)) + return 0; + + return poll_timeout_us(ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_G= PHY_CTRL), + ocp_data & BACKUP_RESTRORE, 200, 20000, false); +} + +static void r8159_init(struct r8152 *tp) +{ + u16 data; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + + /* Enable SW reset */ + ocp_byte_set_bits(tp, MCU_TYPE_USB, 0xcffe, BIT(3)); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd3ca, BIT(0)); + + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); + + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); + + r8153b_u1u2en(tp, false); + + if (wait_autoload_done(tp)) + return; + + if (r8159_wait_backup_restore(tp)) { + rtl_set_inaccessible(tp); + dev_err(&tp->intf->dev, + "init failed, backup-restore timed out\n"); + return; } =20 + r8156b_wait_loading_flash(tp); + + data =3D r8153_phy_status(tp, 0); + if (data =3D=3D PHY_STAT_EXT_INIT) { + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + } + + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); + + r8157_u2p3en(tp, false); + + /* Disable Interrupt Mitigation */ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xcf04, + BIT(0) | BIT(1) | BIT(2) | BIT(7)); + + /* Disable Auto Speed up */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); + + /* MSC timer =3D 0xfff * 8ms =3D 32760 ms */ + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); + + /* U1/U2/L1 idle timer. 500 us */ + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); + + r8157_power_cut_en(tp, false); + r8156_ups_en(tp, false); + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, PREBOOT_OPTION); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_RMT_WAKE, RMT_WAKE_EN); + + /* Clear Warm RST / Bus RST event flag */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, 0xcd06, BIT(11)); + + /* Disable FW u1u2 patch option */ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xb9a6, BIT(0)); + + if (tp->udev->speed >=3D USB_SPEED_SUPER) + r8153b_u1u2en(tp, true); + + usb_enable_lpm(tp->udev); + + r8156_mac_clk_spd(tp, true); + + if (rtl8152_get_speed(tp) & LINK_STATUS) + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); + else + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK, POLL_LINK_CHG); + + set_bit(GREEN_ETHERNET, &tp->flags); + + /* RX aggregation / 16 bytes RX descriptor / Bulk In End transfer */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_DESC_16B | RX_END_TRANSFER_EN); + + /* Disable Rx Zero Len */ + rtl_bmu_clr_bits(tp, 0x2300, BIT(3)); + + /* TX descriptor Signature */ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd4ae, BIT(1)); + + /* Enable u3phy patch backup */ + ocp_write_word(tp, MCU_TYPE_USB, 0xb9a2, 0x0448); + r8156_mdio_force_mode(tp); rtl_tally_reset(tp); =20 @@ -9846,7 +10056,7 @@ static int rtl_ops_init(struct r8152 *tp) tp->eee_en =3D true; tp->eee_adv =3D MDIO_EEE_1000T | MDIO_EEE_100TX; tp->eee_adv2 =3D MDIO_EEE_2_5GT; - ops->init =3D r8156_init; + ops->init =3D r8156b_init; ops->enable =3D rtl8156_enable; ops->disable =3D rtl8153_disable; ops->up =3D rtl8156_up; @@ -9885,7 +10095,7 @@ static int rtl_ops_init(struct r8152 *tp) tp->eee_en =3D true; tp->eee_adv =3D MDIO_EEE_1000T | MDIO_EEE_100TX; tp->eee_adv2 =3D MDIO_EEE_2_5GT | MDIO_EEE_5GT; - ops->init =3D r8156_init; + ops->init =3D r8157_init; ops->enable =3D rtl8156_enable; ops->disable =3D rtl8153_disable; ops->up =3D rtl8156_up; @@ -9907,7 +10117,7 @@ static int rtl_ops_init(struct r8152 *tp) tp->eee_en =3D true; tp->eee_adv =3D MDIO_EEE_100TX | MDIO_EEE_1000T | MDIO_EEE_10GT; tp->eee_adv2 =3D MDIO_EEE_2_5GT | MDIO_EEE_5GT; - ops->init =3D r8156_init; + ops->init =3D r8159_init; ops->enable =3D rtl8156_enable; ops->disable =3D rtl8153_disable; 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Thu, 3 Sep 2026 15:28:54 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Thu, 3 Sep 2026 15:28:54 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 2/8] r8152: support RTL8159 for different packages Date: Thu, 3 Sep 2026 15:28:46 +0800 Message-ID: <20260903072852.58695-3-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL8159 comes in two packages, QFN68 and QFN100, which require different handling. Split RTL_VER_17 into RTL_VER_17_QFN68 and RTL_VER_17_QFN100. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 93 ++++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index d4289323895e3..080b5890efb4e 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -64,6 +64,7 @@ #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ #define PLA_EXTRA_STATUS 0xd398 #define PLA_GPHY_CTRL 0xd3ae +#define PLA_PKG_DET 0xdc48 #define PLA_POL_GPIO_CTRL 0xdc6a #define PLA_EFUSE_DATA 0xdd00 #define PLA_EFUSE_CMD 0xdd02 @@ -290,6 +291,9 @@ #define IFG_144NS BIT(9) #define IFG_96NS (BIT(9) | BIT(8)) =20 +/* PLA_PKG_DET */ +#define PKG_MASK 0x1e + /* PLA_MTPS */ #define MTPS_JUMBO (12 * 1024 / 64) #define MTPS_DEFAULT (6 * 1024 / 64) @@ -1254,7 +1258,8 @@ enum rtl_version { RTL_VER_14, RTL_VER_15, RTL_VER_16, - RTL_VER_17, + RTL_VER_17_QFN68, + RTL_VER_17_QFN100, =20 RTL_VER_MAX }; @@ -3446,7 +3451,8 @@ static void rtl8152_nic_reset(struct r8152 *tp) break; =20 case RTL_VER_16: - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE | CR_TE); break; =20 @@ -3486,7 +3492,7 @@ static void rtl_eee_plus_en(struct r8152 *tp, bool en= able) =20 static void rtl_set_eee_plus(struct r8152 *tp) { - if (tp->version =3D=3D RTL_VER_17) + if (tp->version =3D=3D RTL_VER_17_QFN68 || tp->version =3D=3D RTL_VER_17_= QFN100) return rtl_eee_plus_en(tp, false); =20 if (rtl8152_get_speed(tp) & _10bps) @@ -3674,7 +3680,8 @@ static void r8153_set_rx_early_timeout(struct r8152 *= tp) case RTL_VER_13: case RTL_VER_15: case RTL_VER_16: - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 640 / 8); ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, @@ -3719,7 +3726,8 @@ static void r8153_set_rx_early_size(struct r8152 *tp) ocp_data / 8); break; case RTL_VER_16: - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data / 16); break; @@ -3835,6 +3843,8 @@ static void rtl_rx_vlan_en(struct r8152 *tp, bool ena= ble) case RTL_VER_13: case RTL_VER_15: case RTL_VER_16: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: default: if (enable) ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RCR1, @@ -4514,6 +4524,8 @@ static void r8153_teredo_off(struct r8152 *tp) case RTL_VER_14: case RTL_VER_15: case RTL_VER_16: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: default: /* The bit 0 ~ 7 are relative with teredo settings. They are * W1C (write 1 to clear), so set all 1 to disable it. @@ -4568,7 +4580,8 @@ static void rtl_clear_bp(struct r8152 *tp, u16 type) break; case RTL_VER_14: case RTL_VER_16: - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: default: ocp_write_word(tp, type, USB_BP2_EN, 0); bp_num =3D 16; @@ -4680,7 +4693,8 @@ static bool rtl8152_is_fw_phy_speed_up_ok(struct r815= 2 *tp, struct fw_phy_speed_ case RTL_VER_13: case RTL_VER_15: case RTL_VER_16: - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: default: break; } @@ -5840,7 +5854,8 @@ static void rtl_eee_enable(struct r8152 *tp, bool ena= ble) case RTL_VER_13: case RTL_VER_15: case RTL_VER_16: - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: if (enable) { r8156_eee_en(tp, true); ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); @@ -6431,8 +6446,15 @@ static int rtl8156_enable(struct r8152 *tp) set_tx_qlen(tp); rtl_set_eee_plus(tp); =20 - if (tp->version >=3D RTL_VER_12 && tp->version <=3D RTL_VER_17) - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); + switch (tp->version) { + case RTL_VER_10: + case RTL_VER_11: + break; + default: + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, + RX_AGGR_NUM_MASK); + break; + } =20 r8153_set_rx_early_timeout(tp); r8153_set_rx_early_size(tp); @@ -8120,7 +8142,8 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) sram2_write_w0w1(tp, 0x809d, 0xff00, 0x5000); break; =20 - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: /* Disable bypass turn off clk in ALDPS */ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, 0xd3c8, BIT(0)); =20 @@ -8723,6 +8746,10 @@ static void r8159_init(struct r8152 *tp) /* TX descriptor Signature */ ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd4ae, BIT(1)); =20 + /* Enable u2phy backup restore patch */ + if (tp->version =3D=3D RTL_VER_17_QFN68) + ocp_byte_set_bits(tp, MCU_TYPE_USB, 0xb99c, BIT(0)); + /* Enable u3phy patch backup */ ocp_write_word(tp, MCU_TYPE_USB, 0xb9a2, 0x0448); =20 @@ -10113,7 +10140,8 @@ static int rtl_ops_init(struct r8152 *tp) r8157_desc_init(tp); break; =20 - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: tp->eee_en =3D true; tp->eee_adv =3D MDIO_EEE_100TX | MDIO_EEE_1000T | MDIO_EEE_10GT; tp->eee_adv2 =3D MDIO_EEE_2_5GT | MDIO_EEE_5GT; @@ -10205,7 +10233,8 @@ static int rtl_fw_init(struct r8152 *tp) case RTL_VER_16: rtl_fw->fw_name =3D FIRMWARE_8157_1; break; - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: rtl_fw->fw_name =3D FIRMWARE_8159_1; break; default: @@ -10215,9 +10244,33 @@ static int rtl_fw_init(struct r8152 *tp) return 0; } =20 +static u32 __rtl_get_pkg_det(struct usb_device *udev) +{ + u32 pkg_det =3D 0; + __le32 *tmp; + int ret, i; + + tmp =3D kmalloc_obj(*tmp); + if (!tmp) + return 0; + + for (i =3D 0, ret =3D 0; i < 3 && ret !=3D 4; i++) + ret =3D usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, + PLA_PKG_DET, MCU_TYPE_PLA, tmp, + sizeof(*tmp), USB_CTRL_GET_TIMEOUT); + + if (ret > 0) + pkg_det =3D __le32_to_cpu(*tmp) & PKG_MASK; + + kfree(tmp); + return pkg_det; +} + static u8 __rtl_get_hw_ver(struct usb_device *udev) { u32 ocp_data =3D 0; + u32 pkg_det =3D 0; __le32 *tmp; u8 version; int ret; @@ -10300,7 +10353,16 @@ static u8 __rtl_get_hw_ver(struct usb_device *udev) version =3D RTL_VER_16; break; case 0x2020: - version =3D RTL_VER_17; + pkg_det =3D __rtl_get_pkg_det(udev); + if (pkg_det =3D=3D 0x1e || pkg_det =3D=3D 0x1c) { + version =3D RTL_VER_17_QFN68; + } else if (pkg_det =3D=3D 0x18 || pkg_det =3D=3D 0x1a) { + version =3D RTL_VER_17_QFN100; + } else { + version =3D RTL_VER_UNKNOWN; + dev_info(&udev->dev, "Unknown package %#02x\n", + pkg_det); + } break; default: version =3D RTL_VER_UNKNOWN; @@ -10459,7 +10521,8 @@ static int rtl8152_probe_once(struct usb_interface = *intf, case RTL_VER_13: case RTL_VER_15: case RTL_VER_16: - case RTL_VER_17: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: netdev->max_mtu =3D size_to_mtu(16 * 1024); break; case RTL_VER_01: --=20 2.34.1 From nobody Sat Sep 26 08:38:28 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D38AF402B8F; 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Thu, 3 Sep 2026 15:28:54 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Thu, 3 Sep 2026 15:28:54 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 3/8] r8152: refactor rtl8156_enable, rtl8156_up, and rtl8156_down Date: Thu, 3 Sep 2026 15:28:47 +0800 Message-ID: <20260903072852.58695-4-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL8156B and RTL8157/8159 have different enable, up, and down sequences from RTL8156. Add dedicated rtl8156b_enable (VER_12/13/15), rtl8157_enable, rtl8157_up, and rtl8157_down (VER_16/17) instead of handling per-version differences with inline version guards. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 235 ++++++++++++++++++++++++++++++++-------- 1 file changed, 189 insertions(+), 46 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 080b5890efb4e..aee8d57684205 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -6440,31 +6440,16 @@ static int rtl8156_enable(struct r8152 *tp) if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return -ENODEV; =20 - if (tp->version < RTL_VER_12) - r8156_fc_parameter(tp); - + r8156_fc_parameter(tp); set_tx_qlen(tp); rtl_set_eee_plus(tp); =20 - switch (tp->version) { - case RTL_VER_10: - case RTL_VER_11: - break; - default: - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, - RX_AGGR_NUM_MASK); - break; - } - r8153_set_rx_early_timeout(tp); r8153_set_rx_early_size(tp); =20 speed =3D rtl8152_get_speed(tp); rtl_set_ifg(tp, speed); =20 - if (tp->version >=3D RTL_VER_16) - return rtl_enable(tp); - if (speed & _2500bps) ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, IDLE_SPDWN_EN); @@ -6472,12 +6457,10 @@ static int rtl8156_enable(struct r8152 *tp) ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, IDLE_SPDWN_EN); =20 - if (tp->version < RTL_VER_12) { - if (speed & _1000bps) - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); - else if (speed & _500bps) - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); - } + if (speed & _1000bps) + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); + else if (speed & _500bps) + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); =20 if (tp->udev->speed =3D=3D USB_SPEED_HIGH) { /* USB 0xb45e[3:0] l1_nyet_hird */ @@ -6502,6 +6485,67 @@ static void rtl8156_disable(struct r8152 *tp) rtl8153_disable(tp); } =20 +static int rtl8156b_enable(struct r8152 *tp) +{ + u16 speed; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return -ENODEV; + + set_tx_qlen(tp); + rtl_set_eee_plus(tp); + + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); + + r8153_set_rx_early_timeout(tp); + r8153_set_rx_early_size(tp); + + speed =3D rtl8152_get_speed(tp); + rtl_set_ifg(tp, speed); + + if (speed & _2500bps) + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); + else + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); + + if (tp->udev->speed =3D=3D USB_SPEED_HIGH) { + /* USB 0xb45e[3:0] l1_nyet_hird */ + if (is_flow_control(speed)) + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf); + else + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1); + } + + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + usleep_range(1000, 2000); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + + return rtl_enable(tp); +} + +static int rtl8157_enable(struct r8152 *tp) +{ + u16 speed; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return -ENODEV; + + set_tx_qlen(tp); + rtl_set_eee_plus(tp); + + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); + + r8153_set_rx_early_timeout(tp); + r8153_set_rx_early_size(tp); + + speed =3D rtl8152_get_speed(tp); + rtl_set_ifg(tp, speed); + + return rtl_enable(tp); +} + static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 d= uplex, u32 advertising) { @@ -6862,8 +6906,7 @@ static void rtl8156_up(struct r8152 *tp) return; =20 r8153b_u1u2en(tp, false); - if (tp->version < RTL_VER_16) - r8153_u2p3en(tp, false); + r8153_u2p3en(tp, false); r8153_aldps_en(tp, false); =20 rxdy_gated_en(tp, true); @@ -6876,8 +6919,7 @@ static void rtl8156_up(struct r8152 *tp) =20 ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 - if (tp->version >=3D RTL_VER_16) - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1, BIT(3)); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1, BIT(3)); =20 ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 @@ -6899,11 +6941,11 @@ static void rtl8156_up(struct r8152 *tp) ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, RXFIFO_FULL_MASK, 0x08); =20 - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, PLA_MCU_SPDWN_EN); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 - if (tp->version < RTL_VER_16) - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, - RG_PWRDN_EN | ALL_SPEED_OFF); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, + RG_PWRDN_EN | ALL_SPEED_OFF); =20 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); =20 @@ -6913,10 +6955,19 @@ static void rtl8156_up(struct r8152 *tp) } =20 r8153_aldps_en(tp, true); - if (tp->version < RTL_VER_16) - r8153_u2p3en(tp, true); + r8153_u2p3en(tp, true); =20 - if (tp->version < RTL_VER_16 && tp->udev->speed >=3D USB_SPEED_SUPER) + switch (tp->version) { + case RTL_VER_13: + case RTL_VER_15: + /* Enable Clear_SDR */ + ocp_word_set_bits(tp, MCU_TYPE_USB, 0xd3ca, BIT(15)); + break; + default: + break; + } + + if (tp->udev->speed >=3D USB_SPEED_SUPER) r8153b_u1u2en(tp, true); } =20 @@ -6929,12 +6980,9 @@ static void rtl8156_down(struct r8152 *tp) =20 ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, PLA_MCU_SPDWN_EN); - r8153b_u1u2en(tp, false); - if (tp->version < RTL_VER_16) { - r8153_u2p3en(tp, false); - r8153b_power_cut_en(tp, false); - } + r8153_u2p3en(tp, false); + r8153b_power_cut_en(tp, false); r8153_aldps_en(tp, false); =20 ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); @@ -6956,7 +7004,102 @@ static void rtl8156_down(struct r8152 *tp) */ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); =20 - ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE); + + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, + NOW_IS_OOB | DIS_MCU_CLROOB); + + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + rtl_rx_vlan_en(tp, true); + rxdy_gated_en(tp, false); + + ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR, + RCR_APM | RCR_AM | RCR_AB); + + r8153_aldps_en(tp, true); +} + +static void rtl8157_up(struct r8152 *tp) +{ + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + + r8153b_u1u2en(tp, false); + r8153_aldps_en(tp, false); + + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + + ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); + + rtl8152_nic_reset(tp); + rtl_reset_bmu(tp); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); + + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1, BIT(3)); + + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); + + rtl8156_change_mtu(tp); + + /* share FIFO settings */ + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, RXFIFO_FULL_MASK, + 0x08); + + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, + RG_PWRDN_EN | ALL_SPEED_OFF); + + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); + + if (tp->saved_wolopts !=3D __rtl_get_wol(tp)) { + netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n"); + __rtl_set_wol(tp, tp->saved_wolopts); + } + + r8153_aldps_en(tp, true); + + /* Clear_SDR */ + ocp_byte_set_bits(tp, MCU_TYPE_USB, 0xd378, BIT(7)); + ocp_word_clr_bits(tp, MCU_TYPE_USB, 0xcd06, BIT(15)); +} + +static void rtl8157_down(struct r8152 *tp) +{ + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { + rtl_drop_queued_tx(tp); + return; + } + + r8153b_u1u2en(tp, false); + r8153_aldps_en(tp, false); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); + + /* RX FIFO settings for OOB */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16); + + rtl_disable(tp); + rtl_reset_bmu(tp); + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1526); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64); + + /* Clear teredo wake event. bit[15:8] is the teredo wakeup + * type. Set it to zero. bits[7:0] are the W1C bits about + * the events. Set them to all 1 to clear them. + */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); + + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE); + + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, + NOW_IS_OOB | DIS_MCU_CLROOB); =20 ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 @@ -10084,7 +10227,7 @@ static int rtl_ops_init(struct r8152 *tp) tp->eee_adv =3D MDIO_EEE_1000T | MDIO_EEE_100TX; tp->eee_adv2 =3D MDIO_EEE_2_5GT; ops->init =3D r8156b_init; - ops->enable =3D rtl8156_enable; + ops->enable =3D rtl8156b_enable; ops->disable =3D rtl8153_disable; ops->up =3D rtl8156_up; ops->down =3D rtl8156_down; @@ -10123,10 +10266,10 @@ static int rtl_ops_init(struct r8152 *tp) tp->eee_adv =3D MDIO_EEE_1000T | MDIO_EEE_100TX; tp->eee_adv2 =3D MDIO_EEE_2_5GT | MDIO_EEE_5GT; ops->init =3D r8157_init; - ops->enable =3D rtl8156_enable; + ops->enable =3D rtl8157_enable; ops->disable =3D rtl8153_disable; - ops->up =3D rtl8156_up; - ops->down =3D rtl8156_down; + ops->up =3D rtl8157_up; + ops->down =3D rtl8157_down; ops->unload =3D rtl8153_unload; ops->eee_get =3D r8153_get_eee; ops->eee_set =3D r8152_set_eee; @@ -10146,10 +10289,10 @@ static int rtl_ops_init(struct r8152 *tp) tp->eee_adv =3D MDIO_EEE_100TX | MDIO_EEE_1000T | MDIO_EEE_10GT; tp->eee_adv2 =3D MDIO_EEE_2_5GT | MDIO_EEE_5GT; ops->init =3D r8159_init; - ops->enable =3D rtl8156_enable; + ops->enable =3D rtl8157_enable; ops->disable =3D rtl8153_disable; - ops->up =3D rtl8156_up; - ops->down =3D rtl8156_down; + ops->up =3D rtl8157_up; + ops->down =3D rtl8157_down; ops->unload =3D rtl8153_unload; ops->eee_get =3D r8153_get_eee; ops->eee_set =3D r8152_set_eee; --=20 2.34.1 From nobody Sat Sep 26 08:38:28 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E52062C11D9; Thu, 3 Sep 2026 07:29:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 3 Sep 2026 15:28:54 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Thu, 3 Sep 2026 15:28:54 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 4/8] r8152: refactor r8157_hw_phy_cfg Date: Thu, 3 Sep 2026 15:28:48 +0800 Message-ID: <20260903072852.58695-5-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL8159 has a different hw_phy_cfg sequence from RTL8157. Split r8157_hw_phy_cfg into r8157_hw_phy_cfg (VER_16) and r8159_hw_phy_cfg (VER_17_*), update PHY parameters for RTL8156B/57/59, and add sram2 bitwise operation helpers. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 168 +++++++++++++++++++++++++++++++++------- 1 file changed, 139 insertions(+), 29 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index aee8d57684205..00bd3afe79033 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -655,6 +655,7 @@ enum spd_duplex { /* OCP_POWER_CFG */ #define EEE_CLKDIV_EN 0x8000 #define EN_ALDPS 0x0004 +#define EN_ALDPS_PLLOFF 0x0002 #define EN_10M_PLLOFF 0x0001 =20 /* OCP_EEE_CONFIG1 */ @@ -1992,6 +1993,16 @@ static void sram2_write_w0w1(struct r8152 *tp, u16 a= ddr, u16 clear, u16 set) ocp_reg_write(tp, OCP_SRAM2_DATA, data); } =20 +static void sram2_set_bits(struct r8152 *tp, u16 addr, u16 set) +{ + sram2_write_w0w1(tp, addr, 0, set); +} + +static void sram2_clr_bits(struct r8152 *tp, u16 addr, u16 clear) +{ + sram2_write_w0w1(tp, addr, clear, 0); +} + static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear) { int data; @@ -8082,6 +8093,9 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) sram_write(tp, 0x8074, 0x2417); sram_write(tp, 0x807a, 0x2417); =20 + /* Nway DACONB parameters */ + ocp_reg_w0w1(tp, 0xa4ca, 0x6000, 0x0040); + /* XG PLL */ ocp_reg_w0w1(tp, 0xbf84, 0xe000, 0xa000); break; @@ -8158,11 +8172,14 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); =20 /* Advanced Power Saving parameter */ - ocp_reg_set_bits(tp, 0xa430, BIT(0) | BIT(1)); + ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_10M_PLLOFF | EN_ALDPS_PLLOFF); =20 /* Disable ALDPS force mode */ ocp_reg_clr_bits(tp, 0xa44a, BIT(2)); =20 + /* Disable bypass_turn_off_clk_in_aldps */ + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, 0xd3c8, BIT(0)); + switch (tp->version) { case RTL_VER_16: /* XG_INRX parameter */ @@ -8178,7 +8195,7 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) sram2_write_w0w1(tp, 0x8078, 0xff00, 0x3000); =20 /* green mode */ - sram2_write_w0w1(tp, 0x89e9, 0xff00, 0); + sram2_clr_bits(tp, 0x89e9, 0xff00); sram2_write_w0w1(tp, 0x8ffd, 0xff00, 0x0100); sram2_write_w0w1(tp, 0x8ffe, 0xff00, 0x0200); sram2_write_w0w1(tp, 0x8fff, 0xff00, 0x0400); @@ -8284,12 +8301,85 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) sram2_write_w0w1(tp, 0x807c, 0xff00, 0x5000); sram2_write_w0w1(tp, 0x809d, 0xff00, 0x5000); break; + default: + break; + } + + if (rtl_phy_patch_request(tp, true, true)) + return; + + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); + + ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, EN_10M_CLKDIV); + + tp->ups_info._10m_ckdiv =3D true; + tp->ups_info.eee_plloff_100 =3D false; + tp->ups_info.eee_plloff_giga =3D false; + + ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); + tp->ups_info.eee_ckdiv =3D true; + + rtl_phy_patch_request(tp, false, true); + + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); + + ocp_reg_clr_bits(tp, 0xa428, BIT(9)); + ocp_reg_clr_bits(tp, 0xa5ea, BIT(0) | BIT(1)); + tp->ups_info.lite_mode =3D 0; + + if (tp->eee_en) + rtl_eee_enable(tp, true); + + r8153_aldps_en(tp, true); + r8152b_enable_fc(tp); + + set_bit(PHY_RESET, &tp->flags); +} + +static void r8159_hw_phy_cfg(struct r8152 *tp) +{ + u16 data; + + r8156b_wait_loading_flash(tp); + + ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); + + data =3D r8153_phy_status(tp, 0); + switch (data) { + case PHY_STAT_EXT_INIT: + rtl8152_apply_firmware(tp, true); + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + break; + case PHY_STAT_LAN_ON: + case PHY_STAT_PWRDN: + default: + rtl8152_apply_firmware(tp, false); + break; + } =20 + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + r8153_aldps_en(tp, false); + + data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); + WARN_ON_ONCE(data !=3D PHY_STAT_LAN_ON); + + /* PFM mode */ + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); + + /* Advanced Power Saving parameter */ + ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_10M_PLLOFF | EN_ALDPS_PLLOFF); + + /* Disable ALDPS force mode */ + ocp_reg_clr_bits(tp, 0xa44a, BIT(2)); + + /* Disable bypass_turn_off_clk_in_aldps */ + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, 0xd3c8, BIT(0)); + + switch (tp->version) { case RTL_VER_17_QFN68: case RTL_VER_17_QFN100: - /* Disable bypass turn off clk in ALDPS */ - ocp_byte_clr_bits(tp, MCU_TYPE_PLA, 0xd3c8, BIT(0)); - /* Power level tuning * test mode power level */ @@ -8299,22 +8389,35 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) sram_write_w0w1(tp, 0x81ae, 0xff00, 0x0f00); sram_write_w0w1(tp, 0x81b9, 0xff00, 0xb900); /* normal link TX filter */ - sram2_write_w0w1(tp, 0x83b0, 0x0e00, 0); - sram2_write_w0w1(tp, 0x83c5, 0x0e00, 0); - sram2_write_w0w1(tp, 0x83da, 0x0e00, 0); - sram2_write_w0w1(tp, 0x83ef, 0x0e00, 0); + sram2_clr_bits(tp, 0x83b0, 0x0e00); + sram2_clr_bits(tp, 0x83c5, 0x0e00); + sram2_clr_bits(tp, 0x83da, 0x0e00); + sram2_clr_bits(tp, 0x83ef, 0x0e00); + + ocp_reg_w0w1(tp, 0xbf38, 0x01f0, 0x0160); + ocp_reg_w0w1(tp, 0xbf3a, 0x001f, 0x0014); + /* shorten CLKS latency */ + ocp_reg_clr_bits(tp, 0xbf28, BIT(14) | BIT(13)); + ocp_reg_clr_bits(tp, 0xbf2c, BIT(15) | BIT(14)); + /* CMP_Timer on MP_Timer=3D333 + * GPHY OCP 0xbf28 bit[0] =3D 0x1 + * GPHY OCP 0xbf28 bit[6:1] =3D 0x3 + * GPHY OCP 0xbf28 bit[12:7] =3D 0x3 + */ + ocp_reg_w0w1(tp, 0xbf28, 0x1fff, 0x0187); + ocp_reg_w0w1(tp, 0xbf2a, 0x3f, 0x03); =20 /* AFE power saving for 2.5G & 5G */ sram_write(tp, 0x8173, 0x8620); sram_write(tp, 0x8175, 0x8671); =20 - sram_write_w0w1(tp, 0x817c, 0, BIT(13)); - sram_write_w0w1(tp, 0x8187, 0, BIT(13)); - sram_write_w0w1(tp, 0x8192, 0, BIT(13)); - sram_write_w0w1(tp, 0x819d, 0, BIT(13)); - sram_write_w0w1(tp, 0x81a8, BIT(13), 0); - sram_write_w0w1(tp, 0x81b3, BIT(13), 0); - sram_write_w0w1(tp, 0x81be, 0, BIT(13)); + sram_set_bits(tp, 0x817c, BIT(13)); + sram_set_bits(tp, 0x8187, BIT(13)); + sram_set_bits(tp, 0x8192, BIT(13)); + sram_set_bits(tp, 0x819d, BIT(13)); + sram_clr_bits(tp, 0x81a8, BIT(13)); + sram_clr_bits(tp, 0x81b3, BIT(13)); + sram_set_bits(tp, 0x81be, BIT(13)); =20 sram_write_w0w1(tp, 0x817d, 0xff00, 0xa600); sram_write_w0w1(tp, 0x8188, 0xff00, 0xa600); @@ -8378,10 +8481,10 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) sram2_write_w0w1(tp, 0x84b2, 0xff00, 0x6000); /* Training AAGC PAR (with uc2 patch) */ sram2_write(tp, 0x8ffc, 0x6008); - sram2_write(tp, 0x8ffe, 0xf450); + sram2_write(tp, 0x8ffe, 0xf4ff); /* DAC BGK */ - sram2_write_w0w1(tp, 0x8015, 0, BIT(9)); - sram2_write_w0w1(tp, 0x8016, 0, BIT(11)); + sram2_set_bits(tp, 0x8015, BIT(9)); + sram2_set_bits(tp, 0x8016, BIT(11)); sram2_write_w0w1(tp, 0x8fe6, 0xff00, 0x0800); sram2_write(tp, 0x8fe4, 0x2114); /* 10G PBO table */ @@ -8390,14 +8493,14 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) sram2_write_w0w1(tp, 0x864b, 0xff00, 0xdc00); /* 2.5G ado power window size */ sram2_write_w0w1(tp, 0x8154, 0xc000, 0x4000); - sram2_write_w0w1(tp, 0x8158, 0xc000, 0); + sram2_clr_bits(tp, 0x8158, 0xc000); /* 10G lock far */ sram2_write(tp, 0x826c, 0xffff); sram2_write(tp, 0x826e, 0xffff); /* XG INRX parameter */ sram2_write_w0w1(tp, 0x8872, 0xff00, 0x0e00); - sram_write_w0w1(tp, 0x8012, 0, BIT(11)); - sram_write_w0w1(tp, 0x8012, 0, BIT(14)); + sram_set_bits(tp, 0x8012, BIT(11)); + sram_set_bits(tp, 0x8012, BIT(14)); ocp_reg_set_bits(tp, 0xb576, BIT(0)); sram_write_w0w1(tp, 0x834a, 0xff00, 0x0700); sram2_write_w0w1(tp, 0x8217, 0x3f00, 0x2a00); @@ -8408,7 +8511,7 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) /* improve UBE */ ocp_reg_set_bits(tp, 0xbf0c, 0x7 << 11); /* close Sparse NEC, improve connect 5EUU cable performance */ - sram2_write_w0w1(tp, 0x88de, 0xff00, 0); + sram2_clr_bits(tp, 0x88de, 0xff00); /* 5G slave compatibility issue */ sram2_write(tp, 0x80b4, 0x5195); =20 @@ -8467,8 +8570,15 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) sram2_write(tp, 0x8ff8, 0xaa5a); =20 sram2_write_w0w1(tp, 0x88d5, 0xff00, 0x0200); - break; =20 + /* spdchg_pga1_lpf_cap */ + sram_write_w0w1(tp, 0x84bb, 0xff00, 0x0a00); + sram_write_w0w1(tp, 0x84c0, 0xff00, 0x1600); + + /* ENET PLL jitter improvement */ + ocp_reg_w0w1(tp, 0xbf8a, 0xfc00, 0x2000); + ocp_reg_set_bits(tp, 0xbf88, BIT(2)); + break; default: break; } @@ -8478,9 +8588,9 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) =20 ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); =20 - ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, EN_10M_CLKDIV); - - tp->ups_info._10m_ckdiv =3D true; + ocp_reg_clr_bits(tp, OCP_DOWN_SPEED, + EN_EEE_100 | EN_EEE_1000 | EN_10M_CLKDIV); + tp->ups_info._10m_ckdiv =3D false; tp->ups_info.eee_plloff_100 =3D false; tp->ups_info.eee_plloff_giga =3D false; =20 @@ -8492,7 +8602,7 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); =20 ocp_reg_clr_bits(tp, 0xa428, BIT(9)); - ocp_reg_clr_bits(tp, 0xa5ea, BIT(0) | BIT(1)); + ocp_reg_clr_bits(tp, 0xa5ea, BIT(0) | BIT(1) | BIT(2)); tp->ups_info.lite_mode =3D 0; =20 if (tp->eee_en) @@ -10297,7 +10407,7 @@ static int rtl_ops_init(struct r8152 *tp) ops->eee_get =3D r8153_get_eee; ops->eee_set =3D r8152_set_eee; ops->in_nway =3D rtl8153_in_nway; - ops->hw_phy_cfg =3D r8157_hw_phy_cfg; + ops->hw_phy_cfg =3D r8159_hw_phy_cfg; ops->autosuspend_en =3D rtl8157_runtime_enable; ops->change_mtu =3D rtl8156_change_mtu; tp->rx_buf_sz =3D 48 * 1024; --=20 2.34.1 From nobody Sat Sep 26 08:38:28 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DB6940B0F3; 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Thu, 3 Sep 2026 15:28:55 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Thu, 3 Sep 2026 15:28:54 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 5/8] r8152: support rtl8157_unload and rtl8157_change_mtu Date: Thu, 3 Sep 2026 15:28:49 +0800 Message-ID: <20260903072852.58695-6-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL8157 and RTL8159 need a dedicated unload callback to disable interrupt mitigation and use r8157_power_cut_en instead of r8153_power_cut_en. They also need a dedicated change_mtu that scales MTPS between 10K and 16K depending on the MTU, unlike rtl8156_change_mtu which uses a fixed MTPS. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 47 ++++++++++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 00bd3afe79033..1bf465b1cacb3 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -7031,6 +7031,28 @@ static void rtl8156_down(struct r8152 *tp) r8153_aldps_en(tp, true); } =20 +static void rtl8157_change_mtu(struct r8152 *tp) +{ + u32 max_pkt_size =3D mtu_to_size(tp->netdev->mtu); + u32 ocp_data; + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, max_pkt_size); + + /* Use at least 10K for MTPS */ + ocp_data =3D max_t(u32, max_pkt_size, 10 * 1024) / 64; + + /* 16 * 1024 / 64 =3D 0x100, so the max is 0xff for 8 bits data */ + ocp_data =3D min_t(u32, ocp_data, 0xff); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, ocp_data); + r8156_fc_parameter(tp); + + /* TX share fifo free credit full threshold */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, + ALIGN(max_pkt_size + tp->tx_desc.size, 1024) / 16); +} + static void rtl8157_up(struct r8152 *tp) { if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) @@ -7055,7 +7077,7 @@ static void rtl8157_up(struct r8152 *tp) =20 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); =20 - rtl8156_change_mtu(tp); + rtl8157_change_mtu(tp); =20 /* share FIFO settings */ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, RXFIFO_FULL_MASK, @@ -10187,11 +10209,6 @@ static void rtl8153_unload(struct r8152 *tp) return; =20 r8153_power_cut_en(tp, false); - - if (tp->version >=3D RTL_VER_16) { - /* Disable Interrupt Mitigation */ - ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xcf04, BIT(0) | BIT(1) | BIT(2) | B= IT(7)); - } } =20 static void rtl8153b_unload(struct r8152 *tp) @@ -10202,6 +10219,16 @@ static void rtl8153b_unload(struct r8152 *tp) r8153b_power_cut_en(tp, false); } =20 +static void rtl8157_unload(struct r8152 *tp) +{ + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + + r8157_power_cut_en(tp, false); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xcf04, + BIT(0) | BIT(1) | BIT(2) | BIT(7)); +} + static int r8152_desc_init(struct r8152 *tp) { tp->rx_desc.size =3D sizeof(struct rx_desc); @@ -10380,13 +10407,13 @@ static int rtl_ops_init(struct r8152 *tp) ops->disable =3D rtl8153_disable; ops->up =3D rtl8157_up; ops->down =3D rtl8157_down; - ops->unload =3D rtl8153_unload; + ops->unload =3D rtl8157_unload; ops->eee_get =3D r8153_get_eee; ops->eee_set =3D r8152_set_eee; ops->in_nway =3D rtl8153_in_nway; ops->hw_phy_cfg =3D r8157_hw_phy_cfg; ops->autosuspend_en =3D rtl8157_runtime_enable; - ops->change_mtu =3D rtl8156_change_mtu; + ops->change_mtu =3D rtl8157_change_mtu; tp->rx_buf_sz =3D 32 * 1024; tp->support_2500full =3D 1; tp->support_5000full =3D 1; @@ -10403,13 +10430,13 @@ static int rtl_ops_init(struct r8152 *tp) ops->disable =3D rtl8153_disable; ops->up =3D rtl8157_up; ops->down =3D rtl8157_down; - ops->unload =3D rtl8153_unload; + ops->unload =3D rtl8157_unload; ops->eee_get =3D r8153_get_eee; ops->eee_set =3D r8152_set_eee; ops->in_nway =3D rtl8153_in_nway; ops->hw_phy_cfg =3D r8159_hw_phy_cfg; ops->autosuspend_en =3D rtl8157_runtime_enable; - ops->change_mtu =3D rtl8156_change_mtu; + ops->change_mtu =3D rtl8157_change_mtu; tp->rx_buf_sz =3D 48 * 1024; tp->support_2500full =3D 1; tp->support_5000full =3D 1; --=20 2.34.1 From nobody Sat Sep 26 08:38:28 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A4DA4446E3; Thu, 3 Sep 2026 07:29:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420600; cv=none; b=rfSDOJXaQYHL228nZgfsJMEEEw7XcZz2WET2mKfmF5DpDRiMqVJJpo9WgCAaWtQtmyqBi7AfeCm612BJf5B2XeCZvrXGcIgacziHDL1pr+fcBZRFSilW1fPnbibWTzn/MSnz9KYS2EbM0lJOSNCMIZPDEFxLoJUPe+HT0kef0CA= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1788420535; bh=5jxBQ5lAZdNFYIj+oj2mBMwePFOO853wUxi5efmd17U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=W38kw8feyutWX7v8YmaAhlzThddkAdfjN56VUNiuVO6Aq+Bbu2+ap7ia73vCNWsEM Cm09xQ0smr7JuLujfdeEi0QPFomUQfgGtZPOpLSe6l2cUduWy4mTr7veWb0Z2NA9LM kusGbRkSkjYv10c2GH3UuHizdXciyCOo2JssQPtOpZqo7ascSq6WWj+4hS6AEcxGFc xhX/nD4OTF4fX9FsyGcAG/qba6Pr1Am0VrUxEtbiEAiPGp7q3IjfT8IyIZuKlJElhf H57jk+jDWDlbdd5ECU/DtVDdnH0ecvAcEpiHrV9Evc2tzUBrwoQ9AbYkxfgyOwTX5H ZcfOz6gxyzLLg== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 6837StFcA3295546 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Sep 2026 15:28:55 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Thu, 3 Sep 2026 15:28:54 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 6/8] r8152: add TGPHY access support Date: Thu, 3 Sep 2026 15:28:50 +0800 Message-ID: <20260903072852.58695-7-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL8157 and RTL8159 support a TGPHY interface via USB_TGPHY_CMD/ADDR/DATA, which allows reading/writing PHY registers without changing the OCP base address at 0xe86c. Add r8157_phy_read/phy_write implementing this path, and add phy_read/phy_write function pointers to struct rtl_ops to dispatch the correct access method per chip. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 94 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 1bf465b1cacb3..b4253b00aa64e 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -162,6 +162,9 @@ #define USB_ADV_ADDR 0xd5d6 #define USB_ADV_DATA 0xd5d8 #define USB_ADV_CMD 0xd5dc +#define USB_TGPHY_ADDR 0xd630 +#define USB_TGPHY_DATA 0xd632 +#define USB_TGPHY_CMD 0xd634 #define USB_UPS_CTRL 0xd800 #define USB_POWER_CUT 0xd80a #define USB_MISC_0 0xd81a @@ -511,6 +514,10 @@ #define ADV_CMD_WR BIT(1) #define ADV_CMD_IP BIT(2) =20 +/* USB_TGPHY_CMD */ +#define TGPHY_CMD_BUSY BIT(0) +#define TGPHY_CMD_WR BIT(1) + /* USB_UPS_CTRL */ #define POWER_CUT 0x0100 =20 @@ -960,6 +967,8 @@ struct r8152 { void (*hw_phy_cfg)(struct r8152 *tp); void (*autosuspend_en)(struct r8152 *tp, bool enable); void (*change_mtu)(struct r8152 *tp); + u16 (*phy_read)(struct r8152 *tp, u16 addr); + void (*phy_write)(struct r8152 *tp, u16 addr, u16 data); } rtl_ops; =20 struct ups_info { @@ -1666,7 +1675,7 @@ static void ocp_write_byte(struct r8152 *tp, u16 type= , u16 index, u32 data) generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); } =20 -static u16 ocp_reg_read(struct r8152 *tp, u16 addr) +static u16 r8152_phy_read(struct r8152 *tp, u16 addr) { u16 ocp_base, ocp_index; =20 @@ -1680,7 +1689,7 @@ static u16 ocp_reg_read(struct r8152 *tp, u16 addr) return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); } =20 -static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) +static void r8152_phy_write(struct r8152 *tp, u16 addr, u16 data) { u16 ocp_base, ocp_index; =20 @@ -1694,6 +1703,16 @@ static void ocp_reg_write(struct r8152 *tp, u16 addr= , u16 data) ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); } =20 +static u16 ocp_reg_read(struct r8152 *tp, u16 addr) +{ + return tp->rtl_ops.phy_read(tp, addr); +} + +static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) +{ + tp->rtl_ops.phy_write(tp, addr, data); +} + static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 va= lue) { ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); @@ -2030,6 +2049,61 @@ static int r8152_mdio_test_and_clr_bit(struct r8152 = *tp, u16 addr, u16 clear) return data & clear; } =20 +static int wait_tgphy_cmd_ready(struct r8152 *tp) +{ + u16 ocp_data; + + return poll_timeout_us(ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, + USB_TGPHY_CMD), + !(ocp_data & TGPHY_CMD_BUSY), 2000, 20000, + false); +} + +static int rtl_tgphy_access(struct r8152 *tp, u16 addr, u16 *data, bool wr= ite) +{ + u16 cmd =3D 0; + int ret; + + ret =3D wait_tgphy_cmd_ready(tp); + if (ret < 0) + goto out; + + if (write) { + cmd |=3D TGPHY_CMD_WR; + ocp_write_word(tp, MCU_TYPE_USB, USB_TGPHY_DATA, *data); + } + + ocp_write_word(tp, MCU_TYPE_USB, USB_TGPHY_ADDR, addr); + + cmd |=3D TGPHY_CMD_BUSY; + ocp_write_word(tp, MCU_TYPE_USB, USB_TGPHY_CMD, cmd); + + if (!write) { + ret =3D wait_tgphy_cmd_ready(tp); + if (ret < 0) + goto out; + + *data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_TGPHY_DATA); + } + +out: + return ret; +} + +static u16 r8157_phy_read(struct r8152 *tp, u16 addr) +{ + u16 data =3D 0; + + rtl_tgphy_access(tp, addr, &data, false); + + return data; +} + +static void r8157_phy_write(struct r8152 *tp, u16 addr, u16 data) +{ + rtl_tgphy_access(tp, addr, &data, true); +} + static int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); =20 @@ -10281,6 +10355,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->in_nway =3D rtl8152_in_nway; ops->hw_phy_cfg =3D r8152b_hw_phy_cfg; ops->autosuspend_en =3D rtl_runtime_suspend_enable; + ops->phy_read =3D r8152_phy_read; + ops->phy_write =3D r8152_phy_write; tp->rx_buf_sz =3D 16 * 1024; tp->eee_en =3D true; tp->eee_adv =3D MDIO_EEE_100TX; @@ -10303,6 +10379,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg =3D r8153_hw_phy_cfg; ops->autosuspend_en =3D rtl8153_runtime_enable; ops->change_mtu =3D rtl8153_change_mtu; + ops->phy_read =3D r8152_phy_read; + ops->phy_write =3D r8152_phy_write; if (tp->udev->speed < USB_SPEED_SUPER) tp->rx_buf_sz =3D 16 * 1024; else @@ -10326,6 +10404,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg =3D r8153b_hw_phy_cfg; ops->autosuspend_en =3D rtl8153b_runtime_enable; ops->change_mtu =3D rtl8153_change_mtu; + ops->phy_read =3D r8152_phy_read; + ops->phy_write =3D r8152_phy_write; tp->rx_buf_sz =3D 32 * 1024; tp->eee_en =3D true; tp->eee_adv =3D MDIO_EEE_1000T | MDIO_EEE_100TX; @@ -10350,6 +10430,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg =3D r8156_hw_phy_cfg; ops->autosuspend_en =3D rtl8156_runtime_enable; ops->change_mtu =3D rtl8156_change_mtu; + ops->phy_read =3D r8152_phy_read; + ops->phy_write =3D r8152_phy_write; tp->rx_buf_sz =3D 48 * 1024; tp->support_2500full =3D 1; r8152_desc_init(tp); @@ -10375,6 +10457,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg =3D r8156b_hw_phy_cfg; ops->autosuspend_en =3D rtl8156_runtime_enable; ops->change_mtu =3D rtl8156_change_mtu; + ops->phy_read =3D r8152_phy_read; + ops->phy_write =3D r8152_phy_write; tp->rx_buf_sz =3D 48 * 1024; r8152_desc_init(tp); break; @@ -10392,6 +10476,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg =3D r8153c_hw_phy_cfg; ops->autosuspend_en =3D rtl8153c_runtime_enable; ops->change_mtu =3D rtl8153c_change_mtu; + ops->phy_read =3D r8152_phy_read; + ops->phy_write =3D r8152_phy_write; tp->rx_buf_sz =3D 32 * 1024; tp->eee_en =3D true; tp->eee_adv =3D MDIO_EEE_1000T | MDIO_EEE_100TX; @@ -10414,6 +10500,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg =3D r8157_hw_phy_cfg; ops->autosuspend_en =3D rtl8157_runtime_enable; ops->change_mtu =3D rtl8157_change_mtu; + ops->phy_read =3D r8157_phy_read; + ops->phy_write =3D r8157_phy_write; tp->rx_buf_sz =3D 32 * 1024; tp->support_2500full =3D 1; tp->support_5000full =3D 1; @@ -10437,6 +10525,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg =3D r8159_hw_phy_cfg; ops->autosuspend_en =3D rtl8157_runtime_enable; ops->change_mtu =3D rtl8157_change_mtu; + ops->phy_read =3D r8157_phy_read; + ops->phy_write =3D r8157_phy_write; tp->rx_buf_sz =3D 48 * 1024; tp->support_2500full =3D 1; tp->support_5000full =3D 1; --=20 2.34.1 From nobody Sat Sep 26 08:38:28 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5B262D3A75; Thu, 3 Sep 2026 07:29:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420575; cv=none; b=AYFiRhndje54FSeLQdp5DRLZCFd7NiA0AIjc8eqhlK4G4kcsbPHthirRTncqSreJaRP+xOClczJ92rCC1QHCTLtSoFCxPVuC0tRXb+t2Bby9XFYV7Uh2bdLbIWlUeQt/h8PsSN4ImJYCqvf3jh/SfxW+1gY5MygiURDp+sLs4T0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420575; c=relaxed/simple; bh=Igb+iYGZbsFXlIKDs7XxvHb48lylOBFGEOkUhUkrpQA=; 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Thu, 3 Sep 2026 15:28:54 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 7/8] r8152: support rtl_fc_pause_pkt_en() Date: Thu, 3 Sep 2026 15:28:51 +0800 Message-ID: <20260903072852.58695-8-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The flow control patch was inline in r8156b_init and missing for RTL8156 and RTL8157/8159. Extract it as rtl_fc_pause_pkt_en(), call it from r8156_init and r8156b_init during chip init, and call it from rtl8157_enable with the current link speed for RTL8157 and RTL8159. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 112 ++++++++++++++++++++++++++++++++++------ 1 file changed, 97 insertions(+), 15 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index b4253b00aa64e..2a96f3609c2b0 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -89,6 +89,7 @@ #define PLA_MTPS 0xe615 #define PLA_TXFIFO_CTRL 0xe618 #define PLA_TXFIFO_FULL 0xe61a +#define PLA_PAUSE_LIMIT 0xe61e #define PLA_RSTTALLY 0xe800 #define PLA_CR 0xe813 #define PLA_CRWECR 0xe81c @@ -301,6 +302,10 @@ #define MTPS_JUMBO (12 * 1024 / 64) #define MTPS_DEFAULT (6 * 1024 / 64) =20 +/* PLA_PAUSE_LIMIT */ +#define PAUSE_LIMIT_EN BIT(3) +#define PAUSE_LIMIT_MASK 0xf0 + /* PLA_RSTTALLY */ #define TALLY_RESET 0x0001 =20 @@ -6095,6 +6100,93 @@ static void r8152b_enter_oob(struct r8152 *tp) RCR_APM | RCR_AM | RCR_AB); } =20 +static void rtl_fc_pause_pkt_en(struct r8152 *tp, u16 speed) +{ + int log2_ratio, ratio; + u16 num_pause_pkts; + u32 ocp_data; + + switch (tp->version) { + case RTL_VER_10: + case RTL_VER_11: + ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, + CTRL_TIMER_EN | (1000 / 8)); + + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, + FLOW_CTRL_PATCH_OPT); + + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + break; + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); + + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); + + /* enable fc timer and set timer to 600 ms. */ + ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, + CTRL_TIMER_EN | (600 / 8)); + + ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); + if (!(ocp_data & DACK_DET_EN)) + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, + FLOW_CTRL_PATCH_2); + + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + break; + case RTL_VER_16: + case RTL_VER_17_QFN68: + case RTL_VER_17_QFN100: + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); + + num_pause_pkts =3D 0xa; + ratio =3D 10000; + + if (!(speed & LINK_STATUS)) { + dev_dbg(&tp->intf->dev, "No link\n"); + goto no_link; + } else if (speed & _10bps) { + ratio /=3D 10; + } else if (speed & _100bps) { + ratio /=3D 100; + } else if (speed & _1000bps) { + ratio /=3D 1000; + } else if (speed & _2500bps) { + ratio /=3D 2500; + } else if (speed & _5000bps) { + ratio /=3D 5000; + } else if (speed & _10000bps) { + ratio /=3D 10000; + } else { + dev_err(&tp->intf->dev, "Unknown link speed\n"); + goto no_link; + } + + log2_ratio =3D ilog2(ratio); + num_pause_pkts -=3D log2_ratio; + + /* Round up if ratio is more than halfway to the next power of 2. + * Floating-point is avoided by rewriting + * ratio > 1.5 * 2^log2_ratio as + * 2 * ratio > 3 * 2^log2_ratio + */ + if (2 * ratio > 3 * (1 << log2_ratio)) + num_pause_pkts--; + +no_link: + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_PAUSE_LIMIT, + PAUSE_LIMIT_MASK | PAUSE_LIMIT_EN, + num_pause_pkts << 4); + + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PAUSE_LIMIT, + PAUSE_LIMIT_EN); + break; + default: + break; + } +} + static int r8153_pre_firmware_1(struct r8152 *tp) { int i; @@ -6626,6 +6718,8 @@ static int rtl8157_enable(struct r8152 *tp) r8153_set_rx_early_size(tp); =20 speed =3D rtl8152_get_speed(tp); + rtl_fc_pause_pkt_en(tp, speed); + rtl_set_ifg(tp, speed); =20 return rtl_enable(tp); @@ -8758,6 +8852,8 @@ static void r8156_init(struct r8152 *tp) =20 usb_enable_lpm(tp->udev); =20 + rtl_fc_pause_pkt_en(tp, 0); + r8156_mac_clk_spd(tp, true); =20 ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, @@ -8794,7 +8890,6 @@ static void r8156b_u2phy_backup(struct r8152 *tp) =20 static void r8156b_init(struct r8152 *tp) { - u32 ocp_data; u16 data; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) @@ -8859,20 +8954,7 @@ static void r8156b_init(struct r8152 *tp) =20 usb_enable_lpm(tp->udev); =20 - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); - - ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); - - /* enable fc timer and set timer to 600 ms. */ - ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, - CTRL_TIMER_EN | (600 / 8)); - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); - if (!(ocp_data & DACK_DET_EN)) - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, - FLOW_CTRL_PATCH_2); - - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + rtl_fc_pause_pkt_en(tp, 0); =20 r8156_mac_clk_spd(tp, true); =20 --=20 2.34.1 From nobody Sat Sep 26 08:38:28 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96D593FB07E; Thu, 3 Sep 2026 07:29:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420574; cv=none; b=WWrWr/k1NtaT+ijVgD/qv7k9h0EgVmXLzlpFBmulaIYdfvLGIQANY9ubMq3D13yg5utzi+DbKuubPiDDRvXPogUPslpp+gaN37uT8t0MSIFvWGu435gv1ADU/LIfWYJc84NFE/6R7GYRmWHGDejtPYu3i/5K8iVP/AGAlR+1jl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420574; c=relaxed/simple; bh=u1AEGd4v8vg+H9oKGs7YnfpOC2CfkuqfXBVIKdp7dSM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 8/8] r8152: support UPS for RTL8157 and RTL8159 Date: Thu, 3 Sep 2026 15:28:52 +0800 Message-ID: <20260903072852.58695-9-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL8157 and RTL8159 support UPS but need different enable logic and EEE flag handling than RTL8156. Add r8157_ups_en() and extend r8156_ups_flags() with per-speed EEE flags (100M through 10G) and 5G/10G speed entries for VER_16/17. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 110 +++++++++++++++++++++++++++++++++++----- 1 file changed, 98 insertions(+), 12 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 2a96f3609c2b0..d219b242e1b2d 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -132,6 +132,7 @@ #define USB_BURST_SIZE 0xcfc0 #define USB_FW_FIX_EN0 0xcfca #define USB_FW_FIX_EN1 0xcfcc +#define USB_FW_USE_VER 0xcfd7 #define USB_LPM_CONFIG 0xcfd8 #define USB_ECM_OPTION 0xcfee #define USB_CSTMR 0xcfef /* RTL8153A */ @@ -619,6 +620,11 @@ #define UPS_FLAGS_250M_CKDIV BIT(2) #define UPS_FLAGS_EN_ALDPS BIT(3) #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) +#define UPS_FLAGS_EN_100M_EEE BIT(9) +#define UPS_FLAGS_EN_1000M_EEE BIT(10) +#define UPS_FLAGS_EN_2500M_EEE BIT(11) +#define UPS_FLAGS_EN_5000M_EEE BIT(12) +#define UPS_FLAGS_EN_10G_EEE BIT(13) #define UPS_FLAGS_SPEED_MASK (0xf << 16) #define ups_flags_speed(x) ((x) << 16) #define UPS_FLAGS_EN_EEE BIT(20) @@ -4185,8 +4191,27 @@ static void r8156_ups_flags(struct r8152 *tp) if (tp->ups_info.aldps) ups_flags |=3D UPS_FLAGS_EN_ALDPS; =20 - if (tp->ups_info.eee) - ups_flags |=3D UPS_FLAGS_EN_EEE; + if (tp->ups_info.eee) { + switch (tp->version) { + case RTL_VER_17_QFN68: + if (tp->eee_adv & MDIO_EEE_10GT) + ups_flags |=3D UPS_FLAGS_EN_10G_EEE; + fallthrough; + case RTL_VER_16: + if (tp->eee_adv & MDIO_EEE_100TX) + ups_flags |=3D UPS_FLAGS_EN_100M_EEE; + if (tp->eee_adv & MDIO_EEE_1000T) + ups_flags |=3D UPS_FLAGS_EN_1000M_EEE; + if (tp->eee_adv2 & MDIO_EEE_2_5GT) + ups_flags |=3D UPS_FLAGS_EN_2500M_EEE; + if (tp->eee_adv2 & MDIO_EEE_5GT) + ups_flags |=3D UPS_FLAGS_EN_5000M_EEE; + break; + default: + ups_flags |=3D UPS_FLAGS_EN_EEE; + break; + } + } =20 if (tp->ups_info.flow_control) ups_flags |=3D UPS_FLAGS_EN_FLOW_CTR; @@ -4237,20 +4262,33 @@ static void r8156_ups_flags(struct r8152 *tp) case NWAY_2500M_FULL: ups_flags |=3D ups_flags_speed(9); break; + case NWAY_5000M_FULL: + ups_flags |=3D ups_flags_speed(10); + break; + case NWAY_10000M_FULL: + ups_flags |=3D ups_flags_speed(11); + break; default: break; } =20 - switch (tp->ups_info.lite_mode) { - case 1: - ups_flags |=3D 0 << 5; - break; - case 2: - ups_flags |=3D 2 << 5; + switch (tp->version) { + case RTL_VER_16: + case RTL_VER_17_QFN68: break; - case 0: default: - ups_flags |=3D 1 << 5; + switch (tp->ups_info.lite_mode) { + case 1: + ups_flags |=3D 0 << 5; + break; + case 2: + ups_flags |=3D 2 << 5; + break; + case 0: + default: + ups_flags |=3D 1 << 5; + break; + } break; } =20 @@ -4422,6 +4460,35 @@ static void r8156_ups_en(struct r8152 *tp, bool enab= le) } } =20 +static void r8157_ups_en(struct r8152 *tp, bool enable) +{ + if (enable) { + r8156_ups_flags(tp); + + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE | PHASE2_EN); + + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2, + UPS_FORCE_PWR_DOWN); + } else { + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE); + + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, + UPS_FORCE_PWR_DOWN); + + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { + /* clear USB fw_ver_reg */ + ocp_write_byte(tp, MCU_TYPE_USB, USB_FW_USE_VER, 0); + + tp->rtl_ops.hw_phy_cfg(tp); + + rtl8152_set_speed(tp, tp->autoneg, tp->speed, + tp->duplex, tp->advertising); + } + } +} + static void r8153_power_cut_en(struct r8152 *tp, bool enable) { if (enable) @@ -4580,9 +4647,28 @@ static void rtl8157_runtime_enable(struct r8152 *tp,= bool enable) r8153b_u1u2en(tp, false); r8157_u2p3en(tp, false); rtl_runtime_suspend_enable(tp, true); + + switch (tp->version) { + case RTL_VER_16: + case RTL_VER_17_QFN68: + r8157_ups_en(tp, true); + break; + default: + break; + } } else { r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); + + switch (tp->version) { + case RTL_VER_16: + case RTL_VER_17_QFN68: + r8157_ups_en(tp, false); + break; + default: + break; + } + r8157_u2p3en(tp, true); if (tp->udev->speed >=3D USB_SPEED_SUPER) r8153b_u1u2en(tp, true); @@ -9027,7 +9113,7 @@ static void r8157_init(struct r8152 *tp) ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); =20 r8157_power_cut_en(tp, false); - r8156_ups_en(tp, false); + r8157_ups_en(tp, false); r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); =20 @@ -9137,7 +9223,7 @@ static void r8159_init(struct r8152 *tp) ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); =20 r8157_power_cut_en(tp, false); - r8156_ups_en(tp, false); + r8157_ups_en(tp, false); r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); =20 --=20 2.34.1