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charset="utf-8" Add the compatible string for the Tegra264 XUSB PHY. A dedicated compatible string is used instead of falling back to nvidia,tegra234-xusb-padctl, because Tegra264 is not programming-compatible with Tegra234, even though they share the same DT property set. The driver selects per-SoC data from the compatible string, and Tegra264 differs from Tegra234 in at least: - Tegra264 uses hardware tracking mode (trk_hw_mode), while Tegra234 disables it. - On Tegra234, CYA_TRK_CODE_UPDATE_ON_IDLE needs to be cleared so that the calibration values can be captured while the controller is still in reset. Tegra264 does not require this, and the corresponding handling is not even present for it. A fallback of nvidia,tegra234-xusb-padctl would let an OS that only knows about Tegra234 probe Tegra264 with the wrong programming sequence. This is also why Tegra234 did not fall back to nvidia,tegra194-xusb-padctl in this same binding: the DT schema is shared, but each generation needs its own compatible. Signed-off-by: Wayne Chang Acked-by: Conor Dooley Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- V2 -> V3: Add rationale to the commit message for why Tegra264 does not use a fallback compatible, per Krzysztof's and Conor's review. V1 -> V2: No change .../devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-pad= ctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padct= l.yaml index d8de900a4fce..f6fe3c90b5b0 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml @@ -45,6 +45,7 @@ properties: enum: - nvidia,tegra194-xusb-padctl - nvidia,tegra234-xusb-padctl + - nvidia,tegra264-xusb-padctl =20 reg: items: --=20 2.25.1 From nobody Sat Sep 26 08:37:37 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012046.outbound.protection.outlook.com [40.93.195.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76124377ABE; Thu, 3 Sep 2026 07:20:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Sing-Han Chen The USB2 PAD tracking clock is an optional clock so use devm_clk_get_optional() so a missing clock in devicetree is represented as NULL and probe can continue. clk_prepare_enable() and clk_disable_unprepare() already treat a NULL clock as a no-op. Signed-off-by: Sing-Han Chen Signed-off-by: Wayne Chang Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- V2 -> V3: No change V1 -> V2: No change drivers/phy/tegra/xusb-tegra186.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-teg= ra186.c index 60156aea2707..800be0cbb3f9 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -1045,7 +1045,7 @@ tegra186_usb2_pad_probe(struct tegra_xusb_padctl *pad= ctl, goto out; } =20 - priv->usb2_trk_clk =3D devm_clk_get(&pad->dev, "trk"); + priv->usb2_trk_clk =3D devm_clk_get_optional(&pad->dev, "trk"); if (IS_ERR(priv->usb2_trk_clk)) { err =3D PTR_ERR(priv->usb2_trk_clk); dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err); --=20 2.25.1 From nobody Sat Sep 26 08:37:37 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010008.outbound.protection.outlook.com [52.101.61.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E656641A502; 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charset="utf-8" On Tegra264, the UTMI bias tracking circuit runs at 1 MHz and needs more cycles for the biases to settle than on earlier SoCs such as Tegra234. The existing timeout is therefore not long enough and can cause spurious polling failures during bias pad power-on. Therefore, increase the timeout to 200 cycles to support Tegra264 devices Signed-off-by: Wayne Chang Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- V2 -> V3: No change V1 -> V2: No change drivers/phy/tegra/xusb-tegra186.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-teg= ra186.c index 800be0cbb3f9..9c1bcd4a72ac 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -636,7 +636,7 @@ static void tegra186_utmi_bias_pad_power_on(struct tegr= a_xusb_padctl *padctl) =20 if (padctl->soc->poll_trk_completed) { err =3D padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, - USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100); + USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 200); if (err) { /* The failure with polling on trk complete will not * cause the failure of powering on the bias pad. --=20 2.25.1 From nobody Sat Sep 26 08:37:37 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011003.outbound.protection.outlook.com [40.107.208.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AD6A40B0F3; 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charset="utf-8" Add support for the XUSB pad controller for Tegra264. Most of the Tegra264 XUSB PADCTL registers definition and programming sequence are the same as Tegra234, Tegra264 XUSB PADCTL can share the same driver with Tegra186, Tegra194, and Tegra234 XUSB PADCTL. Signed-off-by: Wayne Chang Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- V2 -> V3: No change V1 -> V2 : Rebase and update the has_per_pad_term for Tegra264 drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 27 ++++++++++++++++++++++++++- drivers/phy/tegra/xusb.c | 6 ++++++ drivers/phy/tegra/xusb.h | 3 +++ 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index eeeea72de117..33a695d4ed59 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -8,4 +8,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D xusb-tegra= 210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) +=3D xusb-tegra186.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) +=3D xusb-tegra186.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) +=3D xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_264_SOC) +=3D xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) +=3D phy-tegra194-p2u.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-teg= ra186.c index 9c1bcd4a72ac..322efdea0d80 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -1668,7 +1668,8 @@ EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); #endif =20 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ - IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) + IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \ + IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC) static const char * const tegra194_xusb_padctl_supply_names[] =3D { "avdd-usb", "vclamp-usb", @@ -1753,6 +1754,30 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_pad= ctl_soc =3D { .has_per_pad_term =3D true, }; EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); + +const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc =3D { + .num_pads =3D ARRAY_SIZE(tegra194_pads), + .pads =3D tegra194_pads, + .ports =3D { + .usb2 =3D { + .ops =3D &tegra186_usb2_port_ops, + .count =3D 4, + }, + .usb3 =3D { + .ops =3D &tegra186_usb3_port_ops, + .count =3D 4, + }, + }, + .ops =3D &tegra186_xusb_padctl_ops, + .supply_names =3D tegra194_xusb_padctl_supply_names, + .num_supplies =3D ARRAY_SIZE(tegra194_xusb_padctl_supply_names), + .supports_gen2 =3D true, + .poll_trk_completed =3D true, + .trk_hw_mode =3D true, + .supports_lp_cfg_en =3D true, + .has_per_pad_term =3D true, +}; +EXPORT_SYMBOL_GPL(tegra264_xusb_padctl_soc); #endif =20 MODULE_AUTHOR("JC Kuo "); diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 9d74c0ecc31b..d0d0b252a205 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -77,6 +77,12 @@ static const struct of_device_id tegra_xusb_padctl_of_ma= tch[] =3D { .compatible =3D "nvidia,tegra234-xusb-padctl", .data =3D &tegra234_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_264_SOC) + { + .compatible =3D "nvidia,tegra264-xusb-padctl", + .data =3D &tegra264_xusb_padctl_soc, + }, #endif { } }; diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 77609e54de66..d8d799d9e752 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -514,5 +514,8 @@ extern const struct tegra_xusb_padctl_soc tegra194_xusb= _padctl_soc; #if defined(CONFIG_ARCH_TEGRA_234_SOC) extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_264_SOC) +extern const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc; +#endif =20 #endif /* __PHY_TEGRA_XUSB_H */ --=20 2.25.1