From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EC9C44AB9B; Wed, 2 Sep 2026 22:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389661; cv=none; b=trxXByk0FGl7o99Jr/5Ck422BXE+YxYkuKF5MxS2j7ZOVVWjmP+Av7rsyLCfymiPXVrAgWHIz/VGeiVC2NuWcNLo2fTf6eXgXkorwVDMvXcp643OMOIRqbHwY+takULw0qUCZRQtDg37uDjafjhpeWsWVU4L9+CJB0VY6yIPRAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389661; c=relaxed/simple; bh=nePb0kyyjWqyo41M5uZpRKK5NGs/j1qWip36phnEELk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pMcFHxllAm8cYgy8nnI6Ah6NR4ksuIQsnQkYROXlfp42m6/gbUAmY7jT5no2KKifF5XH3XiTfta+mQtWs8mo8acIcn21ma4IrrNsdpmqCd3eszvwRBMnXIfunpw3/pS0jhOIRWQ/QhcLWS3z96NrPy0wX1KnJGNEK1jB3yX3tLs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=qJ0FAEqo; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="qJ0FAEqo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788389652; bh=nePb0kyyjWqyo41M5uZpRKK5NGs/j1qWip36phnEELk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qJ0FAEqoVEni6OUx9R97n5GmDzyoSnozbyED1+7NLNSVYzAAqlWgc1qPMXcZ+qHPo mflP5+PlA038RmY9qTuDUpp1xZWJkWpB2LDRNTH2lfCWTJp+WwqrliYVHHWxnmGf5n uax01CbgekhA4amgL5ffe3ps4I/b9Rmj2uZEBC9BZDpADsBPXEcAJn86Ny8Q2KdmV2 9dE/4kXLRnj5EVDMV/kLn2+lp1pqH5sDrcI+nhe24miuI43RI66m0tNaif8p4Dme+6 Gx5ujoy57OiyelXuzTG+EKxD1nxgBz1D3tpKfjQizzrvYH6+DwXU0mV0p6StCCZXkk Sza6vZXr6ACKA== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7876A17E0934; Thu, 03 Sep 2026 00:54:12 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:08 +0300 Subject: [PATCH v4 01/14] dt-bindings: display: vop2: Add missing reset properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-1-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 Document the VOP2 resets corresponding to the AXI, AHB and DCLK_VP0..2 clocks, which are common to all supported SoCs, plus DCLK_VP3 which is provided only on RK3588. While at it, move 'iommus' in the example up into the expected position to keep the properties in alphabetical order. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Cristian Ciocaltea --- .../bindings/display/rockchip/rockchip-vop2.yaml | 46 ++++++++++++++++++= +++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vo= p2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.= yaml index 93da1fb9adc4..f993cef0323b 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -82,6 +82,20 @@ properties: - {} - {} =20 + resets: + minItems: 5 + maxItems: 6 + + reset-names: + minItems: 5 + items: + - const: axi + - const: ahb + - const: dclk_vp0 + - const: dclk_vp1 + - const: dclk_vp2 + - const: dclk_vp3 + rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -148,6 +162,12 @@ allOf: clock-names: maxItems: 5 =20 + resets: + maxItems: 5 + + reset-names: + maxItems: 5 + interrupts: maxItems: 1 =20 @@ -194,6 +214,12 @@ allOf: - {} - const: pll_hdmiphy0 =20 + resets: + maxItems: 5 + + reset-names: + maxItems: 5 + interrupts: minItems: 4 =20 @@ -246,6 +272,12 @@ allOf: - const: pll_hdmiphy0 - const: pll_hdmiphy1 =20 + resets: + minItems: 6 + + reset-names: + minItems: 6 + interrupts: maxItems: 1 =20 @@ -289,9 +321,19 @@ examples: "dclk_vp0", "dclk_vp1", "dclk_vp2"; - power-domains =3D <&power RK3568_PD_VO>; - rockchip,grf =3D <&grf>; iommus =3D <&vop_mmu>; + power-domains =3D <&power RK3568_PD_VO>; + resets =3D <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_VOP0>, + <&cru SRST_VOP1>, + <&cru SRST_VOP2>; + reset-names =3D "axi", + "ahb", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; + rockchip,grf =3D <&grf>; vop_out: ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1180744D03B; Wed, 2 Sep 2026 22:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389659; cv=none; b=EsASUJmUmZuLqFEQCpgwkyr5Uo3hDClOnHwvcHewSXW/83atNYIUFlyRLRZRbyJkkxxS7chQF9vArd73kFBAPFjIKWOSVkadnMxevGWM/9XcPzt9IUNqgW3ZCbz2uWLm3ubDhs/a+/b6zz1sky1e2AECb4w+Ssyl4BlOdAqM0Tc= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-2-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Igor Paunovic X-Mailer: b4 0.15.2 vop2_enable() returns void, so callers cannot tell whether powering up the VOP2 succeeded. Additionally, if rockchip_drm_dma_attach_device() fails, vop2_enable() returns without disabling the core clocks or dropping the runtime PM reference taken earlier, leaking both. Make vop2_enable() return int and unwind all resources on every failure path. As disabling the core clocks is also needed in vop2_disable(), factor it out into a local helper used by both. Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") Reported-by: Sashiko Closes: https://lore.kernel.org/all/20260623202043.8BFE21F000E9@smtp.kernel= .org/ Link: https://lore.kernel.org/all/20260623202043.8BFE21F000E9@smtp.kernel.o= rg/ Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 39 +++++++++++++++++++-----= ---- 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index b2f3a579bbe5..819ea3400bcd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -860,6 +860,13 @@ static int vop2_core_clks_prepare_enable(struct vop2 *= vop2) return ret; } =20 +static void vop2_core_clks_disable_unprepare(struct vop2 *vop2) +{ + clk_disable_unprepare(vop2->pclk); + clk_disable_unprepare(vop2->aclk); + clk_disable_unprepare(vop2->hclk); +} + static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2) { u32 pd; @@ -871,7 +878,7 @@ static void rk3588_vop2_power_domain_enable_all(struct = vop2 *vop2) vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd); } =20 -static void vop2_enable(struct vop2 *vop2) +static int vop2_enable(struct vop2 *vop2) { int ret; u32 version; @@ -879,25 +886,24 @@ static void vop2_enable(struct vop2 *vop2) ret =3D pm_runtime_resume_and_get(vop2->dev); if (ret < 0) { drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); - return; + return ret; } =20 ret =3D vop2_core_clks_prepare_enable(vop2); - if (ret) { - pm_runtime_put_sync(vop2->dev); - return; - } + if (ret) + goto err_put_pm; =20 ret =3D rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); if (ret) { - drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); - return; + drm_err(vop2->drm, "failed to attach dma mapping: %d\n", ret); + goto err_disable_clks; } =20 version =3D vop2_readl(vop2, RK3568_VERSION_INFO); if (version !=3D vop2->version) { drm_err(vop2->drm, "Hardware version(0x%08x) mismatch\n", version); - return; + ret =3D -EINVAL; + goto err_detach_dma; } =20 /* @@ -932,6 +938,17 @@ static void vop2_enable(struct vop2 *vop2) VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); vop2_writel(vop2, RK3568_SYS1_INT_EN, VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); + + return 0; + +err_detach_dma: + rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); +err_disable_clks: + vop2_core_clks_disable_unprepare(vop2); +err_put_pm: + pm_runtime_put_sync(vop2->dev); + + return ret; } =20 static void vop2_disable(struct vop2 *vop2) @@ -942,9 +959,7 @@ static void vop2_disable(struct vop2 *vop2) =20 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register); =20 - clk_disable_unprepare(vop2->pclk); - clk_disable_unprepare(vop2->aclk); - clk_disable_unprepare(vop2->hclk); + vop2_core_clks_disable_unprepare(vop2); } =20 static bool vop2_vp_dsp_lut_is_enabled(struct vop2_video_port *vp) --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBE7644A40F; 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Thu, 03 Sep 2026 00:54:13 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:10 +0300 Subject: [PATCH v4 03/14] drm/rockchip: vop2: Balance state on atomic_enable() error paths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-3-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Igor Paunovic X-Mailer: b4 0.15.2 vop2_crtc_atomic_enable() prepares vp->dclk and, for the first CRTC, calls vop2_enable(), incrementing the shared vop2->enable_count before programming VOP2 registers. Two later failure points return early with only vop2_unlock(), leaking the dclk prepare, the enable_count increment, and the core clocks / PM runtime reference from vop2_enable(). Since the disable path decrements enable_count unconditionally, the leaked increment skews the count, causing an underflow or premature shutdown of core clocks and PM runtime while another CRTC is active. Moreover, cleaning up on the enable error paths alone is insufficient. A CRTC whose atomic_enable() bailed is still committed as active, so vop2_crtc_atomic_disable() still runs its full teardown, releasing the same dclk prepare and enable_count a second time, thus underflowing both counts and, where vop2_enable() ran, touching VOP registers with core clocks gated. Fix this by reverting exactly what was set up on failure, and track the per-VP bring-up state so atomic_disable() skips teardown when atomic_enable() never completed. Additionally, ensure any further hardware programming is also skipped within the affected RPM commit tail, i.e. in the callbacks gated by drm_atomic_helper_commit_planes(): vop2_crtc_atomic_begin(), vop2_plane_atomic_update{update|disable}() and vop2_crtc_atomic_flush(). Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") Reported-by: Sashiko Closes: https://lore.kernel.org/all/20260623202043.8BFE21F000E9@smtp.kernel= .org/ Link: https://lore.kernel.org/all/20260623202043.8BFE21F000E9@smtp.kernel.o= rg/ Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 68 ++++++++++++++++++++++--= ---- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 6 +++ 2 files changed, 59 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 819ea3400bcd..060f9395a235 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1033,6 +1033,9 @@ static void vop2_crtc_atomic_disable(struct drm_crtc = *crtc, =20 vop2_lock(vop2); =20 + if (!vp->enabled) + goto out_unlock; + old_crtc_state =3D drm_atomic_get_old_crtc_state(state, crtc); drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); =20 @@ -1063,11 +1066,14 @@ static void vop2_crtc_atomic_disable(struct drm_crt= c *crtc, =20 clk_disable_unprepare(vp->dclk); =20 + vp->enabled =3D false; + vop2->enable_count--; =20 if (!vop2->enable_count) vop2_disable(vop2); =20 +out_unlock: vop2_unlock(vop2); =20 if (crtc->state->event && !crtc->state->active) { @@ -1197,13 +1203,21 @@ static void vop2_plane_atomic_disable(struct drm_pl= ane *plane, struct drm_plane_state *old_pstate =3D NULL; struct vop2_win *win =3D to_vop2_win(plane); struct vop2 *vop2 =3D win->vop2; + struct vop2_video_port *vp; =20 drm_dbg(vop2->drm, "%s disable\n", win->data->name); =20 if (state) old_pstate =3D drm_atomic_get_old_plane_state(state, plane); - if (old_pstate && !old_pstate->crtc) - return; + + if (old_pstate) { + if (!old_pstate->crtc) + return; + + vp =3D to_vop2_video_port(old_pstate->crtc); + if (!vp->enabled) + return; + } =20 vop2_win_disable(win); vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); @@ -1298,6 +1312,9 @@ static void vop2_plane_atomic_update(struct drm_plane= *plane, if (WARN_ON(!crtc)) return; =20 + if (!vp->enabled) + return; + if (!pstate->visible) { vop2_plane_atomic_disable(plane, state); return; @@ -1803,8 +1820,11 @@ static void vop2_crtc_atomic_enable(struct drm_crtc = *crtc, return; } =20 - if (!vop2->enable_count) - vop2_enable(vop2); + if (!vop2->enable_count) { + ret =3D vop2_enable(vop2); + if (ret) + goto err_unprepare_dclk; + } =20 vop2->enable_count++; =20 @@ -1831,10 +1851,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc = *crtc, clock =3D vop2->ops->setup_intf_mux(vp, rkencoder->crtc_endpoint_id, pol= flags); } =20 - if (!clock) { - vop2_unlock(vop2); - return; - } + if (!clock) + goto err_put_enable_count; =20 if (vcstate->output_mode =3D=3D ROCKCHIP_OUT_MODE_AAAA && !(vp_data->feature & VOP2_VP_FEATURE_OUTPUT_10BIT)) @@ -1852,8 +1870,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, default: drm_err(vop2->drm, "Unknown DRM_MODE_CONNECTOR %d\n", vcstate->output_type); - vop2_unlock(vop2); - return; + goto err_put_enable_count; } else out_mode =3D vcstate->output_mode; @@ -1965,6 +1982,18 @@ static void vop2_crtc_atomic_enable(struct drm_crtc = *crtc, =20 drm_crtc_vblank_on(crtc); =20 + vp->enabled =3D true; + + vop2_unlock(vop2); + + return; + +err_put_enable_count: + if (!--vop2->enable_count) + vop2_disable(vop2); + +err_unprepare_dclk: + clk_disable_unprepare(vp->dclk); vop2_unlock(vop2); } =20 @@ -2023,6 +2052,9 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *c= rtc, struct vop2_video_port *vp =3D to_vop2_video_port(crtc); struct vop2 *vop2 =3D vp->vop2; =20 + if (!vp->enabled) + return; + vop2->ops->setup_overlay(vp); } =20 @@ -2034,13 +2066,19 @@ static void vop2_crtc_atomic_flush(struct drm_crtc = *crtc, struct vop2_video_port *vp =3D to_vop2_video_port(crtc); struct vop2 *vop2 =3D vp->vop2; =20 - /* In case of modeset, gamma lut update already happened in atomic enable= */ - if (!drm_atomic_crtc_needs_modeset(crtc_state) && crtc_state->color_mgmt_= changed) - vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state); + if (vp->enabled) { + /* + * In case of modeset, gamma lut update already happened + * in atomic enable. + */ + if (!drm_atomic_crtc_needs_modeset(crtc_state) && + crtc_state->color_mgmt_changed) + vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state); =20 - vop2_post_config(crtc, false, crtc_state, old_crtc_state); + vop2_post_config(crtc, false, crtc_state, old_crtc_state); =20 - vop2_cfg_done(vp); + vop2_cfg_done(vp); + } =20 spin_lock_irq(&crtc->dev->event_lock); =20 diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index ffcb39c130aa..b209b2d5b96d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -243,6 +243,12 @@ struct vop2_video_port { =20 struct completion dsp_hold_completion; =20 + /** + * @enabled: CRTC fully brought up by atomic_enable(); allows + * atomic_disable() to skip teardown after a failed enable. + */ + bool enabled; + /** * @win_mask: Bitmask of windows attached to the video port; */ --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DE6842E43A; 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Thu, 03 Sep 2026 00:54:14 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:11 +0300 Subject: [PATCH v4 04/14] drm/rockchip: vop2: Send pending event when atomic_enable() fails Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-4-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Igor Paunovic X-Mailer: b4 0.15.2 vop2_crtc_atomic_flush() stashes the CRTC completion event in vp->event and relies on the frame start interrupt (VP_INT_FS_FIELD) to deliver it later via drm_crtc_send_vblank_event(). Since atomic_enable() runs before atomic_flush(), bailing on an error path makes it skip drm_crtc_vblank_on() and leave the video port disabled. atomic_flush() still traps the event in vp->event, but since the port never scans out, the frame start interrupt does not fire and the event is not delivered. Userspace waiting for the flip completion then blocks indefinitely. Note the event cannot be flushed from atomic_disable(), as userspace waits for the completion before committing the next state, so the disable does not arrive and draining it there would deadlock. Use the newly added vp->enabled flag to detect this in atomic_flush() and send the event immediately when the port did not come up, rather than deferring it to an interrupt that will never occur. This also avoids the spurious drm_crtc_vblank_get() WARN previously hit on the failed enable path, where the vblank is not on. Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") Reported-by: Sashiko Closes: https://lore.kernel.org/all/20260706194935.AC7601F000E9@smtp.kernel= .org/ Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 060f9395a235..8755b614df34 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2083,8 +2083,19 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *= crtc, spin_lock_irq(&crtc->dev->event_lock); =20 if (crtc->state->event) { - WARN_ON(drm_crtc_vblank_get(crtc)); - vp->event =3D crtc->state->event; + /* + * A failed atomic_enable() leaves the video port disabled with + * no scanout, so the frame start interrupt that normally + * delivers vp->event never fires. Send the event right away in + * that case to avoid stalling the flip completion. + */ + if (vp->enabled) { + WARN_ON(drm_crtc_vblank_get(crtc)); + vp->event =3D crtc->state->event; + } else { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + } + crtc->state->event =3D NULL; } =20 --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DF8543CED9; Wed, 2 Sep 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389666; cv=none; b=qfpQDj1zfoT2sHE35XEX30h9jrWtaNB2wTfLONaoSUuO0k2Og9/azlt6JrjONGisjMtkPR8SBE0DEo68Yptw635o6QZqsZN6x65HiDFr3qNrippo8JC+D/S3O2Q6z2P+0fNEDYLSUsth12N4AX33hOzWisce6W0HsHyxv0/u600= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389666; c=relaxed/simple; bh=uokXooPe/YyPpbYpuJUZKqfnA74pZwHjqzOJTRd6cqs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GoWWjr1ripXVVv3rg/3p+cZlbLRicUf5WZCSRO/t9S1W5woF5qGevTgldoDYsLBUk+lnqCF0h8VJb2ouYAVZFD6jhcrAxVkMqvH5AQVw3hJN8kGBS04orcStIasgKU38rBKcVzKyZ1ZTW4I4mMUQINAoO9lY8rXt55ztIMwnnPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ASWRh1wV; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ASWRh1wV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788389655; bh=uokXooPe/YyPpbYpuJUZKqfnA74pZwHjqzOJTRd6cqs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ASWRh1wVChyBPbzjq1kQU98yGV59YK+iTLGxXgPnrSmdndmk0Y4g3qc3MkbOxQBbx TloBMyF2XmYbtWwbwV2kArp0F12zEqS6AUhXHT9mDCklZTqEUIlzoQcHa4giyiCCyg PZ5asU8mn5NXwXUP2CnV4QUy93vRc/TeY/iBM/8pNv4w7iZ0c6yimAiG7Kt8X3nE7L ukJvGNQpTZuDmMuqvkBfYtGBZC5FaspIt6WTMU/vFhpt3NFZGddhwMQrMZQgdIIOtw rofjvI9Q2VsstzqfLZtcfB78ol1Y83T5OG1sZw/xLvNs0rLUZGRddUGCPGCs252lUO YO/9b1qyWakvA== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 46A6917E1122; Thu, 03 Sep 2026 00:54:15 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:12 +0300 Subject: [PATCH v4 05/14] drm/rockchip: vop2: Avoid division by zero when computing max_dclk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-5-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Igor Paunovic X-Mailer: b4 0.15.2 The DCLK reparenting logic in vop2_crtc_atomic_enable() is gated only on the presence of an HDMI PHY PLL on the SoC. This condition is true on any board that wires up an HDMI PHY, even when the CRTC is currently driving a non-HDMI output such as DSI or LVDS. Those encoders do not set vcstate->output_bpc, so it stays 0, hence the subsequent DIV_ROUND_CLOSEST_ULL() then divides by zero. Note this division happens before the drm_for_each_encoder_mask() loop that would establish whether the pipe is actually driven by HDMI, so the loop provides no protection. Default bpc to 8 when it would otherwise be 0. The resulting max_dclk value is a don't-care on the non-HDMI paths that trigger this, since the encoder loop will not select the PHY PLL as the DCLK source there. Fixes: b0362c45c401 ("drm/rockchip: vop2: Check bpc before switching DCLK s= ource") Reported-by: Sashiko Closes: https://lore.kernel.org/all/20260623203310.9F8C81F000E9@smtp.kernel= .org/ Link: https://lore.kernel.org/all/20260623203310.9F8C81F000E9@smtp.kernel.o= rg/ Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 8755b614df34..12a6341e3c98 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1931,8 +1931,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, * to 4K@60Hz, if available, otherwise keep using the system CRU. */ if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) { - unsigned long max_dclk =3D DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8, - vcstate->output_bpc); + unsigned int bpc =3D vcstate->output_bpc ?: 8; + unsigned long max_dclk =3D DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8,= bpc); + if (clock <=3D max_dclk) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask)= { struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 930CF449EA0; Wed, 2 Sep 2026 22:54:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389669; cv=none; b=aCWcVi39KCh8NC/a30zADAuNwPlx5aIZW4uU7n5TJWGZwJJWeF/ftPz+mFBFv3o+v/594jKZ2MlLiBXve4Hhm/zSE7UVQf6CF4AN3UEF4DuEmhUyU8vW3V6scjChAMENrMAtpDF5c3AVb/aEFw7HflqHGSFudQzTYJrOe60GDZE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-6-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Igor Paunovic X-Mailer: b4 0.15.2 VOP2_MAX_DCLK_RATE is defined as an unsigned long and is used scaled by the color-depth ratio when computing the maximum DCLK the HDMI PHY PLL can source. On architectures where unsigned long is 32-bit, VOP2_MAX_DCLK_RATE * 8 is evaluated in 32-bit arithmetic and overflows: 4800000000 wraps to 505032704 before it is promoted to the 64-bit argument of DIV_ROUND_CLOSEST_ULL(). At 8 bpc this collapses max_dclk from the intended 600 MHz down to roughly 63 MHz. As a result, low-resolution modes (e.g. 640x480 or 720x480, whose pixel clocks are well under 30 MHz) still pass the clock <=3D max_dclk check and are reparented to the HDMI PHY PLL as expected, but higher-resolution modes such as 1280x720 (~74 MHz), 1920x1080 (~148 MHz) and above are wrongly rejected and fall back to the system CRU as the DCLK source. Define the constant as unsigned long long so that every expression using it is evaluated in 64-bit arithmetic, independent of the width of unsigned long. This future-proofs any additional users of the macro as well. Fixes: b0362c45c401 ("drm/rockchip: vop2: Check bpc before switching DCLK s= ource") Reported-by: Sashiko Closes: https://lore.kernel.org/all/20260623203310.9F8C81F000E9@smtp.kernel= .org/ Link: https://lore.kernel.org/all/20260623203310.9F8C81F000E9@smtp.kernel.o= rg/ Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 12a6341e3c98..c3f72cac6369 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -102,7 +102,7 @@ enum vop2_afbc_format { VOP2_AFBC_FMT_INVALID =3D -1, }; =20 -#define VOP2_MAX_DCLK_RATE 600000000UL +#define VOP2_MAX_DCLK_RATE 600000000ULL =20 /* * bus-format types. --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64AD840F72E; Wed, 2 Sep 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389669; cv=none; b=CuLVESNFD74L5Vnd137FAeowsQkuF3jyV87wMWiZddKyZg23d5KLufR+kBEB55Ynfsma1gri1I/1kitZiCiYCfL5z0VC4qD/e14JnElPIwWOwUqgVB0xJL2W1yeXVEh3TM+82ERnHUT4BTwjiEE9K++u0yRoZ1v5za3ZnhWciyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389669; c=relaxed/simple; bh=nhanI0NgfqdM/AwSXDXRufUIPmxI7Lu+oX5TN4Dvyo0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a3bPTspZ6hE2aev7PD2/+mer9QY8wMrCe5sPdUA99/zs5hs5t4yB5+8F4gwqBhWXlFsWPXkQV70ExSG4exy5wp1c+tQ27NpoOqyFSs8ycXN11UTEaD4vdZdt2ChBuZ+s0RNGkvFTf0EN2UQxgLEQq7PdUAYPOKpjCxPfBXV86pA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=H9Pw8UOV; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="H9Pw8UOV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788389656; bh=nhanI0NgfqdM/AwSXDXRufUIPmxI7Lu+oX5TN4Dvyo0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=H9Pw8UOVCIgmaR3CFlNoUsV/vTX1gDIuu71i2lICLfrpHEDMSy9aG/pU8iAKDhwgU G9ZY6jCf30XzMYq3mgWgSzFIYq31JmIdW82jcSpinIopsZiWYGmrw+I2UCsFWonrMB O+HNrGTb4ok7TxaT4XRuSGXAYRcywYSnL2x0atZwDq/voYiQTs911lUFbEWkICg5JT SlfhHel01c/YK9baJ8jagoVEfKjXKfQu32egQ8naWigs0VIO3hk5K2I3SjJPgTHtsG RkmbbwWTUE4Vzc/QwZaudTvKJInQuFucfszv6Sm12oS0CHxzj3aDxuRhX6EiWEBV2H smM58h90czKXQ== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id A279217E12C2; Thu, 03 Sep 2026 00:54:16 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:14 +0300 Subject: [PATCH v4 07/14] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-7-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 Assert the AXI reset in the CRTC disable path, and the VP DCLK reset in the enable path. These resets are intended to leave the hardware in a clean state for the next use, helping recover from exceptions such as IOMMU page faults, as well as to prevent random display output glitches, such as a blank image, observed when switching modes that also change the color format, e.g. from RGB to YUV420 and vice versa. For now this seems to affect only the RK3588, hence the resets are optional and will be provided in the device tree for this SoC only. Co-developed-by: Andy Yan Signed-off-by: Andy Yan Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 36 ++++++++++++++++++++++++= ++++ drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 4 ++++ 2 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index c3f72cac6369..21b8a5960086 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #include @@ -867,6 +868,26 @@ static void vop2_core_clks_disable_unprepare(struct vo= p2 *vop2) clk_disable_unprepare(vop2->hclk); } =20 +static void vop2_reset_assert_deassert(struct vop2 *vop2, struct reset_con= trol *rstc) +{ + int ret; + + if (!rstc) + return; + + ret =3D reset_control_assert(rstc); + if (ret < 0) { + drm_warn(vop2->drm, "failed to assert reset: %d\n", ret); + return; + } + + udelay(10); + + ret =3D reset_control_deassert(rstc); + if (ret < 0) + drm_err(vop2->drm, "failed to deassert reset: %d\n", ret); +} + static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2) { u32 pd; @@ -953,6 +974,8 @@ static int vop2_enable(struct vop2 *vop2) =20 static void vop2_disable(struct vop2 *vop2) { + vop2_reset_assert_deassert(vop2, vop2->axi_rst); + rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); =20 pm_runtime_put_sync(vop2->dev); @@ -1981,6 +2004,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, =20 vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); =20 + vop2_reset_assert_deassert(vop2, vp->dclk_rst); + drm_crtc_vblank_on(crtc); =20 vp->enabled =3D true; @@ -2596,6 +2621,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) return dev_err_probe(drm->dev, PTR_ERR(vp->dclk), "failed to get %s\n", dclk_name); =20 + vp->dclk_rst =3D devm_reset_control_get_optional_exclusive(vop2->dev, + dclk_name); + if (IS_ERR(vp->dclk_rst)) + return dev_err_probe(drm->dev, PTR_ERR(vp->dclk_rst), + "failed to get %s reset\n", dclk_name); + np =3D of_graph_get_remote_node(dev->of_node, i, -1); if (!np) { drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); @@ -2955,6 +2986,11 @@ static int vop2_bind(struct device *dev, struct devi= ce *master, void *data) return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy1), "failed to get pll_hdmiphy1\n"); =20 + vop2->axi_rst =3D devm_reset_control_get_optional_exclusive(vop2->dev, "a= xi"); + if (IS_ERR(vop2->axi_rst)) + return dev_err_probe(drm->dev, PTR_ERR(vop2->axi_rst), + "failed to get axi reset\n"); + vop2->irq =3D platform_get_irq(pdev, 0); if (vop2->irq < 0) return dev_err_probe(drm->dev, vop2->irq, "cannot find irq for vop2\n"); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index b209b2d5b96d..1c2d7d97a6c2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -165,6 +165,8 @@ enum vop2_win_regs { VOP2_WIN_MAX_REG, }; =20 +struct reset_control; + struct vop2_regs_dump { const char *name; u32 base; @@ -238,6 +240,7 @@ struct vop2_video_port { struct vop2 *vop2; struct clk *dclk; struct clk *dclk_src; + struct reset_control *dclk_rst; unsigned int id; const struct vop2_video_port_data *data; =20 @@ -335,6 +338,7 @@ struct vop2 { struct clk *pclk; struct clk *pll_hdmiphy0; struct clk *pll_hdmiphy1; + struct reset_control *axi_rst; =20 /* optional internal rgb encoder */ struct rockchip_rgb *rgb; --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A2C0451985; Wed, 2 Sep 2026 22:54:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389672; cv=none; b=cwkFLxbZWa+Aw06jkIPonOzakSNFEWItOmQzkSbjPEQ/PVUROg/Gyv5hWnDo+X/OOMJwSkAp5f/6QUHtiPprNq/pZkfjWXJV2xj/u3ol2rDGRCbHaKVXWnV0FXl5vCEISdNEsx6kkBR8Hnq5Dd4jAbe14gN4UzKTLpaqbkMIFCg= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-8-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 Currently the color depth is always factored into the DCLK source decision for HDMI output, which can break certain modes when operating with depths greater than 8 bpc. When the required transmission rate exceeds the 600 MHz limit of the HDMI PHY PLL, e.g. for 4K@60Hz 10-bit RGB output, VOP2 will normally fall back to using the less accurate system CRU as a DCLK source, assuming HDMI 2.1 FRL is supported by the pipeline, otherwise the mode will be rejected. For YUV420 output format this never happens, as it uses half of the RGB bandwidth, hence the rate remains within the PHY PLL limits. On the other hand, YUV422 always transmits two 12-bit components per clock cycle, regardless of the color depth, which from a clock-rate perspective is equivalent to three 8-bit RGB components. For example, 4K@60Hz 10-bit YUV422 requires the same bandwidth as 4K@60Hz 8-bit RGB, typically 594 MHz. However, VOP2 wrongly assumes it needs 742.5 MHz (594 * 10 / 8) and ends up switching the DCLK source. As a consequence, the modes requiring uncommon pixel clocks, such as those corresponding to fractional refresh rates, will fail. An example is 3840x2160@59.94Hz, which would likely rely on the 593.407 MHz clock rate unsupported by the system CRU. Note this only affects YUV422 with color depths greater than 8 bpc; for 8-bit YUV422 the 8/bpc factor is unity and the bandwidth check is already correct. Prevent the incorrect switches of DCLK source to system CRU for YUV422 output format by forcing 8 bpc when checking the bandwidth. Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 21b8a5960086..4b4346cf38cd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1954,7 +1954,15 @@ static void vop2_crtc_atomic_enable(struct drm_crtc = *crtc, * to 4K@60Hz, if available, otherwise keep using the system CRU. */ if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) { - unsigned int bpc =3D vcstate->output_bpc ?: 8; + /* + * YUV422 always transmits two 12-bit components per clock + * cycle, regardless of the color depth, which from a rate + * perspective is equivalent to three 8-bit RGB components. + * Force 8 bpc here so the bandwidth check reflects the actual + * TMDS rate and avoids an unnecessary DCLK source switch. + */ + unsigned int bpc =3D vcstate->output_mode =3D=3D ROCKCHIP_OUT_MODE_YUV42= 2 ? + 8 : (vcstate->output_bpc ?: 8); unsigned long max_dclk =3D DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8,= bpc); =20 if (clock <=3D max_dclk) { --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 713414519A2; Wed, 2 Sep 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389668; cv=none; b=TLbipOVDLZ6/EE8HpfgQSfJ6vaaY+OaCPjumaglPKPAQFZhQrx7tOvrjGaFUtbllDMIwiS21CrKvD90cqpEq17Xl40ZYp1Fqh77difPfkWaUmtf2olu6KFPpyx3hlLRCSYz75b6NL4qN/1SwKSbGBzOv0JTUkcibrdk9tJFITL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389668; c=relaxed/simple; bh=4Y2qxlgOWfwgTAMIt77CU07XuhytRH/hQI3tSCxInDo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DpexsMySMm26SiedPjkpUnktDhZWb4rdO+1/tEiZrd2CxcLFC9B516fEqORT56vtSvjX5gVlOcquHSkKcn6MvwNrMV4ICftjAjyVRQlwQ3AC1A9oIuDivkImCHe59w23PlM0iHieH20rQzo6EBANXI0TNk4Wr9fUPAnI1jqWYBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=XII7FQF7; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="XII7FQF7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788389658; bh=4Y2qxlgOWfwgTAMIt77CU07XuhytRH/hQI3tSCxInDo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XII7FQF7D4ip0eJ8RFs9T5uiC3U5ixz13ooH+KF1pVSchbWcyrg8lGXo1LjzKyjRH wQNybnWL3Bk0uEA+kePRq9Se5mfa8UEMKEqx2YYbKp7N06NRjjV5q733uWaOyjlD/d gfJSwHeI/IGyiB42Rlu22WmTkq/mhcRUDMtOTfB3D2J9lkihDq/QRQ+K7Ybn7OtD5i u7EuKvSjAUg8EGo+sTN9ceGFWXPvUzLK/5yyWJ1SjWTURmjLtmiCbUnhkPN03eem/s Wk7lO7KKt+WepL26FhiJunX2XEFPtVo5Ab0Md0X7qJVm5+sbYzRPSW/eCskVUKdHrM IX4hTlQM7QNpQ== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0A16F17E14D2; Thu, 03 Sep 2026 00:54:18 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:16 +0300 Subject: [PATCH v4 09/14] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-9-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 The DCLK parent switch logic for HDMI0 and HDMI1 PHY PLLs was duplicated, with each endpoint repeating the same clk_get_parent(), clk_set_parent() and error handling calls. Refactor this by first selecting the appropriate PHY PLL clock handle based on the active HDMI endpoint, then performing the parent switch in a single shared code path. Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 36 +++++++++++-------------= ---- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 4b4346cf38cd..e78cddc184d3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1964,42 +1964,34 @@ static void vop2_crtc_atomic_enable(struct drm_crtc= *crtc, unsigned int bpc =3D vcstate->output_mode =3D=3D ROCKCHIP_OUT_MODE_YUV42= 2 ? 8 : (vcstate->output_bpc ?: 8); unsigned long max_dclk =3D DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8,= bpc); + struct clk *pll_hdmiphy =3D NULL; =20 if (clock <=3D max_dclk) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask)= { struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); =20 if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { - if (!vop2->pll_hdmiphy0) - break; - - if (!vp->dclk_src) - vp->dclk_src =3D clk_get_parent(vp->dclk); - - ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI0 PHY PLL: %d\n", - ret); + pll_hdmiphy =3D vop2->pll_hdmiphy0; break; } =20 if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI1) { - if (!vop2->pll_hdmiphy1) - break; - - if (!vp->dclk_src) - vp->dclk_src =3D clk_get_parent(vp->dclk); - - ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI1 PHY PLL: %d\n", - ret); + pll_hdmiphy =3D vop2->pll_hdmiphy1; break; } } } + + if (pll_hdmiphy) { + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); + + ret =3D clk_set_parent(vp->dclk, pll_hdmiphy); + if (ret < 0) + drm_warn(vop2->drm, + "Failed to switch DCLK to HDMI PHY PLL: %d\n", + ret); + } } =20 clk_set_rate(vp->dclk, clock); --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 704474503F1; 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Thu, 03 Sep 2026 00:54:18 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:17 +0300 Subject: [PATCH v4 10/14] drm/rockchip: vop2: Switch to enum vop_csc_format Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-10-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 Improve code readability in vop2_setup_csc_mode() by using enum vop_csc_format for the csc_mode variable, as well as for the return type of the vop2_convert_csc_mode() helper, which already returns CSC_* enumerators. While at it, replace the nonsensical 'csc_mode =3D false' assignment in the no-conversion branch with the equivalent CSC_BT601L, which carries the same value (0) but is type-correct. Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index e78cddc184d3..04db4c037421 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -648,7 +648,7 @@ static void vop2_setup_scale(struct vop2 *vop2, const s= truct vop2_win *win, } } =20 -static int vop2_convert_csc_mode(int csc_mode) +static enum vop_csc_format vop2_convert_csc_mode(int csc_mode) { switch (csc_mode) { case V4L2_COLORSPACE_SMPTE170M: @@ -711,7 +711,7 @@ static void vop2_setup_csc_mode(struct vop2_video_port = *vp, int input_csc =3D V4L2_COLORSPACE_DEFAULT; int output_csc =3D vcstate->color_space; bool r2y_en, y2r_en; - int csc_mode; + enum vop_csc_format csc_mode; =20 if (is_input_yuv && !is_output_yuv) { y2r_en =3D true; @@ -724,7 +724,7 @@ static void vop2_setup_csc_mode(struct vop2_video_port = *vp, } else { y2r_en =3D false; r2y_en =3D false; - csc_mode =3D false; + csc_mode =3D CSC_BT601L; } =20 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AFA84307AB; Wed, 2 Sep 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389669; cv=none; b=BgdD2lF7yDK0BMTcWLBW5sRM4wyIXACllyJsnYS8VJUXJQYU0ufJmq0P+qtJOMs8BUxhPaRCi18QXXG+KvZDQJVMj+A4P8Prlj7x51cP2gW7pGqF6LdgvgwSHaR+x3chRVIe1hUkEngWnwxGqhIH0yt5rdGrjkGjtc2GaIMe0n8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389669; c=relaxed/simple; bh=RLXuKnPox06j4wbM9Vn0tJZHFuu37LGXOLpeZ4QJUyk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Thu, 03 Sep 2026 00:54:19 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:18 +0300 Subject: [PATCH v4 11/14] drm/bridge: dw-hdmi-qp: Log resolution and refresh rate in atomic_enable() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-11-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 The debug entry in the HDMI branch of dw_hdmi_qp_bridge_atomic_enable() logged the mode field as the fixed 'HDMI' label, giving no information about the actual display timing being configured. Extend it to also include the active resolution and refresh rate, retrieved from the CRTC mode in the incoming atomic state: dw_hdmi_qp_bridge_atomic_enable mode=3DHDMI:1920x1080@50Hz fmt=3DRGB rate= =3D185625000 bpc=3D10 This makes the log line self-contained and directly useful when debugging mode-setting issues, format negotiation, or TMDS rate mismatches without having to cross-reference a separate mode dump. Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index cfd1b18c06e6..0e6142301791 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -752,6 +752,8 @@ static void dw_hdmi_qp_bridge_atomic_enable(struct drm_= bridge *bridge, { struct dw_hdmi_qp *hdmi =3D bridge->driver_private; struct drm_connector_state *conn_state; + const struct drm_display_mode *mode; + struct drm_crtc_state *crtc_state; struct drm_connector *connector; unsigned int op_mode; =20 @@ -764,9 +766,15 @@ static void dw_hdmi_qp_bridge_atomic_enable(struct drm= _bridge *bridge, return; =20 if (connector->display_info.is_hdmi) { - dev_dbg(hdmi->dev, "%s mode=3DHDMI %s rate=3D%llu bpc=3D%u\n", __func__, + crtc_state =3D drm_atomic_get_new_crtc_state(state, conn_state->crtc); + mode =3D &crtc_state->mode; + dev_dbg(hdmi->dev, + "%s mode=3DHDMI:%ux%u@%uHz fmt=3D%s rate=3D%llu bpc=3D%u\n", + __func__, mode->hdisplay, mode->vdisplay, + drm_mode_vrefresh(mode), drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_forma= t), conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc); + op_mode =3D 0; hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; } else { --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 982874534AE; Wed, 2 Sep 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389667; cv=none; b=l3w3Pqo9PhucQFIgmEKm01v9uX+3HWHK/3SWVJms0czImxaoPB74tsSXijuNJVTdDedKGVzqbbikTJe4eifrmuELXZjAIby0FBOzNcbZdJ7gV9/vXVox/eD1FXR4h9+UB/pBs0beeCQxPqhCghVqhPM9rxGDXsvFaOUX7R3sTG8= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-12-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 Rockchip DW HDMI QP encoder supports YUV 4:2:2 output through ROCKCHIP_OUT_MODE_YUV422, but was limited to 8-bit depth via MEDIA_BUS_FMT_UYVY8_1X16. Add support for its 10-bit counterpart MEDIA_BUS_FMT_UYVY10_1X20, which carries two 10-bit components per clock cycle on a 20-bit wide bus. YUV 4:2:2 always transmits two 12-bit components per pixel, regardless of the color depth. From a clock-rate perspective this is equivalent to three 8-bit RGB components, so configure the HDMI PHY with 8 bpc when YUV 4:2:2 is in use to keep its output clock aligned with the TMDS character rate. Otherwise the PHY PLL output would be scaled by bpc/8 for higher color depths, producing a clock rate that confuses downstream consumers such as the VOP2 display controller. Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 9c4cf68d79d5..78473f9a0fce 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -215,6 +215,7 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_enc= oder *encoder, s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; break; case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_UYVY10_1X20: s->output_mode =3D ROCKCHIP_OUT_MODE_YUV422; break; case MEDIA_BUS_FMT_UYYVYY8_0_5X24: @@ -226,7 +227,14 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_en= coder *encoder, } =20 phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; - phy_cfg.hdmi.bpc =3D conn_state->hdmi.output_bpc; + /* + * YUV422 always transmits two 12-bit components per clock cycle, + * regardless of the color depth, which from a rate perspective is + * equivalent to three 8-bit RGB components. Force 8 bpc here to + * keep the PHY PLL output aligned with the TMDS character rate. + */ + phy_cfg.hdmi.bpc =3D (s->output_mode =3D=3D ROCKCHIP_OUT_MODE_YUV422 ? + 8 : conn_state->hdmi.output_bpc); =20 ret =3D phy_configure(hdmi->phy, &phy_cfg); if (!ret) { --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 653F444E651; Wed, 2 Sep 2026 22:54:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389673; cv=none; b=ieEYZ1uekmGnbDHyVL+cMSYneypdM0LwPcqVly6XwEFWJA7J4Dgmt0ksuwLXism15hcA4gU/KrcW9WL4kWxkfngrwyczVQJqgi/yttmxVwbIUVCCoknXxixtWXZFFFUfQW70/8z2YiI4+uiz0K8pjNf0Qsyg33H6asu4kyscLrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389673; c=relaxed/simple; bh=doU00+D+YerVdhuX8oEp8HqeUZPH5lDfQa2OrdpPg08=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nEH25EzYRMYnEWPLzF6PhYuo1Ql+dwVLthI7RnZV+rvnRidLp+cDYFOZh/MQyuvlohR0SeAjFkN/IpiMiDOb8QMiV1/i55xhK00g9U7Ecgw1siNmykRgS5Y04qSXw2OL/bpKqzeHwtQkttBCVGLYkLTxZN3FR2OkZabAl3E3B2E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ANHi+++J; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ANHi+++J" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788389660; bh=doU00+D+YerVdhuX8oEp8HqeUZPH5lDfQa2OrdpPg08=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ANHi+++J2Md8u/D8ccNqvdoTO7Cik8rIgQX/iw+qjsxqV7xHCEnXI97HauDrMmtlU UcI90Ei/Cr6QeH4OWsLzxvAQg0ZrplSbGAIZ6Bps9kja7ub0iIZxYHRJt0145ZD61O 1siqZ/XJpn/qjbwPjK9hq22Kc1zj3I6vNdKj0mFuo2Z+jOXIgObue6/gBE6AoYCUqB 91YQ3JDEiTBxPjZS99d7pTKMt0uP82U4DohnumiKonoAuhJnGORzjcylSub4/pql8i /WoGQW18NGTdh///V0ZITqa1O9yXTFSMgsqn8ZcXCisMSs5ldeXN6Yu3WYhvJ+tzrb JEt4HorcZf9Hw== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id C3F7317E35C2; Thu, 03 Sep 2026 00:54:20 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:20 +0300 Subject: [PATCH v4 13/14] drm/rockchip: dw_hdmi_qp: Enable YUV420 output format Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-13-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 Both RK3576 and RK3588 SoCs are capable of driving the YUV420 output color format, and the required bus-format handling and VOP2 support are already in place. Advertise it via the platform supported formats so the HDMI core can select it. YUV420 halves the TMDS bandwidth compared to RGB/YUV444, which enables high-resolution modes such as 4K@60Hz on links that cannot otherwise carry the full-bandwidth signal. Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 78473f9a0fce..1af29066a0a3 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -611,7 +611,8 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev,= struct device *master, =20 plat_data.supported_formats =3D BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444) | BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444) | - BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422); + BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422) | + BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420); =20 encoder =3D &hdmi->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm, dev->of_node); --=20 2.55.0 From nobody Sat Sep 26 09:21:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A1AF450911; Wed, 2 Sep 2026 22:54:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389674; cv=none; b=nglQFbCLanb6KUpNSV8FK/KhjoA2hAYRrIQOhXMYwHPknXXpu/r8bUU25LmU0yZ1kGwXaaCAc1SzAMdkgRFao90oH66qCs/qP2sg9PEUNhyiKq/917JABhEKcBbkGtjzwxUw1wfvvzh+E5VeQ9nb171dqSgCg9UMbYdSlwpaeIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389674; c=relaxed/simple; bh=UsF0ka6JQJB52yMGxTjsFQSKOLo4iowxPUK1+eAGX70=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KArdmkZrVo3OzXRdb2uOXqtgDE/3J4scC5s8C/5HjwgOgnJn1itCeyh2NpJhnVQncpy3ANXKLtPeRPVcVQU2Cjf7wGRg5dYgpU4YnBH4Gjq6e4Irv5o3X5JLDk9c2FhAQFSQTv03C+AplZoh2nNB++shuy7y9F6IYwedti/rM2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=hjEhu5Be; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="hjEhu5Be" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788389661; bh=UsF0ka6JQJB52yMGxTjsFQSKOLo4iowxPUK1+eAGX70=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hjEhu5BewWnQ8GNU+sykpkxRHoAjvI4z6S47LruS2zoJOCX2G+HQDamW0Naez/0tY C9kQJCN8n5aWnR5XRIyuQP7za9/HyL9EDFwFyKsk1IdQgD+a5rZLtUq4Z88xWvEx6z sV/CjSimjRKmR0ZhtKCbgPY5mC8U6QxyFjb2uM1MoHxRNJAjvic21IGvGH+/twMxDb 2DWRXmoX1MhlCASD+/austkZXn7sf0sWVxWk7y7z6aoOdRLznDI+MpK9deKyS3TBy2 c85lXmSxs63n1WCfXavc8nly4GqqYVrQDO4emoprTK9whUi9Q966AShU2AImzl7N9/ oPYM8+tiw5ujQ== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7B9C117E0914; Thu, 03 Sep 2026 00:54:21 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:21 +0300 Subject: [PATCH v4 14/14] arm64: dts: rockchip: Add RK3588 VOP2 resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260903-dw-hdmi-qp-yuv-v4-14-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Igor Paunovic X-Mailer: b4 0.15.2 Add the missing reset properties to VOP2 on RK3588. Co-developed-by: Andy Yan Signed-off-by: Andy Yan Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 376ad04e0786..574264b9cd9c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1651,6 +1651,18 @@ vop: vop@fdd90000 { "pll_hdmiphy0"; iommus =3D <&vop_mmu>; power-domains =3D <&power RK3588_PD_VOP>; + resets =3D <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_D_VOP0>, + <&cru SRST_D_VOP1>, + <&cru SRST_D_VOP2>, + <&cru SRST_D_VOP3>; + reset-names =3D "axi", + "ahb", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3"; rockchip,grf =3D <&sys_grf>; rockchip,vop-grf =3D <&vop_grf>; rockchip,vo1-grf =3D <&vo1_grf>; --=20 2.55.0