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Wed, 02 Sep 2026 14:43:26 -0700 (PDT) From: Alex Elder To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mani@kernel.org, krishna.chundru@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, sushrut.trivedi@oss.qualcomm.com, umang.chheda@oss.qualcomm.com, rosh@debian.org, jsandom@axon.com, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio , Abel Vesa Subject: [PATCH v3 1/6] arm64: dts: qcom: qcs6490-rb3gen2: clean up PCI function nodes Date: Wed, 2 Sep 2026 16:43:15 -0500 Message-ID: <20260902214321.1721477-2-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902214321.1721477-1-elder@riscstar.com> References: <20260902214321.1721477-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TC9564 SoC contains a PCIe switch with three downstream ports. The third downstream port connects to an embedded PCI endpoint, and that endpoint implements two PCI functions. The devicetree node describing those functions incorrectly includes this property: device_type =3D "pci"; That property should only be used for a PCI device "that implements a PCI bus", but not a PCIe function. So remove the device_type property from the nodes representing the two embedded PCI functions. Additionally, only PCI bridge nodes should be named "pcie@" (or "pci@"). PCI endpoint nodes are typically named based on the functionality they implement (e.g., "ethernet@"). In this case, the role of these PCI functions is not (yet) specified, and furthermore they will be used with PCI endpoint buses. Rename these to use "dev@", following the convention used in of_pci_make_dev_node() for dynamically-created devicetree nodes. Finally, those properties contain #address-cells, #size-cells, and ranges properties. And although these properties *will* be appropriate for these functions on an RB3gen2, they are not normally used for PCI functions. So remove these properties as well; we'll include them in the commit that actually adds a pci-ep-bus sub-node to these PCI function nodes. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Fixes: aa7b4bbcb3a1d ("arm64: dts: qcom: qcs6490-rb3gen2: Add TC9563 PCIe s= witch node") Signed-off-by: Alex Elder --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index a13315bf0fb07..3bb5fca8e2b13 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -954,20 +954,12 @@ pcie@3,0 { ranges; bus-range =3D <0x5 0xff>; =20 - pcie@0,0 { + dev@0,0 { reg =3D <0x50000 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; =20 - pcie@0,1 { + dev@0,1 { reg =3D <0x50100 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; }; }; --=20 2.53.0 From nobody Sat Sep 26 09:16:54 2026 Received: from mail-qt1-f174.google.com (mail-qt1-f174.google.com [209.85.160.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DAE04AA1ED for ; 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Wed, 02 Sep 2026 14:43:28 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90e9ee06d30sm28372546d6.6.2026.09.02.14.43.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 14:43:27 -0700 (PDT) From: Alex Elder To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mani@kernel.org, krishna.chundru@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, sushrut.trivedi@oss.qualcomm.com, umang.chheda@oss.qualcomm.com, rosh@debian.org, jsandom@axon.com, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio , Abel Vesa Subject: [PATCH v3 2/6] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI function nodes Date: Wed, 2 Sep 2026 16:43:16 -0500 Message-ID: <20260902214321.1721477-3-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902214321.1721477-1-elder@riscstar.com> References: <20260902214321.1721477-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The qcs6490-rb3gen2-industrial-mezzanine overlay defines two nodes representing TC956x chips, each of which contains a PCIe switch and an embedded endpoint that implements two PCIe functions. The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes. In addition, only PCI bridge nodes should be named "pcie@" (or "pci@"). PCI endpoint nodes are typically named based on the functionality they implement (e.g., "ethernet@"). In this case, the role of these PCI functions is not (yet) specified, and furthermore they will be used with PCI endpoint buses. Rename these to use "dev@", following the convention used in of_pci_make_dev_node() for dynamically-created devicetree nodes. Finally, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Fixes: 4559b435f741b ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzani= ne: Add TC9563 PCIe switch node for PCIe0") Signed-off-by: Alex Elder --- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 24 ++++--------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.= dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 46bb52c667a4d..5259f4f4f8574 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -130,20 +130,12 @@ pcie@3,0 { ranges; bus-range =3D <0x5 0xff>; =20 - pcie@0,0 { + dev@0,0 { reg =3D <0x50000 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; =20 - pcie@0,1 { + dev@0,1 { reg =3D <0x50100 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; 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Wed, 02 Sep 2026 14:43:29 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90e9ee06d30sm28372546d6.6.2026.09.02.14.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 14:43:29 -0700 (PDT) From: Alex Elder To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mani@kernel.org, krishna.chundru@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, sushrut.trivedi@oss.qualcomm.com, umang.chheda@oss.qualcomm.com, rosh@debian.org, jsandom@axon.com, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio , Abel Vesa Subject: [PATCH v3 3/6] arm64: dts: qcom: lemans-evk-ifp-mezzanine: clean up PCI function nodes Date: Wed, 2 Sep 2026 16:43:17 -0500 Message-ID: <20260902214321.1721477-4-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902214321.1721477-1-elder@riscstar.com> References: <20260902214321.1721477-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The lemans-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions. The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes. In addition, only PCI bridge nodes should be named "pcie@" (or "pci@"). PCI endpoint nodes are typically named based on the functionality they implement (e.g., "ethernet@"). In this case, the role of these PCI functions is not (yet) specified, and furthermore they will be used with PCI endpoint buses. Rename these to use "dev@", following the convention used in of_pci_make_dev_node() for dynamically-created devicetree nodes. Finally, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Fixes: b64abb26a2916 ("arm64: dts: qcom: lemans-evk: Add IFP Mezzanine") Signed-off-by: Alex Elder --- .../boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/= arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 6cfa0bc1440e9..e42314c648579 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -271,20 +271,12 @@ pcie@3,0 { ranges; bus-range =3D <0x5 0xff>; =20 - pcie@0,0 { + dev@0,0 { reg =3D <0x50000 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; =20 - pcie@0,1 { + dev@0,1 { reg =3D <0x50100 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; }; }; --=20 2.53.0 From nobody Sat Sep 26 09:16:54 2026 Received: from mail-qv1-f51.google.com (mail-qv1-f51.google.com [209.85.219.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 247FB3A380C for ; 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Wed, 02 Sep 2026 14:43:31 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90e9ee06d30sm28372546d6.6.2026.09.02.14.43.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 14:43:30 -0700 (PDT) From: Alex Elder To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mani@kernel.org, krishna.chundru@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, sushrut.trivedi@oss.qualcomm.com, umang.chheda@oss.qualcomm.com, rosh@debian.org, jsandom@axon.com, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio , Abel Vesa Subject: [PATCH v3 4/6] arm64: dts: qcom: monaco-evk-ifp-mezzanine: clean up PCI function nodes Date: Wed, 2 Sep 2026 16:43:18 -0500 Message-ID: <20260902214321.1721477-5-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902214321.1721477-1-elder@riscstar.com> References: <20260902214321.1721477-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The monaco-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions. The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes. In addition, only PCI bridge nodes should be named "pcie@" (or "pci@"). PCI endpoint nodes are typically named based on the functionality they implement (e.g., "ethernet@"). In this case, the role of these PCI functions is not (yet) specified, and furthermore they will be used with PCI endpoint buses. Rename these to use "dev@", following the convention used in of_pci_make_dev_node() for dynamically-created devicetree nodes. Finally, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Fixes: 5a67924d2fc57 ("arm64: dts: qcom: monaco-evk: Add IFP Mezzanine") Signed-off-by: Alex Elder --- .../boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/= arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index ca5bf0fe5ec6e..4f727ff6ecb61 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -117,20 +117,12 @@ pcie@3,0 { ranges; bus-range =3D <0x5 0xff>; =20 - pcie@0,0 { + dev@0,0 { reg =3D <0x50000 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; =20 - pcie@0,1 { + dev@0,1 { reg =3D <0x50100 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; }; }; --=20 2.53.0 From nobody Sat Sep 26 09:16:54 2026 Received: from mail-qv1-f54.google.com (mail-qv1-f54.google.com [209.85.219.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 597C83EA977 for ; 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Wed, 02 Sep 2026 14:43:32 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90e9ee06d30sm28372546d6.6.2026.09.02.14.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 14:43:32 -0700 (PDT) From: Alex Elder To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mani@kernel.org, krishna.chundru@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, sushrut.trivedi@oss.qualcomm.com, umang.chheda@oss.qualcomm.com, rosh@debian.org, jsandom@axon.com, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio , Abel Vesa Subject: [PATCH v3 5/6] arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: clean up PCI function nodes Date: Wed, 2 Sep 2026 16:43:19 -0500 Message-ID: <20260902214321.1721477-6-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902214321.1721477-1-elder@riscstar.com> References: <20260902214321.1721477-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Thundercomm AI Mini PC G1 IoT devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions. The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes. In addition, only PCI bridge nodes should be named "pcie@" (or "pci@"). PCI endpoint nodes are typically named based on the functionality they implement (e.g., "ethernet@"). In this case, the role of these PCI functions is not (yet) specified, and furthermore they will be used with PCI endpoint buses. Rename these to use "dev@", following the convention used in of_pci_make_dev_node() for dynamically-created devicetree nodes. Finally, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Fixes: 1cde54c54b83b ("arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini P= C G1 IoT") Signed-off-by: Alex Elder --- .../dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts = b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 31bafa2cf51db..51b59a75c1e03 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -790,20 +790,12 @@ pcie@3,0 { ranges; bus-range =3D <0x5 0xff>; =20 - pcie@0,0 { + dev@0,0 { reg =3D <0x50000 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; =20 - pcie@0,1 { + dev@0,1 { reg =3D <0x50100 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; 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Wed, 02 Sep 2026 14:43:33 -0700 (PDT) From: Alex Elder To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mani@kernel.org, krishna.chundru@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, sushrut.trivedi@oss.qualcomm.com, umang.chheda@oss.qualcomm.com, rosh@debian.org, jsandom@axon.com, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Manivannan Sadhasivam Subject: [PATCH v3 6/6] arm64: dts: qcom: qcs8550-rb5gen2: clean up PCI function nodes Date: Wed, 2 Sep 2026 16:43:20 -0500 Message-ID: <20260902214321.1721477-7-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902214321.1721477-1-elder@riscstar.com> References: <20260902214321.1721477-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Qualcomm RB5gen2 devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions. The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes. In addition, only PCI bridge nodes should be named "pci@" (or "pcie@"). PCI endpoint nodes are typically named based on the functionality they implement (e.g., "ethernet@"). In this case, the role of these PCI functions is not (yet) specified, and furthermore they will be used with PCI endpoint buses. Rename these to use "dev@", following the convention used in of_pci_make_dev_node() for dynamically-created devicetree nodes. Finally, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used. Fixes: 33cae252054a6 ("arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board= support") Reviewed-by: Abel Vesa Reviewed-by: Manivannan Sadhasivam Signed-off-by: Alex Elder --- arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot= /dts/qcom/qcs8550-rb5gen2.dts index 9df8dcd6c62b6..e6340f7d30dd8 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts @@ -1126,20 +1126,12 @@ pcie@3,0 { ranges; bus-range =3D <0x5 0xff>; =20 - pci@0,0 { + dev@0,0 { reg =3D <0x50000 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; =20 - pci@0,1 { + dev@0,1 { reg =3D <0x50100 0x0 0x0 0x0 0x0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges; }; }; }; --=20 2.53.0