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Wed, 2 Sep 2026 09:40:21 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Edward Srouji , Gal Pressman , Kees Cook , Leon Romanovsky , , , Maher Sanalla , Mark Bloch , Or Har-Toov , Parav Pandit , Patrisious Haddad , Saeed Mahameed , Shay Drori , Simon Horman , Tariq Toukan Subject: [PATCH net 1/4] net/mlx5: SD, serialize SD LAG init/cleanup against LAG mode changes Date: Wed, 2 Sep 2026 19:37:13 +0300 Message-ID: <20260902163716.3656279-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260902163716.3656279-1-tariqt@nvidia.com> References: <20260902163716.3656279-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|DM4PR12MB9069:EE_ X-MS-Office365-Filtering-Correlation-Id: 74d37b64-40ef-40b4-3d8f-08df0910f2cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|82310400026|7416014|376014|1800799024|6133799003|56012099006|10067099003|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: BqPb5FiNVYXrehd64M6jk4RNlkSwaAH4+uqZ0xE8c/vLPumT4IUE1Gp2Q+3TtANvNYT1DtKwwWTM2nhfOecforyGJhz04NrCJpVIgJIvkEIkBzMqxpUTEaIiK6mH8+1K5UYq7tiCy0KoauQUD8G1X6bdamvx8SnNeyH8LgZlNSL8jmK2bRxsk+N22Pa14lv2bXHomIJUAhnZ6OlqvykAN1BEYGz646WhFSynNHT6pCQtRi03IFcORwX5RrmBOYQI+kJOoA5L+YL7tqYJkVZtt2Kbawbjx9ZfMvH5i7MPaSBFlh97i/LOTGhcZpxYbzVniRhabp4VeWrqCpURQxesEXv7OcW/vohiUzHh77dVqyCcCiF+l/0DR2blZ5ae/O+DBiaoAjuMjtPn8yiwG6ko/4R8t0K3fUgi+j5ZpRBKZbtWh/LZCjVEVe6DjXfdG4GsiEzmiwtnYgbmjpqaQpFPUmpdL0TM9zTpv6QZjelmUpDNo2wHYMGvd46GQ+wyAdTmaAt07W/JBkd8mY1fjSGvdM7dKdAacHobVbiR1wU1cy53BFRvdY8s8S5R13F0kgByNx7mqcARGknyV1uwdU6bZjktIlxGRen3D052Vvig8nsPjx1+WD5t1WGHY04qB9FYldYsc6JJOGgNaMcAjKl1SYIa5U0SpkpbIRPyqd/d8E0YKEPj34iRnK9DH/L8O2vU9gOXlc1WxruRtl73p1GzvA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(82310400026)(7416014)(376014)(1800799024)(6133799003)(56012099006)(10067099003)(11063799006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jAM0DVhjWcFZgipwT6Ez4j6phwlys7Vgm+O6NXv3mAkGzZq1Zpm+86dlgsExu6/yFjmix1yrZAXyxe5d66E9tPJoh/5n6wf7oYnUblG9LjZGw3U3q+BReP5LKC3NYWUEfB5riy5LmgbUdr4kPPsbFXbjsISfeGhuDqX7RAfD5EkGIdHAPxCj50xFrqBBNDZ9LdQSdn3St2JSusCkHKyKsPvmsM1Mk6CzkMtqoUo4L7DhgwTA+vLauh0T8m/OtTouCIJtGzSHDZI3oF23UncN6Yzxus1/tR518Sm9HpoXE46zjzPwbsdc0EcsjdxiJfoWVaIaUjC0A+3idP5vifWRKsvNB6NHXiP8DByErhxNjkPHKbGNCz1Mk4KXcizV1oA/mSlK4FsVnaBRfT2mawmrRAETLXZTdd1hsVxfRYUZsAe1RP9hvIEOdr4QoJKYqkXe X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 16:40:50.6354 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74d37b64-40ef-40b4-3d8f-08df0910f2cf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB9069 Content-Type: text/plain; charset="utf-8" From: Shay Drory A secondary SD is spliced into the primary's shared LAG device (ldev) by sd_lag_init() and removed by sd_lag_cleanup(). The LAG mode-change paths drop ldev->lock mid-operation while iterating ldev->pfs, and rely on ldev->mode_changes_in_progress to keep the member set stable across that window. sd_lag_cleanup() did not honor ldev->mode_changes_in_progress. Which means a concurrent SD teardown could xa_erase() and kfree() a pf out of ldev->pfs during a mode change's dropped-lock window, leading to a NULL/use-after-free dereference of the secondary pf. Make sd_lag_init() and sd_lag_cleanup() wait until mode_changes_in_progress drops to zero before touching ldev, mirroring mlx5_lag_remove_mdev(). In addition, fold the SD shared-FDB teardown in mlx5_lag_disable_change() into the main locked section. Otherwise the two acquire sd_devcom and mode_changes_in_progress in opposite orders - sd_lag_init/cleanup takes sd_devcom then waits on mode_changes_in_progress, while disable_change increments mode_changes_in_progress then takes sd_devcom - an ABBA deadlock. The same ABBA deadlock is present in mlx5_eswitch_disable(), which takes sd_devcom between mlx5_lag_disable_change() and mlx5_lag_enable_change(). Move that call after mlx5_lag_enable_change(), matching the ordering already used by mlx5_devlink_eswitch_mode_set(). Fixes: 3c103110835d ("net/mlx5: SD, introduce Socket Direct LAG") Signed-off-by: Shay Drory Reviewed-by: Akiva Goldberger Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 2 +- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 30 +++++++++---------- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 13 ++++++++ 3 files changed, 28 insertions(+), 17 deletions(-) Internal sashiko comment: diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c > index ee2fdefa1945..2b2b7f3916f7 100644 > --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c > +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c > @@ -342,7 +342,14 @@ static void sd_lag_init(struct mlx5_core_dev *dev) > return; > } > > +recheck: > mutex_lock(&ldev->lock); > + if (ldev->mode_changes_in_progress) { > + mutex_unlock(&ldev->lock); > + msleep(100); > + goto recheck; > + } > + Does this open-coded retry loop reimplement a wait mechanism without immediate wakeups or fairness? It looks like we are polling the mode_changes_in_progress flag using a hard coded msleep(100). Could this unnecessarily delay the initialization path if the condition clears much sooner than 100ms? Would it be better to use a proper synchronization primitive like a waitqueue here instead of an ad-hoc flag loop? [SD] This is the same check as in mlx5_lag_remove_mdev(). I agree we need to change it, but this is net-next material diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index b6e2c153b4f7..50e158b6a684 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2062,8 +2062,8 @@ void mlx5_eswitch_disable(struct mlx5_eswitch *esw) mlx5_esw_reps_unblock(esw); =20 esw->mode =3D MLX5_ESWITCH_LEGACY; - mlx5_sd_eswitch_mode_set(esw->dev, MLX5_ESWITCH_LEGACY); mlx5_lag_enable_change(esw->dev); + mlx5_sd_eswitch_mode_set(esw->dev, MLX5_ESWITCH_LEGACY); } =20 static int mlx5_esw_sf_max_pf_functions(struct mlx5_core_dev *dev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 2285c889c215..aee5ce471eba 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -2589,6 +2589,8 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *de= v) mpesw =3D ldev->mode =3D=3D MLX5_LAG_MODE_MPESW; if (mpesw) mlx5_mpesw_sd_devcoms_lock(ldev); + else if (sd_devcom) + mlx5_devcom_comp_lock(sd_devcom); mutex_lock(&ldev->lock); =20 ldev->mode_changes_in_progress++; @@ -2599,26 +2601,22 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *= dev) mlx5_disable_lag(ldev); } =20 + if (sd_devcom) { + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { + pf =3D mlx5_lag_pf(ldev, i); + if (pf->dev =3D=3D dev && pf->sd_fdb_active) { + mlx5_lag_shared_fdb_destroy(ldev, pf->group_id); + break; + } + } + } + mutex_unlock(&ldev->lock); if (mpesw) mlx5_mpesw_sd_devcoms_unlock(ldev); + else if (sd_devcom) + mlx5_devcom_comp_unlock(sd_devcom); mlx5_devcom_comp_unlock(primary->priv.hca_devcom_comp); - - if (!sd_devcom) - return; - - /* Teardown SD shared FDB for this device's group if active */ - mlx5_devcom_comp_lock(sd_devcom); - mutex_lock(&ldev->lock); - mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { - pf =3D mlx5_lag_pf(ldev, i); - if (pf->dev =3D=3D dev && pf->sd_fdb_active) { - mlx5_lag_shared_fdb_destroy(ldev, pf->group_id); - break; - } - } - mutex_unlock(&ldev->lock); - mlx5_devcom_comp_unlock(sd_devcom); } =20 void mlx5_lag_enable_change(struct mlx5_core_dev *dev) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index 4cdc50cd6f03..99cf455a61e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -345,7 +345,14 @@ static void sd_lag_init(struct mlx5_core_dev *dev) return; } =20 +recheck: mutex_lock(&ldev->lock); + if (ldev->mode_changes_in_progress) { + mutex_unlock(&ldev->lock); + msleep(100); + goto recheck; + } + pf =3D mlx5_lag_pf_by_dev(ldev, primary); if (!pf) { sd_warn(primary, "%s: primary not registered in ldev, skipping\n", @@ -388,7 +395,13 @@ static void sd_lag_cleanup(struct mlx5_core_dev *dev) if (!ldev) return; =20 +recheck: mutex_lock(&ldev->lock); + if (ldev->mode_changes_in_progress) { + mutex_unlock(&ldev->lock); + msleep(100); + goto recheck; + } mlx5_sd_for_each_secondary(i, primary, pos) mlx5_ldev_remove_mdev(ldev, pos); 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Wed, 2 Sep 2026 09:40:26 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Edward Srouji , Gal Pressman , Kees Cook , Leon Romanovsky , , , Maher Sanalla , Mark Bloch , Or Har-Toov , Parav Pandit , Patrisious Haddad , Saeed Mahameed , Shay Drori , Simon Horman , Tariq Toukan Subject: [PATCH net 2/4] net/mlx5: devcom, Base component size on linked devices Date: Wed, 2 Sep 2026 19:37:14 +0300 Message-ID: <20260902163716.3656279-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260902163716.3656279-1-tariqt@nvidia.com> References: <20260902163716.3656279-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|MW3PR12MB4412:EE_ X-MS-Office365-Filtering-Correlation-Id: 02991cb5-5d65-4e2a-e72a-08df0910f499 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700016|23010399003|82310400026|10067099003|56012099006|11063799006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 3ZZe+lPUL1LYwstnc9H0zHqG3Vhq9mextmG5Z+Sxio5m9xlXGxt8/nN9bWEFOf4Cn7ZUNli1ef/hpPdwXypbvWPjapaXuOz0skm43vEH6q+S+jZhn/6Xrtwl+xLW+zBmBffrYh9MfA9QplIUPTYOLK05hhz9YiGDEp0A+/Yw6Qig/WSiVBOpn0ixMfFSnSRExz8gl4SXrEFqKuA25qeCN0oiojGOkGnIZqFVqK3l22cfGj19a5mgtm5ui8LpvMUpOvrtBxAUX2J2iJp0Mp0Ov1Iw4/JzuF+2Q7hSDrjd8vXS+JG5mSGo4Ond0ki6xPEkndLLFP85DgK562+0cSQ9VEl8E+aRMBdM3Xd7BPCNEZbnxlPQwgB4c1wtNNAO58WJ/q3mSQ/CM4Goh9DDDuV3721SLDa2RvzdniYZuoRvQiVjolDG7dAwb5UPWC3ftXHaG46BP8DIWXbzLtrjlfkFBiudoDvUCunOvid9XHCMWJMJor0tgZ5ix2z4/bQ/UfodmqywmTJMGTtRzsyLQdCOW/O8aLDgq4R5St/5x/XKarSlFlzgnfKb8UiJN3CwVFTP40iPM3GP+Oj5IROptKu7fbCFsfkw4IeQZD/bEo2BryeMNpxcqmoXwIP19INVnci+XQAernaJk0KKBaydXVRA90LWfYVAXo7dadm9xmbRxDPwyFI6i07t7/wH7E0Q82oMOpEhHnTnzYqgLt2ZH496/w== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700016)(23010399003)(82310400026)(10067099003)(56012099006)(11063799006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4LFnNeu1t7azm/m0I1ytjVJYkIgQC2OhnmoUR/Lpye45YRTX6g+ilXqIbOpgcr1h8Nu/FRnTCT9krck29N+gWRN3ZUa34nKlFvMXsRnBdaDyqA9TCysuH10bcFi4RruOSS+YJUqDLAEgJ9+A4l1VceFJGIE8brPZ0Bf+x1F2xUcJQq5xALvJARXcbclg3oIGBBBRVLAJDWm0JOcH/ZTHjeiyAVZd+4sjHfECoqavRvfSJ46WKVvWEhdSJTRy4mSZIJI1WmiecWsym0ZsIpd5AQU7BCdGUCtnYGFShBr9rj6kpwubE51Nhx9Z2vD1ocM+vKVQiA5XwmRl/CNePxCuZOy3ys6VZJdKOjmILiTgw6I9r5xCuMjssSB4KOakuefP2DN5vQLWyC2bQM9jLjzoa9YIziTKpjXAeJb2JZ4kuweLL+BCCggXULEvIGvM2cDO X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 16:40:53.6241 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02991cb5-5d65-4e2a-e72a-08df0910f499 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4412 Content-Type: text/plain; charset="utf-8" From: Shay Drory mlx5_devcom_comp_get_size() returns the component's kref count. That kref is bumped in mlx5_devcom_register_component() under comp_list_lock, before the comp_dev is linked onto comp_dev_list_head under comp->sem. The event broadcast (mlx5_devcom_locked_send_event()) walks that list. Hence, a caller can read the expected size, but send_event won't be sent to all peers. In the SD group registration path, this lets a member broadcast its role-election event over an incomplete list, electing a primary that never completes the group, is never marked ready, and leaves the group with a stale primary. Track the number of linked comp_devs in a dedicated counter, maintained under comp->sem together with the list add/remove, and return it from mlx5_devcom_comp_get_size(). Fixes: 9bb1ac80738a ("net/mlx5: devcom, Add component size getter") Signed-off-by: Shay Drory Reviewed-by: Akiva Goldberger Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c b/drivers= /net/ethernet/mellanox/mlx5/core/lib/devcom.c index 64f92427602d..75855481522b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c @@ -37,6 +37,7 @@ struct mlx5_devcom_comp { struct mlx5_devcom_key key; mlx5_devcom_event_handler_t handler; struct kref ref; + int nr_devs; bool ready; struct rw_semaphore sem; struct lock_class_key lock_key; @@ -170,6 +171,7 @@ devcom_alloc_comp_dev(struct mlx5_devcom_dev *devc, =20 down_write(&comp->sem); list_add_tail(&devcom->list, &comp->comp_dev_list_head); + WRITE_ONCE(comp->nr_devs, comp->nr_devs + 1); up_write(&comp->sem); =20 return devcom; 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Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Edward Srouji , Gal Pressman , Kees Cook , Leon Romanovsky , , , Maher Sanalla , Mark Bloch , Or Har-Toov , Parav Pandit , Patrisious Haddad , Saeed Mahameed , Shay Drori , Simon Horman , Tariq Toukan Subject: [PATCH net 3/4] net/mlx5: SD, unload reps on shared FDB create error path Date: Wed, 2 Sep 2026 19:37:15 +0300 Message-ID: <20260902163716.3656279-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260902163716.3656279-1-tariqt@nvidia.com> References: <20260902163716.3656279-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|PH7PR12MB7115:EE_ X-MS-Office365-Filtering-Correlation-Id: 60ee3f6b-111e-4469-eaa8-08df0910f64e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|23010399003|36860700016|82310400026|10067099003|11063799006|22082099003|56012099006|18002099003; X-Microsoft-Antispam-Message-Info: Z0CmY1EXnB+7gmdnyH1b/uP1RJAlNewoU9NZvONgAAmbjVwqw/1J1TvE+fR0JHhnjt5NWepF1ANZ8DvsRxXlS0j8clssCwgKzz4FYheCpkPik7Dp56lk5fRl8bGrtldOdwgX41DiTxM+Ea0NntB+z3yhiijr3mVSTKl8sNkKcnUNoECN485EASGs7LByfJCBPNvdKrV7nkHMd7dWGTMI1hze9yYtIU/8Hq7gkHXRB8E1L/OZ8CENoJRayun0N0hPUb2NBveiNX2RuwWyIPqPv8jYfZalBLxZF31oY1ujGtcRPVJ/2vECFQEj1h1A+ib4X2woGioKhs3d6RRFooAvTkarQvy8DGIyEfa2F/Hv5TnRgZHau4QW/eohA3QHV+GZIHFYRBQB6HOUEAveJEiQbjpEQucJ4Uvt7L4OQk8X90YlezDFuvxQFp+RwlDfgXUqMW0nzXywu8LmNTANBKkBH3JZpcEf8Ygaa248wiGOX0xI49m/1orEvjvHhaFb2K9XPYDsDoqkm0bmvuYxjSJaoVXBY6y5SSw9o/ycwGnshKGk6YAEomMSy8nRWpnt+b3jkIjcIInOVql+KubVFi79itZ42DvGYvRlxsIZw5EuSC5vfBRHXz7VkJGAnFM5/IumC2o5+KUpQ8dZucIxZyLhR1zS+y2fCc6w5bOzfdxQ0Jsg9VVCJ4bHXDUgbzPod0fceIjnlPF/wdgHfBfaKjzRyQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(23010399003)(36860700016)(82310400026)(10067099003)(11063799006)(22082099003)(56012099006)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JvkaBRJBJxYGxqD4ifys5Ak3KiX/QkrUmVNEL6MpnaE7ABT3pHR8LPTUC45YYrNk6ZoJuPbv1Rdl2SDGQpBmueqb6lYVUXDtfj6IqcqBm5NbjXHh3tCu5soYk7i359F6mygcPA336Kun0Kui5VBMFYbuiMw27KbDDzNKoxgWj+INVd3VUCA4FOFFno2iP8dXveVS70cTbdIMhhaS2bG4mU+7HkBpBAnu0R/UZdLgVmJgnaRUTl0Uv/UQ9WYETqvajg/Va4jrLflmkzYb9OpdsAQkvCOjSFt6acQuRTQIBpWUHkrhD1tg64O3dMahG+TnXqlpjLZ1d0q6vCgfiPVD46pCuWlepUuKUwWXVie96Gw5NAAivbguh13xm6ixBQh9Bi38nHQSJlgDCElDvKtS0iUElbm8uPRHbb+GQp/WEOZdSlJSLsP4YsIWoZQcSKe3 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 16:40:56.4854 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60ee3f6b-111e-4469-eaa8-08df0910f64e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7115 Content-Type: text/plain; charset="utf-8" From: Shay Drory The teardown path unloads the representors; align the create error path to do the same. Fixes: 68c2dd59a6c7 ("net/mlx5: E-Switch, Tie rep load/unload to SD LAG sta= te") Signed-off-by: Shay Drory Reviewed-by: Akiva Goldberger Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/dri= vers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c index 6b4ad3c53f2f..424040918fa3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c @@ -270,6 +270,7 @@ int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, pf->sd_fdb_active =3D false; } mlx5_lag_destroy_single_fdb_filter(ldev, group_id); + mlx5_lag_unload_reps_from_locked(ldev, filter); } err_add_devices: mlx5_lag_add_devices_filter(ldev, filter); --=20 2.44.0 From nobody Sat Sep 26 09:19:21 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010028.outbound.protection.outlook.com [52.101.193.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68FBA4AA013; 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Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Edward Srouji , Gal Pressman , Kees Cook , Leon Romanovsky , , , Maher Sanalla , Mark Bloch , Or Har-Toov , Parav Pandit , Patrisious Haddad , Saeed Mahameed , Shay Drori , Simon Horman , Tariq Toukan Subject: [PATCH net 4/4] net/mlx5: LAG, reload IB reps of LAG master before the rest Date: Wed, 2 Sep 2026 19:37:16 +0300 Message-ID: <20260902163716.3656279-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260902163716.3656279-1-tariqt@nvidia.com> References: <20260902163716.3656279-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|SJ0PR12MB6944:EE_ X-MS-Office365-Filtering-Correlation-Id: 700b4b53-59d8-4839-6fe9-08df0910ff0d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|82310400026|23010399003|7416014|10067099003|11063799006|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 0t0TPXqbA+Q8FrhyLGifx7Wv3Nu3BDKADIpYLPFavAHrqo7t1tFVwvIqs41m2GE12ICiDcgt8MyuVoD9cAiY0mXG7Lstujpuu2Z49/53hNK/fCbjn3aTyrDptN23ADUrJrIPWkTlnmtPCymE1G9AfOlJ6kvhHyD4dd+WtuuRdYyuSemzBEVQ2a9DpvyTYOPXn2tjbwMNyvA0VDVLpDFjPT7MsTak5Abww0CRzO+wqWvUhIieVJdFZqiQGRxzuV8zrXN4pMwQfzjz2XOSkTeeZJ2dJ9LtYpXOdhExis7tn+22SFk5ejvKXOfHjojMcZ//sCH7U5eETDpor8URT/DjLbUz05QWyn5+Ta9QdMQKVxYMlJdy0ZsWlVM2hVYPP8Vr9Jn53C3I8C/toQrj4YU3D6jKsYvdOM5kFVidHPcWcUq9BrbtoiDIB5k5bPzWXcoKMVHDlSsvA1NlSUTtppWPjzeX6LJMHCd3g0K+fZysqlLK7P+oO36f8yH4t6otmbw5a9HcGojs7owK4J+Th1PzqEPUjyT9upL6CL/dwkuxgshv14d/xK+jM/h5WY6AwL6o2OhNYP6ZBQvwu2QiFzx77WbjniCdX4Y5iW4vM9kmxt4tmmsrOljUWllWTKoUsukQocYfkktYgFHki3obyyjRwu1n84GhAQBue/zK6XvZpK1U5mfBGqy35jYWUxKpxkJx4EDKXVOzzibr7N2luvJ8lw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(82310400026)(23010399003)(7416014)(10067099003)(11063799006)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sY2r71yshw+yYzpK+hVew3pw9tzLxsBD9puiMiUFnhCz+uhFA03RnixmBpQICf7GaYtCKHNe+4HqcwtgmCNy5S/vEVTJZY/dbfpOgx+XSdwXkvWbWGI8SZMRAJV3TI/5b+yN9cAsXNhwMprNDfnepRc/S1yadraL3gRJWvCsmAHHBOlyFRGMeR0sEf6S4NKkWr54NJKI1hrbL2a41/6l6ooiPFKrVa2DAGdlx5eTa2EySWQ5PgldWDyaGoJRU2Sg+ZTaXk25ln/kUFKx+fDcUxVMN1agzrDl7nTHAC8eUsNTjocYk0b0zXMnXjPB/delStciSYIHqxQ0WUUIxllQhEkMG94uyVrlS3mXVKCgs1+apvcnZsvwvvBNw7BHbeYRQfFDSP/NMqPJP5jL5vEHp+CUTNnit4ZhgSWYJ/o6VWzkQUW4hAiqTBOAxz0+UD1t X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 16:41:11.2081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 700b4b53-59d8-4839-6fe9-08df0910ff0d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6944 Content-Type: text/plain; charset="utf-8" From: Shay Drory In a shared-FDB LAG the master device creates the bond IB device; the other LAG members do not create their own, they populate a port inside the master's IB device. mlx5_lag_reload_ib_reps_unlocked() reloaded the members' IB reps in iteration order, with no guarantee the master is reloaded first. When a non-master member is reloaded before the master, it tries to populate its port in an IB device that has not been recreated yet. Hence, reload the master's IB reps first, then every other member. Fixes: 2b204cdb1206 ("net/mlx5: LAG, use xa_alloc to manage LAG device indi= ces") Signed-off-by: Shay Drory Reviewed-by: Akiva Goldberger Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 44 ++++++++++++++----- 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index aee5ce471eba..4984c812268c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1263,25 +1263,45 @@ void mlx5_lag_remove_devices(struct mlx5_lag *ldev) mlx5_lag_remove_devices_filter(ldev, MLX5_LAG_FILTER_PORTS); } =20 +static int mlx5_lag_reload_ib_reps_idx(struct mlx5_lag *ldev, int idx, + u32 flags) +{ + struct lag_func *pf =3D mlx5_lag_pf(ldev, idx); + struct mlx5_eswitch *esw; + int ret; + + if (pf->dev->priv.flags & flags) + return 0; + + esw =3D pf->dev->priv.eswitch; + mlx5_esw_reps_block(esw); + ret =3D mlx5_eswitch_reload_ib_reps(esw); + mlx5_esw_reps_unblock(esw); + + return ret; +} + static int mlx5_lag_reload_ib_reps_unlocked(struct mlx5_lag *ldev, u32 fla= gs, u32 filter, bool cont_on_fail) { - struct lag_func *pf; + int master_idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); int ret; int i; =20 + if (master_idx < 0) + return -EINVAL; + + ret =3D mlx5_lag_reload_ib_reps_idx(ldev, master_idx, flags); + if (ret && !cont_on_fail) + return ret; + mlx5_lag_for_each(i, 0, ldev, filter) { - pf =3D mlx5_lag_pf(ldev, i); - if (!(pf->dev->priv.flags & flags)) { - struct mlx5_eswitch *esw; - - esw =3D pf->dev->priv.eswitch; - mlx5_esw_reps_block(esw); - ret =3D mlx5_eswitch_reload_ib_reps(esw); - mlx5_esw_reps_unblock(esw); - if (ret && !cont_on_fail) - return ret; - } + if (i =3D=3D master_idx) + continue; + ret =3D mlx5_lag_reload_ib_reps_idx(ldev, i, flags); + if (ret && !cont_on_fail) + return ret; } =20 return 0; --=20 2.44.0