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charset="utf-8" From: John Madieu rzv2h_cpg_fixed_mod_status_clk_register() looks up priv->clks[core->parent] twice, with an IS_ERR() check after each lookup. The second lookup is a leftover from an earlier refactor: the value cannot have changed between the two reads, so the second IS_ERR() check is dead code. Drop the duplicated lookup and check. No functional change intended. Signed-off-by: John Madieu Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/rzv2h-cpg.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 7003d59ac34b..86f6f2f700a6 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -923,9 +923,6 @@ rzv2h_cpg_fixed_mod_status_clk_register(const struct cp= g_core_clk *core, return ERR_CAST(parent); =20 parent_name =3D __clk_get_name(parent); - parent =3D priv->clks[core->parent]; - if (IS_ERR(parent)) - return ERR_CAST(parent); =20 clk_hw_data =3D devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); if (!clk_hw_data) --=20 2.34.1 From nobody Sat Sep 26 10:04:05 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011034.outbound.protection.outlook.com [52.101.125.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 746C8471D09; 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Wed, 2 Sep 2026 19:50:13 +0900 (JST) From: Ovidiu Panait To: geert+renesas@glider.be, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu , Ovidiu Panait Subject: [PATCH 2/2] clk: renesas: rzv2h: Convert to clk_hw based provider API Date: Wed, 2 Sep 2026 10:49:39 +0000 Message-ID: <20260902104939.25522-3-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260902104939.25522-1-ovidiu.panait.rb@renesas.com> References: <20260902104939.25522-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYO1EPF00005020:EE_|TYCPR01MB7137:EE_ X-MS-Office365-Filtering-Correlation-Id: 67fb4bd2-8fe2-4336-ce6d-08df08dff9ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|376014|82310400026|36860700016|22082099003|18002099003|56012099006|10067099003|11063799006; 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charset="utf-8" From: John Madieu The driver mixes the clk consumer API with the clk_hw provider API for its internal clock storage and OF lookup callback. Convert it to use clk_hw consistently. No functional change intended. Signed-off-by: John Madieu Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/rzv2h-cpg.c | 151 ++++++++++++++------------------ 1 file changed, 68 insertions(+), 83 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 86f6f2f700a6..9b0d691b1f5d 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -99,7 +99,7 @@ struct rzv2h_pll_dsi_info { * @dev: CPG device * @base: CPG register block base address * @rmw_lock: protects register accesses - * @clks: Array containing all Core and Module Clocks + * @clks: Array containing all Core and Module clk_hw entries * @num_core_clks: Number of Core Clocks in clks[] * @num_mod_clks: Number of Module Clocks in clks[] * @resets: Array of resets @@ -115,7 +115,7 @@ struct rzv2h_cpg_priv { void __iomem *base; spinlock_t rmw_lock; =20 - struct clk **clks; + struct clk_hw **clks; unsigned int num_core_clks; unsigned int num_mod_clks; struct rzv2h_reset *resets; @@ -332,14 +332,14 @@ static const struct clk_ops rzv2h_cpg_plldsi_div_ops = =3D { .set_rate =3D rzv2h_cpg_plldsi_div_set_rate, }; =20 -static struct clk * __init +static struct clk_hw * __init rzv2h_cpg_plldsi_div_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { struct rzv2h_plldsi_div_clk *clk_hw_data; - struct clk **clks =3D priv->clks; + struct clk_hw **clks =3D priv->clks; struct clk_init_data init =3D {}; - const struct clk *parent; + const struct clk_hw *parent; const char *parent_name; struct clk_hw *clk_hw; int ret; @@ -356,7 +356,7 @@ rzv2h_cpg_plldsi_div_clk_register(const struct cpg_core= _clk *core, clk_hw_data->ddiv =3D core->cfg.ddiv; clk_hw_data->dtable =3D core->dtable; =20 - parent_name =3D __clk_get_name(parent); + parent_name =3D clk_hw_get_name(parent); init.name =3D core->name; init.ops =3D &rzv2h_cpg_plldsi_div_ops; init.flags =3D core->flag; @@ -370,7 +370,7 @@ rzv2h_cpg_plldsi_div_clk_register(const struct cpg_core= _clk *core, if (ret) return ERR_PTR(ret); =20 - return clk_hw->clk; + return clk_hw; } =20 static int rzv2h_cpg_plldsi_determine_rate(struct clk_hw *hw, @@ -577,7 +577,7 @@ static const struct clk_ops rzv2h_cpg_plldsi_smux_ops = =3D { .set_duty_cycle =3D rzv2h_cpg_plldsi_smux_set_duty_cycle, }; =20 -static struct clk * __init +static struct clk_hw * __init rzv2h_cpg_plldsi_smux_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { @@ -620,7 +620,7 @@ rzv2h_cpg_plldsi_smux_clk_register(const struct cpg_cor= e_clk *core, if (ret) return ERR_PTR(ret); =20 - return clk_hw->clk; + return clk_hw; } =20 static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw) @@ -705,14 +705,14 @@ static const struct clk_ops rzv2h_cpg_pll_ops =3D { .recalc_rate =3D rzv2h_cpg_pll_clk_recalc_rate, }; =20 -static struct clk * __init +static struct clk_hw * __init rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv, const struct clk_ops *ops) { struct device *dev =3D priv->dev; struct clk_init_data init =3D {}; - const struct clk *parent; + const struct clk_hw *parent; const char *parent_name; struct pll_clk *pll_clk; int ret; @@ -729,7 +729,7 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *c= ore, priv->pll_dsi_info[core->cfg.pll.instance].pll_dsi_limits =3D core->cfg.pll.limits; =20 - parent_name =3D __clk_get_name(parent); + parent_name =3D clk_hw_get_name(parent); init.name =3D core->name; init.ops =3D ops; init.flags =3D 0; @@ -744,7 +744,7 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *c= ore, if (ret) return ERR_PTR(ret); =20 - return pll_clk->hw.clk; + return &pll_clk->hw; } =20 static unsigned long rzv2h_ddiv_recalc_rate(struct clk_hw *hw, @@ -820,7 +820,7 @@ static const struct clk_ops rzv2h_ddiv_clk_divider_ops = =3D { .set_rate =3D rzv2h_ddiv_set_rate, }; =20 -static struct clk * __init +static struct clk_hw * __init rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { @@ -829,7 +829,7 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *= core, struct device *dev =3D priv->dev; u8 shift =3D cfg_ddiv.shift; u8 width =3D cfg_ddiv.width; - const struct clk *parent; + const struct clk_hw *parent; const char *parent_name; struct clk_divider *div; struct ddiv_clk *ddiv; @@ -839,7 +839,7 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *= core, if (IS_ERR(parent)) return ERR_CAST(parent); =20 - parent_name =3D __clk_get_name(parent); + parent_name =3D clk_hw_get_name(parent); =20 if ((shift + width) > 16) return ERR_PTR(-EINVAL); @@ -872,15 +872,15 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk= *core, if (ret) return ERR_PTR(ret); =20 - return div->hw.clk; + return &div->hw; } =20 -static struct clk * __init +static struct clk_hw * __init rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { struct smuxed mux =3D core->cfg.smux; - const struct clk_hw *clk_hw; + struct clk_hw *clk_hw; =20 clk_hw =3D devm_clk_hw_register_mux(priv->dev, core->name, core->parent_names, core->num_parents, @@ -890,7 +890,7 @@ rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *c= ore, if (IS_ERR(clk_hw)) return ERR_CAST(clk_hw); =20 - return clk_hw->clk; + return clk_hw; } =20 static int @@ -906,14 +906,14 @@ rzv2h_clk_ff_mod_status_is_enabled(struct clk_hw *hw) return !!(val & bitmask); } =20 -static struct clk * __init +static struct clk_hw * __init rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { struct rzv2h_ff_mod_status_clk *clk_hw_data; struct clk_init_data init =3D { }; struct clk_fixed_factor *fix; - const struct clk *parent; + const struct clk_hw *parent; const char *parent_name; int ret; =20 @@ -922,7 +922,7 @@ rzv2h_cpg_fixed_mod_status_clk_register(const struct cp= g_core_clk *core, if (IS_ERR(parent)) return ERR_CAST(parent); =20 - parent_name =3D __clk_get_name(parent); + parent_name =3D clk_hw_get_name(parent); =20 clk_hw_data =3D devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); if (!clk_hw_data) @@ -946,18 +946,18 @@ rzv2h_cpg_fixed_mod_status_clk_register(const struct = cpg_core_clk *core, if (ret) return ERR_PTR(ret); =20 - return clk_hw_data->fix.hw.clk; + return &clk_hw_data->fix.hw; } =20 -static struct clk +static struct clk_hw *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) { unsigned int clkidx =3D clkspec->args[1]; struct rzv2h_cpg_priv *priv =3D data; struct device *dev =3D priv->dev; + struct clk_hw *clk_hw; const char *type; - struct clk *clk; =20 switch (clkspec->args[0]) { case CPG_CORE: @@ -966,7 +966,7 @@ static struct clk dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); return ERR_PTR(-EINVAL); } - clk =3D priv->clks[clkidx]; + clk_hw =3D priv->clks[clkidx]; break; =20 case CPG_MOD: @@ -975,7 +975,7 @@ static struct clk dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); return ERR_PTR(-EINVAL); } - clk =3D priv->clks[priv->num_core_clks + clkidx]; + clk_hw =3D priv->clks[priv->num_core_clks + clkidx]; break; =20 default: @@ -983,25 +983,25 @@ static struct clk return ERR_PTR(-EINVAL); } =20 - if (IS_ERR(clk)) + if (IS_ERR(clk_hw)) dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx, - PTR_ERR(clk)); + PTR_ERR(clk_hw)); else - dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", - clkspec->args[0], clkspec->args[1], clk, - clk_get_rate(clk)); - return clk; + dev_dbg(dev, "clock (%u, %u) is %s at %lu Hz\n", + clkspec->args[0], clkspec->args[1], + clk_hw_get_name(clk_hw), clk_hw_get_rate(clk_hw)); + return clk_hw; } =20 static void __init rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { - struct clk *clk =3D ERR_PTR(-EOPNOTSUPP), *parent; + struct clk_hw *clk_hw =3D ERR_PTR(-EOPNOTSUPP), *parent; unsigned int id =3D core->id, div =3D core->div; struct device *dev =3D priv->dev; const char *parent_name; - struct clk_hw *clk_hw; + struct clk *clk; =20 WARN_DEBUG(id >=3D priv->num_core_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) !=3D -ENOENT); @@ -1009,70 +1009,72 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_c= lk *core, switch (core->type) { case CLK_TYPE_IN: clk =3D of_clk_get_by_name(priv->dev->of_node, core->name); + if (IS_ERR(clk)) { + clk_hw =3D ERR_CAST(clk); + goto fail; + } + clk_hw =3D __clk_get_hw(clk); break; case CLK_TYPE_FF: WARN_DEBUG(core->parent >=3D priv->num_core_clks); parent =3D priv->clks[core->parent]; if (IS_ERR(parent)) { - clk =3D parent; + clk_hw =3D parent; goto fail; } =20 - parent_name =3D __clk_get_name(parent); + parent_name =3D clk_hw_get_name(parent); clk_hw =3D devm_clk_hw_register_fixed_factor(dev, core->name, parent_name, CLK_SET_RATE_PARENT, core->mult, div); - if (IS_ERR(clk_hw)) - clk =3D ERR_CAST(clk_hw); - else - clk =3D clk_hw->clk; break; case CLK_TYPE_FF_MOD_STATUS: if (!priv->ff_mod_status_ops) { priv->ff_mod_status_ops =3D devm_kzalloc(dev, sizeof(*priv->ff_mod_status_ops), GFP_KERNEL); if (!priv->ff_mod_status_ops) { - clk =3D ERR_PTR(-ENOMEM); + clk_hw =3D ERR_PTR(-ENOMEM); goto fail; } memcpy(priv->ff_mod_status_ops, &clk_fixed_factor_ops, sizeof(const struct clk_ops)); priv->ff_mod_status_ops->is_enabled =3D rzv2h_clk_ff_mod_status_is_enab= led; } - clk =3D rzv2h_cpg_fixed_mod_status_clk_register(core, priv); + clk_hw =3D rzv2h_cpg_fixed_mod_status_clk_register(core, priv); break; case CLK_TYPE_PLL: - clk =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops); + clk_hw =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops); break; case CLK_TYPE_DDIV: - clk =3D rzv2h_cpg_ddiv_clk_register(core, priv); + clk_hw =3D rzv2h_cpg_ddiv_clk_register(core, priv); break; case CLK_TYPE_SMUX: - clk =3D rzv2h_cpg_mux_clk_register(core, priv); + clk_hw =3D rzv2h_cpg_mux_clk_register(core, priv); break; case CLK_TYPE_PLLDSI: - clk =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_plldsi_ops); + clk_hw =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_plldsi_ops); break; case CLK_TYPE_PLLDSI_DIV: - clk =3D rzv2h_cpg_plldsi_div_clk_register(core, priv); + clk_hw =3D rzv2h_cpg_plldsi_div_clk_register(core, priv); break; case CLK_TYPE_PLLDSI_SMUX: - clk =3D rzv2h_cpg_plldsi_smux_clk_register(core, priv); + clk_hw =3D rzv2h_cpg_plldsi_smux_clk_register(core, priv); break; default: goto fail; } =20 - if (IS_ERR(clk)) + if (IS_ERR(clk_hw)) goto fail; =20 - dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); - priv->clks[id] =3D clk; + dev_dbg(dev, "Core clock %s at %lu Hz\n", + clk_hw_get_name(clk_hw), clk_hw_get_rate(clk_hw)); + priv->clks[id] =3D clk_hw; return; =20 fail: dev_err(dev, "Failed to register core clock %s: %ld\n", - core->name, PTR_ERR(clk)); + core->name, PTR_ERR(clk_hw)); } =20 static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv, @@ -1119,15 +1121,10 @@ static void rzv2h_mod_clock_mstop_disable(struct rz= v2h_cpg_priv *priv, =20 static int rzv2h_parent_clk_mux_to_index(struct clk_hw *hw) { - struct clk_hw *parent_hw; - struct clk *parent_clk; + struct clk_hw *parent_hw =3D clk_hw_get_parent(hw); struct clk_mux *mux; u32 val; =20 - /* This will always succeed, so no need to check for IS_ERR() */ - parent_clk =3D clk_get_parent(hw->clk); - - parent_hw =3D __clk_get_hw(parent_clk); mux =3D to_clk_mux(parent_hw); =20 val =3D readl(mux->reg) >> mux->shift; @@ -1227,8 +1224,8 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk= *mod, struct mod_clock *clock =3D NULL; struct device *dev =3D priv->dev; struct clk_init_data init =3D {}; - struct clk *parent, *clk; const char *parent_name; + struct clk_hw *parent; unsigned int id; int ret; =20 @@ -1239,13 +1236,13 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_c= lk *mod, =20 parent =3D priv->clks[mod->parent]; if (IS_ERR(parent)) { - clk =3D parent; + ret =3D PTR_ERR(parent); goto fail; } =20 clock =3D devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL); if (!clock) { - clk =3D ERR_PTR(-ENOMEM); + ret =3D -ENOMEM; goto fail; } =20 @@ -1255,7 +1252,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk= *mod, if (mod->critical) init.flags |=3D CLK_IS_CRITICAL; =20 - parent_name =3D __clk_get_name(parent); + parent_name =3D clk_hw_get_name(parent); init.parent_names =3D &parent_name; init.num_parents =3D 1; =20 @@ -1270,12 +1267,10 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_c= lk *mod, clock->mstop_data =3D mod->mstop_data; =20 ret =3D devm_clk_hw_register(dev, &clock->hw); - if (ret) { - clk =3D ERR_PTR(ret); + if (ret) goto fail; - } =20 - priv->clks[id] =3D clock->hw.clk; + priv->clks[id] =3D &clock->hw; =20 /* * Ensure the module clocks and MSTOP bits are synchronized when they are @@ -1314,8 +1309,8 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk= *mod, return; =20 fail: - dev_err(dev, "Failed to register module clock %s: %ld\n", - mod->name, PTR_ERR(clk)); + dev_err(dev, "Failed to register module clock %s: %d\n", + mod->name, ret); } =20 static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev, @@ -1448,7 +1443,7 @@ static bool rzv2h_cpg_is_pm_clk(struct rzv2h_cpg_pd *= pd, if (priv->clks[priv->num_core_clks + id] =3D=3D ERR_PTR(-ENOENT)) return false; =20 - clock =3D to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]= )); + clock =3D to_mod_clock(priv->clks[priv->num_core_clks + id]); =20 return !clock->no_pm; } @@ -1547,19 +1542,13 @@ static int __init rzv2h_cpg_add_pm_domains(struct r= zv2h_cpg_priv *priv) return of_genpd_add_provider_simple(np, &pd->genpd); } =20 -static void rzv2h_cpg_del_clk_provider(void *data) -{ - of_clk_del_provider(data); -} - static int __init rzv2h_cpg_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; const struct rzv2h_cpg_info *info; struct rzv2h_cpg_priv *priv; unsigned int nclks, i; - struct clk **clks; + struct clk_hw **clks; int error; =20 info =3D of_device_get_match_data(dev); @@ -1610,11 +1599,7 @@ static int __init rzv2h_cpg_probe(struct platform_de= vice *pdev) for (i =3D 0; i < info->num_mod_clks; i++) rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv); =20 - error =3D of_clk_add_provider(np, rzv2h_cpg_clk_src_twocell_get, priv); - if (error) - return error; - - error =3D devm_add_action_or_reset(dev, rzv2h_cpg_del_clk_provider, np); + error =3D devm_of_clk_add_hw_provider(dev, rzv2h_cpg_clk_src_twocell_get,= priv); if (error) return error; =20 --=20 2.34.1