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Wed, 02 Sep 2026 00:39:48 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v2 1/2] pinctrl: imx: answer OUTPUT_ENABLE/INPUT_ENABLE queries from the pad register Date: Wed, 2 Sep 2026 09:39:45 +0200 Message-ID: <20260902073946.3709080-2-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260902073946.3709080-1-mehmet.fide@gmail.com> References: <20260902073946.3709080-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide The mmio pinconf get callback ignores which parameter was requested and returns the raw conf register, so a generic query through pinctrl_gpio_get_config() gets register bits back instead of the packed parameter it asked for. Decode the requested parameter and answer PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_INPUT_ENABLE on SoCs that declare where those bits live in the pad register; Vybrid has OBE at bit 1 and IBE at bit 0. The answer is 0 with the bit value as the argument, which is what the pinctrl_gpio_get_config() users (gpio-by-pinctrl, and gpio-mmio in the next patch) expect. Everything else, including pins the device tree never configured, gets -ENOTSUPP. The only in-tree user of the raw register was the debugfs group dump, which called the callback with an uninitialized config; it now reads the register through its own helper, like the single pin dump already did. This gives gpio-mmio a way to read back the line direction on chips whose direction lives in the pin controller. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide --- v2: - the pin_config_get callback answers only the parameters the SoC declares and returns -ENOTSUPP otherwise; the debugfs group dump reads the raw register through its own helper instead of calling the callback with an uninitialized config (Sashiko) - subject prefix pinctrl: imx: drivers/pinctrl/freescale/pinctrl-imx.c | 51 +++++++++++++++++++++-- drivers/pinctrl/freescale/pinctrl-imx.h | 4 ++ drivers/pinctrl/freescale/pinctrl-vf610.c | 2 + 3 files changed, 54 insertions(+), 3 deletions(-) drivers/pinctrl/freescale/pinctrl-imx.c | 51 +++++++++++++++++++++-- drivers/pinctrl/freescale/pinctrl-imx.h | 4 ++ drivers/pinctrl/freescale/pinctrl-vf610.c | 2 + 3 files changed, 54 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/free= scale/pinctrl-imx.c index 9a45b376d36f..506ee6627c82 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -21,6 +21,7 @@ =20 #include #include +#include #include #include =20 @@ -291,8 +292,8 @@ struct pinmux_ops imx_pmx_ops =3D { .set_mux =3D imx_pmx_set, }; =20 -static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_= id, - unsigned long *config) +static int imx_pinconf_get_raw_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) { struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info =3D ipctl->info; @@ -312,6 +313,38 @@ static int imx_pinconf_get_mmio(struct pinctrl_dev *pc= tldev, unsigned pin_id, return 0; } =20 +static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info =3D ipctl->info; + const struct imx_pin_reg *pin_reg =3D &ipctl->pin_regs[pin_id]; + enum pin_config_param param =3D pinconf_to_config_param(*config); + unsigned int mask; + u32 raw; + + /* only the parameters the SoC declares a pad bit for */ + switch (param) { + case PIN_CONFIG_OUTPUT_ENABLE: + mask =3D info->obe_mask; + break; + case PIN_CONFIG_INPUT_ENABLE: + mask =3D info->ibe_mask; + break; + default: + mask =3D 0; + break; + } + + if (!mask || pin_reg->conf_reg =3D=3D -1) + return -ENOTSUPP; + + raw =3D readl(ipctl->base + pin_reg->conf_reg); + *config =3D pinconf_to_config_packed(param, !!(raw & mask)); + + return 0; +} + static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { @@ -324,6 +357,18 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, return imx_pinconf_get_mmio(pctldev, pin_id, config); } =20 +static int imx_pinconf_get_raw(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info =3D ipctl->info; + + if (info->flags & IMX_USE_SCU) + return info->imx_pinconf_get(pctldev, pin_id, config); + else + return imx_pinconf_get_raw_mmio(pctldev, pin_id, config); +} + static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *configs, unsigned num_configs) @@ -426,7 +471,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_d= ev *pctldev, struct imx_pin *pin =3D &((struct imx_pin *)(grp->data))[i]; =20 name =3D pin_get_name(pctldev, pin->pin); - ret =3D imx_pinconf_get(pctldev, pin->pin, &config); + ret =3D imx_pinconf_get_raw(pctldev, pin->pin, &config); if (ret) return; seq_printf(s, " %s: 0x%lx\n", name, config); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/free= scale/pinctrl-imx.h index f65ff45b4003..8fa7e1e2521d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -91,6 +91,10 @@ struct imx_pinctrl_soc_info { unsigned int mux_mask; u8 mux_shift; =20 + /* OBE/IBE bits in the conf register, 0 if the pad does not have them */ + unsigned int obe_mask; + unsigned int ibe_mask; + int (*gpio_set_direction)(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/fr= eescale/pinctrl-vf610.c index 76a4bc0181a0..77d077618782 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -319,6 +319,8 @@ static const struct imx_pinctrl_soc_info vf610_pinctrl_= info =3D { .gpio_set_direction =3D vf610_pmx_gpio_set_direction, .mux_mask =3D 0x700000, .mux_shift =3D 20, + .obe_mask =3D 0x2, + .ibe_mask =3D 0x1, }; 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Wed, 02 Sep 2026 00:39:49 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v2 2/2] gpio: mmio: track the direction of chips without direction registers Date: Wed, 2 Sep 2026 09:39:46 +0200 Message-ID: <20260902073946.3709080-3-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260902073946.3709080-1-mehmet.fide@gmail.com> References: <20260902073946.3709080-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide A generic chip with GPIO_GENERIC_PINCTRL_BACKEND and no direction registers sets the direction through pinctrl but has no get_direction callback, so every gpiod_get_direction() call trips the WARN in gpiolib and the direction gpiolib reports is whatever it assumed. On a Vybrid Colibri module that is 21 backtraces per boot. Keep the direction of such a chip in the existing shadow: the direction setters update sdir under the chip lock, and get_direction() is the shadow-reading path already used for unreadable direction registers. That keeps the callback usable in atomic context, which it has to be: gpiochip_lock_as_irq() calls it for !can_sleep chips from gpiochip_irq_domain_activate(), under the irq descriptor lock. The pad's actual state is read once, in process context, when a line is requested: gpiolib calls request() right before get_direction() for a new line, so the shadow is seeded from PIN_CONFIG_OUTPUT_ENABLE there and the line reports what the pin controller says. Lines pinctrl cannot answer for keep the input default, which is what gpiolib assumed before. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide --- v2: - keep the direction in the chip's shadow and reuse the shadow-reading get_direction(); seed the shadow from pinctrl in request(), because gpiochip_lock_as_irq() calls get_direction() under the irq descriptor lock for !can_sleep chips (Sashiko) - lines pinctrl cannot answer for keep the input default, no error returned to gpiochip_lock_as_irq() (Sashiko) - drop the claim about the initial direction scan, it runs before the pin ranges exist (Sashiko) drivers/gpio/gpio-mmio.c | 65 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 4 deletions(-) drivers/gpio/gpio-mmio.c | 63 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index 7e4b3e8d609f..84bf8cc7a0c7 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -49,6 +49,7 @@ o ` ~~~~\___/~~~~ ` control= ler in FPGA is ,.` #include #include #include +#include #include #include #include @@ -372,7 +373,17 @@ static int gpio_mmio_dir_in_err(struct gpio_chip *gc, = unsigned int gpio) =20 static int gpio_mmio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) { - return gpio_mmio_dir_return(gc, gpio, false); + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; + + ret =3D gpio_mmio_dir_return(gc, gpio, false); + if (ret) + return ret; + + guard(raw_spinlock_irqsave)(&chip->lock); + chip->sdir &=3D ~gpio_mmio_line2mask(gc, gpio); + + return 0; } =20 static int gpio_mmio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, @@ -384,9 +395,19 @@ static int gpio_mmio_dir_out_err(struct gpio_chip *gc,= unsigned int gpio, static int gpio_mmio_simple_dir_out(struct gpio_chip *gc, unsigned int gpi= o, int val) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; + gc->set(gc, gpio, val); =20 - return gpio_mmio_dir_return(gc, gpio, true); + ret =3D gpio_mmio_dir_return(gc, gpio, true); + if (ret) + return ret; + + guard(raw_spinlock_irqsave)(&chip->lock); + chip->sdir |=3D gpio_mmio_line2mask(gc, gpio); + + return 0; } =20 static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio) @@ -601,20 +622,54 @@ static int gpio_mmio_setup_direction(struct gpio_gene= ric_chip *chip, gc->direction_input =3D gpio_mmio_dir_in_err; else gc->direction_input =3D gpio_mmio_simple_dir_in; + + if (cfg->flags & GPIO_GENERIC_PINCTRL_BACKEND) { + chip->dir_unreadable =3D true; + gc->get_direction =3D gpio_mmio_get_dir; + } } =20 return 0; } =20 +/* + * Without direction registers the direction lives in the pin controller, + * so seed the shadow from there when a line is requested. + */ +static void gpio_mmio_seed_dir_from_pinctrl(struct gpio_chip *gc, + unsigned int gpio) +{ + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + unsigned long config; + + if (!IS_ENABLED(CONFIG_PINCTRL) || chip->reg_dir_out || chip->reg_dir_in) + return; + + config =3D pinconf_to_config_packed(PIN_CONFIG_OUTPUT_ENABLE, 0); + if (pinctrl_gpio_get_config(gc, gpio, &config)) + return; + + guard(raw_spinlock_irqsave)(&chip->lock); + if (config) + chip->sdir |=3D gpio_mmio_line2mask(gc, gpio); + else + chip->sdir &=3D ~gpio_mmio_line2mask(gc, gpio); +} + static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin) { struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; =20 if (gpio_pin >=3D gc->ngpio) return -EINVAL; =20 - if (chip->pinctrl) - return gpiochip_generic_request(gc, gpio_pin); + if (chip->pinctrl) { + ret =3D gpiochip_generic_request(gc, gpio_pin); + if (ret) + return ret; + gpio_mmio_seed_dir_from_pinctrl(gc, gpio_pin); + } =20 return 0; } --=20 2.54.0