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Tue, 01 Sep 2026 23:23:54 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH 1/2] pinctrl: imx: answer OUTPUT_ENABLE/INPUT_ENABLE queries from the pad register Date: Wed, 2 Sep 2026 08:23:51 +0200 Message-ID: <20260902062352.3600368-2-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260902062352.3600368-1-mehmet.fide@gmail.com> References: <20260902062352.3600368-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide The mmio pinconf get callback ignores which parameter was requested and returns the raw conf register, so a generic query through pinctrl_gpio_get_config() gets register bits back instead of the packed parameter it asked for. Decode the requested parameter and answer PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_INPUT_ENABLE on SoCs that declare where those bits live in the pad register; Vybrid has OBE at bit 1 and IBE at bit 0. The answer is 0 with the bit value as the argument, which is what the pinctrl_gpio_get_config() users (gpio-by-pinctrl, and gpio-mmio in the next patch) expect. Pins the device tree never configured have no register offset and get -ENOTSUPP, without the error message meant for configuration attempts. Other parameters keep the historic raw-register behaviour, which the debugfs dump still relies on. This gives gpio-mmio a way to read back the line direction on chips whose direction lives in the pin controller. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide --- drivers/pinctrl/freescale/pinctrl-imx.c | 30 +++++++++++++++++++++++ drivers/pinctrl/freescale/pinctrl-imx.h | 4 +++ drivers/pinctrl/freescale/pinctrl-vf610.c | 2 ++ 3 files changed, 36 insertions(+) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/free= scale/pinctrl-imx.c index 9a45b376d36f..5da1a76b0141 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -21,6 +21,7 @@ =20 #include #include +#include #include #include =20 @@ -297,6 +298,35 @@ static int imx_pinconf_get_mmio(struct pinctrl_dev *pc= tldev, unsigned pin_id, struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info =3D ipctl->info; const struct imx_pin_reg *pin_reg =3D &ipctl->pin_regs[pin_id]; + enum pin_config_param param =3D pinconf_to_config_param(*config); + unsigned int mask =3D 0; + u32 raw; + + /* + * Only OUTPUT_ENABLE/INPUT_ENABLE are decoded, and only when the SoC + * declares the bits. Everything else still returns the raw conf + * register, the debugfs dump depends on it. + */ + switch (param) { + case PIN_CONFIG_OUTPUT_ENABLE: + mask =3D info->obe_mask; + break; + case PIN_CONFIG_INPUT_ENABLE: + mask =3D info->ibe_mask; + break; + default: + break; + } + + if (mask) { + /* pin not configured, nothing to report */ + if (pin_reg->conf_reg =3D=3D -1) + return -ENOTSUPP; + + raw =3D readl(ipctl->base + pin_reg->conf_reg); + *config =3D pinconf_to_config_packed(param, !!(raw & mask)); + return 0; + } =20 if (pin_reg->conf_reg =3D=3D -1) { dev_err(ipctl->dev, "Pin(%s) does not support config function\n", diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/free= scale/pinctrl-imx.h index f65ff45b4003..8fa7e1e2521d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -91,6 +91,10 @@ struct imx_pinctrl_soc_info { unsigned int mux_mask; u8 mux_shift; =20 + /* OBE/IBE bits in the conf register, 0 if the pad does not have them */ + unsigned int obe_mask; + unsigned int ibe_mask; + int (*gpio_set_direction)(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/fr= eescale/pinctrl-vf610.c index 76a4bc0181a0..77d077618782 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -319,6 +319,8 @@ static const struct imx_pinctrl_soc_info vf610_pinctrl_= info =3D { .gpio_set_direction =3D vf610_pmx_gpio_set_direction, .mux_mask =3D 0x700000, .mux_shift =3D 20, + .obe_mask =3D 0x2, + .ibe_mask =3D 0x1, }; =20 static const struct of_device_id vf610_pinctrl_of_match[] =3D { --=20 2.54.0 From nobody Sat Sep 26 11:01:14 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E996D374A0E for ; Wed, 2 Sep 2026 06:23:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 01 Sep 2026 23:23:56 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce4776131sm49735335e9.11.2026.09.01.23.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 23:23:55 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH 2/2] gpio: mmio: get the direction from pinctrl when there are no direction registers Date: Wed, 2 Sep 2026 08:23:52 +0200 Message-ID: <20260902062352.3600368-3-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260902062352.3600368-1-mehmet.fide@gmail.com> References: <20260902062352.3600368-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide A generic chip with GPIO_GENERIC_PINCTRL_BACKEND and no direction registers already sets the direction through pinctrl, but leaves gc->get_direction unset, so every gpiod_get_direction() call trips the WARN in gpiolib and the initial line state is guessed. On a Vybrid Colibri module that is 21 backtraces per boot. Install a get_direction callback for that combination which asks the pinctrl backend for PIN_CONFIG_OUTPUT_ENABLE, the same way gpio-by-pinctrl does it and mirroring how the direction setters are forwarded. Pins the pin controller cannot answer for report -ENOTSUPP; gpiolib ignores that when requesting a line and in the debugfs dump, and such pins cannot change direction through this chip either, as the setters fail for them too. The one caller that does not ignore it is gpiochip_lock_as_irq(), which now refuses such a pin as an interrupt where it previously had nothing to check against. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide --- drivers/gpio/gpio-mmio.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index 7e4b3e8d609f..b2aa74a734e4 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -49,6 +49,7 @@ o ` ~~~~\___/~~~~ ` control= ler in FPGA is ,.` #include #include #include +#include #include #include #include @@ -365,6 +366,28 @@ static int gpio_mmio_dir_return(struct gpio_chip *gc, = unsigned int gpio, return pinctrl_gpio_direction_input(gc, gpio); } =20 +/* + * Without direction registers the direction lives in the pin controller + * (Vybrid: the OBE bit in the iomuxc pad), so ask pinctrl. + */ +static int gpio_mmio_pinctrl_get_dir(struct gpio_chip *gc, unsigned int gp= io) +{ + unsigned long config; + int ret; + +#ifdef CONFIG_PINCTRL + if (list_empty(&gc->gpiodev->pin_ranges)) + return -EOPNOTSUPP; +#endif + + config =3D pinconf_to_config_packed(PIN_CONFIG_OUTPUT_ENABLE, 0); + ret =3D pinctrl_gpio_get_config(gc, gpio, &config); + if (ret) + return ret; + + return config ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + static int gpio_mmio_dir_in_err(struct gpio_chip *gc, unsigned int gpio) { return -EINVAL; @@ -601,6 +624,10 @@ static int gpio_mmio_setup_direction(struct gpio_gener= ic_chip *chip, gc->direction_input =3D gpio_mmio_dir_in_err; else gc->direction_input =3D gpio_mmio_simple_dir_in; + + if (IS_ENABLED(CONFIG_PINCTRL) && + cfg->flags & GPIO_GENERIC_PINCTRL_BACKEND) + gc->get_direction =3D gpio_mmio_pinctrl_get_dir; } =20 return 0; --=20 2.54.0