From nobody Sat Sep 26 10:03:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D720F438010; Wed, 2 Sep 2026 10:17:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788344245; cv=none; b=AUgJTD6klAJ6rfJVdwFhOjwzZG8MtvYyTPGzjMxGv0j9n+9AXU6E/8nZ7woGW/NH2MOvRVsrzoHtNJdS9G4Uk7Lx8G1IzCkSbUy1Ngk7wNOVFMsxIZyXV2dyxNZGUTD5IxgqfcrCOzYrAgR5JdXQfhZQRhcK8+jhe5u7VfmclJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788344245; c=relaxed/simple; bh=uXGoHVoCMVAvk/7IMrwWDqOKU6jWK4CSoPbCqiJ75Uc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u77jzBuxWa9AeS+m8/bYenwjAi0EfEW5YN8gsiw0Mu9408xjo5cSUnQeiKORrwlVFqraNiney6GDooyt72qJjSPJEA6BVLb3AOsSOIHLxLWy9qSvRAdE9fOgMFsze5fl2s9Vok9E8kUFWYxJfpzqMjIN+26/CyIQG+iwzfb0jBs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Aey/hSzq; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Aey/hSzq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2B7601F000E9; Wed, 2 Sep 2026 10:17:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788344243; bh=nycq3aRWVmMkJG98XrfmSjFlDVof1o+Pu6wjD3dM7JU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Aey/hSzq/zcodAEWtBmn3vlyJVIhne9U9azupruwV2/V09dZ1mC4shTvqKALCdsGW V6tqNUzJvQZyLyAUmnyMsj7RuMNrfQJ/l61GY2PgP3sEu4uih77pTApkPAYeq4aqA0 LzZ9NwpPWRSN/k9q15zHPDFw7+UElgdl/TSfKt+pWIZJYbaMLz0jnfd/js3dEdY+Lk yJqNFwIHSAP+R+5d9wcoxdikbVzn+0OIKHRppRRUDrbpkhzrUrPdsiiwzn/tyiaiVU toFxnjFqfK84vskd9c7RmBo0//TlRMz7uKHU1OzXaE0MPgiQ+/MknnL4OlRrDfgba4 8SCKXMh3imTzA== From: Thierry Reding Date: Wed, 02 Sep 2026 12:17:37 +0200 Subject: [PATCH 1/8] ARM: tegra: Clean up AHUB on Tegra124 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260902-tegra-ahub-dt-cleanup-v1-1-028f3c5e72f6@nvidia.com> References: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> In-Reply-To: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> To: Thierry Reding , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter Cc: Charan Pedumuru , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2437; i=treding@nvidia.com; h=from:subject:message-id; bh=GwIyfv32VB2Odbu5JQ3LyQj4clsaBfk7P0iiNSXE28s=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBql/fGS9hE1d1FuvuhZa+Mr4l2n2ARx67nl5VBn 0UKKSC5Xu2JAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCapf3xgAKCRDdI6zXfz6z of9sD/0XcKmSdFGQmaVl7VUy4CqVUC+zkci5PshHWRG9hWCPluruecRrQZiYcqCCkgLZEbdhz0F DnJxeK9SLAZbUbKDx0jDrOt/fnIeUNkZL3b5qF2zpr/Hy2CSuKvRIbbCbPOZo5aWBZyZ7WAjabA r/aqyj8eTOgTpAxT04df7Tco7UZizJy/c9yBWzf16sOXEj4x2NysNGFKmqGTBBZWn4fLD+ACCG0 M7ypZ7P8q0FZWK8bi2DogWwzIZ5WIre6GJqN8FT6a8D27Zy/vJPw49Hn49OjufXiboj7zqr9bEO EVSV21ZEC9jVkWK8eoezQN6SJ63EiHEt81Ayi5SDadzwwZq1zswXk6SKGRt/oVf7qNQsqGvrmFG FuB0YaaaQ0ab81jNvGSD7TJxs08A9ULTunQI76AN2zkZRqLLIapmkHHpi8/ouYQmgeMWYoB9cXU +48NHi9TEWOeV54giiISPqoVKaBE7qZYLb/umBXE9pDbWe8vRWoIyJ63YZjQMWZAakP+Ykp869V IrOkg93fBoNITzKUD9OeSpl77kMcKSWXtZgTAdP+zvdLnjr5HFflXUeYclG+hx53DwNgiy0Wnpd siyYIuhZ361kZVcUT0b0FC6mVYPC1IU9tUgUCjCE3LVX1d5Ls3yC0ytA39oLJNN9LDJ9U9PDzAg YfyRinuBH8iKFuQ== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Use #address-cells =3D <1> and #size-cells =3D <1> because we don't need 64-bit register addressing for this hardware. While at it, also adjust the ranges property to encompass the entire AHUB range as per the TRM. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra124.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvi= dia/tegra124.dtsi index ce4efa1de509..7a71dba42dc0 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -1114,13 +1114,13 @@ ahub@70300000 { "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9"; - ranges; - #address-cells =3D <2>; - #size-cells =3D <2>; + ranges =3D <0x7030000 0x0 0x70300000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; =20 tegra_i2s0: i2s@70301000 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301000 0x0 0x100>; + reg =3D <0x70301000 0x100>; nvidia,ahub-cif-ids =3D <4 4>; clocks =3D <&tegra_car TEGRA124_CLK_I2S0>; resets =3D <&tegra_car 30>; @@ -1130,7 +1130,7 @@ tegra_i2s0: i2s@70301000 { =20 tegra_i2s1: i2s@70301100 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301100 0x0 0x100>; + reg =3D <0x70301100 0x100>; nvidia,ahub-cif-ids =3D <5 5>; clocks =3D <&tegra_car TEGRA124_CLK_I2S1>; resets =3D <&tegra_car 11>; @@ -1140,7 +1140,7 @@ tegra_i2s1: i2s@70301100 { =20 tegra_i2s2: i2s@70301200 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301200 0x0 0x100>; + reg =3D <0x70301200 0x100>; nvidia,ahub-cif-ids =3D <6 6>; clocks =3D <&tegra_car TEGRA124_CLK_I2S2>; resets =3D <&tegra_car 18>; @@ -1150,7 +1150,7 @@ tegra_i2s2: i2s@70301200 { =20 tegra_i2s3: i2s@70301300 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301300 0x0 0x100>; + reg =3D <0x70301300 0x100>; nvidia,ahub-cif-ids =3D <7 7>; clocks =3D <&tegra_car TEGRA124_CLK_I2S3>; resets =3D <&tegra_car 101>; @@ -1160,7 +1160,7 @@ tegra_i2s3: i2s@70301300 { =20 tegra_i2s4: i2s@70301400 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301400 0x0 0x100>; + reg =3D <0x70301400 0x100>; nvidia,ahub-cif-ids =3D <8 8>; clocks =3D <&tegra_car TEGRA124_CLK_I2S4>; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Use #address-cells =3D <1> and #size-cells =3D <1> because we don't need 64-bit register addressing for this hardware. While at it, also adjust the ranges property to encompass the entire AHUB range as per the TRM. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts= /nvidia/tegra132.dtsi index 26cd11a8a4a1..3463fa637b37 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -936,13 +936,13 @@ ahub@70300000 { "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9"; - ranges; - #address-cells =3D <2>; - #size-cells =3D <2>; + ranges =3D <0x70300000 0x0 0x70300000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; =20 tegra_i2s0: i2s@70301000 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301000 0x0 0x100>; + reg =3D <0x70301000 0x100>; nvidia,ahub-cif-ids =3D <4 4>; clocks =3D <&tegra_car TEGRA124_CLK_I2S0>; clock-names =3D "i2s"; @@ -953,7 +953,7 @@ tegra_i2s0: i2s@70301000 { =20 tegra_i2s1: i2s@70301100 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301100 0x0 0x100>; + reg =3D <0x70301100 0x100>; nvidia,ahub-cif-ids =3D <5 5>; clocks =3D <&tegra_car TEGRA124_CLK_I2S1>; clock-names =3D "i2s"; @@ -964,7 +964,7 @@ tegra_i2s1: i2s@70301100 { =20 tegra_i2s2: i2s@70301200 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301200 0x0 0x100>; + reg =3D <0x70301200 0x100>; nvidia,ahub-cif-ids =3D <6 6>; clocks =3D <&tegra_car TEGRA124_CLK_I2S2>; clock-names =3D "i2s"; @@ -975,7 +975,7 @@ tegra_i2s2: i2s@70301200 { =20 tegra_i2s3: i2s@70301300 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301300 0x0 0x100>; + reg =3D <0x70301300 0x100>; nvidia,ahub-cif-ids =3D <7 7>; clocks =3D <&tegra_car TEGRA124_CLK_I2S3>; clock-names =3D "i2s"; @@ -986,7 +986,7 @@ tegra_i2s3: i2s@70301300 { =20 tegra_i2s4: i2s@70301400 { compatible =3D "nvidia,tegra124-i2s"; - reg =3D <0x0 0x70301400 0x0 0x100>; + reg =3D <0x70301400 0x100>; nvidia,ahub-cif-ids =3D <8 8>; clocks =3D <&tegra_car TEGRA124_CLK_I2S4>; clock-names =3D "i2s"; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding The AHUB range is a full 64 KiB according to the TRM, so update the ranges property accordingly. This is merely cosmetic. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts= /nvidia/tegra210.dtsi index 5f5e5370d709..9cc4c89dd1d6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1461,7 +1461,7 @@ tegra_ahub: ahub@702d0800 { assigned-clock-rates =3D <81600000>; #address-cells =3D <1>; #size-cells =3D <1>; - ranges =3D <0x702d0000 0x702d0000 0x0000e400>; + ranges =3D <0x702d0000 0x702d0000 0x00010000>; status =3D "disabled"; =20 tegra_admaif: admaif@702d0000 { --=20 2.55.0 From nobody Sat Sep 26 10:03:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F06D43CE7E; Wed, 2 Sep 2026 10:17:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788344254; cv=none; b=bmyUC/GMA/LTTLKc3TG7ytHeVknn6xbMI2RXcy46z+AVacrunpDsJkHZrvLA+QGWxgOXrsK/1rTbs1U4S1g2kSDvT7XE7TaSOU3h48puRss3fQ8Ml8BeWP+dCEhyQ73M4Gq18s5Ogsw1qLQeKo5nHAaBp9MhmHUCmeJyOJn2PK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788344254; c=relaxed/simple; bh=6bcqWblRKpqpQZ9sqOeIybNdtbPHL97nRqrBeUHO4/M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lqOXjli5K/uZ5T3NIQKx3L/4rz1JwjHggJpxlrRikJWTD0XFd3J1O4NOhMmOkz71em0ikWXnbK0QOGl1w1TpOHaQJA0NOPMzrDL0SoVVapCkh32fhwto/lyfARi9e91VPtYfBOb10Z9TpfNMNJDU9rWQw7MWbgBxYgbusgBxAJ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=manso9Nq; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="manso9Nq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 04AFA1F000E9; Wed, 2 Sep 2026 10:17:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788344251; bh=41jVJO8G26mYTHVILyoQBOQnZmXsYy0cm3FiQK04Rcs=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=manso9Nqz7tijKJiDoVSqSydWPCKuF4HHBnMFXqeX+GRlklNhRrRFs0RPQVr/etdt XIjzW91Mif5x1prATJEic6G7TfAHCsYA622t+3v5LreLVSQDiN7kisZuyI/OaG8Nz+ 2RjHdCPninOktY6KUhCFRewZ5eFS5Tn69CK+K5qCk4ErcbK2ndMkMhHKxTNl9O1Q4B /kpMIN444wGdLhdWHm/hc6qBlcVIA9TPRD2tMky2OmKsb9oEAoorBRcd3U/s755AaS 9CWJYNA6kkGLAQBiVi6W7OCCNe+t2C+o/0fsY94bBHF5eshAEV6BlKvla/ua4Y1UOG G8IwNqhrGJnTQ== From: Thierry Reding Date: Wed, 02 Sep 2026 12:17:40 +0200 Subject: [PATCH 4/8] arm64: tegra: Clean up AHUB on Tegra186 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260902-tegra-ahub-dt-cleanup-v1-4-028f3c5e72f6@nvidia.com> References: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> In-Reply-To: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> To: Thierry Reding , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter Cc: Charan Pedumuru , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10860; i=treding@nvidia.com; h=from:subject:message-id; bh=j5jnheSxYU0q+VC9CegVr/kwAiwUCY7+wPx3JN8fObk=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBql/fG8V3K9ksjAYJ3Il834A3X2DFUffN4oKRL8 aNtS5joc8mJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCapf3xgAKCRDdI6zXfz6z oUdeD/97i+ft0wtwRKn8opxw8VXYo7gse6pfX32uBareSz/3pwfsaWRhcFGrwL4sL9s/Vp+Fx88 zC9lzyzhs4i5Gd3EwqV0CX6ET8maQDuW5GovqJjlT9tEFRNvXSYKEPZWyGVcq5KUF1d+NM/qeFI zdR/7c9XpsbZLpKmepmhomKGJQYJvIfXoSzwrp+dwIordtiPi64uQPJBUFGapyHqOxC+CqBAQIj pjieCpuKbcJ8TjKL3WJprbRoYFZd9Juqohqy3NJnqZYj6lijM/wemC6D3y/u4Gt0UdfTE/qiU/m IwF7ZOVVsGFkAC2bXuBH5gy8Bb/CkKPzcA802siRKXBB4POp9BNC6nk1u/H9wNpZGiu3g8GYRjm KdJtX9dBcodB4SgNXqtNqpYp6dVGzCmMhi5E1gqBdKNsJuJjJmAsHJrYFZpnrY/01XYUcvZo52l ofrLHJuIq2DeYd7YXJ3YFuthwKPMu0yKUHT1ei4TC4IBgyVcIzo74OAiCY9A2RZ+v90OwOGs+N/ ikBmRg/pAyYz1gIKD4U3iEAgvoLDCCOacQIh5s8513E5YwqlDGAXIRfuQW6n3sQ80TsqO74b+cn zLXyHhqvLnb1UX2vex0mvy3OocXOhPCc13txazLEIhg6CNOFAhKIER0l9ZJZegWqXoLS7ykjZLx gQh7Y5GnU9NDgkA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Use #address-cells =3D <1> and #size-cells =3D <1> because we don't need 64-bit register addressing for this hardware. While at it, also adjust the ranges property to encompass the entire AHUB range as per the TRM. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 ++++++++++++++++------------= ---- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts= /nvidia/tegra186.dtsi index 705af0373a09..623d5e654323 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -142,15 +142,15 @@ tegra_ahub: ahub@2900800 { assigned-clocks =3D <&bpmp TEGRA186_CLK_AHUB>; assigned-clock-parents =3D <&bpmp TEGRA186_CLK_PLLP_OUT0>; assigned-clock-rates =3D <81600000>; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges =3D <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x02900000 0x0 0x02900000 0x20000>; status =3D "disabled"; =20 tegra_i2s1: i2s@2901000 { compatible =3D "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901000 0x0 0x100>; + reg =3D <0x2901000 0x100>; clocks =3D <&bpmp TEGRA186_CLK_I2S1>, <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -164,7 +164,7 @@ tegra_i2s1: i2s@2901000 { tegra_i2s2: i2s@2901100 { compatible =3D "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901100 0x0 0x100>; + reg =3D <0x2901100 0x100>; clocks =3D <&bpmp TEGRA186_CLK_I2S2>, <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -178,7 +178,7 @@ tegra_i2s2: i2s@2901100 { tegra_i2s3: i2s@2901200 { compatible =3D "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901200 0x0 0x100>; + reg =3D <0x2901200 0x100>; clocks =3D <&bpmp TEGRA186_CLK_I2S3>, <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -192,7 +192,7 @@ tegra_i2s3: i2s@2901200 { tegra_i2s4: i2s@2901300 { compatible =3D "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901300 0x0 0x100>; + reg =3D <0x2901300 0x100>; clocks =3D <&bpmp TEGRA186_CLK_I2S4>, <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -206,7 +206,7 @@ tegra_i2s4: i2s@2901300 { tegra_i2s5: i2s@2901400 { compatible =3D "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901400 0x0 0x100>; + reg =3D <0x2901400 0x100>; clocks =3D <&bpmp TEGRA186_CLK_I2S5>, <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -220,7 +220,7 @@ tegra_i2s5: i2s@2901400 { tegra_i2s6: i2s@2901500 { compatible =3D "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901500 0x0 0x100>; + reg =3D <0x2901500 0x100>; clocks =3D <&bpmp TEGRA186_CLK_I2S6>, <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -234,7 +234,7 @@ tegra_i2s6: i2s@2901500 { tegra_sfc1: sfc@2902000 { compatible =3D "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902000 0x0 0x200>; + reg =3D <0x2902000 0x200>; sound-name-prefix =3D "SFC1"; status =3D "disabled"; }; @@ -242,7 +242,7 @@ tegra_sfc1: sfc@2902000 { tegra_sfc2: sfc@2902200 { compatible =3D "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902200 0x0 0x200>; + reg =3D <0x2902200 0x200>; sound-name-prefix =3D "SFC2"; status =3D "disabled"; }; @@ -250,7 +250,7 @@ tegra_sfc2: sfc@2902200 { tegra_sfc3: sfc@2902400 { compatible =3D "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902400 0x0 0x200>; + reg =3D <0x2902400 0x200>; sound-name-prefix =3D "SFC3"; status =3D "disabled"; }; @@ -258,7 +258,7 @@ tegra_sfc3: sfc@2902400 { tegra_sfc4: sfc@2902600 { compatible =3D "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902600 0x0 0x200>; + reg =3D <0x2902600 0x200>; sound-name-prefix =3D "SFC4"; status =3D "disabled"; }; @@ -266,7 +266,7 @@ tegra_sfc4: sfc@2902600 { tegra_amx1: amx@2903000 { compatible =3D "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg =3D <0x0 0x2903000 0x0 0x100>; + reg =3D <0x2903000 0x100>; sound-name-prefix =3D "AMX1"; status =3D "disabled"; }; @@ -274,7 +274,7 @@ tegra_amx1: amx@2903000 { tegra_amx2: amx@2903100 { compatible =3D "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg =3D <0x0 0x2903100 0x0 0x100>; + reg =3D <0x2903100 0x100>; sound-name-prefix =3D "AMX2"; status =3D "disabled"; }; @@ -282,7 +282,7 @@ tegra_amx2: amx@2903100 { tegra_amx3: amx@2903200 { compatible =3D "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg =3D <0x0 0x2903200 0x0 0x100>; + reg =3D <0x2903200 0x100>; sound-name-prefix =3D "AMX3"; status =3D "disabled"; }; @@ -290,7 +290,7 @@ tegra_amx3: amx@2903200 { tegra_amx4: amx@2903300 { compatible =3D "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg =3D <0x0 0x2903300 0x0 0x100>; + reg =3D <0x2903300 0x100>; sound-name-prefix =3D "AMX4"; status =3D "disabled"; }; @@ -298,7 +298,7 @@ tegra_amx4: amx@2903300 { tegra_adx1: adx@2903800 { compatible =3D "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903800 0x0 0x100>; + reg =3D <0x2903800 0x100>; sound-name-prefix =3D "ADX1"; status =3D "disabled"; }; @@ -306,7 +306,7 @@ tegra_adx1: adx@2903800 { tegra_adx2: adx@2903900 { compatible =3D "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903900 0x0 0x100>; + reg =3D <0x2903900 0x100>; sound-name-prefix =3D "ADX2"; status =3D "disabled"; }; @@ -314,7 +314,7 @@ tegra_adx2: adx@2903900 { tegra_adx3: adx@2903a00 { compatible =3D "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903a00 0x0 0x100>; + reg =3D <0x2903a00 0x100>; sound-name-prefix =3D "ADX3"; status =3D "disabled"; }; @@ -322,14 +322,14 @@ tegra_adx3: adx@2903a00 { tegra_adx4: adx@2903b00 { compatible =3D "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903b00 0x0 0x100>; + reg =3D <0x2903b00 0x100>; sound-name-prefix =3D "ADX4"; status =3D "disabled"; }; =20 tegra_dmic1: dmic@2904000 { compatible =3D "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904000 0x0 0x100>; + reg =3D <0x2904000 0x100>; clocks =3D <&bpmp TEGRA186_CLK_DMIC1>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA186_CLK_DMIC1>; @@ -341,7 +341,7 @@ tegra_dmic1: dmic@2904000 { =20 tegra_dmic2: dmic@2904100 { compatible =3D "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904100 0x0 0x100>; + reg =3D <0x2904100 0x100>; clocks =3D <&bpmp TEGRA186_CLK_DMIC2>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA186_CLK_DMIC2>; @@ -353,7 +353,7 @@ tegra_dmic2: dmic@2904100 { =20 tegra_dmic3: dmic@2904200 { compatible =3D "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904200 0x0 0x100>; + reg =3D <0x2904200 0x100>; clocks =3D <&bpmp TEGRA186_CLK_DMIC3>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA186_CLK_DMIC3>; @@ -365,7 +365,7 @@ tegra_dmic3: dmic@2904200 { =20 tegra_dmic4: dmic@2904300 { compatible =3D "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904300 0x0 0x100>; + reg =3D <0x2904300 0x100>; clocks =3D <&bpmp TEGRA186_CLK_DMIC4>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA186_CLK_DMIC4>; @@ -377,7 +377,7 @@ tegra_dmic4: dmic@2904300 { =20 tegra_dspk1: dspk@2905000 { compatible =3D "nvidia,tegra186-dspk"; - reg =3D <0x0 0x2905000 0x0 0x100>; + reg =3D <0x2905000 0x100>; clocks =3D <&bpmp TEGRA186_CLK_DSPK1>; clock-names =3D "dspk"; assigned-clocks =3D <&bpmp TEGRA186_CLK_DSPK1>; @@ -389,7 +389,7 @@ tegra_dspk1: dspk@2905000 { =20 tegra_dspk2: dspk@2905100 { compatible =3D "nvidia,tegra186-dspk"; - reg =3D <0x0 0x2905100 0x0 0x100>; + reg =3D <0x2905100 0x100>; clocks =3D <&bpmp TEGRA186_CLK_DSPK2>; clock-names =3D "dspk"; assigned-clocks =3D <&bpmp TEGRA186_CLK_DSPK2>; @@ -402,9 +402,9 @@ tegra_dspk2: dspk@2905100 { tegra_ope1: processing-engine@2908000 { compatible =3D "nvidia,tegra186-ope", "nvidia,tegra210-ope"; - reg =3D <0x0 0x2908000 0x0 0x100>; - #address-cells =3D <2>; - #size-cells =3D <2>; + reg =3D <0x2908000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; ranges; sound-name-prefix =3D "OPE1"; status =3D "disabled"; @@ -412,20 +412,20 @@ tegra_ope1: processing-engine@2908000 { equalizer@2908100 { compatible =3D "nvidia,tegra186-peq", "nvidia,tegra210-peq"; - reg =3D <0x0 0x2908100 0x0 0x100>; + reg =3D <0x2908100 0x100>; }; =20 dynamic-range-compressor@2908200 { compatible =3D "nvidia,tegra186-mbdrc", "nvidia,tegra210-mbdrc"; - reg =3D <0x0 0x2908200 0x0 0x200>; + reg =3D <0x2908200 0x200>; }; }; =20 tegra_mvc1: mvc@290a000 { compatible =3D "nvidia,tegra186-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x290a000 0x0 0x200>; + reg =3D <0x290a000 0x200>; sound-name-prefix =3D "MVC1"; status =3D "disabled"; }; @@ -433,7 +433,7 @@ tegra_mvc1: mvc@290a000 { tegra_mvc2: mvc@290a200 { compatible =3D "nvidia,tegra186-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x290a200 0x0 0x200>; + reg =3D <0x290a200 0x200>; sound-name-prefix =3D "MVC2"; status =3D "disabled"; }; @@ -441,14 +441,14 @@ tegra_mvc2: mvc@290a200 { tegra_amixer: amixer@290bb00 { compatible =3D "nvidia,tegra186-amixer", "nvidia,tegra210-amixer"; - reg =3D <0x0 0x290bb00 0x0 0x800>; + reg =3D <0x290bb00 0x800>; sound-name-prefix =3D "MIXER1"; status =3D "disabled"; }; =20 tegra_admaif: admaif@290f000 { compatible =3D "nvidia,tegra186-admaif"; - reg =3D <0x0 0x0290f000 0x0 0x1000>; + reg =3D <0x0290f000 0x1000>; dmas =3D <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -494,7 +494,7 @@ tegra_admaif: admaif@290f000 { =20 tegra_asrc: asrc@2910000 { compatible =3D "nvidia,tegra186-asrc"; - reg =3D <0x0 0x2910000 0x0 0x2000>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260902-tegra-ahub-dt-cleanup-v1-5-028f3c5e72f6@nvidia.com> References: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> In-Reply-To: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> To: Thierry Reding , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter Cc: Charan Pedumuru , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11004; i=treding@nvidia.com; h=from:subject:message-id; bh=hbQL2klgrEPLzSnyomCfTSbDn1+k23jngl5f6rHZZvE=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBql/fGNPJbHVRq2nS3/msNw0JZheoiKkz8khgu/ lSjhm8bn+yJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCapf3xgAKCRDdI6zXfz6z oU0qEACAeQ2ohpv7bdWlr+OIwEzT03/P8KTrRQqYY7+/HG/PDB7ESC2x3l0qXTNNlZp3r9ys3+O C6a6SANknJbYD1fcg0hkQPp5e93dQYKaAK5+AFJmIxd/0G8vp7OMPHQvc7AJlT2FwoFg1sr499h QDoT9kSh271qk3GFWH+2+ydw72el4NzDdZ+xN4aGLghujGmtWoszZOZGhOMm7bg1L+u/bY4E1uF tIs22cWmQA0pEjmlBsFu/WlevrtCuQlRnEiXlUBOIMklx7yEpQ001NM7QGmOwe8t0/UKHVr82Dg Q3+kQZZIP4EVL6dwqoEXtf3C/nFiNP6M8R0uQtW8yzshoGRS6vLcQ6f0bCPKskoKpt8vzoytVtj ZTSdenpt/EurdgLa9Z58Mb9kccQ5kqz9gZuj6q1MA8oh54egLRTFF4U7o9AjRvH7mJO92gdjkHc cXpoYRoE+HZ3BAVk7fJ87AAbWUo2uycRCKFyrHb/69xv8E0OB59FcxZwezbvjJSrnrtLkWXnha7 JRNGuevMUubFpjyuGFIjCXGHGRtJRV19GgN57XrshmPiwLtim6eTcoFk8S7e9nnKZzDlG78u6va 7iIwlpJydVU13JQjdg/uyX6eAHC+eIzvD606q31i5EJPPDjZPd4YHl6R8eEmLWTtxVpF3M9BaTv DuH6ant2eoLDFfw== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Use #address-cells =3D <1> and #size-cells =3D <1> because we don't need 64-bit register addressing for this hardware. While at it, also adjust the ranges property to encompass the entire AHUB range as per the TRM. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 74 ++++++++++++++++------------= ---- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index 2b5001d2c3ab..13a95008c186 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -231,14 +231,14 @@ tegra_ahub: ahub@2900800 { assigned-clock-rates =3D <81600000>; status =3D "disabled"; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges =3D <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x02900000 0x0 0x02900000 0x20000>; =20 tegra_i2s1: i2s@2901000 { compatible =3D "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901000 0x0 0x100>; + reg =3D <0x2901000 0x100>; clocks =3D <&bpmp TEGRA194_CLK_I2S1>, <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -252,7 +252,7 @@ tegra_i2s1: i2s@2901000 { tegra_i2s2: i2s@2901100 { compatible =3D "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901100 0x0 0x100>; + reg =3D <0x2901100 0x100>; clocks =3D <&bpmp TEGRA194_CLK_I2S2>, <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -266,7 +266,7 @@ tegra_i2s2: i2s@2901100 { tegra_i2s3: i2s@2901200 { compatible =3D "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901200 0x0 0x100>; + reg =3D <0x2901200 0x100>; clocks =3D <&bpmp TEGRA194_CLK_I2S3>, <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -280,7 +280,7 @@ tegra_i2s3: i2s@2901200 { tegra_i2s4: i2s@2901300 { compatible =3D "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901300 0x0 0x100>; + reg =3D <0x2901300 0x100>; clocks =3D <&bpmp TEGRA194_CLK_I2S4>, <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -294,7 +294,7 @@ tegra_i2s4: i2s@2901300 { tegra_i2s5: i2s@2901400 { compatible =3D "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901400 0x0 0x100>; + reg =3D <0x2901400 0x100>; clocks =3D <&bpmp TEGRA194_CLK_I2S5>, <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -308,7 +308,7 @@ tegra_i2s5: i2s@2901400 { tegra_i2s6: i2s@2901500 { compatible =3D "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901500 0x0 0x100>; + reg =3D <0x2901500 0x100>; clocks =3D <&bpmp TEGRA194_CLK_I2S6>, <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -322,7 +322,7 @@ tegra_i2s6: i2s@2901500 { tegra_sfc1: sfc@2902000 { compatible =3D "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902000 0x0 0x200>; + reg =3D <0x2902000 0x200>; sound-name-prefix =3D "SFC1"; status =3D "disabled"; }; @@ -330,7 +330,7 @@ tegra_sfc1: sfc@2902000 { tegra_sfc2: sfc@2902200 { compatible =3D "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902200 0x0 0x200>; + reg =3D <0x2902200 0x200>; sound-name-prefix =3D "SFC2"; status =3D "disabled"; }; @@ -338,7 +338,7 @@ tegra_sfc2: sfc@2902200 { tegra_sfc3: sfc@2902400 { compatible =3D "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902400 0x0 0x200>; + reg =3D <0x2902400 0x200>; sound-name-prefix =3D "SFC3"; status =3D "disabled"; }; @@ -346,35 +346,35 @@ tegra_sfc3: sfc@2902400 { tegra_sfc4: sfc@2902600 { compatible =3D "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902600 0x0 0x200>; + reg =3D <0x2902600 0x200>; sound-name-prefix =3D "SFC4"; status =3D "disabled"; }; =20 tegra_amx1: amx@2903000 { compatible =3D "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903000 0x0 0x100>; + reg =3D <0x2903000 0x100>; sound-name-prefix =3D "AMX1"; status =3D "disabled"; }; =20 tegra_amx2: amx@2903100 { compatible =3D "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903100 0x0 0x100>; + reg =3D <0x2903100 0x100>; sound-name-prefix =3D "AMX2"; status =3D "disabled"; }; =20 tegra_amx3: amx@2903200 { compatible =3D "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903200 0x0 0x100>; + reg =3D <0x2903200 0x100>; sound-name-prefix =3D "AMX3"; status =3D "disabled"; }; =20 tegra_amx4: amx@2903300 { compatible =3D "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903300 0x0 0x100>; + reg =3D <0x2903300 0x100>; sound-name-prefix =3D "AMX4"; status =3D "disabled"; }; @@ -382,7 +382,7 @@ tegra_amx4: amx@2903300 { tegra_adx1: adx@2903800 { compatible =3D "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903800 0x0 0x100>; + reg =3D <0x2903800 0x100>; sound-name-prefix =3D "ADX1"; status =3D "disabled"; }; @@ -390,7 +390,7 @@ tegra_adx1: adx@2903800 { tegra_adx2: adx@2903900 { compatible =3D "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903900 0x0 0x100>; + reg =3D <0x2903900 0x100>; sound-name-prefix =3D "ADX2"; status =3D "disabled"; }; @@ -398,7 +398,7 @@ tegra_adx2: adx@2903900 { tegra_adx3: adx@2903a00 { compatible =3D "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903a00 0x0 0x100>; + reg =3D <0x2903a00 0x100>; sound-name-prefix =3D "ADX3"; status =3D "disabled"; }; @@ -406,7 +406,7 @@ tegra_adx3: adx@2903a00 { tegra_adx4: adx@2903b00 { compatible =3D "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903b00 0x0 0x100>; + reg =3D <0x2903b00 0x100>; sound-name-prefix =3D "ADX4"; status =3D "disabled"; }; @@ -414,7 +414,7 @@ tegra_adx4: adx@2903b00 { tegra_dmic1: dmic@2904000 { compatible =3D "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904000 0x0 0x100>; + reg =3D <0x2904000 0x100>; clocks =3D <&bpmp TEGRA194_CLK_DMIC1>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA194_CLK_DMIC1>; @@ -427,7 +427,7 @@ tegra_dmic1: dmic@2904000 { tegra_dmic2: dmic@2904100 { compatible =3D "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904100 0x0 0x100>; + reg =3D <0x2904100 0x100>; clocks =3D <&bpmp TEGRA194_CLK_DMIC2>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA194_CLK_DMIC2>; @@ -440,7 +440,7 @@ tegra_dmic2: dmic@2904100 { tegra_dmic3: dmic@2904200 { compatible =3D "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904200 0x0 0x100>; + reg =3D <0x2904200 0x100>; clocks =3D <&bpmp TEGRA194_CLK_DMIC3>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA194_CLK_DMIC3>; @@ -453,7 +453,7 @@ tegra_dmic3: dmic@2904200 { tegra_dmic4: dmic@2904300 { compatible =3D "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904300 0x0 0x100>; + reg =3D <0x2904300 0x100>; clocks =3D <&bpmp TEGRA194_CLK_DMIC4>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA194_CLK_DMIC4>; @@ -466,7 +466,7 @@ tegra_dmic4: dmic@2904300 { tegra_dspk1: dspk@2905000 { compatible =3D "nvidia,tegra194-dspk", "nvidia,tegra186-dspk"; - reg =3D <0x0 0x2905000 0x0 0x100>; + reg =3D <0x2905000 0x100>; clocks =3D <&bpmp TEGRA194_CLK_DSPK1>; clock-names =3D "dspk"; assigned-clocks =3D <&bpmp TEGRA194_CLK_DSPK1>; @@ -479,7 +479,7 @@ tegra_dspk1: dspk@2905000 { tegra_dspk2: dspk@2905100 { compatible =3D "nvidia,tegra194-dspk", "nvidia,tegra186-dspk"; - reg =3D <0x0 0x2905100 0x0 0x100>; + reg =3D <0x2905100 0x100>; clocks =3D <&bpmp TEGRA194_CLK_DSPK2>; clock-names =3D "dspk"; assigned-clocks =3D <&bpmp TEGRA194_CLK_DSPK2>; @@ -492,31 +492,31 @@ tegra_dspk2: dspk@2905100 { tegra_ope1: processing-engine@2908000 { compatible =3D "nvidia,tegra194-ope", "nvidia,tegra210-ope"; - reg =3D <0x0 0x2908000 0x0 0x100>; + reg =3D <0x2908000 0x100>; sound-name-prefix =3D "OPE1"; status =3D "disabled"; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; ranges; =20 equalizer@2908100 { compatible =3D "nvidia,tegra194-peq", "nvidia,tegra210-peq"; - reg =3D <0x0 0x2908100 0x0 0x100>; + reg =3D <0x2908100 0x100>; }; =20 dynamic-range-compressor@2908200 { compatible =3D "nvidia,tegra194-mbdrc", "nvidia,tegra210-mbdrc"; - reg =3D <0x0 0x2908200 0x0 0x200>; + reg =3D <0x2908200 0x200>; }; }; =20 tegra_mvc1: mvc@290a000 { compatible =3D "nvidia,tegra194-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x290a000 0x0 0x200>; + reg =3D <0x290a000 0x200>; sound-name-prefix =3D "MVC1"; status =3D "disabled"; }; @@ -524,7 +524,7 @@ tegra_mvc1: mvc@290a000 { tegra_mvc2: mvc@290a200 { compatible =3D "nvidia,tegra194-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x290a200 0x0 0x200>; + reg =3D <0x290a200 0x200>; sound-name-prefix =3D "MVC2"; status =3D "disabled"; }; @@ -532,7 +532,7 @@ tegra_mvc2: mvc@290a200 { tegra_amixer: amixer@290bb00 { compatible =3D "nvidia,tegra194-amixer", "nvidia,tegra210-amixer"; - reg =3D <0x0 0x290bb00 0x0 0x800>; + reg =3D <0x290bb00 0x800>; sound-name-prefix =3D "MIXER1"; status =3D "disabled"; }; @@ -540,7 +540,7 @@ tegra_amixer: amixer@290bb00 { tegra_admaif: admaif@290f000 { compatible =3D "nvidia,tegra194-admaif", "nvidia,tegra186-admaif"; - reg =3D <0x0 0x0290f000 0x0 0x1000>; + reg =3D <0x0290f000 0x1000>; dmas =3D <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -591,7 +591,7 @@ tegra_admaif: admaif@290f000 { tegra_asrc: asrc@2910000 { compatible =3D "nvidia,tegra194-asrc", "nvidia,tegra186-asrc"; - reg =3D <0x0 0x2910000 0x0 0x2000>; + reg =3D <0x2910000 0x2000>; sound-name-prefix =3D "ASRC1"; status =3D "disabled"; }; --=20 2.55.0 From nobody Sat Sep 26 10:03:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 307C043F096; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260902-tegra-ahub-dt-cleanup-v1-6-028f3c5e72f6@nvidia.com> References: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> In-Reply-To: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> To: Thierry Reding , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter Cc: Charan Pedumuru , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10939; i=treding@nvidia.com; h=from:subject:message-id; bh=WT8ymqFWkLY1Ro1AD/3nGXACUszqWSLYryOIK7D1E+s=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBql/fHzD9FzdyV22RExrGdHF3MtZG5ggvKyThTA AebO2q7dtuJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCapf3xwAKCRDdI6zXfz6z od3iD/90NJX0MgJPYLUUAOuUo6BdEBLRg5jomlDBxkN2ek8XUxVYzfUr1+5kQxJ3+KE1tyMAmfC XpPiKg25bhFRldhlyB3iamvItepiJCt4Ylz9cX9mEsdf+pPWcb05E4hTHTIwd75Di86JwNpynKU IwdYycEjR2XemYYbvdwmXIB/VGwZ3HtfE1ToU1k5irsqk3MLDDBncbqCBcSxLdYez92/u9b30bU 3bKiXgQ29LKEXBGXAOjYzPPqU/jyN7YzvN3+CbZeTDPqlyJ0xIpRy0zSB89fopTH6HmEcog7QHA aQGufuxedbcpey/xVCfM4/0mIWK6+z6mexhpe2sNFFABfH/V8nOrysc9nomvdkMb8akmq3rl746 tMaExWlfnsUE4sMmPBajktKwCAzjI/mvpN17tRhqZVCmD07vYJVqVGmMpnevT14xSuKpYqxtWxB ULfvfFoABAGunrkfv6XV8JbvCJ9yBjTSngGhPt59IzHGYDsPkbsjxGDQqiaBMTypFW05r6X2Cym rapay9uvdlcFP00tpbbZ3Qn6IFM/NVZxFtPrKJQ4lMROg3zfOlk5qBUTtuJxNjHM3woAt/vHOKt hIBaaneqiqBvcYOxA2X3syvxMhiU96U3kw451ColFMUp2MbBN3LG1ufmK89eVuM7HN6SyvX9Ve+ jqL/9gV/60P5knw== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Use #address-cells =3D <1> and #size-cells =3D <1> because we don't need 64-bit register addressing for this hardware. While at it, also adjust the ranges property to encompass the entire AHUB range as per the TRM. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 74 ++++++++++++++++------------= ---- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 5e29316a4d75..5311245334de 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -245,14 +245,14 @@ tegra_ahub: ahub@2900800 { assigned-clock-rates =3D <81600000>; status =3D "disabled"; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges =3D <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x02900000 0x0 0x02900000 0x20000>; =20 tegra_i2s1: i2s@2901000 { compatible =3D "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901000 0x0 0x100>; + reg =3D <0x2901000 0x100>; clocks =3D <&bpmp TEGRA234_CLK_I2S1>, <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -288,7 +288,7 @@ i2s1_dap: endpoint { tegra_i2s2: i2s@2901100 { compatible =3D "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901100 0x0 0x100>; + reg =3D <0x2901100 0x100>; clocks =3D <&bpmp TEGRA234_CLK_I2S2>, <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -324,7 +324,7 @@ i2s2_dap: endpoint { tegra_i2s3: i2s@2901200 { compatible =3D "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901200 0x0 0x100>; + reg =3D <0x2901200 0x100>; clocks =3D <&bpmp TEGRA234_CLK_I2S3>, <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -360,7 +360,7 @@ i2s3_dap: endpoint { tegra_i2s4: i2s@2901300 { compatible =3D "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901300 0x0 0x100>; + reg =3D <0x2901300 0x100>; clocks =3D <&bpmp TEGRA234_CLK_I2S4>, <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -396,7 +396,7 @@ i2s4_dap: endpoint { tegra_i2s5: i2s@2901400 { compatible =3D "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901400 0x0 0x100>; + reg =3D <0x2901400 0x100>; clocks =3D <&bpmp TEGRA234_CLK_I2S5>, <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -432,7 +432,7 @@ i2s5_dap: endpoint { tegra_i2s6: i2s@2901500 { compatible =3D "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg =3D <0x0 0x2901500 0x0 0x100>; + reg =3D <0x2901500 0x100>; clocks =3D <&bpmp TEGRA234_CLK_I2S6>, <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; clock-names =3D "i2s", "sync_input"; @@ -468,7 +468,7 @@ i2s6_dap: endpoint { tegra_sfc1: sfc@2902000 { compatible =3D "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902000 0x0 0x200>; + reg =3D <0x2902000 0x200>; sound-name-prefix =3D "SFC1"; =20 ports { @@ -496,7 +496,7 @@ sfc1_cif_out: endpoint { tegra_sfc2: sfc@2902200 { compatible =3D "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902200 0x0 0x200>; + reg =3D <0x2902200 0x200>; sound-name-prefix =3D "SFC2"; =20 ports { @@ -524,7 +524,7 @@ sfc2_cif_out: endpoint { tegra_sfc3: sfc@2902400 { compatible =3D "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902400 0x0 0x200>; + reg =3D <0x2902400 0x200>; sound-name-prefix =3D "SFC3"; =20 ports { @@ -552,7 +552,7 @@ sfc3_cif_out: endpoint { tegra_sfc4: sfc@2902600 { compatible =3D "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x2902600 0x0 0x200>; + reg =3D <0x2902600 0x200>; sound-name-prefix =3D "SFC4"; =20 ports { @@ -580,7 +580,7 @@ sfc4_cif_out: endpoint { tegra_amx1: amx@2903000 { compatible =3D "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903000 0x0 0x100>; + reg =3D <0x2903000 0x100>; sound-name-prefix =3D "AMX1"; =20 ports { @@ -632,7 +632,7 @@ amx1_out: endpoint { tegra_amx2: amx@2903100 { compatible =3D "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903100 0x0 0x100>; + reg =3D <0x2903100 0x100>; sound-name-prefix =3D "AMX2"; =20 ports { @@ -684,7 +684,7 @@ amx2_out: endpoint { tegra_amx3: amx@2903200 { compatible =3D "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903200 0x0 0x100>; + reg =3D <0x2903200 0x100>; sound-name-prefix =3D "AMX3"; =20 ports { @@ -736,7 +736,7 @@ amx3_out: endpoint { tegra_amx4: amx@2903300 { compatible =3D "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg =3D <0x0 0x2903300 0x0 0x100>; + reg =3D <0x2903300 0x100>; sound-name-prefix =3D "AMX4"; =20 ports { @@ -788,7 +788,7 @@ amx4_out: endpoint { tegra_adx1: adx@2903800 { compatible =3D "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903800 0x0 0x100>; + reg =3D <0x2903800 0x100>; sound-name-prefix =3D "ADX1"; =20 ports { @@ -840,7 +840,7 @@ adx1_out4: endpoint { tegra_adx2: adx@2903900 { compatible =3D "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903900 0x0 0x100>; + reg =3D <0x2903900 0x100>; sound-name-prefix =3D "ADX2"; =20 ports { @@ -892,7 +892,7 @@ adx2_out4: endpoint { tegra_adx3: adx@2903a00 { compatible =3D "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903a00 0x0 0x100>; + reg =3D <0x2903a00 0x100>; sound-name-prefix =3D "ADX3"; =20 ports { @@ -944,7 +944,7 @@ adx3_out4: endpoint { tegra_adx4: adx@2903b00 { compatible =3D "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg =3D <0x0 0x2903b00 0x0 0x100>; + reg =3D <0x2903b00 0x100>; sound-name-prefix =3D "ADX4"; =20 ports { @@ -997,7 +997,7 @@ adx4_out4: endpoint { tegra_dmic1: dmic@2904000 { compatible =3D "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904000 0x0 0x100>; + reg =3D <0x2904000 0x100>; clocks =3D <&bpmp TEGRA234_CLK_DMIC1>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA234_CLK_DMIC1>; @@ -1031,7 +1031,7 @@ dmic1_dap: endpoint { tegra_dmic2: dmic@2904100 { compatible =3D "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904100 0x0 0x100>; + reg =3D <0x2904100 0x100>; clocks =3D <&bpmp TEGRA234_CLK_DMIC2>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA234_CLK_DMIC2>; @@ -1065,7 +1065,7 @@ dmic2_dap: endpoint { tegra_dmic3: dmic@2904200 { compatible =3D "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904200 0x0 0x100>; + reg =3D <0x2904200 0x100>; clocks =3D <&bpmp TEGRA234_CLK_DMIC3>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA234_CLK_DMIC3>; @@ -1099,7 +1099,7 @@ dmic3_dap: endpoint { tegra_dmic4: dmic@2904300 { compatible =3D "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x2904300 0x0 0x100>; + reg =3D <0x2904300 0x100>; clocks =3D <&bpmp TEGRA234_CLK_DMIC4>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA234_CLK_DMIC4>; @@ -1133,7 +1133,7 @@ dmic4_dap: endpoint { tegra_dspk1: dspk@2905000 { compatible =3D "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg =3D <0x0 0x2905000 0x0 0x100>; + reg =3D <0x2905000 0x100>; clocks =3D <&bpmp TEGRA234_CLK_DSPK1>; clock-names =3D "dspk"; assigned-clocks =3D <&bpmp TEGRA234_CLK_DSPK1>; @@ -1167,7 +1167,7 @@ dspk1_dap: endpoint { tegra_dspk2: dspk@2905100 { compatible =3D "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg =3D <0x0 0x2905100 0x0 0x100>; + reg =3D <0x2905100 0x100>; clocks =3D <&bpmp TEGRA234_CLK_DSPK2>; clock-names =3D "dspk"; assigned-clocks =3D <&bpmp TEGRA234_CLK_DSPK2>; @@ -1201,23 +1201,23 @@ dspk2_dap: endpoint { tegra_ope1: processing-engine@2908000 { compatible =3D "nvidia,tegra234-ope", "nvidia,tegra210-ope"; - reg =3D <0x0 0x2908000 0x0 0x100>; + reg =3D <0x2908000 0x100>; sound-name-prefix =3D "OPE1"; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; ranges; =20 equalizer@2908100 { compatible =3D "nvidia,tegra234-peq", "nvidia,tegra210-peq"; - reg =3D <0x0 0x2908100 0x0 0x100>; + reg =3D <0x2908100 0x100>; }; =20 dynamic-range-compressor@2908200 { compatible =3D "nvidia,tegra234-mbdrc", "nvidia,tegra210-mbdrc"; - reg =3D <0x0 0x2908200 0x0 0x200>; + reg =3D <0x2908200 0x200>; }; =20 ports { @@ -1247,7 +1247,7 @@ ope1_cif_out_ep: endpoint { tegra_mvc1: mvc@290a000 { compatible =3D "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x290a000 0x0 0x200>; + reg =3D <0x290a000 0x200>; sound-name-prefix =3D "MVC1"; =20 ports { @@ -1275,7 +1275,7 @@ mvc1_cif_out: endpoint { tegra_mvc2: mvc@290a200 { compatible =3D "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x290a200 0x0 0x200>; + reg =3D <0x290a200 0x200>; sound-name-prefix =3D "MVC2"; =20 ports { @@ -1303,7 +1303,7 @@ mvc2_cif_out: endpoint { tegra_amixer: amixer@290bb00 { compatible =3D "nvidia,tegra234-amixer", "nvidia,tegra210-amixer"; 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Wed, 2 Sep 2026 10:17:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788344259; bh=n0SJRaGdS4MG/TqpmgJaAYbQroom687Cpb0dW+qqIm4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=WdQ3DbJoOwFmyD0lG336eEfmrsGzJz6OeQBjZMIjztwTgAMiTVsDGgF+SORtVVmtG rPda2OR8MF1KtOXW02npDJne2+yKFCBeKesOBOxaGF1mAHYRonKPCCau/KNR7Xuvqt sEzEqBBi61sAMlxLLs807BFzmwhOIauL8X8GVQbjjupGWx3GcBbH11Qv0a9sGxbuUQ gr8TfKGdVMBP98X8KUGRAYVIqhEz1Hiz59mT1oe4RCjCK6O39eT1rc2AOHLBSY1h80 a+yihtjpz8gV7otg5dqwS6HSP/6THDa9C08HHnzfM0q9clPJQQ3CpTPTfCiy3rMAVI gVTDlbBdn3jvw== From: Thierry Reding Date: Wed, 02 Sep 2026 12:17:43 +0200 Subject: [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260902-tegra-ahub-dt-cleanup-v1-7-028f3c5e72f6@nvidia.com> References: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> In-Reply-To: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> To: Thierry Reding , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter Cc: Charan Pedumuru , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Use #address-cells =3D <1> and #size-cells =3D <1> because we don't need 64-bit register addressing for this hardware. While at it, also adjust the ranges property to encompass the entire AHUB range as per the TRM. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 118 +++++++++++++++------------= ---- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 6b2e3a6ab810..4ed7dabafee5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -129,13 +129,13 @@ aconnect@9000000 { power-domains =3D <&bpmp TEGRA264_POWER_DOMAIN_AUD>; status =3D "disabled"; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges =3D <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x9000000 0x0 0x9000000 0x2000000>; =20 adma: dma-controller@9440000 { compatible =3D "nvidia,tegra264-adma"; - reg =3D <0x0 0x9440000 0x0 0xb0000>; + reg =3D <0x9440000 0xb0000>; interrupt-parent =3D <&agic_page0>; interrupts =3D , , @@ -209,22 +209,22 @@ adma: dma-controller@9440000 { =20 tegra_ahub: ahub@9630000 { compatible =3D "nvidia,tegra264-ahub"; - reg =3D <0x0 0x9630000 0x0 0x10000>; + reg =3D <0x9630000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_AHUB>; clock-names =3D "ahub"; assigned-clocks =3D <&bpmp TEGRA264_CLK_AHUB>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLAON_APE>; status =3D "disabled"; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; /* ADMA is under AHUB range, its excluded in the defined range */ - ranges =3D <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>, - <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>; + ranges =3D <0x9280000 0x0 0x9280000 0x1c0000>, + <0x9510000 0x0 0x9510000 0x370000>; =20 tegra_i2s1: i2s@9280000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x9280000 0x0 0x10000>; + reg =3D <0x9280000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S1>, <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -259,7 +259,7 @@ i2s1_dap: endpoint { =20 tegra_i2s2: i2s@9290000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x9290000 0x0 0x10000>; + reg =3D <0x9290000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S2>, <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -294,7 +294,7 @@ i2s2_dap: endpoint { =20 tegra_i2s3: i2s@92a0000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x92a0000 0x0 0x10000>; + reg =3D <0x92a0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S3>, <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -329,7 +329,7 @@ i2s3_dap: endpoint { =20 tegra_i2s4: i2s@92b0000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x92b0000 0x0 0x10000>; + reg =3D <0x92b0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S4>, <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -364,7 +364,7 @@ i2s4_dap: endpoint { =20 tegra_i2s5: i2s@92c0000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x92c0000 0x0 0x10000>; + reg =3D <0x92c0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S5>, <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -399,7 +399,7 @@ i2s5_dap: endpoint { =20 tegra_i2s6: i2s@92d0000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x92d0000 0x0 0x10000>; + reg =3D <0x92d0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S6>, <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -434,7 +434,7 @@ i2s6_dap: endpoint { =20 tegra_i2s7: i2s@92e0000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x92e0000 0x0 0x10000>; + reg =3D <0x92e0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S7>, <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -469,7 +469,7 @@ i2s7_dap: endpoint { =20 tegra_i2s8: i2s@92f0000 { compatible =3D "nvidia,tegra264-i2s"; - reg =3D <0x0 0x92f0000 0x0 0x10000>; + reg =3D <0x92f0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S8>, <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; clock-names =3D "i2s", "sync_input"; @@ -505,7 +505,7 @@ i2s8_dap: endpoint { tegra_dmic1: dmic@9300000 { compatible =3D "nvidia,tegra264-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x9300000 0x0 0x10000>; + reg =3D <0x9300000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; @@ -539,7 +539,7 @@ dmic1_dap: endpoint { tegra_dmic2: dmic@9310000 { compatible =3D "nvidia,tegra264-dmic", "nvidia,tegra210-dmic"; - reg =3D <0x0 0x9310000 0x0 0x10000>; + reg =3D <0x9310000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; clock-names =3D "dmic"; assigned-clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; @@ -573,7 +573,7 @@ dmic2_dap: endpoint { tegra_dspk1: dspk@9380000 { compatible =3D "nvidia,tegra264-dspk", "nvidia,tegra186-dspk"; - reg =3D <0x0 0x9380000 0x0 0x10000>; + reg =3D <0x9380000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_DSPK1>; clock-names =3D "dspk"; assigned-clocks =3D <&bpmp TEGRA264_CLK_DSPK1>; @@ -606,7 +606,7 @@ dspk1_dap: endpoint { =20 tegra_amx1: amx@9510000 { compatible =3D "nvidia,tegra264-amx"; - reg =3D <0x0 0x9510000 0x0 0x10000>; + reg =3D <0x9510000 0x10000>; sound-name-prefix =3D "AMX1"; =20 ports { @@ -657,7 +657,7 @@ amx1_out: endpoint { =20 tegra_amx2: amx@9520000 { compatible =3D "nvidia,tegra264-amx"; - reg =3D <0x0 0x9520000 0x0 0x10000>; + reg =3D <0x9520000 0x10000>; sound-name-prefix =3D "AMX2"; =20 ports { @@ -708,7 +708,7 @@ amx2_out: endpoint { =20 tegra_amx3: amx@9530000 { compatible =3D "nvidia,tegra264-amx"; - reg =3D <0x0 0x9530000 0x0 0x10000>; + reg =3D <0x9530000 0x10000>; sound-name-prefix =3D "AMX3"; =20 ports { @@ -759,7 +759,7 @@ amx3_out: endpoint { =20 tegra_amx4: amx@9540000 { compatible =3D "nvidia,tegra264-amx"; - reg =3D <0x0 0x9540000 0x0 0x10000>; + reg =3D <0x9540000 0x10000>; sound-name-prefix =3D "AMX4"; =20 ports { @@ -810,7 +810,7 @@ amx4_out: endpoint { =20 tegra_amx5: amx@9550000 { compatible =3D "nvidia,tegra264-amx"; - reg =3D <0x0 0x9550000 0x0 0x10000>; + reg =3D <0x9550000 0x10000>; sound-name-prefix =3D "AMX5"; =20 ports { @@ -861,7 +861,7 @@ amx5_out: endpoint { =20 tegra_amx6: amx@9560000 { compatible =3D "nvidia,tegra264-amx"; - reg =3D <0x0 0x9560000 0x0 0x10000>; + reg =3D <0x9560000 0x10000>; sound-name-prefix =3D "AMX6"; =20 ports { @@ -912,7 +912,7 @@ amx6_out: endpoint { =20 tegra_adx1: adx@9590000 { compatible =3D "nvidia,tegra264-adx"; - reg =3D <0x0 0x9590000 0x0 0x10000>; + reg =3D <0x9590000 0x10000>; sound-name-prefix =3D "ADX1"; =20 ports { @@ -963,7 +963,7 @@ adx1_out4: endpoint { =20 tegra_adx2: adx@95a0000 { compatible =3D "nvidia,tegra264-adx"; - reg =3D <0x0 0x95a0000 0x0 0x10000>; + reg =3D <0x95a0000 0x10000>; sound-name-prefix =3D "ADX2"; =20 ports { @@ -1014,7 +1014,7 @@ adx2_out4: endpoint { =20 tegra_adx3: adx@95b0000 { compatible =3D "nvidia,tegra264-adx"; - reg =3D <0x0 0x95b0000 0x0 0x10000>; + reg =3D <0x95b0000 0x10000>; sound-name-prefix =3D "ADX3"; =20 ports { @@ -1065,7 +1065,7 @@ adx3_out4: endpoint { =20 tegra_adx4: adx@95c0000 { compatible =3D "nvidia,tegra264-adx"; - reg =3D <0x0 0x95c0000 0x0 0x10000>; + reg =3D <0x95c0000 0x10000>; sound-name-prefix =3D "ADX4"; =20 ports { @@ -1116,7 +1116,7 @@ adx4_out4: endpoint { =20 tegra_adx5: adx@95d0000 { compatible =3D "nvidia,tegra264-adx"; - reg =3D <0x0 0x95d0000 0x0 0x10000>; + reg =3D <0x95d0000 0x10000>; sound-name-prefix =3D "ADX5"; =20 ports { @@ -1167,7 +1167,7 @@ adx5_out4: endpoint { =20 tegra_adx6: adx@95e0000 { compatible =3D "nvidia,tegra264-adx"; - reg =3D <0x0 0x95e0000 0x0 0x10000>; + reg =3D <0x95e0000 0x10000>; sound-name-prefix =3D "ADX6"; =20 ports { @@ -1218,7 +1218,7 @@ adx6_out4: endpoint { =20 tegra_admaif: admaif@9610000 { compatible =3D "nvidia,tegra264-admaif"; - reg =3D <0x0 0x9610000 0x0 0x10000>; + reg =3D <0x9610000 0x10000>; dmas =3D <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -1556,7 +1556,7 @@ admaif31: endpoint { tegra_sfc1: sfc@9700000 { compatible =3D "nvidia,tegra264-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x9700000 0x0 0x10000>; + reg =3D <0x9700000 0x10000>; sound-name-prefix =3D "SFC1"; =20 ports { @@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint { tegra_sfc2: sfc@9710000 { compatible =3D "nvidia,tegra264-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x9710000 0x0 0x10000>; + reg =3D <0x9710000 x0 0x10000>; sound-name-prefix =3D "SFC2"; =20 ports { @@ -1612,7 +1612,7 @@ sfc2_cif_out: endpoint { tegra_sfc3: sfc@9720000 { compatible =3D "nvidia,tegra264-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x9720000 0x0 0x10000>; + reg =3D <0x9720000 0x10000>; sound-name-prefix =3D "SFC3"; =20 ports { @@ -1640,7 +1640,7 @@ sfc3_cif_out: endpoint { tegra_sfc4: sfc@9730000 { compatible =3D "nvidia,tegra264-sfc", "nvidia,tegra210-sfc"; - reg =3D <0x0 0x9730000 0x0 0x10000>; + reg =3D <0x9730000 0x10000>; sound-name-prefix =3D "SFC4"; =20 ports { @@ -1668,22 +1668,22 @@ sfc4_cif_out: endpoint { tegra_ope1: processing-engine@9780000 { compatible =3D "nvidia,tegra264-ope", "nvidia,tegra210-ope"; - reg =3D <0x0 0x9780000 0x0 0x10000>; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges =3D <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>; + reg =3D <0x9780000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x9780000 0x9780000 0x30000>; sound-name-prefix =3D "OPE1"; =20 equalizer@9790000 { compatible =3D "nvidia,tegra264-peq", "nvidia,tegra210-peq"; - reg =3D <0x0 0x9790000 0x0 0x10000>; + reg =3D <0x9790000 0x10000>; }; =20 dynamic-range-compressor@97a0000 { compatible =3D "nvidia,tegra264-mbdrc", "nvidia,tegra210-mbdrc"; - reg =3D <0x0 0x97a0000 0x0 0x10000>; + reg =3D <0x97a0000 0x10000>; }; =20 ports { @@ -1713,7 +1713,7 @@ ope1_cif_out_ep: endpoint { tegra_mvc1: mvc@9800000 { compatible =3D "nvidia,tegra264-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x9800000 0x0 0x10000>; + reg =3D <0x9800000 0x10000>; sound-name-prefix =3D "MVC1"; =20 ports { @@ -1741,7 +1741,7 @@ mvc1_cif_out: endpoint { tegra_mvc2: mvc@9810000 { compatible =3D "nvidia,tegra264-mvc", "nvidia,tegra210-mvc"; - reg =3D <0x0 0x9810000 0x0 0x10000>; + reg =3D <0x9810000 0x10000>; sound-name-prefix =3D "MVC2"; =20 ports { @@ -1769,7 +1769,7 @@ mvc2_cif_out: endpoint { tegra_amixer: amixer@9820000 { compatible =3D "nvidia,tegra264-amixer", "nvidia,tegra210-amixer"; - reg =3D <0x0 0x9820000 0x0 0x10000>; + reg =3D <0x9820000 0x10000>; sound-name-prefix =3D "MIXER1"; =20 ports { @@ -1900,7 +1900,7 @@ mix_out5: endpoint { =20 tegra_asrc: asrc@9850000 { compatible =3D "nvidia,tegra264-asrc"; - reg =3D <0x0 0x9850000 0x0 0x10000>; + reg =3D <0x9850000 0x10000>; sound-name-prefix =3D "ASRC1"; =20 ports { @@ -3197,8 +3197,8 @@ agic_page0: interrupt-controller@9960000 { "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; - reg =3D <0x0 0x9961000 0x0 0x1000>, - <0x0 0x9962000 0x0 0x1000>; + reg =3D <0x9961000 0x1000>, + <0x9962000 0x1000>; interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; @@ -3211,8 +3211,8 @@ agic_page1: interrupt-controller@9970000 { "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; - reg =3D <0x0 0x9971000 0x0 0x1000>, - <0x0 0x9972000 0x0 0x1000>; + reg =3D <0x9971000 0x1000>, + <0x9972000 0x1000>; interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; @@ -3225,8 +3225,8 @@ agic_page2: interrupt-controller@9980000 { "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; - reg =3D <0x0 0x9981000 0x0 0x1000>, - <0x0 0x9982000 0x0 0x1000>; + reg =3D <0x9981000 0x1000>, + <0x9982000 0x1000>; interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; @@ -3239,8 +3239,8 @@ agic_page3: interrupt-controller@9990000 { "nvidia,tegra210-agic"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260902-tegra-ahub-dt-cleanup-v1-8-028f3c5e72f6@nvidia.com> References: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> In-Reply-To: <20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com> To: Thierry Reding , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter Cc: Charan Pedumuru , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=25297; i=treding@nvidia.com; h=from:subject:message-id; bh=kRqN8Qxq+TFAQbzKJQeayHK8HQsX44xJTReAIa+mH24=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBql/fHlcjvhgDl+Du52Jkwn8NFnega+ZK5cdTGz RtCmy8JfmqJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCapf3xwAKCRDdI6zXfz6z oeaOD/969YnfdIPss+34+6KJouMjzy2oyJw1zB+z1SN6sJUdy7C6WtaA9buX6oHk6xdesX4Bgmc 5u1tiPd1Z4gwGgK9/vSwX7B+7MbYMiSjxPYflbh14s/wsMYyC/CdW7Eg+hqEOWtaSTcmkzX7Wvx TpETT1wBZ0bx+B8B0AAITg5kFVVE0vXfw1gQLM4Vh05vrWwmQmqldQVYQJLQ/lAYbNJ8ueRL75/ 6HCLZ8fcRVJwi6wfj+i8tumr1PyNEQCcVDv2x7n33DKZ0E8BOYcf3EQbaqMyXwlbCq/RVCv63dv 9sJSeYKNLleM/LaO6CFVr6gjVzo48bFJnyMg9/XBLex32WOeXV6U72JQfhG5DVqpCvX8VLIjgrC 1Lv5xFQeWr9JXdd31DX4xXd8gOLlMvU6bzaPd1CP2xdgrApEVBtv5u8oqtnjUNfn88QECnDZhzX bdtEpQLrhdC9UV6Lx1DYoFfeXdSO2ppVqEMyHK8A5lXRo9A/asIUWkZnFlZnV/dyktlRM5q5+4E kDyYXkc8EbDoiVQHT9ktz7xKPH3vmWyVSuXd91424NPx1UAYrzbUgMMjPivzaYqDG6JTRJ3++Qo yOPNA36qUEwDX0ZaCwNKbGmsAISsM28Sk0e+KnJbu4sVJWo6AwcFwl9KwQnpBKais5zFW54hd3g 6AJG3qjE8rb+OXA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Properly align property names and values, and remove gratuitous wrapping. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 376 +++++++++++++++------------= ---- 1 file changed, 177 insertions(+), 199 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 4ed7dabafee5..f011cd6e56e0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -122,9 +122,9 @@ hsp_top: hsp@8800000 { =20 aconnect@9000000 { compatible =3D "nvidia,tegra264-aconnect", - "nvidia,tegra210-aconnect"; + "nvidia,tegra210-aconnect"; clocks =3D <&bpmp TEGRA264_CLK_APE>, - <&bpmp TEGRA264_CLK_ADSP>; + <&bpmp TEGRA264_CLK_ADSP>; clock-names =3D "ape", "apb2ape"; power-domains =3D <&bpmp TEGRA264_POWER_DOMAIN_AUD>; status =3D "disabled"; @@ -138,69 +138,69 @@ adma: dma-controller@9440000 { reg =3D <0x9440000 0xb0000>; interrupt-parent =3D <&agic_page0>; interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; #dma-cells =3D <1>; clocks =3D <&bpmp TEGRA264_CLK_AHUB>; clock-names =3D "d_audio"; @@ -226,7 +226,7 @@ tegra_i2s1: i2s@9280000 { compatible =3D "nvidia,tegra264-i2s"; reg =3D <0x9280000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S1>, - <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; clock-names =3D "i2s", "sync_input"; assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S1>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -296,7 +296,7 @@ tegra_i2s3: i2s@92a0000 { compatible =3D "nvidia,tegra264-i2s"; reg =3D <0x92a0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S3>, - <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; clock-names =3D "i2s", "sync_input"; assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S3>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -331,7 +331,7 @@ tegra_i2s4: i2s@92b0000 { compatible =3D "nvidia,tegra264-i2s"; reg =3D <0x92b0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S4>, - <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; clock-names =3D "i2s", "sync_input"; assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S4>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -366,7 +366,7 @@ tegra_i2s5: i2s@92c0000 { compatible =3D "nvidia,tegra264-i2s"; reg =3D <0x92c0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S5>, - <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; clock-names =3D "i2s", "sync_input"; assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S5>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -401,7 +401,7 @@ tegra_i2s6: i2s@92d0000 { compatible =3D "nvidia,tegra264-i2s"; reg =3D <0x92d0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S6>, - <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; clock-names =3D "i2s", "sync_input"; assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S6>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -436,7 +436,7 @@ tegra_i2s7: i2s@92e0000 { compatible =3D "nvidia,tegra264-i2s"; reg =3D <0x92e0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S7>, - <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; clock-names =3D "i2s", "sync_input"; assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S7>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -471,7 +471,7 @@ tegra_i2s8: i2s@92f0000 { compatible =3D "nvidia,tegra264-i2s"; reg =3D <0x92f0000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_I2S8>, - <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; clock-names =3D "i2s", "sync_input"; assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S8>; assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -504,7 +504,7 @@ i2s8_dap: endpoint { =20 tegra_dmic1: dmic@9300000 { compatible =3D "nvidia,tegra264-dmic", - "nvidia,tegra210-dmic"; + "nvidia,tegra210-dmic"; reg =3D <0x9300000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; clock-names =3D "dmic"; @@ -538,7 +538,7 @@ dmic1_dap: endpoint { =20 tegra_dmic2: dmic@9310000 { compatible =3D "nvidia,tegra264-dmic", - "nvidia,tegra210-dmic"; + "nvidia,tegra210-dmic"; reg =3D <0x9310000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; clock-names =3D "dmic"; @@ -572,7 +572,7 @@ dmic2_dap: endpoint { =20 tegra_dspk1: dspk@9380000 { compatible =3D "nvidia,tegra264-dspk", - "nvidia,tegra186-dspk"; + "nvidia,tegra186-dspk"; reg =3D <0x9380000 0x10000>; clocks =3D <&bpmp TEGRA264_CLK_DSPK1>; clock-names =3D "dspk"; @@ -1220,74 +1220,73 @@ tegra_admaif: admaif@9610000 { compatible =3D "nvidia,tegra264-admaif"; reg =3D <0x9610000 0x10000>; dmas =3D <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>, - <&adma 21>, <&adma 21>, - <&adma 22>, <&adma 22>, - <&adma 23>, <&adma 23>, - <&adma 24>, <&adma 24>, - <&adma 25>, <&adma 25>, - <&adma 26>, <&adma 26>, - <&adma 27>, <&adma 27>, - <&adma 28>, <&adma 28>, - <&adma 29>, <&adma 29>, - <&adma 30>, <&adma 30>, - <&adma 31>, <&adma 31>, - <&adma 32>, <&adma 32>; + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>, + <&adma 21>, <&adma 21>, + <&adma 22>, <&adma 22>, + <&adma 23>, <&adma 23>, + <&adma 24>, <&adma 24>, + <&adma 25>, <&adma 25>, + <&adma 26>, <&adma 26>, + <&adma 27>, <&adma 27>, + <&adma 28>, <&adma 28>, + <&adma 29>, <&adma 29>, + <&adma 30>, <&adma 30>, + <&adma 31>, <&adma 31>, + <&adma 32>, <&adma 32>; dma-names =3D "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20", - "rx21", "tx21", - "rx22", "tx22", - "rx23", "tx23", - "rx24", "tx24", - "rx25", "tx25", - "rx26", "tx26", - "rx27", "tx27", - "rx28", "tx28", - "rx29", "tx29", - "rx30", "tx30", - "rx31", "tx31", - "rx32", "tx32"; + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20", + "rx21", "tx21", + "rx22", "tx22", + "rx23", "tx23", + "rx24", "tx24", + "rx25", "tx25", + "rx26", "tx26", + "rx27", "tx27", + "rx28", "tx28", + "rx29", "tx29", + "rx30", "tx30", + "rx31", "tx31", + "rx32", "tx32"; =20 - interconnects =3D - <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, - <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; - interconnect-names =3D "dma-mem", "write"; + interconnects =3D <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names =3D "dma-mem", "write"; =20 iommus =3D <&smmu1 TEGRA264_SID_APE>; =20 @@ -1555,7 +1554,7 @@ admaif31: endpoint { =20 tegra_sfc1: sfc@9700000 { compatible =3D "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; + "nvidia,tegra210-sfc"; reg =3D <0x9700000 0x10000>; sound-name-prefix =3D "SFC1"; =20 @@ -1583,7 +1582,7 @@ sfc1_cif_out: endpoint { =20 tegra_sfc2: sfc@9710000 { compatible =3D "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; + "nvidia,tegra210-sfc"; reg =3D <0x9710000 x0 0x10000>; sound-name-prefix =3D "SFC2"; =20 @@ -1611,7 +1610,7 @@ sfc2_cif_out: endpoint { =20 tegra_sfc3: sfc@9720000 { compatible =3D "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; + "nvidia,tegra210-sfc"; reg =3D <0x9720000 0x10000>; sound-name-prefix =3D "SFC3"; =20 @@ -1639,7 +1638,7 @@ sfc3_cif_out: endpoint { =20 tegra_sfc4: sfc@9730000 { compatible =3D "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; + "nvidia,tegra210-sfc"; reg =3D <0x9730000 0x10000>; sound-name-prefix =3D "SFC4"; =20 @@ -1667,7 +1666,7 @@ sfc4_cif_out: endpoint { =20 tegra_ope1: processing-engine@9780000 { compatible =3D "nvidia,tegra264-ope", - "nvidia,tegra210-ope"; + "nvidia,tegra210-ope"; reg =3D <0x9780000 0x10000>; #address-cells =3D <1>; #size-cells =3D <1>; @@ -1676,13 +1675,13 @@ tegra_ope1: processing-engine@9780000 { =20 equalizer@9790000 { compatible =3D "nvidia,tegra264-peq", - "nvidia,tegra210-peq"; + "nvidia,tegra210-peq"; reg =3D <0x9790000 0x10000>; }; =20 dynamic-range-compressor@97a0000 { compatible =3D "nvidia,tegra264-mbdrc", - "nvidia,tegra210-mbdrc"; + "nvidia,tegra210-mbdrc"; reg =3D <0x97a0000 0x10000>; }; =20 @@ -1694,8 +1693,7 @@ port@0 { reg =3D <0x0>; =20 ope1_cif_in_ep: endpoint { - remote-endpoint =3D - <&xbar_ope1_in_ep>; + remote-endpoint =3D <&xbar_ope1_in_ep>; }; }; =20 @@ -1703,8 +1701,7 @@ ope1_out_port: port@1 { reg =3D <0x1>; =20 ope1_cif_out_ep: endpoint { - remote-endpoint =3D - <&xbar_ope1_out_ep>; + remote-endpoint =3D <&xbar_ope1_out_ep>; }; }; }; @@ -1712,7 +1709,7 @@ ope1_cif_out_ep: endpoint { =20 tegra_mvc1: mvc@9800000 { compatible =3D "nvidia,tegra264-mvc", - "nvidia,tegra210-mvc"; + "nvidia,tegra210-mvc"; reg =3D <0x9800000 0x10000>; sound-name-prefix =3D "MVC1"; =20 @@ -1740,7 +1737,7 @@ mvc1_cif_out: endpoint { =20 tegra_mvc2: mvc@9810000 { compatible =3D "nvidia,tegra264-mvc", - "nvidia,tegra210-mvc"; + "nvidia,tegra210-mvc"; reg =3D <0x9810000 0x10000>; sound-name-prefix =3D "MVC2"; =20 @@ -1768,7 +1765,7 @@ mvc2_cif_out: endpoint { =20 tegra_amixer: amixer@9820000 { compatible =3D "nvidia,tegra264-amixer", - "nvidia,tegra210-amixer"; + "nvidia,tegra210-amixer"; reg =3D <0x9820000 0x10000>; sound-name-prefix =3D "MIXER1"; =20 @@ -1911,8 +1908,7 @@ port@0 { reg =3D <0x0>; =20 asrc_in1_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_in1_ep>; + remote-endpoint =3D <&xbar_asrc_in1_ep>; }; }; =20 @@ -1920,8 +1916,7 @@ port@1 { reg =3D <0x1>; =20 asrc_in2_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_in2_ep>; + remote-endpoint =3D <&xbar_asrc_in2_ep>; }; }; =20 @@ -1929,8 +1924,7 @@ port@2 { reg =3D <0x2>; =20 asrc_in3_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_in3_ep>; + remote-endpoint =3D <&xbar_asrc_in3_ep>; }; }; =20 @@ -1938,8 +1932,7 @@ port@3 { reg =3D <0x3>; =20 asrc_in4_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_in4_ep>; + remote-endpoint =3D <&xbar_asrc_in4_ep>; }; }; =20 @@ -1947,8 +1940,7 @@ port@4 { reg =3D <0x4>; =20 asrc_in5_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_in5_ep>; + remote-endpoint =3D <&xbar_asrc_in5_ep>; }; }; =20 @@ -1956,8 +1948,7 @@ port@5 { reg =3D <0x5>; =20 asrc_in6_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_in6_ep>; + remote-endpoint =3D <&xbar_asrc_in6_ep>; }; }; =20 @@ -1965,8 +1956,7 @@ port@6 { reg =3D <0x6>; =20 asrc_in7_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_in7_ep>; + remote-endpoint =3D <&xbar_asrc_in7_ep>; }; }; =20 @@ -1974,8 +1964,7 @@ asrc_out1_port: port@7 { reg =3D <0x7>; =20 asrc_out1_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_out1_ep>; + remote-endpoint =3D <&xbar_asrc_out1_ep>; }; }; =20 @@ -1983,8 +1972,7 @@ asrc_out2_port: port@8 { reg =3D <0x8>; =20 asrc_out2_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_out2_ep>; + remote-endpoint =3D <&xbar_asrc_out2_ep>; }; }; =20 @@ -1992,8 +1980,7 @@ asrc_out3_port: port@9 { reg =3D <0x9>; =20 asrc_out3_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_out3_ep>; + remote-endpoint =3D <&xbar_asrc_out3_ep>; }; }; =20 @@ -2001,8 +1988,7 @@ asrc_out4_port: port@a { reg =3D <0xa>; =20 asrc_out4_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_out4_ep>; + remote-endpoint =3D <&xbar_asrc_out4_ep>; }; }; =20 @@ -2010,8 +1996,7 @@ asrc_out5_port: port@b { reg =3D <0xb>; =20 asrc_out5_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_out5_ep>; + remote-endpoint =3D <&xbar_asrc_out5_ep>; }; }; =20 @@ -2019,8 +2004,7 @@ asrc_out6_port: port@c { reg =3D <0xc>; =20 asrc_out6_ep: endpoint { - remote-endpoint =3D - <&xbar_asrc_out6_ep>; + remote-endpoint =3D <&xbar_asrc_out6_ep>; }; }; }; @@ -3194,13 +3178,12 @@ xbar_ope1_out_ep: endpoint { =20 agic_page0: interrupt-controller@9960000 { compatible =3D "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; reg =3D <0x9961000 0x1000>, <0x9962000 0x1000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; clock-names =3D "clk"; status =3D "disabled"; @@ -3208,13 +3191,12 @@ agic_page0: interrupt-controller@9960000 { =20 agic_page1: interrupt-controller@9970000 { compatible =3D "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; reg =3D <0x9971000 0x1000>, <0x9972000 0x1000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; clock-names =3D "clk"; status =3D "disabled"; @@ -3222,13 +3204,12 @@ agic_page1: interrupt-controller@9970000 { =20 agic_page2: interrupt-controller@9980000 { compatible =3D "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; reg =3D <0x9981000 0x1000>, <0x9982000 0x1000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; clock-names =3D "clk"; status =3D "disabled"; @@ -3236,13 +3217,12 @@ agic_page2: interrupt-controller@9980000 { =20 agic_page3: interrupt-controller@9990000 { compatible =3D "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; reg =3D <0x9991000 0x1000>, <0x9992000 0x1000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; clock-names =3D "clk"; status =3D "disabled"; @@ -3250,13 +3230,12 @@ agic_page3: interrupt-controller@9990000 { =20 agic_page4: interrupt-controller@99a0000 { compatible =3D "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; reg =3D <0x99a1000 0x1000>, <0x99a2000 0x1000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; clock-names =3D "clk"; status =3D "disabled"; @@ -3264,13 +3243,12 @@ agic_page4: interrupt-controller@99a0000 { =20 agic_page5: interrupt-controller@99b0000 { compatible =3D "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells =3D <3>; interrupt-controller; reg =3D <0x99b1000 0x1000>, <0x99b2000 0x1000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_ADSP>; clock-names =3D "clk"; status =3D "disabled"; --=20 2.55.0