From nobody Sat Sep 26 12:28:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C4B639CCFB; Tue, 1 Sep 2026 13:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788268204; cv=none; b=esMT9rIAKp3T4iNSVPyR4cHm14wHqlggWQwbwWJmVCZv/ft4HYo2Thy+SYAch9p+ku9FZyWXhbCYKa3GdAKBbnY6UyCg6tjE57mkxXB0Tromr3dNkGC95FoILT4NmWYschUQEZ6hAD6kvtzGHAxluyhupaDx5ZWbolhSY6T4ArU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788268204; c=relaxed/simple; bh=Os9AuvzRzG0f+Y2I0XOn+G0fvp35+7MOlXwgaM4MGgM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rt8FYPzqVWrI08QoQnp4IkUOOyESba04C1+02fn726oUm1DhGQrfEAmLQAKnWSrLe0aTsiu9YVqR8RNZpinUK9rX87F8AhKe/EbCOz11IcPLd22dmsGdbHExQT8mm5dxdFz6FpvmIyED2h1+ujeWfVX3gfOUX5QFNcD8ufnrVzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=OCh+IWUJ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OCh+IWUJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788268203; x=1819804203; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Os9AuvzRzG0f+Y2I0XOn+G0fvp35+7MOlXwgaM4MGgM=; b=OCh+IWUJFceIRz1aMHb91XaxNlXZXGXwtZAmY9/LHRTiG4mdeYMXy/pl G2W4FT7b+M8D+sfgbyqnfJNX0AbZl3VKK2YG6CQ8YGs+VPgXoUACngBRx IC0RXmkZ3hYcO3XOuLLZ4R71knCA8gJqiPNpJSaRBuzuAbr5YITovzi19 LwBm3lAjx59ybSWuyj8+qXn0ocEkV+0DruATV/BzkyeQQOrnSsVh/Pc8Q uGn3Shhj8RosCWBDyFQjfHw1hj9d0nGu2n7Ojuk12JCzHo9VcseTOGGTB FoWI+fAM1RrVWsp9wyph5w9q0fvWGbmZr8Tl2pxvn4znZoSiwbsle+x2p g==; X-CSE-ConnectionGUID: HkgnOFsiS46D6BBWKJNlFg== X-CSE-MsgGUID: LAQgWUQIQfi4wgG5GGIeNw== X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="63297039" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Sep 2026 06:10:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 1 Sep 2026 06:10:01 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 1 Sep 2026 06:09:57 -0700 From: Parthiban Veerasooran To: , , , , , , CC: , , , Parthiban Veerasooran Subject: [PATCH net-next 1/3] net: phy: microchip_t1s: fix collision detection on PLCA status change Date: Tue, 1 Sep 2026 18:39:46 +0530 Message-ID: <20260901130948.212914-2-parthiban.veerasooran@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901130948.212914-1-parthiban.veerasooran@microchip.com> References: <20260901130948.212914-1-parthiban.veerasooran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The existing lan86xx_plca_set_cfg() adjusted collision detection statically at the point the user configured PLCA via ethtool: disabled when PLCA was enabled, re-enabled when PLCA was disabled. This only handled the explicit user-driven mode change and missed the dynamic transitions that the PHY performs autonomously. In a 10BASE-T1S multidrop network, the PHY tracks BEACON availability and continuously transitions between PLCA online (actively receiving BEACONs from the coordinator) and PLCA offline (no BEACON present). When PLCA goes offline after having been configured online, collision detection remained disabled, causing the bus to operate in CSMA/CD mode without collision detection =E2=80=94 a silent and hard-to-diagnose error. Fix this by monitoring the PLCA Status Changed (PSTC) interrupt. PSTC fires on every PST bit transition in the PLCA Status register. Add lan86xx_config_intr() to enable/disable the PSTCM mask bit in IMSK1 (bit 11, active-low enable) and lan86xx_handle_interrupt() to service it. On each interrupt, PLCA operational status is retrieved via genphy_c45_plca_get_status(). When PLCA comes online, collision detection is disabled via COL_DET_CTRL0 (bit 15). When PLCA goes offline, collision detection is re-enabled to restore correct CSMA/CD operation. Wire these handlers to all supported PHY variants: LAN867X Rev.B1, C1, C2 and LAN865X Rev.B0/B1. LAN867X PHYs may run with phydev->irq =3D=3D PHY_POLL on boards where the PHY interrupt is not routed to the host. The existing static CDEN write in lan86xx_plca_set_cfg() is retained as a baseline so that collision detection is correct even when the interrupt handler never runs. The limitation is that autonomous PLCA mode transitions between ethtool reconfigurations are not tracked on such boards. LAN865X is excluded from the static write because its interrupt is always routed via the MAC-PHY SPI driver and the interrupt handler always runs. Fixes: 78341049fbcd ("net: phy: microchip_t1s: configure collision detectio= n based on PLCA mode") Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 97 +++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index 73c23d311d72..afb7e52594e7 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -27,6 +27,14 @@ #define LAN865X_REG_CFGPARAM_CTRL 0x00DA #define LAN865X_REG_STS2 0x0019 =20 +/* PHY interrupt status and mask registers (MDIO_MMD_VEND2). The status bi= ts + * are read-to-clear; a mask bit is enabled by writing 0. + */ +#define LAN86XX_REG_STS1 0x0018 +#define LAN86XX_REG_IMSK1 0x001C + +#define LAN86XX_STS1_PLCA_STS_CHANGED BIT(11) + /* Collision Detector Control 0 Register */ #define LAN86XX_REG_COL_DET_CTRL0 0x0087 #define COL_DET_CTRL0_ENABLE_BIT_MASK BIT(15) @@ -458,6 +466,16 @@ static int lan86xx_plca_set_cfg(struct phy_device *phy= dev, if (ret) return ret; =20 + /* PHYs with routed interrupts handle CDEN dynamically via the interrupt + * handler, so skip the static write. PHYs running with PHY_POLL have no + * interrupt handler, so apply the static CDEN write as a baseline on + * every ethtool PLCA reconfiguration. The limitation is that autonomous + * PLCA mode transitions between ethtool reconfigurations are not + * tracked on such boards. + */ + if (phydev->irq !=3D PHY_POLL) + return 0; + if (plca_cfg->enabled) return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_COL_DET_CTRL0, @@ -506,6 +524,77 @@ static int lan86xx_read_status(struct phy_device *phyd= ev) return 0; } =20 +static int lan86xx_config_intr(struct phy_device *phydev) +{ + int ret; + + if (phydev->interrupts =3D=3D PHY_INTERRUPT_ENABLED) { + /* Read to clear any pending status before enabling. */ + ret =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_STS1); + if (ret < 0) + return ret; + + /* A mask bit of 0 enables the corresponding interrupt. */ + return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, + LAN86XX_REG_IMSK1, + LAN86XX_STS1_PLCA_STS_CHANGED); + } + + ret =3D phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_IMSK1, + LAN86XX_STS1_PLCA_STS_CHANGED); + if (ret) + return ret; + + /* Read to clear any pending status after disabling. */ + ret =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_STS1); + if (ret < 0) + return ret; + + return 0; +} + +static irqreturn_t lan86xx_handle_interrupt(struct phy_device *phydev) +{ + struct phy_plca_status plca_st; + irqreturn_t ret_irq =3D IRQ_NONE; + int sts1, ret; + + /* Reading the status register clears the latched event bits. */ + sts1 =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_STS1); + if (sts1 < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + if (sts1 & LAN86XX_STS1_PLCA_STS_CHANGED) { + ret =3D genphy_c45_plca_get_status(phydev, &plca_st); + if (ret < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + /* AN1760/AN1699: disable collision detection in PLCA mode to + * improve signal quality; re-enable it in CSMA/CD mode. + * + * https://www.microchip.com/en-us/application-notes/an1760 + * https://www.microchip.com/en-us/application-notes/an1699 + */ + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND2, + LAN86XX_REG_COL_DET_CTRL0, + COL_DET_CTRL0_ENABLE_BIT_MASK, + plca_st.pst ? COL_DET_DISABLE : + COL_DET_ENABLE); + if (ret < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + ret_irq =3D IRQ_HANDLED; + } + + return ret_irq; +} + static struct phy_driver microchip_t1s_driver[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1), @@ -513,6 +602,8 @@ static struct phy_driver microchip_t1s_driver[] =3D { .features =3D PHY_BASIC_T1S_P2MP_FEATURES, .config_init =3D lan867x_revb1_config_init, .read_status =3D lan86xx_read_status, + .config_intr =3D lan86xx_config_intr, + .handle_interrupt =3D lan86xx_handle_interrupt, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .set_plca_cfg =3D genphy_c45_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, @@ -523,6 +614,8 @@ static struct phy_driver microchip_t1s_driver[] =3D { .features =3D PHY_BASIC_T1S_P2MP_FEATURES, .config_init =3D lan867x_revc_config_init, .read_status =3D lan86xx_read_status, + .config_intr =3D lan86xx_config_intr, + .handle_interrupt =3D lan86xx_handle_interrupt, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, @@ -533,6 +626,8 @@ static struct phy_driver microchip_t1s_driver[] =3D { .features =3D PHY_BASIC_T1S_P2MP_FEATURES, .config_init =3D lan867x_revc_config_init, .read_status =3D lan86xx_read_status, + .config_intr =3D lan86xx_config_intr, + .handle_interrupt =3D lan86xx_handle_interrupt, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, @@ -556,6 +651,8 @@ static struct phy_driver microchip_t1s_driver[] =3D { .features =3D PHY_BASIC_T1S_P2MP_FEATURES, .config_init =3D lan865x_revb_config_init, .read_status =3D lan86xx_read_status, + .config_intr =3D lan86xx_config_intr, + .handle_interrupt =3D lan86xx_handle_interrupt, .read_mmd =3D genphy_read_mmd_c45, .write_mmd =3D genphy_write_mmd_c45, .get_plca_cfg =3D genphy_c45_plca_get_cfg, --=20 2.43.0 From nobody Sat Sep 26 12:28:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEE403F9270; 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charset="utf-8" The integrated PHY has no dedicated interrupt line; its interrupt is delivered in-band as the PHYINT bit in STATUS0, which raises the MAC-PHY SPI interrupt via the extended status. phy_mac_interrupt() only triggers a link-status re-read and cannot make the PHY driver read and acknowledge its interrupt source registers, so expose the PHY interrupt to phylib as a nested virtual IRQ instead. Use dummy_irq_chip as the irqchip, map a virtual IRQ and assign it to phydev->irq before phy_connect_direct() so phylib enters interrupt mode and uses the PHY driver's config_intr/handle_interrupt. Unmask PHYINT in INT_MASK0, and when it is seen in the extended status, dispatch handle_nested_irq() synchronously from the sleepable threaded IRQ. PHYINT is level triggered, so acking the PHY source there clears it before the next data chunk, avoiding a storm. Signed-off-by: Parthiban Veerasooran --- drivers/net/ethernet/oa_tc6.c | 69 +++++++++++++++++++++++++++++++++-- include/linux/oa_tc6.h | 2 + 2 files changed, 68 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index 417c15d1ff42..6c93a61d8d2d 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -70,6 +72,8 @@ struct oa_tc6 { struct phy_device *phydev; struct mii_bus *mdiobus; struct spi_device *spi; + struct irq_domain *phy_irq_domain; + int phy_virq; struct mutex spi_ctrl_lock; /* Protects spi control transfer */ spinlock_t tx_skb_lock; /* Protects tx skb handling */ void *spi_ctrl_tx_buf; @@ -575,6 +579,44 @@ static void oa_tc6_mdiobus_unregister(struct oa_tc6 *t= c6) mdiobus_free(tc6->mdiobus); } =20 +static int oa_tc6_phy_irq_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_data(irq, domain->host_data); + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_nested_thread(irq, true); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops oa_tc6_phy_irq_domain_ops =3D { + .map =3D oa_tc6_phy_irq_map, +}; + +static int oa_tc6_phy_irq_setup(struct oa_tc6 *tc6) +{ + tc6->phy_irq_domain =3D + irq_domain_create_linear(NULL, 1, + &oa_tc6_phy_irq_domain_ops, tc6); + if (!tc6->phy_irq_domain) + return -ENOMEM; + + tc6->phy_virq =3D irq_create_mapping(tc6->phy_irq_domain, 0); + if (!tc6->phy_virq) { + irq_domain_remove(tc6->phy_irq_domain); + return -ENOMEM; + } + + return 0; +} + +static void oa_tc6_phy_irq_teardown(struct oa_tc6 *tc6) +{ + irq_dispose_mapping(tc6->phy_virq); + irq_domain_remove(tc6->phy_irq_domain); +} + static int oa_tc6_phy_init(struct oa_tc6 *tc6) { int ret; @@ -600,6 +642,16 @@ static int oa_tc6_phy_init(struct oa_tc6 *tc6) return -ENODEV; } =20 + ret =3D oa_tc6_phy_irq_setup(tc6); + if (ret) { + oa_tc6_mdiobus_unregister(tc6); + return ret; + } + + /* Deliver the PHY interrupt through the nested virtual IRQ. Set before + * phy_connect_direct() so phylib enters interrupt mode. + */ + tc6->phydev->irq =3D tc6->phy_virq; tc6->phydev->is_internal =3D true; ret =3D phy_connect_direct(tc6->netdev, tc6->phydev, &oa_tc6_handle_link_change, @@ -607,6 +659,7 @@ static int oa_tc6_phy_init(struct oa_tc6 *tc6) if (ret) { netdev_err(tc6->netdev, "Can't attach PHY to %s\n", tc6->mdiobus->id); + oa_tc6_phy_irq_teardown(tc6); oa_tc6_mdiobus_unregister(tc6); return ret; } @@ -622,6 +675,7 @@ static void oa_tc6_phy_exit(struct oa_tc6 *tc6) return; =20 phy_disconnect(tc6->phydev); + oa_tc6_phy_irq_teardown(tc6); oa_tc6_mdiobus_unregister(tc6); } =20 @@ -661,7 +715,7 @@ static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); } =20 -static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) +static int oa_tc6_unmask_interrupts(struct oa_tc6 *tc6) { u32 regval; int ret; @@ -670,7 +724,8 @@ static int oa_tc6_unmask_macphy_error_interrupts(struct= oa_tc6 *tc6) if (ret) return ret; =20 - regval &=3D ~(OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK | + regval &=3D ~(OA_TC6_INT_MASK0_PHY_INT_MASK | + OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK | OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK | OA_TC6_INT_MASK0_HEADER_ERR_MASK); @@ -763,6 +818,14 @@ static int oa_tc6_process_extended_status(struct oa_tc= 6 *tc6) return ret; } =20 + /* Dispatch the PHY interrupt to phylib via the nested virtual IRQ so + * the PHY driver reads and acknowledges its status. PHYINT is level + * triggered, so doing this synchronously here (in the sleepable + * threaded IRQ) clears the source before the next data chunk. + */ + if (FIELD_GET(OA_TC6_STATUS0_PHY_INT, value)) + handle_nested_irq(tc6->phy_virq); + if (FIELD_GET(OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { tc6->rx_buf_overflow =3D true; oa_tc6_cleanup_ongoing_rx_skb(tc6); @@ -1400,7 +1463,7 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, st= ruct net_device *netdev, return NULL; } =20 - ret =3D oa_tc6_unmask_macphy_error_interrupts(tc6); + ret =3D oa_tc6_unmask_interrupts(tc6); if (ret) { dev_err(&tc6->spi->dev, "MAC-PHY error interrupts unmask failed: %d\n", ret); diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 27f652d4920b..c470ddddc77f 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -30,6 +30,7 @@ =20 /* Status Register #0 */ #define OA_TC6_REG_STATUS0 0x0008 +#define OA_TC6_STATUS0_PHY_INT BIT(7) #define OA_TC6_STATUS0_RESETC BIT(6) /* Reset Complete */ #define OA_TC6_STATUS0_HEADER_ERROR BIT(5) #define OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR BIT(4) @@ -43,6 +44,7 @@ =20 /* Interrupt Mask Register #0 */ #define OA_TC6_REG_INT_MASK0 0x000C +#define OA_TC6_INT_MASK0_PHY_INT_MASK BIT(7) #define OA_TC6_INT_MASK0_HEADER_ERR_MASK BIT(5) #define OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) #define OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) --=20 2.43.0 From nobody Sat Sep 26 12:28:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 460F8472541; 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charset="utf-8" LAN867X Rev.D0 introduces a Collision Counting and MAC Forwarding Control field (CCMFC, bits 10:9) in the Collision Detector Control 0 register (CDCTL0, 0x0087). When configured to the OA default value (0x1), the hardware automatically gates collision forwarding to the MAC based on the live PLCA_Status: collisions are neither counted nor forwarded when PLCA_Status is OK, and are counted and forwarded when PLCA_Status is not OK. This eliminates the inherent delay between a PLCA status change and the software interrupt handler toggling CDEN, which was a limitation on older revisions that had no hardware alternative. Since CCMFC handles collision gating autonomously, the PSTC interrupt handler for Rev.D0 only needs to update the link status selection on each PLCA status transition. Configure CCMFC to the OA default in lan867x_revd0_config_init(). Add lan867x_revd0_handle_interrupt() to handle two separate events: 1. Link Status Change (LNKSTSC): Triggers the phylib state machine via phy_trigger_machine() to re-evaluate link status and perform necessary state transitions. 2. PLCA Status Change (PSTC): Reads the current PLCA operational status via genphy_c45_plca_get_status() and calls lan867x_revd0_link_active_selection() to update the link status selection accordingly. Unmask both link status change and PLCA status change interrupt masks for Rev.D0 in lan86xx_config_intr(). Wire up .config_intr and .handle_interrupt for Rev.D0 using the shared lan86xx_config_intr() and the new handler. Fixes: e7e756779afa ("net: phy: microchip_t1s: add support for Microchip LA= N867X Rev.D0 PHY") Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 68 +++++++++++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index afb7e52594e7..c3a738c7425b 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -33,6 +33,7 @@ #define LAN86XX_REG_STS1 0x0018 #define LAN86XX_REG_IMSK1 0x001C =20 +#define LAN86XX_STS1_LINK_STS_CHANGED BIT(13) #define LAN86XX_STS1_PLCA_STS_CHANGED BIT(11) =20 /* Collision Detector Control 0 Register */ @@ -40,6 +41,9 @@ #define COL_DET_CTRL0_ENABLE_BIT_MASK BIT(15) #define COL_DET_ENABLE BIT(15) #define COL_DET_DISABLE 0x0000 +#define COL_DET_CTRL0_CCMFC_MASK GENMASK(10, 9) +/* OA default: collisions gated by PLCA_Status in hardware */ +#define COL_DET_CTRL0_CCMFC_OA_DEFAULT BIT(9) =20 /* LAN8670/1/2 Rev.D0 Link Status Selection Register */ #define LAN867X_REG_LINK_STATUS_CTRL 0x0012 @@ -502,6 +506,18 @@ static int lan867x_revd0_config_init(struct phy_device= *phydev) return ret; } =20 + /* AN1760: configure CCMFC to OA default so that the hardware + * automatically gates collision forwarding to the MAC based on + * PLCA_Status. Collisions are neither counted nor forwarded when + * PLCA_Status =3D OK, eliminating the need for software-driven CDEN + * toggling in the interrupt handler. CDEN remains enabled. + */ + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_COL_DET_CTRL0, + COL_DET_CTRL0_CCMFC_MASK, + COL_DET_CTRL0_CCMFC_OA_DEFAULT); + if (ret) + return ret; + /* Initially the PHY will be in CSMA/CD mode by default. So it is * required to set the link always active as it doesn't support * autoneg. @@ -526,8 +542,12 @@ static int lan86xx_read_status(struct phy_device *phyd= ev) =20 static int lan86xx_config_intr(struct phy_device *phydev) { + u16 mask =3D LAN86XX_STS1_PLCA_STS_CHANGED; int ret; =20 + if (phydev->phy_id =3D=3D PHY_ID_LAN867X_REVD0) + mask |=3D LAN86XX_STS1_LINK_STS_CHANGED; + if (phydev->interrupts =3D=3D PHY_INTERRUPT_ENABLED) { /* Read to clear any pending status before enabling. */ ret =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_STS1); @@ -536,12 +556,11 @@ static int lan86xx_config_intr(struct phy_device *phy= dev) =20 /* A mask bit of 0 enables the corresponding interrupt. */ return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, - LAN86XX_REG_IMSK1, - LAN86XX_STS1_PLCA_STS_CHANGED); + LAN86XX_REG_IMSK1, mask); } =20 ret =3D phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_IMSK1, - LAN86XX_STS1_PLCA_STS_CHANGED); + mask); if (ret) return ret; =20 @@ -595,6 +614,47 @@ static irqreturn_t lan86xx_handle_interrupt(struct phy= _device *phydev) return ret_irq; } =20 +static irqreturn_t lan867x_revd0_handle_interrupt(struct phy_device *phyde= v) +{ + struct phy_plca_status plca_st; + irqreturn_t ret_irq =3D IRQ_NONE; + int sts1, ret; + + /* Reading the status register clears the latched event bits. */ + sts1 =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_STS1); + if (sts1 < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + if (sts1 & LAN86XX_STS1_LINK_STS_CHANGED) { + phy_trigger_machine(phydev); + ret_irq =3D IRQ_HANDLED; + } + + if (sts1 & LAN86XX_STS1_PLCA_STS_CHANGED) { + ret =3D genphy_c45_plca_get_status(phydev, &plca_st); + if (ret < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + /* Collision detection is handled autonomously by the hardware + * via CCMFC. Only the link status selection needs to be updated + * on each PLCA status transition. + */ + ret =3D lan867x_revd0_link_active_selection(phydev, plca_st.pst); + if (ret < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + ret_irq =3D IRQ_HANDLED; + } + + return ret_irq; +} + static struct phy_driver microchip_t1s_driver[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1), @@ -637,6 +697,8 @@ static struct phy_driver microchip_t1s_driver[] =3D { .name =3D "LAN867X Rev.D0", .features =3D PHY_BASIC_T1S_P2MP_FEATURES, .config_init =3D lan867x_revd0_config_init, + .config_intr =3D lan86xx_config_intr, + .handle_interrupt =3D lan867x_revd0_handle_interrupt, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, --=20 2.43.0