From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DD9D37E5FA for ; Tue, 1 Sep 2026 08:30:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251420; cv=none; b=Dm9mJVHSZhfyQ/oYXNOdLye+SMSKTUa12AYaY6amROA4DXenyKVri8VQbj9dJNK7ngOJ05lNVustFgPsaFSo44lOqijmcgzSnvnT/JnvusjKkfYNBYJVDLJ3Rc8IHO/9Kolixx0qlMTvdq6PaHZmoDNDQZxCyeKamPplRQNfXD0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251420; c=relaxed/simple; bh=WmcKxR366QifZfmN82COzbRyA6rgiThjX8rzkh1EBYU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z8Mh2PqZZmXOQ6hmUhiAMvPklFi21rbsbq2n9daD3RqVbLOw5w6PzCY5GzwWAaShFub8TSzBxF2FobPtwMJ5sBHxEVHFfY5YSbJGjMTlE1P1p3boYVFLZXNjqbV74iw6e+8IFeZa1V2boz2MAsqxOwH8Y2Y6MfQfNJaq4iNLw88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QLkwE+bl; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QLkwE+bl" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-49b8be0409fso4539495e9.2 for ; Tue, 01 Sep 2026 01:30:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251417; x=1788856217; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=YyxU6GfAU2OYJBof45H0mHXE5/R7CERzacXu0RY4THE=; b=QLkwE+blrc11Q26Sa8ryOvlCucEUZjmO9QMXIB3DdagXIMTO6IZoRX8m8GWRN3WhGZ 0LCJlDzbysO1k4EPjqq5aE+nleDjkTA4XTFQmEBa3Aj9uTCAP9RFRPpyu/o/gNGJ4s3s 6to2xVM5A/Pyo43WDJJgsClVak+Ynb+oqgOG4rDAW+BMytzsZJzDLmFKI8oHnyyNku2N we9wrCRJ8GOODqShw16BtLE8jKazjz6HMJSl4zYSdLWu3XY8O8BdgHvochbTDPWUkRGA nivBX5vDi4xCC62J0r5f78N9EVpJsqZ0OosqJ6IFC/08D845YRIRJ38sUo5lX+LpNICa jfHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251417; x=1788856217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=YyxU6GfAU2OYJBof45H0mHXE5/R7CERzacXu0RY4THE=; b=lJ1DkAdmhLLLkiULs57odJIgys8qx5TH9mSTLOWRKC39eRwNOnKuabqDKxde7TBNbN zLP59mtJweG16ehJqgmNYDO0hZvm9HwAYi2cXlzSNtse3Th198Tkys2F+84sVNxdM1EN YMThQFoqabd9A4r2uk7rGWiya7O5mhxreOattAM/r9FnCRUm+jqf0FWR3fZeNdSm/nyn vLaf4MaNlAsFKSJf8DPfyoxH5PCNAPWk+yur7OpVUuHFSFiB+AgYvpGmO4erqLc953fj rXTktKOIbKiYwSyfA5KUxYWwCHsaVsZVonghJX76tuPoFmTy0gdGKQ9nNDFTCM49psUc wGzg== X-Forwarded-Encrypted: i=1; AHgh+Rog3mEEeukiiVL91dKTw+MMvaj1WF7JOW7e0cB901F9RHTD4dFyl7jVPme3xqjWMAQ2ZYv418ukbO0Tns8=@vger.kernel.org X-Gm-Message-State: AFuF++kdNM70Oy3QP7g55UVAVC/5cU5iB8H8qyi2pvYiWOF61FK3u75n GYIWhkW+ddSA/15xYQT6QJO+TNQXmhg3C5CfEjxgVfAGGxrBS8tmxObZ X-Gm-Gg: AR+sD12U3yjAqV3JmZnZLFtAB3LeFOEnWeetkgchnH5juNK2gTjHbLSfnQkAc6j077K TUpbySjFaj+A7hSkDDN0aO4ob7SAppYFVZq1e3oZ2T1GT70Z8Cpe7PXUCyQyZvdTHcb5WpZdomY O4QG3dTnWi0zUldo8As7ZEkDdbvA3nVV8n1Ct0v6mhSKWPTyqiRBuGJ64T00GPoCvzMjS5AF8zf KwVATfXWtfniKp/ufIBaQmKLiV0o0Nab99zlGtIhFMOn28V3E66RJQ9UbrxBOeEzFLTbg+VzzrD LgYgQ2Vf0skrg4OfYyRATFcIu6s0suYHCCrhje+Dyn7fdVGqUA4LjcFhRbaMOf2BasmdWABN4AB xUbFFjGSwGinAQU3VABq9kfPqDwYhTiM8NOvWkSGks+8O6ICEdV2qCWspDHtdJXjxpBVIwAy7JQ d58lfUFfmUTg4GxdSQNrfTN7A9Yhg9wFIb/XDRSQ+iCmVEG4j8tZ7F12m7yny3mP/RT9uegXEAB 35YMTC1GxvHo1mLXdFjqF0RwkOU5tf4VvOCRgWmZ2FJ4xXNUmtR X-Received: by 2002:a05:600c:4592:b0:495:5890:8f6c with SMTP id 5b1f17b1804b1-49b91c290c1mr378787125e9.7.1788251416552; Tue, 01 Sep 2026 01:30:16 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:16 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 01/12] net: phylink: keep and use MAC supported_interfaces in phylink struct Date: Tue, 1 Sep 2026 10:29:16 +0200 Message-ID: <20260901083001.8044-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add in phylink struct a copy of supported_interfaces from phylink_config and make use of that instead of relying on phylink_config value. This in preparation for support of PCS handling internally to phylink where a PCS can be removed or added after the phylink is created and we need both a reference of the supported_interfaces value from phylink_config and an internal value that can be updated with the new PCS info. Tested-by: Maxime Chevallier Reviewed-by: Maxime Chevallier Signed-off-by: Christian Marangi --- drivers/net/phy/phylink.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 3ec3bb439109..7f7a7328124f 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -60,6 +60,11 @@ struct phylink { /* The link configuration settings */ struct phylink_link_state link_config; =20 + /* What interface are supported by the current link. + * Can change on removal or addition of new PCS. + */ + DECLARE_PHY_INTERFACE_MASK(supported_interfaces); + /* The current settings */ phy_interface_t cur_interface; =20 @@ -628,7 +633,7 @@ static int phylink_validate_mask(struct phylink *pl, st= ruct phy_device *phy, static int phylink_validate(struct phylink *pl, unsigned long *supported, struct phylink_link_state *state) { - const unsigned long *interfaces =3D pl->config->supported_interfaces; + const unsigned long *interfaces =3D pl->supported_interfaces; =20 if (state->interface =3D=3D PHY_INTERFACE_MODE_NA) return phylink_validate_mask(pl, NULL, supported, state, @@ -1904,6 +1909,9 @@ struct phylink *phylink_create(struct phylink_config = *config, __set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); timer_setup(&pl->link_poll, phylink_fixed_poll, 0); =20 + phy_interface_copy(pl->supported_interfaces, + pl->config->supported_interfaces); + linkmode_fill(pl->supported); linkmode_copy(pl->link_config.advertising, pl->supported); phylink_validate(pl, pl->supported, &pl->link_config); @@ -2025,7 +2033,7 @@ static int phylink_validate_phy(struct phylink *pl, s= truct phy_device *phy, * those which the host supports. */ phy_interface_and(interfaces, phy->possible_interfaces, - pl->config->supported_interfaces); + pl->supported_interfaces); =20 if (phy_interface_empty(interfaces)) { phylink_err(pl, "PHY has no common interfaces\n"); @@ -2825,12 +2833,12 @@ static phy_interface_t phylink_sfp_select_interface= (struct phylink *pl, return interface; } =20 - if (!test_bit(interface, pl->config->supported_interfaces)) { + if (!test_bit(interface, pl->supported_interfaces)) { phylink_err(pl, "selection of interface failed, SFP selected %s (%u) but MAC suppor= ts %*pbl\n", phy_modes(interface), interface, (int)PHY_INTERFACE_MODE_MAX, - pl->config->supported_interfaces); + pl->supported_interfaces); return PHY_INTERFACE_MODE_NA; } =20 @@ -3758,14 +3766,14 @@ static int phylink_sfp_config_optical(struct phylin= k *pl) =20 phylink_dbg(pl, "optical SFP: interfaces=3D[mac=3D%*pbl, sfp=3D%*pbl]\n", (int)PHY_INTERFACE_MODE_MAX, - pl->config->supported_interfaces, + pl->supported_interfaces, (int)PHY_INTERFACE_MODE_MAX, pl->sfp_interfaces); =20 /* Find the union of the supported interfaces by the PCS/MAC and * the SFP module. */ - phy_interface_and(pl->sfp_interfaces, pl->config->supported_interfaces, + phy_interface_and(pl->sfp_interfaces, pl->supported_interfaces, pl->sfp_interfaces); if (phy_interface_empty(pl->sfp_interfaces)) { phylink_err(pl, "unsupported SFP module: no common interface modes\n"); @@ -3936,7 +3944,7 @@ static int phylink_sfp_connect_phy(void *upstream, st= ruct phy_device *phy) =20 /* Set the PHY's host supported interfaces */ phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces, - pl->config->supported_interfaces); + pl->supported_interfaces); =20 /* Do the initial configuration */ return phylink_sfp_config_phy(pl, phy); --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D80C472070 for ; Tue, 1 Sep 2026 08:30:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251424; cv=none; b=H5wRxySij6BJFu52YpQB0Q0MxeuON+cWC/eZJDWQAsavPChCfHM+FYwco9lwjuVYTIoZW/EdPfRueBKJ+dU1zKdjE2MEDzaBC92OiZS3GbT8E4mDoXd2QNlw7UeuvuhfrGYLjbj3vQIA+CGqtJ8GgWXjK7bQ/thZUcbHTVaVhKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251424; c=relaxed/simple; bh=/CaW9400iWF+vydRQLS5TtJ9sUkwbJ3aAwJwhD/vFA0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UN1jnwv/dSQwyvGKLFJTcdIFCSge6HoUvPil0aiQbTYu+HVakuDICtajivQhvttRkT9/MmRoTcd0P/EQS+L4yq5dnVTUHPyWxsJQxb1wMR1WrY/mKioEbhC5zCyzXf6jWuQcbVj4tF9TVgaCXrl7MtLrcbPn4qN56fT5pKJGEuI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=qL4707t1; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qL4707t1" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4953e04ef16so6002315e9.2 for ; Tue, 01 Sep 2026 01:30:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251420; x=1788856220; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=maMRW+Ek7ZgmZNwmAfrlWeahbEBicqs8Vx7VlZAPfiE=; b=qL4707t1YpkIYcAigsCBY2wZUhwScbNEoS4YxKIfJ7NyRf4WORNm9HDIR1kxjx5hip zpNVB1hpRXQST/PAAW1Dlqwr0Flmxp8wWFH65xX3zy7Xmk69yJHMPbeyZXS29emHSaDW mCCEVtmSaqgF2cFDWxLwiIYn0afK9GD6yCIGH6IIcWwTrnucjdqbSWCu6r5/gS3vHOdD 1c+aCP85N6ClJxh//C6PvYfQpZzO3g4Te2YHlVqoM3p0IvGoSCspDrVhlrOOSX8CVAXr pXUXZBE98MExsmzURhJaheMIbcaCbjYhldLpOksSB3a2Sxx7jWlCWQPdpawWtKWuJ2HL Hryg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251420; x=1788856220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=maMRW+Ek7ZgmZNwmAfrlWeahbEBicqs8Vx7VlZAPfiE=; b=D++jiehKZOY6G1QWpmxCNphzPaWIS2zVhemqG345Y4UpQiJDMJzlaMFKbiGrhb/D9m l61O3ElnFroZ9kKCIJHfy4piOgwbvfoQzld+M6cgcHWwe5zgPL0WvgjP0NxyxKNfZSnx 4IcKDY1mnHxcoXCLxlgs16mFsrj+nHr66njHpL9Z4uEUKENCjpGLVch81k4ChGXtauAQ HHDhLgl3jNxwEmpk8HCdy5kGdsi3TFWcarlxX693dqCP6yTFZbd4nyhdCeXoU05sr4Z3 ewkAVUTB2sy3TLv6NBMgVPyom1JKEc3CLkc89GuS6n2Vi8T1xsp8CfqLHvbKgaQbEWD3 gxZQ== X-Forwarded-Encrypted: i=1; AHgh+Roix3t5DEunJqakgKMuzfvRjNjTsLDeB4jbvE12/b1p8VuBxa+fP0Lx7Ix5Axzrj6x860YVGBH4bwCB0aU=@vger.kernel.org X-Gm-Message-State: AFuF++meHW7QmM0DzvkZFUSFaq/O0cNVvkr0jsj8lt1JdLsbK0n9VmSk 1ejUVuI73Hzo0mgjymk2y1T+v+YQP852SIXvzKmT41xcOi1x+LxQ6Ni4 X-Gm-Gg: AR+sD13mXMO9GOystJKxSZk8ueHrro6bfLqsFT+++0USmkq40yjoIVKTGWeDoiiUzbf BOhGnW5PAELbCLKKvxzsfp1PP+tZ+HyjEoxnyYuw2oWl+X4f6HEns8z8A9zUPn3n+aIFf1IKbxj NGU4TbSBDj59WUt/Q5Re6jQw5WgDlQ2YNCZwDYxtkiJEimEDeFM+fHfLLNdtj/XQs81YDEnLZ5/ Oktj1lnwNJs2bjHvTwSEvQrFfFta7V/zzhgiHAqqwwDy0laTz83yJVWRdsK05HRLo+LPNZfUiMq mZ3lOoRUbkm0fLhZvsyE8EFup2T0O/9rDi9bHWKohkh3PLmvgBIGJiw2Rlkz0+WAQZi+7WYzx+q C0euwYCRZi4KOhtSg9qkJuOLoNKv5VOZtwXCAv4DgzO6Y7QZ6xEz6sbOwtlpxNrt2hYUbWYSFKu FMQCEg9LiGR4ap9OQsquIzBEgiemh0S41F2Xr7P9+JWo+kiukCURFBHUOnI5LgwSq356uY/NXEr q8gyrN7KJ48gG0DXzszzfCrS/5YPrSxveWyQ8143Qazhavndhc8nQ== X-Received: by 2002:a05:600c:1f8f:b0:495:48d7:f178 with SMTP id 5b1f17b1804b1-49b91c44ec6mr452249575e9.11.1788251418833; Tue, 01 Sep 2026 01:30:18 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:18 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 02/12] net: phylink: introduce internal phylink PCS handling Date: Tue, 1 Sep 2026 10:29:17 +0200 Message-ID: <20260901083001.8044-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce internal handling of PCS for phylink. This is an alternative way to .mac_select_pcs that moves the selection logic of the PCS entirely to phylink with the usage of the supported_interface value in the PCS struct. MAC should now provide a callback to fill the available PCS in phylink_config in .fill_available_pcs and fill the .num_possible_pcs with the number of elements in the array. MAC should also define a new bitmap, pcs_interfaces, in phylink_config to define for what interface mode a dedicated PCS is required. On phylink_create(), an array of PCS pointer is allocated of size .num_possible_pcs from phylink_config and .fill_available_pcs from phylink_config is called passing as args the just allocated array and the number of possible element in it. MAC will fill this passed array with all the available PCS. This array is then parsed and a linked list of PCS is created based on the allocated PCS array filled by MAC via .fill_available_pcs(). Every PCS in phylink PCS list gets then linked to the phylink instance by setting the phylink value in phylink_pcs struct to the phylink instance. Also the supported_interface value in phylink struct is updated with the new supported_interface from the provided PCS. On phylink_destroy(), every PCS in phylink PCS list is unlinked from the phylink instance by setting the phylink value in phylink_pcs struct to NULL and removed from the PCS list. phylink_validate_mac_and_pcs(), phylink_major_config() and phylink_inband_caps() are updated to support this new implementation with the PCS list stored in phylink. They will make use of phylink_validate_pcs_interface() that will loop for every PCS in the phylink PCS available list and find one that supports the passed interface. phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs where if a supported_interface value is not set for the PCS struct, then it's assumed every interface is supported. A MAC is required to implement either a .mac_select_pcs or make use of the PCS list implementation. Implementing both will result in a fail on phylink_create(). A MAC defining .num_possible_pcs in phylink_config MUST also define a .fill_available_pcs or phylink_create() will fail with an negative error. phylink value in phylink_pcs struct with this implementation is used to track from PCS side when it's attached to a phylink instance. PCS driver will make use of this information to correctly detach from a phylink instance if needed. phylink_pcs_change() is also changed to verify that the PCS that triggered a link change is the one that is currently used by the phylink instance. The .mac_select_pcs implementation is not changed but it's expected that every MAC driver migrates to the new implementation to later deprecate and remove .mac_select_pcs. Signed-off-by: Christian Marangi --- drivers/net/phy/phylink.c | 195 ++++++++++++++++++++++++++++++++++---- include/linux/phylink.h | 16 ++++ 2 files changed, 191 insertions(+), 20 deletions(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 7f7a7328124f..d7391a60f01f 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -60,6 +60,9 @@ struct phylink { /* The link configuration settings */ struct phylink_link_state link_config; =20 + /* List of available PCS */ + struct list_head pcs_list; + /* What interface are supported by the current link. * Can change on removal or addition of new PCS. */ @@ -517,6 +520,22 @@ static void phylink_validate_mask_caps(unsigned long *= supported, linkmode_and(state->advertising, state->advertising, mask); } =20 +static int phylink_validate_pcs_interface(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + /* If PCS define an empty supported_interfaces value, assume + * all interface are supported. + */ + if (phy_interface_empty(pcs->supported_interfaces)) + return 0; + + /* Ensure that this PCS supports the interface mode */ + if (!test_bit(interface, pcs->supported_interfaces)) + return -EINVAL; + + return 0; +} + static int phylink_validate_mac_and_pcs(struct phylink *pl, unsigned long *supported, struct phylink_link_state *state) @@ -530,6 +549,21 @@ static int phylink_validate_mac_and_pcs(struct phylink= *pl, pcs =3D pl->mac_ops->mac_select_pcs(pl->config, state->interface); if (IS_ERR(pcs)) return PTR_ERR(pcs); + /* + * Find a PCS in available PCS list for the requested interface. + * + * Skip searching if the MAC doesn't require a dedicated PCS for + * the requested interface. + */ + } else if (test_bit(state->interface, pl->config->pcs_interfaces)) { + struct phylink_pcs *tmp; + + list_for_each_entry(tmp, &pl->pcs_list, list) { + if (!phylink_validate_pcs_interface(tmp, state->interface)) { + pcs =3D tmp; + break; + } + } } =20 if (pcs) { @@ -544,13 +578,10 @@ static int phylink_validate_mac_and_pcs(struct phylin= k *pl, return -EINVAL; } =20 - /* Ensure that this PCS supports the interface which the MAC - * returned it for. It is an error for the MAC to return a PCS - * that does not support the interface mode. - */ - if (!phy_interface_empty(pcs->supported_interfaces) && - !test_bit(state->interface, pcs->supported_interfaces)) { - phylink_err(pl, "MAC returned PCS which does not support %s\n", + /* Recheck PCS to handle legacy way for .mac_select_pcs */ + ret =3D phylink_validate_pcs_interface(pcs, state->interface); + if (ret) { + phylink_err(pl, "selected PCS does not support %s\n", phy_modes(state->interface)); return -EINVAL; } @@ -963,12 +994,22 @@ static void phylink_pcs_enable_eee(struct phylink_pcs= *pcs) static unsigned int phylink_inband_caps(struct phylink *pl, phy_interface_t interface) { - struct phylink_pcs *pcs; + struct phylink_pcs *pcs =3D NULL; =20 - if (!pl->mac_ops->mac_select_pcs) - return 0; + if (pl->mac_ops->mac_select_pcs) { + pcs =3D pl->mac_ops->mac_select_pcs(pl->config, + interface); + } else if (test_bit(interface, pl->config->pcs_interfaces)) { + struct phylink_pcs *tmp; + + list_for_each_entry(tmp, &pl->pcs_list, list) { + if (!phylink_validate_pcs_interface(tmp, interface)) { + pcs =3D tmp; + break; + } + } + } =20 - pcs =3D pl->mac_ops->mac_select_pcs(pl->config, interface); if (IS_ERR_OR_NULL(pcs)) return 0; =20 @@ -1265,10 +1306,36 @@ static void phylink_major_config(struct phylink *pl= , bool restart, pl->major_config_failed =3D true; return; } + /* Find a PCS in available PCS list for the requested interface. + * This doesn't overwrite the previous .mac_select_pcs as either + * .mac_select_pcs or PCS list implementation are permitted. + * + * Skip searching if the MAC doesn't require a dedicated PCS for + * the requested interface. + */ + } else if (test_bit(state->interface, pl->config->pcs_interfaces)) { + struct phylink_pcs *tmp; + + list_for_each_entry(tmp, &pl->pcs_list, list) { + if (!phylink_validate_pcs_interface(tmp, + state->interface)) { + pcs =3D tmp; + break; + } + } =20 - pcs_changed =3D pl->pcs !=3D pcs; + if (!pcs) { + phylink_err(pl, + "couldn't find a PCS for %s\n", + phy_modes(state->interface)); + + pl->major_config_failed =3D true; + return; + } } =20 + pcs_changed =3D pl->pcs !=3D pcs; + phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising); =20 phylink_dbg(pl, "major config, active %s/%s/%s\n", @@ -1295,13 +1362,15 @@ static void phylink_major_config(struct phylink *pl= , bool restart, if (pcs_changed) { phylink_pcs_disable(pl->pcs); =20 - if (pl->pcs) - pl->pcs->phylink =3D NULL; + if (pl->mac_ops->mac_select_pcs) { + if (pl->pcs) + pl->pcs->phylink =3D NULL; =20 - if (pcs) - pcs->phylink =3D pl; + if (pcs) + pcs->phylink =3D pl; + } =20 - pl->pcs =3D pcs; + WRITE_ONCE(pl->pcs, pcs); } =20 if (pl->pcs) @@ -1834,6 +1903,44 @@ int phylink_set_fixed_link(struct phylink *pl, } EXPORT_SYMBOL_GPL(phylink_set_fixed_link); =20 +static int phylink_fill_available_pcs(struct phylink *pl, + struct phylink_config *config) +{ + struct phylink_pcs **pcss; + int i, ret; + + if (!config->num_possible_pcs) + return 0; + + if (!config->fill_available_pcs) { + dev_err(config->dev, + "phylink: error: num_possible_pcs defined but no fill_available_pcs\n"); + return -EINVAL; + } + + pcss =3D kzalloc_objs(*pcss, config->num_possible_pcs); + if (!pcss) + return -ENOMEM; + + ret =3D config->fill_available_pcs(config, pcss, config->num_possible_pcs= ); + if (ret < 0) + goto out; + + for (i =3D 0; i < config->num_possible_pcs; i++) { + struct phylink_pcs *pcs =3D pcss[i]; + + if (!pcs) + continue; + + list_add_tail(&pcs->list, &pl->pcs_list); + } + +out: + kfree(pcss); + + return ret; +} + /** * phylink_create() - create a phylink instance * @config: a pointer to the target &struct phylink_config @@ -1855,9 +1962,20 @@ struct phylink *phylink_create(struct phylink_config= *config, phy_interface_t iface, const struct phylink_mac_ops *mac_ops) { + struct phylink_pcs *tmp, *pcs; struct phylink *pl; int ret; =20 + /* + * Make sure either PCS internal validation or .mac_select_pcs + * is used. Return error if both are defined. + */ + if (config->num_possible_pcs && mac_ops->mac_select_pcs) { + dev_err(config->dev, + "phylink: error: either phylink_config .num_possible_pcs or .mac_select= _pcs must be used\n"); + return ERR_PTR(-EINVAL); + } + /* Validate the supplied configuration */ if (phy_interface_empty(config->supported_interfaces)) { dev_err(config->dev, @@ -1872,6 +1990,7 @@ struct phylink *phylink_create(struct phylink_config = *config, mutex_init(&pl->phydev_mutex); mutex_init(&pl->state_mutex); INIT_WORK(&pl->resolve, phylink_resolve); + INIT_LIST_HEAD(&pl->pcs_list); =20 pl->config =3D config; if (config->type =3D=3D PHYLINK_NETDEV) { @@ -1909,16 +2028,31 @@ struct phylink *phylink_create(struct phylink_confi= g *config, __set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); timer_setup(&pl->link_poll, phylink_fixed_poll, 0); =20 + /* Fill the PCS list with available PCS from phylink config */ + ret =3D phylink_fill_available_pcs(pl, config); + if (ret < 0) + goto free_pl; + + /* Link available PCS to phylink */ + list_for_each_entry(pcs, &pl->pcs_list, list) + pcs->phylink =3D pl; + phy_interface_copy(pl->supported_interfaces, pl->config->supported_interfaces); =20 + /* Update supported interfaces */ + list_for_each_entry(pcs, &pl->pcs_list, list) + phy_interface_or(pl->supported_interfaces, + pl->supported_interfaces, + pcs->supported_interfaces); + linkmode_fill(pl->supported); linkmode_copy(pl->link_config.advertising, pl->supported); phylink_validate(pl, pl->supported, &pl->link_config); =20 ret =3D phylink_parse_mode(pl, fwnode); if (ret < 0) - goto free_pl; + goto unlink_pcs_list; =20 if (pl->cfg_link_an_mode =3D=3D MLO_AN_FIXED) { ret =3D phylink_parse_fixedlink(pl, fwnode); @@ -1937,6 +2071,11 @@ struct phylink *phylink_create(struct phylink_config= *config, release_link_gpio: if (pl->link_gpio) gpiod_put(pl->link_gpio); +unlink_pcs_list: + list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) { + list_del(&pcs->list); + pcs->phylink =3D NULL; + } free_pl: kfree(pl); return ERR_PTR(ret); @@ -1954,11 +2093,20 @@ EXPORT_SYMBOL_GPL(phylink_create); */ void phylink_destroy(struct phylink *pl) { + struct phylink_pcs *pcs, *tmp; + sfp_bus_del_upstream(pl->sfp_bus); if (pl->link_gpio) gpiod_put(pl->link_gpio); =20 cancel_work_sync(&pl->resolve); + + /* Remove every PCS from phylink PCS list */ + list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) { + pcs->phylink =3D NULL; + list_del(&pcs->list); + } + kfree(pl); } EXPORT_SYMBOL_GPL(phylink_destroy); @@ -2410,8 +2558,15 @@ void phylink_pcs_change(struct phylink_pcs *pcs, boo= l up) { struct phylink *pl =3D pcs->phylink; =20 - if (pl) - phylink_link_changed(pl, up, "pcs"); + /* + * Ignore PCS link state change if the PCS is not + * attached to a phylink instance or the phylink + * instance is not currently using this PCS. + */ + if (!pl || READ_ONCE(pl->pcs) !=3D pcs) + return; + + phylink_link_changed(pl, up, "pcs"); } EXPORT_SYMBOL_GPL(phylink_pcs_change); =20 diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 1dda5c7ed5f1..2c647238c7ce 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -12,6 +12,7 @@ struct ethtool_cmd; struct fwnode_handle; struct net_device; struct phylink; +struct phylink_pcs; =20 enum { MLO_PAUSE_NONE, @@ -151,6 +152,8 @@ enum phylink_op_type { * if MAC link is at %MLO_AN_FIXED mode. * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx * are supported by the MAC/PCS. + * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a + * dedicated PCS is required. * @lpi_interfaces: bitmap describing which PHY interface modes can support * LPI signalling. * @mac_capabilities: MAC pause/speed/duplex capabilities. @@ -160,6 +163,10 @@ enum phylink_op_type { * @wol_phy_legacy: Use Wake-on-Lan with PHY even if phy_can_wakeup() is f= alse * @wol_phy_speed_ctrl: Use phy speed control on suspend/resume * @wol_mac_support: Bitmask of MAC supported %WAKE_* options + * @num_possible_pcs: num of possible phylink_pcs PCS + * @fill_available_pcs: callback to fill the available PCS in the passed + * array struct of phylink_pcs PCS available_pcs up to + * num_possible_pcs. */ struct phylink_config { struct device *dev; @@ -172,6 +179,7 @@ struct phylink_config { void (*get_fixed_state)(struct phylink_config *config, struct phylink_link_state *state); DECLARE_PHY_INTERFACE_MASK(supported_interfaces); + DECLARE_PHY_INTERFACE_MASK(pcs_interfaces); DECLARE_PHY_INTERFACE_MASK(lpi_interfaces); unsigned long mac_capabilities; unsigned long lpi_capabilities; @@ -182,6 +190,11 @@ struct phylink_config { bool wol_phy_legacy; bool wol_phy_speed_ctrl; u32 wol_mac_support; + + unsigned int num_possible_pcs; + int (*fill_available_pcs)(struct phylink_config *config, + struct phylink_pcs **available_pcs, + unsigned int num_possible_pcs); }; =20 void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed); @@ -497,6 +510,9 @@ struct phylink_pcs { struct phylink *phylink; bool poll; bool rxc_always_on; + + /* private: */ + struct list_head list; }; =20 /** --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B757D471CE0 for ; Tue, 1 Sep 2026 08:30:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251429; cv=none; b=rNeFtMPhlWx4gCMyeW0ANLP/iO6gSdok+gLRDL8nD3vPxPQHLW3U8HFyHUWDxwTOX7S6eUfzYUrYqVVnoHS28qam1J/kUCOeZN9H2Yyt7NK0+HZdub9YC+xPM8bZ5cP37ETTsYrgxS0Pdv+InIgscqNq37O2/6gQi+KvV8D1b6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251429; c=relaxed/simple; bh=JxtVKSVJselOm57RGynHd4w+gBcE1GOn2gNwNHqzQGc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i7ACBYxSjcbKfbBqlE8/gqCxV7Pr5chl5qpWrTe4YHS/PfVHxLWpaXuJmryMspou92sNI06ctTwjxdbpv9vbtHWQfT0n3aYkKwpBnM/QYzie3wGwl6pzW5pWtC45mxnzW3mAgHuTAHEcqaiXFmpTpsUFXO5jduu3r5km2OS82Ys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aNSGkYJt; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aNSGkYJt" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-49cca4ffdcfso4199035e9.0 for ; Tue, 01 Sep 2026 01:30:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251425; x=1788856225; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=b2AbUJS6svto10VmUX2onyMIwPmCSimxxv4SKkwxJe4=; b=aNSGkYJt5HPMxIo9RQZ+R1SiP2cjNqC5QALYSoBuzpobSoFWI7WdnePnWc3Bu1xICm hKtS59E0ENj73zs4d7mwNrGMbFUB1zJHtUoug1rp+mK6ES6hFg7SjA3wZ3GllTm1ypVh oiFCha5NRAFGkxJHazcxUdSCpIcM3VcYIIIHIKggirWqRgfJ+FKFtRr8eeES+IusMMRX XV9WGOf+bmHRPVf4coJ4HKwqJyn++rkMrr/hazZGEK6HMMgiTUnGll3FC+ZTHYagBpDS wt+POhKm3QynL6FMJQZebF0ohDY6D2f6YJt1VMOBTz2655YJtzqRwndLjJEsVtv1+Z3+ QjOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251425; x=1788856225; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=b2AbUJS6svto10VmUX2onyMIwPmCSimxxv4SKkwxJe4=; b=pYD5fHZWTzSCxf6AdOHD65TpGJUaCLY8lbvDZmFXZVriclL9H5Dc/fg3oxWupt3tSR gG7Z/G/+mnDFiSf09QYCylVMV3aR//gc9+HzKqfX93zAX24rQ7l+EcGhxSUendynzPTs XcbnYwJJAB1+1ITzGOS6DetIlpOmXZQzL3AlbfKt3c79WToNZC4e9bmdccVTgwIQ/rgt s6y84nogIpmFLNUjHpmSM6cQaWEDrm4zalGsv1xMk8schlzWlicWRiZTRaCGvfYlNKdt CqlQM4eNoPJiBE3UFdox8I/RD/zd2mnkpvt1RNYdRq5cdNqeBGp2kjIoGpDDUMfRqaaM yROw== X-Forwarded-Encrypted: i=1; AHgh+Rq5y6/WoliKXrryGrK/mTGQHgaM/eP7kvgET3/HgeGJEKiqJ0zpkcllAHTRhmoQkgeTuFChZub/a9wWN/M=@vger.kernel.org X-Gm-Message-State: AFuF++mmyHEgC9eJBXUIKrAD17L4y850tMXXCPdDtvG5xKIIVEwb+Ei9 prWeXjQ+DBDRAWxkkh81eQQI5xVw1FOUeg6HbobZ5RgzMhNHKI0SWjHb X-Gm-Gg: AR+sD13pwtANsAwlqi2nm/agWcIDnq1jlA+unVZoRIkRH3AlJiB9/uvTgu/Eo2VzcOy TfOMOb6VSwoplPEYZm66fSytHBfSBeWKZ5oRbeZaUUCisOhABjhjnQ3jISxpBxoGtRDqIDaX5AB Z+w9F4f2b5WibbfQOO1G7CdkX+qlqERXysu9p8rLhqwo7Ixy8XIIgWmVAzGnLH5MvmD5rQF7PKN NiwWEn4zZwCMbkN9ddxBsEx87xQc7OZ4spH76xAx/iNQWJBRMUOowPdnZII0U07zsivIP9LQfFu 3vvlthFu499TApgmGcCiPOZ0OOlrlU4ejjaTMepWGw4eme3kP2exgswKjkP57KaYhdpIccFehic UxjB9dOIsX9QaDfd+w4xXF8eMqw+DPSG6XNncHtJB7y51fxiP6JPkoCQhEkGoO6nPr1wUAwMny6 UdCwJFq4Fjb7K795BlKlZDKT2qE6QLc/DH6wp409lNcE0O4UTKW+JsPbPwfM+bEYfuOgoVo4wn9 8BPyIIb9du4zguILaMA1+P++qgSgdV5HKbA7xBxKR8BULbETaPx X-Received: by 2002:a05:600c:1c0a:b0:493:bd2a:93be with SMTP id 5b1f17b1804b1-49b91c276efmr522392855e9.6.1788251421393; Tue, 01 Sep 2026 01:30:21 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:20 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Cc: Daniel Golle Subject: [PATCH net-next v15 03/12] net: pcs: implement Firmware node support for PCS driver Date: Tue, 1 Sep 2026 10:29:18 +0200 Message-ID: <20260901083001.8044-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement the foundation of Firmware node support for PCS driver. To support this, implement a simple Provider API where a PCS driver can expose multiple PCS with an xlate .fwnode_xlate function. PCS driver will have to call fwnode_pcs_add_provider() and pass the firmware node pointer and a xlate function to return the correct PCS for the passed #pcs-cells. This will register the PCS in a global list of providers so that consumer can access it. The consumer will then use fwnode_pcs_get() to get the actual PCS by passing the firmware node pointer and the index for #pcs-cells. For a simple implementation where #pcs-cells is 0 and the PCS driver expose a single PCS, the xlate function fwnode_pcs_simple_xlate() is provided. For an advanced implementation a custom xlate function is required. On removal the PCS driver must delete itself from the provider list using fwnode_pcs_del_provider(). A devm variant devm_fwnode_pcs_add() is provided to automate the release procedure. Generic functions fwnode_phylink_pcs_count() and fwnode_phylink_pcs_parse() are provided for MAC driver that will declare PCS in DT (or ACPI). Function fwnode_phylink_pcs_count() will parse "pcs-handle" property and will return the number of PCS entries described in the passed firmware node. Function fwnode_phylink_pcs_parse() will parse "pcs-handle" property and fill the passed available_pcs array with the available PCS found up to passed num_pcs value. It's worth to mention that this function will ignore PCS that still needs to be probed (returning -ENODEV) and such PCS won't be added to the available_pcs array. Co-developed-by: Daniel Golle Signed-off-by: Daniel Golle Signed-off-by: Christian Marangi --- drivers/net/pcs/Kconfig | 6 + drivers/net/pcs/Makefile | 1 + drivers/net/pcs/pcs.c | 245 +++++++++++++++++++++++++++++++ include/linux/pcs/pcs-provider.h | 70 +++++++++ include/linux/pcs/pcs.h | 74 ++++++++++ 5 files changed, 396 insertions(+) create mode 100644 drivers/net/pcs/pcs.c create mode 100644 include/linux/pcs/pcs-provider.h create mode 100644 include/linux/pcs/pcs.h diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index e417fd66f660..ba2caec866a5 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -5,6 +5,12 @@ =20 menu "PCS device drivers" =20 +config FWNODE_PCS + bool "PCS Firmware Node" + depends on ACPI || OF || COMPILE_TEST + help + Firmware node PCS accessors + config PCS_XPCS tristate "Synopsys DesignWare Ethernet XPCS" select PHYLINK diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index 4f7920618b90..3005cdd89ab7 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 # Makefile for Linux PCS drivers =20 +obj-$(CONFIG_FWNODE_PCS) +=3D pcs.o pcs_xpcs-$(CONFIG_PCS_XPCS) :=3D pcs-xpcs.o pcs-xpcs-plat.o \ pcs-xpcs-nxp.o pcs-xpcs-wx.o =20 diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c new file mode 100644 index 000000000000..39550d9a12a2 --- /dev/null +++ b/drivers/net/pcs/pcs.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include + +MODULE_DESCRIPTION("PCS library"); +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); + +struct fwnode_pcs_provider { + struct list_head link; + + struct fwnode_handle *fwnode; + struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec, + void *data); + + void *data; +}; + +static LIST_HEAD(fwnode_pcs_providers); +static DEFINE_MUTEX(fwnode_pcs_mutex); + +struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *= pcsspec, + void *data) +{ + return data; +} +EXPORT_SYMBOL_GPL(fwnode_pcs_simple_xlate); + +struct fwnode_pcs_provider * +fwnode_pcs_add_provider(struct fwnode_handle *fwnode, + struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcssp= ec, + void *data), + void *data) +{ + struct fwnode_pcs_provider *pp; + + if (!fwnode) + return ERR_PTR(-EINVAL); + + pp =3D kzalloc_obj(*pp); + if (!pp) + return ERR_PTR(-ENOMEM); + + pp->fwnode =3D fwnode_handle_get(fwnode); + pp->data =3D data; + pp->fwnode_xlate =3D fwnode_xlate; + + mutex_lock(&fwnode_pcs_mutex); + + list_add(&pp->link, &fwnode_pcs_providers); + fwnode_dev_initialized(fwnode, true); + + mutex_unlock(&fwnode_pcs_mutex); + + pr_debug("Added pcs provider from %pfwf\n", fwnode); + + return pp; +} +EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider); + +void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp) +{ + if (IS_ERR_OR_NULL(pp)) + return; + + mutex_lock(&fwnode_pcs_mutex); + + list_del(&pp->link); + fwnode_dev_initialized(pp->fwnode, false); + + mutex_unlock(&fwnode_pcs_mutex); + + fwnode_handle_put(pp->fwnode); + kfree(pp); +} +EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider); + +static void devm_fwnode_pcs_del(struct device *dev, void *res) +{ + struct fwnode_pcs_provider *pp =3D *(struct fwnode_pcs_provider **)res; + + fwnode_pcs_del_provider(pp); +} + +struct fwnode_pcs_provider * +devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwn= ode, + struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *= pcsspec, + void *data), + void *data) +{ + struct fwnode_pcs_provider **ptr, *pp; + + ptr =3D devres_alloc(devm_fwnode_pcs_del, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + pp =3D fwnode_pcs_add_provider(fwnode, fwnode_xlate, data); + + if (!IS_ERR(pp)) { + *ptr =3D pp; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return pp; +} +EXPORT_SYMBOL_GPL(devm_fwnode_pcs_add_provider); + +static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode, + int index, const char *name, + struct fwnode_reference_args *out_args) +{ + if (!fwnode) + return -EINVAL; + + if (name) { + index =3D fwnode_property_match_string(fwnode, "pcs-names", + name); + if (index < 0) + return index; + } + + return fwnode_property_get_reference_args(fwnode, "pcs-handle", + "#pcs-cells", 0, index, + out_args); +} + +static struct phylink_pcs * +__fwnode_pcs_get_from_pcsspec_provider(struct fwnode_reference_args *pcssp= ec, + struct fwnode_pcs_provider *provider) +{ + if (provider->fwnode !=3D pcsspec->fwnode) + return ERR_PTR(-EINVAL); + + return provider->fwnode_xlate(pcsspec, provider->data); +} + +static struct phylink_pcs * +fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec) +{ + struct fwnode_pcs_provider *provider; + struct phylink_pcs *pcs =3D NULL; + + if (!pcsspec) + return ERR_PTR(-EINVAL); + + mutex_lock(&fwnode_pcs_mutex); + list_for_each_entry(provider, &fwnode_pcs_providers, link) { + pcs =3D __fwnode_pcs_get_from_pcsspec_provider(pcsspec, provider); + if (!IS_ERR(pcs)) + break; + } + mutex_unlock(&fwnode_pcs_mutex); + + return !IS_ERR_OR_NULL(pcs) ? pcs : ERR_PTR(-ENODEV); +} + +static struct phylink_pcs *__fwnode_pcs_get(const struct fwnode_handle *fw= node, + unsigned int index, const char *con_id) +{ + struct fwnode_reference_args pcsspec; + struct phylink_pcs *pcs; + int ret; + + ret =3D fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec); + if (ret) + return ERR_PTR(ret); + + pcs =3D fwnode_pcs_get_from_pcsspec(&pcsspec); + fwnode_handle_put(pcsspec.fwnode); + + return pcs; +} + +struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode, uns= igned int index) +{ + return __fwnode_pcs_get(fwnode, index, NULL); +} +EXPORT_SYMBOL_GPL(fwnode_pcs_get); + +unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode) +{ + struct fwnode_reference_args out_args; + int index =3D 0; + int ret; + + while (true) { + ret =3D fwnode_property_get_reference_args(fwnode, "pcs-handle", + "#pcs-cells", 0, index, + &out_args); + /* We expect to reach an -ENOENT error while counting */ + if (ret) + break; + + fwnode_handle_put(out_args.fwnode); + index++; + } + + return index; +} +EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count); + +int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode, + struct phylink_pcs **available_pcs, + unsigned int num_pcs) +{ + unsigned int i, found =3D 0; + + if (!available_pcs) + return -EINVAL; + + if (!fwnode_property_present(fwnode, "pcs-handle")) + return -ENODEV; + + for (i =3D 0; i < num_pcs; i++) { + struct phylink_pcs *pcs; + + pcs =3D fwnode_pcs_get(fwnode, i); + if (IS_ERR(pcs)) { + /* Exit early if no PCS remain.*/ + if (PTR_ERR(pcs) =3D=3D -ENOENT) + break; + + /* + * Ignore -ENODEV error for PCS that still + * needs to probe. + */ + if (PTR_ERR(pcs) =3D=3D -ENODEV) + continue; + + return PTR_ERR(pcs); + } + + available_pcs[found] =3D pcs; + found++; + } + + return found; +} +EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse); diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provi= der.h new file mode 100644 index 000000000000..15c198ffdd58 --- /dev/null +++ b/include/linux/pcs/pcs-provider.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __LINUX_PCS_PROVIDER_H +#define __LINUX_PCS_PROVIDER_H + +struct fwnode_pcs_provider; + +/** + * fwnode_pcs_simple_xlate - Simple xlate function to retrieve PCS + * @pcsspec: reference arguments + * @data: Context data (assumed assigned to the single PCS) + * + * Returns: the PCS pointed by data. + */ +struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *= pcsspec, + void *data); + +/** + * fwnode_pcs_add_provider - Registers a new PCS provider + * @fwnode: Firmware node + * @fwnode_xlate: xlate function to retrieve the PCS + * @data: Context data + * + * Register and add a new PCS provider to the global providers list + * for the firmware node. The relevant PCS from the PCS provider + * is retrieved from the passed fwnode_xlate function. + * + * The xlate function MUST return a pointer to an existing, already-alloca= ted + * struct phylink_pcs and MUST NOT dynamically allocate a new PCS. + * The same PCS object must be returned for a given firmware reference and= args, + * as PCS pointer identity is used to associate PCS objects with their pro= vider. + * + * Returns: A pointer to the registered PCS provider on success, or + * an ERR_PTR() encoded error code on failure. + */ +struct fwnode_pcs_provider * +fwnode_pcs_add_provider(struct fwnode_handle *fwnode, + struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcssp= ec, + void *data), + void *data); + +/** + * fwnode_pcs_del_provider - Removes a PCS provider + * @pp: PCS provider returned by fwnode_pcs_add_provider() + */ +void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp); + +/** + * devm_fwnode_pcs_add_provider - Registers a new PCS provider + * @dev: Device of the PCS provider + * @fwnode: Firmware node + * @fwnode_xlate: xlate function to retrieve the PCS + * @data: Context data + * + * Register and add a new PCS provider to the global providers list + * for the firmware node. The relevant PCS from the PCS provider + * is retrieved from the passed fwnode_xlate function. While at that, it + * also associates the device with the PCS provider using devres. + * On driver detach, release function is invoked on the devres data, + * then, devres data is freed. + * + * Returns: A pointer to the registered PCS provider on success, or + * an ERR_PTR() encoded error code on failure. + */ +struct fwnode_pcs_provider * +devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwn= ode, + struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *= pcsspec, + void *data), + void *data); + +#endif /* __LINUX_PCS_PROVIDER_H */ diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h new file mode 100644 index 000000000000..ef2134c578c7 --- /dev/null +++ b/include/linux/pcs/pcs.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __LINUX_PCS_H +#define __LINUX_PCS_H + +#include + +#if IS_ENABLED(CONFIG_FWNODE_PCS) +/** + * fwnode_pcs_get - Retrieves a PCS from a firmware node + * @fwnode: firmware node + * @index: index fwnode PCS handle in firmware node + * + * Get a PCS from the firmware node at index. + * + * Returns: a pointer to the phylink_pcs or a negative error pointer. Can + * return -ENODEV if the PCS is not present in global providers list (eith= er + * due to driver still needs to be probed or it failed to probe/removed). + */ +struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode, + unsigned int index); + +/** + * fwnode_phylink_pcs_count - Count PCS entries described in firmware node + * @fwnode: firmware node + * + * Helper function to count the number of PCS entries referenced by the + * "pcs-handle" property in a firmware node. + * + * Note that this function counts all PCS references in the firmware node, + * regardless of whether the corresponding PCS devices are already probed. + * + * Returns: number of PCS entries described in the firmware node. + */ +unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode); + +/** + * fwnode_phylink_pcs_parse - Parse available PCS from firmware node + * @fwnode: firmware node + * @available_pcs: pointer to preallocated array of PCS + * @num_pcs: maximum number of PCS entries to scan + * + * Helper function that parses PCS references from the "pcs-handle" + * property of a firmware node and fills @available_pcs with PCS that are + * currently available up to @num_pcs. + * + * Only PCS that are currently available are stored in @available_pcs. + * PCS that returns -ENODEV are skipped. + * + * Returns: number of PCS stored in @available_pcs, or negative error code. + */ +int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode, + struct phylink_pcs **available_pcs, + unsigned int num_pcs); +#else +static inline struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handl= e *fwnode, + unsigned int index) +{ + return ERR_PTR(-ENOENT); +} + +static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *= fwnode) +{ + return 0; +} + +static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode, + struct phylink_pcs **available_pcs, + unsigned int num_pcs) +{ + return -EOPNOTSUPP; +} +#endif + +#endif /* __LINUX_PCS_H */ --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC5D147126B for ; Tue, 1 Sep 2026 08:30:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251427; cv=none; b=ktmTS46LBQaGjGg2yuNW5Vyq9Lgsd1psjLuDAsEXnryFilxV+ab9aFhwuZ09exKRU4yJrh4bXEjE5lUVYk/ir/CRWCweuWZGupWcJeplVucMApKUsS5TB1Q4wHx+uzne7vFCwbumcsgGClwLg+gqGsMRI7aZa9sKid0NzpkTPvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251427; c=relaxed/simple; bh=QkfsO9iIXWwWqn2LLgm3fPfnrSGchfrNPnJ7yZr1hKw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VbhXfck9OmGuyRAiDmu+cTt7+4xFesdb6qUwxRFn62Kdyn26YK/sU/oKrlLvO9B3jnJLPWo0239M70bjHyzv43hJ5ZaC90JsPT1lKtGj0LCM/upW5XvQy7Z25flF336duPvoUYqdrn74s5h+ce0fX5rYJD4MHs3CoTPPV0jsx1g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BPP5AhIT; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BPP5AhIT" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-49ccfbe062eso23055315e9.3 for ; Tue, 01 Sep 2026 01:30:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251424; x=1788856224; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=4Go8JUbpoOJsxHq3SuM6SXORIBsWItiVTBm2QkGFiCE=; b=BPP5AhITsB5ekQI+qVkeySJghnZ+NyqZ6+QcizNHbYn3ZpQL2jDnsyRoZfPeQfjq84 /3B+oe+Qh/EcQYSS0ngjZyku61Rwu5lWm0uIYfVsm/idRicRTmZo/2RaRfKrYkI0OW9o okPxe+l4uDgjp8K0MxsIcsrhOD6jC0BoInSYsCVFDnuYgfFSUiAGNB2hfw+9GEUNHDxs tDEQ0czGOkC6t8SVnCzDHk35/65JPPZE6QA8zU1vk9mxwGGpWLdGPggsIWi5KZ2HwtOI U8DKRtUtlqTip7RojD9YqgmVND8df6TmVuKjUtUcRSljYBpduo/eZ/WRsaG12kgejNGn 2ajQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251424; x=1788856224; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=4Go8JUbpoOJsxHq3SuM6SXORIBsWItiVTBm2QkGFiCE=; b=nZENmJERDWRnGsNjBDdtGfLNt3kPvfnHgSbk0uJ2g78xHNfiGszQPirfayb+hF72aU g6H7/2Raetu21YzhzteDPbcJm7p3HKsq4aOeECtkd0s657nF2Pgon3XvQ5EBbtMcONsn 6MR1PYn0fRrn5w+8ocNbeW9Kwa49YFZViUZCbcraqsrrCk1zwH7iX5wNChzXpvagq1O0 aFGZcxPOjSHQr7n8/rym8M+oXU72TK9jCsaFWmXG8dExnVFEnWY/5SfDNxVcGrq/+/FZ SP6UUx3Xl6CZqld7UL10V45oECiXU0FK4TWWvVQEdJWvhD/D1N/JFV4l6j1ydNonOwaq bxzg== X-Forwarded-Encrypted: i=1; AHgh+RogEYRTS8iSieEElVtlgjHeJBNPdHDnTNUJvjDABph+k913cQ9IolsAujHqoXN1+FHlaqnZ0roVdCss0+I=@vger.kernel.org X-Gm-Message-State: AFuF++nEROGlmXPYk1ui0qNeamHLIJu+byXn7D6RvF8ORIGoXO74FNSK LEPM3hS9gJfFqVwuH/rsuOSKXBoMIraeTWD3S/5zgdlsTdURmbwHzWU7 X-Gm-Gg: AR+sD11pB3YnjSz+1ZkIokn3RlipPSHwwy4w23i+KrjdZfQDLhT/diVZBJR3lBtrg3I nB60KL/otTsoVZPbq8NwUnHy/NALjq7Q7C/CeHZCQuQLFqnADv7ViK/+86wgt4HprI9gA4dJu/k LofgqYSWEYc1EL8wkechWy2eTi28jKS7aSftwc0V6yL5nbKST2nHRAye17DTqgTrFdY31BLioeG b+8dtS9+uRXBJfaqLkGjKL7nxze/PKPyhKqw6N58Q+hAauhPwKwK4Qn0akj53oXZE4zkGnFQ77B Cnphw61u0b95NtE0efujQBKwUgifr4+fyWhipaVypzc5sfFPnJHlm3BPf1wSFBfqufEZe3hiqsF c/cvLyBb3luOn+vVjQr+sWg7hBaBosOCLX0E0/zTZS5a/93XXqJWc1J3+Iz6ZeNHmVQGXyKspDd 7DUiiv52V1OAZAFCWCNH5x/hU0ZVzXr+u6zuZflV7SU42WTsZzvg8IlFv24YgAAzPeJMn6UIKsp s3Oq/7gqQA/WTy+PKImCQqatyYooyAbHXbWRCEOzca2Z+CImS2Y X-Received: by 2002:a05:600c:4453:b0:499:8777:ccba with SMTP id 5b1f17b1804b1-49b91c486abmr438008405e9.12.1788251423887; Tue, 01 Sep 2026 01:30:23 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:23 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 04/12] net: phylink: save phylink instance fwnode on phylink_create Date: Tue, 1 Sep 2026 10:29:19 +0200 Message-ID: <20260901083001.8044-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The firmware node associated with the phylink instance might differ from the device firmware node passed in phylink_config as such device can reference the parent switch or other platform peripherals. Some function might need to reference this firmware node after phylink_create so add a dedicated fwnode entry in phylink internal struct and save it on phylink_create(). Signed-off-by: Christian Marangi --- drivers/net/phy/phylink.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index d7391a60f01f..96f72eb5a6fa 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -44,6 +44,7 @@ struct phylink { const struct phylink_mac_ops *mac_ops; struct phylink_config *config; struct phylink_pcs *pcs; + struct fwnode_handle *fwnode; struct device *dev; unsigned int old_link_state:1; =20 @@ -1993,6 +1994,7 @@ struct phylink *phylink_create(struct phylink_config = *config, INIT_LIST_HEAD(&pl->pcs_list); =20 pl->config =3D config; + pl->fwnode =3D fwnode_handle_get((struct fwnode_handle *)fwnode); if (config->type =3D=3D PHYLINK_NETDEV) { pl->netdev =3D to_net_dev(config->dev); netif_carrier_off(pl->netdev); @@ -2077,6 +2079,7 @@ struct phylink *phylink_create(struct phylink_config = *config, pcs->phylink =3D NULL; } free_pl: + fwnode_handle_put(pl->fwnode); kfree(pl); return ERR_PTR(ret); } @@ -2107,6 +2110,8 @@ void phylink_destroy(struct phylink *pl) list_del(&pcs->list); } =20 + fwnode_handle_put(pl->fwnode); + kfree(pl); } EXPORT_SYMBOL_GPL(phylink_destroy); --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8020F46D544 for ; Tue, 1 Sep 2026 08:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251466; cv=none; b=BmAlvG2XCX2+kW5ZihHD3S4Il5ARclnYjPDP1q2lrB6FiVirfGt1j3IzasOQzpMfGcDfvNiLqRU9Bl2p5aweZIVYZ42drLkQQbwKq+PTe1sxc0p7m1rZ29yNNDkbUKS75uL94fWt4Ypm/5sl3gZ8Vztj5/Dv+hfuvp5QalKIRJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251466; c=relaxed/simple; bh=PHc0cqyRutr7l5wmKXDEH0LZ7DIczZsOXF8paliJM74=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d0+i1KSpQ51DGb9o/oucW0MkzCUYs5ZN9REvl1bdlQjUtq2SGZDp4haIhs3gf8eG+7YncRPfkknHn4Rm9eng2zi2w/KKOHG06TsJqQXZMxowC1zrZavmf6EbV5GOxsLY+cv+9OY+5hclV7gE1lpLLBn11iEyDL2F47PT1xXT+zA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cRqFz4g+; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cRqFz4g+" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-c252c7270faso748485366b.3 for ; Tue, 01 Sep 2026 01:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251462; x=1788856262; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=tUE+/AHcRUnA8SePV2VdX4HXvQGh2hBEeQpD97QfJfY=; b=cRqFz4g+DD4w9kC65eOYNZgDqstUQt11EGsXJY7hc5mTLJ420Yee1losRXEvpSU4ml oPooMTfaHIXsOUR3qw1HsVRd6T7Zex0XYsFVv8de/NhwU2E3jrIKoj4Y75xg2LLlmQUr fBPk1ZP1Svr8By/OI/XzBOc33Y+KaN1c3szPu8laOqt2uTyYvI5Lxl3ZBvl+FzIHgSgf ehipsAveucw18OD5ErcWnst1/PwfQLBYGMardQFGkOB45eseyE6MgU+SdmSbJT2YwTbu 2PnYMrhHTzHn6flYazABfTIgKNuexmQmazJsvOBaRmuRslpsGM7SNJ0csTcofNEEU8wr HEhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251462; x=1788856262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=tUE+/AHcRUnA8SePV2VdX4HXvQGh2hBEeQpD97QfJfY=; b=kKMzJ7PAKhm7Ce4vxpv11g4n6nmhYsoA5CP6EXnk9FbJZ1pPpDyJi61+pzoZ/jxJz3 2RtQNcFUeC2Dz6bwRD28a6q3E2Nq3ZfXOmj7gf57FPi/M5cnmzGJmo2HVmX1uoO842Ox A0SWPYo4y6b86i8LV5NdScC8xu6c80UegsJv9NdSMXHR3Q6MxJbIJSUB8cz2iKFIDORT IBhaczolZ4/jE414ON8+3FXJMmyIaV5UCQifzLcvnoLnJwFnXDX5Z11m9Dp1alucvH06 uLRMgstk6+Pry67uQ34Ej3a8OLtj4j2rHIv7EQazsQ5NX/ofbjR0Co29+WyRq5b+R7QB wJVg== X-Forwarded-Encrypted: i=1; AHgh+Rp1bMla3OFC+JN9xrXxCB6PfTBer89WcR1vrczfyXpqiqZQv7fs+3rW0E91KcaXUC2PNj1MTOF6fRVFHOA=@vger.kernel.org X-Gm-Message-State: AFuF++mjcRydRDTw3yR07aHx8x0OJ3glv5aRR7ASnp6WVYmKlwGc27wg s/JXAw4+5BDkTpTn30caY+fitKeQ+CwREJPhG6rJT9Ro6ZNKYw5iCGkS X-Gm-Gg: AR+sD12gXVe+3zk2PrJRV1tNz/3ScD0TMrLt2+H89+w6fdoVkzteO0LmP/Zu73kj1KS zYm+QG8tE9XG/l1mylIPaKYxHM0vQxpE8u2VEsj+RCz/iE2V6PHKOULvazhWuttaTwsfj8UKx79 fqDq/62/NsMMbNHfdr1CCYzjEfBTmSzrbqDccVwKG7G5Hv8b+zUUp1KvElTOY0CIraGaDBvzxhr JEiN4lKUMbmBiuCAE/6ROgXRIS7DMBqCLpMPJuRGxZS644tXE3PhcfZAxz7kl5iaFjWvjrQG7xc IXxDitVVUKZhr89QduZ0BF3DH/XkClt7JORoXewRFD8bCsqOuZ/3ld55YZLrgtQkX5GIwXFu59A zXF2+Gmfvee+tcs7NSA8MlsMT8H+1FflBxwpidMadS7F5AuM8y/D/JohYFGbw8sy+uWXeH4yPWV 9T5YlRHYPsyrno9O8swFB6ZmY2iW266EWge+NrYS2fdDnabQBYtpk+OV+RITOsAjmxtqVQXdb3X vPo/NN1eL1iibjPm11c8Q2m4f71pUTPkyMbocKkekHR4PkhcX5l X-Received: by 2002:a05:600c:4705:b0:499:dbae:43d3 with SMTP id 5b1f17b1804b1-49cdc452433mr99372965e9.9.1788251426480; Tue, 01 Sep 2026 01:30:26 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:25 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 05/12] net: phylink: support PCS provider release Date: Tue, 1 Sep 2026 10:29:20 +0200 Message-ID: <20260901083001.8044-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for release of fwnode PCS from a PCS provider. This works by creating a global notifier for the PCS provider and making each phylink instance that makes use of fwnode subscribe to this notifier. The PCS notifier will emit the event FWNODE_PCS_PROVIDER_DEL every time a new PCS provider is released. phylink will then react to this event and will call the new function fwnode_pcs_matches_provider() on each PCS of the phylink instance and will check if the PCS is provided by the PCS provider that is getting released. If a related PCS is found, then such PCS is removed from the phylink instance PCS list and the supported_interfaces value is updated. The flag force_major_config is set to make phylink resolve reconfigure the interface (even if it didn't change). This is needed to handle the special case when the current PCS used by phylink is removed and a major_config is needed to propagae the configuration change. With this option enabled we also force mac_config even if the PHY link is not up for the in-band case. Finally a phylink resolve is triggered to handle the PCS removal. Protect every access of phylink pcs_list with state_mutex to handle async PCS provider release. Signed-off-by: Christian Marangi --- drivers/net/pcs/pcs.c | 47 +++++++++++++ drivers/net/phy/phylink.c | 141 ++++++++++++++++++++++++++++++++++++-- include/linux/pcs/pcs.h | 69 +++++++++++++++++++ 3 files changed, 250 insertions(+), 7 deletions(-) diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c index 39550d9a12a2..25b3248e8b93 100644 --- a/drivers/net/pcs/pcs.c +++ b/drivers/net/pcs/pcs.c @@ -22,6 +22,19 @@ struct fwnode_pcs_provider { =20 static LIST_HEAD(fwnode_pcs_providers); static DEFINE_MUTEX(fwnode_pcs_mutex); +static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list); + +int register_fwnode_pcs_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb); +} +EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier); + +int unregister_fwnode_pcs_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&fwnode_pcs_notify_list, nb); +} +EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier); =20 struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *= pcsspec, void *data) @@ -74,6 +87,11 @@ void fwnode_pcs_del_provider(struct fwnode_pcs_provider = *pp) =20 mutex_unlock(&fwnode_pcs_mutex); =20 + /* Signal phylink to release any PCS from this provider */ + blocking_notifier_call_chain(&fwnode_pcs_notify_list, + FWNODE_PCS_PROVIDER_DEL, + pp); + fwnode_handle_put(pp->fwnode); kfree(pp); } @@ -183,6 +201,35 @@ struct phylink_pcs *fwnode_pcs_get(const struct fwnode= _handle *fwnode, unsigned } EXPORT_SYMBOL_GPL(fwnode_pcs_get); =20 +bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider, + const struct fwnode_handle *fwnode, + struct phylink_pcs *pl_pcs) +{ + struct fwnode_reference_args pcsspec; + int index =3D 0; + int ret; + + while (true) { + struct phylink_pcs *pcs; + + ret =3D fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec); + if (ret) + return false; + + pcs =3D __fwnode_pcs_get_from_pcsspec_provider(&pcsspec, provider); + if (!IS_ERR(pcs) && pcs =3D=3D pl_pcs) { + fwnode_handle_put(pcsspec.fwnode); + return true; + } + + fwnode_handle_put(pcsspec.fwnode); + index++; + } + + return false; +} +EXPORT_SYMBOL_GPL(fwnode_pcs_matches_provider); + unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode) { struct fwnode_reference_args out_args; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 96f72eb5a6fa..e88c1effe880 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -63,6 +64,7 @@ struct phylink { =20 /* List of available PCS */ struct list_head pcs_list; + struct notifier_block fwnode_pcs_nb; =20 /* What interface are supported by the current link. * Can change on removal or addition of new PCS. @@ -545,11 +547,15 @@ static int phylink_validate_mac_and_pcs(struct phylin= k *pl, unsigned long capabilities; int ret; =20 + mutex_lock(&pl->state_mutex); + /* Get the PCS for this interface mode */ if (pl->mac_ops->mac_select_pcs) { pcs =3D pl->mac_ops->mac_select_pcs(pl->config, state->interface); - if (IS_ERR(pcs)) + if (IS_ERR(pcs)) { + mutex_unlock(&pl->state_mutex); return PTR_ERR(pcs); + } /* * Find a PCS in available PCS list for the requested interface. * @@ -573,6 +579,7 @@ static int phylink_validate_mac_and_pcs(struct phylink = *pl, * error and backtrace rather than oopsing the kernel. */ if (!pcs->ops) { + mutex_unlock(&pl->state_mutex); phylink_err(pl, "interface %s: uninitialised PCS\n", phy_modes(state->interface)); dump_stack(); @@ -582,6 +589,7 @@ static int phylink_validate_mac_and_pcs(struct phylink = *pl, /* Recheck PCS to handle legacy way for .mac_select_pcs */ ret =3D phylink_validate_pcs_interface(pcs, state->interface); if (ret) { + mutex_unlock(&pl->state_mutex); phylink_err(pl, "selected PCS does not support %s\n", phy_modes(state->interface)); return -EINVAL; @@ -590,8 +598,10 @@ static int phylink_validate_mac_and_pcs(struct phylink= *pl, /* Validate the link parameters with the PCS */ if (pcs->ops->pcs_validate) { ret =3D pcs->ops->pcs_validate(pcs, supported, state); - if (ret < 0 || phylink_is_empty_linkmode(supported)) + if (ret < 0 || phylink_is_empty_linkmode(supported)) { + mutex_unlock(&pl->state_mutex); return -EINVAL; + } =20 /* Ensure the advertising mask is a subset of the * supported mask. @@ -601,6 +611,8 @@ static int phylink_validate_mac_and_pcs(struct phylink = *pl, } } =20 + mutex_unlock(&pl->state_mutex); + /* Then validate the link parameters with the MAC */ if (pl->mac_ops->mac_get_caps) capabilities =3D pl->mac_ops->mac_get_caps(pl->config, @@ -996,6 +1008,9 @@ static unsigned int phylink_inband_caps(struct phylink= *pl, phy_interface_t interface) { struct phylink_pcs *pcs =3D NULL; + int ret =3D 0; + + mutex_lock(&pl->state_mutex); =20 if (pl->mac_ops->mac_select_pcs) { pcs =3D pl->mac_ops->mac_select_pcs(pl->config, @@ -1012,9 +1027,14 @@ static unsigned int phylink_inband_caps(struct phyli= nk *pl, } =20 if (IS_ERR_OR_NULL(pcs)) - return 0; + goto exit; + + ret =3D phylink_pcs_inband_caps(pcs, interface); + +exit: + mutex_unlock(&pl->state_mutex); =20 - return phylink_pcs_inband_caps(pcs, interface); + return ret; } =20 static void phylink_pcs_poll_stop(struct phylink *pl) @@ -1555,7 +1575,9 @@ static void phylink_mac_initial_config(struct phylink= *pl, bool force_restart) phylink_apply_manual_flow(pl, &link_state); if (phy) mutex_lock(&phy->lock); + mutex_lock(&pl->state_mutex); phylink_major_config(pl, force_restart, &link_state); + mutex_unlock(&pl->state_mutex); if (phy) mutex_unlock(&phy->lock); } @@ -1923,6 +1945,9 @@ static int phylink_fill_available_pcs(struct phylink = *pl, if (!pcss) return -ENOMEM; =20 + /* Lock state_mutex while filling to handle PCS notify */ + mutex_lock(&pl->state_mutex); + ret =3D config->fill_available_pcs(config, pcss, config->num_possible_pcs= ); if (ret < 0) goto out; @@ -1937,11 +1962,89 @@ static int phylink_fill_available_pcs(struct phylin= k *pl, } =20 out: + mutex_unlock(&pl->state_mutex); + kfree(pcss); =20 return ret; } =20 +static void phylink_del_pcs(struct phylink *pl, struct phylink_pcs *pcs) +{ + lockdep_assert_held(&pl->state_mutex); + + list_del(&pcs->list); + pcs->phylink =3D NULL; + + /* + * Check if we are removing the PCS currently + * in use by this phylink instance. If this is the case, + * tear down the link, force phylink resolve to reconfigure the + * interface mode, disable the current PCS and set the + * phylink PCS to NULL. + */ + if (pl->pcs =3D=3D pcs) { + if (pl->old_link_state) { + phylink_link_down(pl); + pl->old_link_state =3D false; + } + if (pl->cfg_link_an_mode =3D=3D MLO_AN_INBAND) + timer_delete_sync(&pl->link_poll); + phylink_pcs_disable(pl->pcs); + + pl->force_major_config =3D true; + WRITE_ONCE(pl->pcs, NULL); + } +} + +static int pcs_provider_notify(struct notifier_block *self, + unsigned long val, void *data) +{ + struct phylink *pl =3D container_of(self, struct phylink, fwnode_pcs_nb); + struct fwnode_pcs_provider *pp =3D data; + struct phylink_pcs *pcs, *tmp; + bool resolve =3D false; + + rtnl_lock(); + + mutex_lock(&pl->state_mutex); + + /* + * Loop all the PCS for phylink instance and check if + * this notification is relevant for some of them. + */ + list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) { + if (!fwnode_pcs_matches_provider(pp, pl->fwnode, pcs)) + continue; + + phylink_del_pcs(pl, pcs); + resolve =3D true; + } + + /* Exit early if nothing has changed */ + if (!resolve) { + mutex_unlock(&pl->state_mutex); + rtnl_unlock(); + return NOTIFY_DONE; + } + + /* Refresh supported interfaces */ + phy_interface_copy(pl->supported_interfaces, + pl->config->supported_interfaces); + list_for_each_entry(pcs, &pl->pcs_list, list) + phy_interface_or(pl->supported_interfaces, + pl->supported_interfaces, + pcs->supported_interfaces); + + mutex_unlock(&pl->state_mutex); + + rtnl_unlock(); + + phylink_run_resolve(pl); + + return NOTIFY_OK; +} + /** * phylink_create() - create a phylink instance * @config: a pointer to the target &struct phylink_config @@ -2030,10 +2133,18 @@ struct phylink *phylink_create(struct phylink_confi= g *config, __set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); timer_setup(&pl->link_poll, phylink_fixed_poll, 0); =20 + /* First register notifier for hotplug PCS events */ + if (!phy_interface_empty(config->pcs_interfaces)) { + pl->fwnode_pcs_nb.notifier_call =3D pcs_provider_notify; + register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb); + } + /* Fill the PCS list with available PCS from phylink config */ ret =3D phylink_fill_available_pcs(pl, config); if (ret < 0) - goto free_pl; + goto unregister_pcs_notify; + + mutex_lock(&pl->state_mutex); =20 /* Link available PCS to phylink */ list_for_each_entry(pcs, &pl->pcs_list, list) @@ -2048,13 +2159,15 @@ struct phylink *phylink_create(struct phylink_confi= g *config, pl->supported_interfaces, pcs->supported_interfaces); =20 + mutex_unlock(&pl->state_mutex); + linkmode_fill(pl->supported); linkmode_copy(pl->link_config.advertising, pl->supported); phylink_validate(pl, pl->supported, &pl->link_config); =20 ret =3D phylink_parse_mode(pl, fwnode); if (ret < 0) - goto unlink_pcs_list; + goto unregister_pcs_notify; =20 if (pl->cfg_link_an_mode =3D=3D MLO_AN_FIXED) { ret =3D phylink_parse_fixedlink(pl, fwnode); @@ -2073,11 +2186,17 @@ struct phylink *phylink_create(struct phylink_confi= g *config, release_link_gpio: if (pl->link_gpio) gpiod_put(pl->link_gpio); -unlink_pcs_list: +unregister_pcs_notify: + if (pl->fwnode_pcs_nb.notifier_call) + unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb); + /* PCS notifier might queue a resolve, cancel it */ + cancel_work_sync(&pl->resolve); + mutex_lock(&pl->state_mutex); list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) { list_del(&pcs->list); pcs->phylink =3D NULL; } + mutex_unlock(&pl->state_mutex); free_pl: fwnode_handle_put(pl->fwnode); kfree(pl); @@ -2102,14 +2221,22 @@ void phylink_destroy(struct phylink *pl) if (pl->link_gpio) gpiod_put(pl->link_gpio); =20 + /* Unregister notifier for late PCS attach */ + if (pl->fwnode_pcs_nb.notifier_call) + unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb); + cancel_work_sync(&pl->resolve); =20 + mutex_lock(&pl->state_mutex); + /* Remove every PCS from phylink PCS list */ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) { pcs->phylink =3D NULL; list_del(&pcs->list); } =20 + mutex_unlock(&pl->state_mutex); + fwnode_handle_put(pl->fwnode); =20 kfree(pl); diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h index ef2134c578c7..83e0a2ad4b09 100644 --- a/include/linux/pcs/pcs.h +++ b/include/linux/pcs/pcs.h @@ -4,7 +4,38 @@ =20 #include =20 +enum fwnode_pcs_notify_event { + FWNODE_PCS_PROVIDER_DEL, +}; + +struct fwnode_pcs_provider; + #if IS_ENABLED(CONFIG_FWNODE_PCS) +/** + * register_fwnode_pcs_notifier - Register a notifier block for fwnode + * PCS events + * @nb: pointer to the notifier block + * + * Registers a notifier block to the fwnode_pcs_notify_list blocking + * notifier chain. This allows phylink instance to subscribe for + * PCS provider events. + * + * Returns: 0 or a negative error. + */ +int register_fwnode_pcs_notifier(struct notifier_block *nb); + +/** + * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode + * PCS events + * @nb: pointer to the notifier block + * + * Unregisters a notifier block to the fwnode_pcs_notify_list blocking + * notifier chain. + * + * Returns: 0 or a negative error. + */ +int unregister_fwnode_pcs_notifier(struct notifier_block *nb); + /** * fwnode_pcs_get - Retrieves a PCS from a firmware node * @fwnode: firmware node @@ -19,6 +50,27 @@ struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode, unsigned int index); =20 +/** + * fwnode_pcs_matches_provider() - Check whether a PCS belongs to a provid= er + * @provider: PCS provider to check + * @fwnode: firmware node containing the PCS references + * @pl_pcs: PCS to check + * + * Parse the PCS references from the "pcs-handle" property of a firmware n= ode + * and use provider to determine whether pl_pcs is one of the PCS provided= by + * provider. + * + * This function is intended to be used when handling provider removal + * notifications, where the provider is already known and its PCS need to = be + * identified among the PCS associated with a phylink instance. + * + * Returns: true if pl_pcs is provided by provider and referenced by fwnod= e, + * false otherwise. + */ +bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider, + const struct fwnode_handle *fwnode, + struct phylink_pcs *pl_pcs); + /** * fwnode_phylink_pcs_count - Count PCS entries described in firmware node * @fwnode: firmware node @@ -52,12 +104,29 @@ int fwnode_phylink_pcs_parse(struct fwnode_handle *fwn= ode, struct phylink_pcs **available_pcs, unsigned int num_pcs); #else +static inline int register_fwnode_pcs_notifier(struct notifier_block *nb) +{ + return -EOPNOTSUPP; +} + +static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb) +{ + return -EOPNOTSUPP; +} + static inline struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handl= e *fwnode, unsigned int index) { return ERR_PTR(-ENOENT); } =20 +static inline bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider = *provider, + const struct fwnode_handle *fwnode, + struct phylink_pcs *pl_pcs) +{ + return false; +} + static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *= fwnode) { return 0; --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAB65472070 for ; Tue, 1 Sep 2026 08:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251433; cv=none; b=reWV+n9CIjkrRXPYFUrtgG09cz/ISwj6YMOrVoPOmGlyClUfyJf8PSlC2DoLPKa/ZwBcmWjb+k5Qn63HbXXlT6GHZdW4ixKlcBZEon+PcLJNdswzyNYdmvnGPc4ChfwoXOvNgICcTk+dJPb58iqFgP/AeL4LHoOFKfxnsZAbP20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251433; c=relaxed/simple; bh=Uy7P1hFgMzyHDTtxqH1mm6G4FHdl8e+SoPnghgSBiuM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nrWwjVJRVJpiCWyrW4ZyCmjojgVx0iGd9ksxvXFEiczbr9tCmpQxmKYZuo88j/8pDrklXOmytVznJEK8vlYRRx1Mcx8OhaejqxE1wMT4XydedbNjoWI4hk89j9lSglivnuMt1juAGbZvo5EMW7tMG08+kXyOUtWELtGnDvnEgek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=e/rlO8p/; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e/rlO8p/" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-49954b88fffso31547335e9.0 for ; Tue, 01 Sep 2026 01:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251430; x=1788856230; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=2HZi6igNNcqvFjQiOZ0hxc12kwxhpH+s4rFAv99wT4E=; b=e/rlO8p/OM5Hy27994zDGQCO4bekOcDuXiSQQLIHaOYiOQA3LNirRMT/DktvY/quoF XdU7PTNL9IPebluGIr8UO2l3F9VFvj1ywWpiTvPK9M932b9GoI1g5ItWqov6p2QHAuQA +Pbh7TtM1P8dry5hpbjAoI2xLuhVCrKOEQYYWcRGnBQKUTC6yLB55RXzeRkOcz0Mo2ZC u0YsPH5ONrtZZH0XJ+WViKJRN2UAJL60pJW4JHA3v6RmKBlQq+j3nsgBIJPi6TO8GfhX ZGUBLyBAjjvNGSbqkX0PzY8Ew5xm2NKVE09RPQd3bQng8bQeO4uRunDAN4oirU1rqfWl iiiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251430; x=1788856230; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=2HZi6igNNcqvFjQiOZ0hxc12kwxhpH+s4rFAv99wT4E=; b=nOqhnyPiY8w5oKG5NxDexIuMEtNJCuyAqSMkG/Aq1vDfXXyNkF6kM8Xno5tPGhLcio s01MCUdw3fze2Q2eJCcZifEtKoFX18bCZOkVkEXWBmTcDn0GeThaTjfT7ZW1h8oPRXg5 X0hfKJMvsbX8ol44d6mvTXvoq5PE3QaPm8QYPgQ/FJkMGvI7CIuvEnCwH94LMo/H6pG/ 5CpjEoPi15ra7NNvSIrYDTlx9hJdn77IJ4y6ESsaqxzDWsaEHUoAyYjYq4h8bVSwb1J7 vxCHNk3y80DG4fB3Jlzw6qiLyDYr/qRFLVvriFblc9BgHE97qvHEiAQBNGSKraZsisYi wGWQ== X-Forwarded-Encrypted: i=1; AHgh+RpDvMZYdP1iD7FnN323Qvsw0CxHRmETC6BovhEfMP1BEllQrzUAFXIPo230dKDLBPgEOEUgGmGfBML0UWw=@vger.kernel.org X-Gm-Message-State: AFuF++nG3YwqUaT2fVi61aqSxDN6nY7qRMHfGyFa66O/xFkaxMfxP5ov 9qoJSc4Cr7Q2Z2fTaIdwxNn6g1sidQdLn/AAt9+OcKfkPpMdqKeUbwyI X-Gm-Gg: AR+sD13cn7xJjCDp9ej6xo7mL3O8HavB2ktdgl6Axc39/tGtsNI7ghsDAvMwjpFfvcc Q9OdomCkT5RT/l9IYQh5rlxqQfic0Cr3SBgO0toZV6v+EagUFWAJEiQMzVkN5vXrg5kTGaWPjRe /k/A03qvg5V54oYPqVn62Z7cBkx7EhecmeMeTHshAxWF+IOLQQ6sMqoHup4m8hssnAYVxAjcAtU u9/iYUkPb3mcp3p56lgjaDrSgdwax01MqeLz8GamV0yeqAeNxNfDsVYFBFGE+bQlar3UJhVAmtm 5CuVRiYa6IAT8PYioVWV22b4KgBKLLi1MSKhO8ARk62706pedok6wXRXCByVCiFy0IoZOmmUjVM bRrcRhWDFhMGQRe84cSdrU/6L+KCc3cJpFAOd8X0nPNV0fWODfQmsxVrurr6TexsedkJZpO0xV1 eYIc2HBeoA6SckPxrdd8BEw8uUelWHRj5vq/EkDcE712o+Q+MqqT4E+Cpv0lnynpbyb9TiSOzb8 XVjAMOjmmOhKZgyRSHQvvCEVKo4+lkwAeus236NayaOXXPJmhtf X-Received: by 2002:a05:600c:3155:b0:49b:910c:7703 with SMTP id 5b1f17b1804b1-49b91c3dcb4mr475751855e9.9.1788251429893; Tue, 01 Sep 2026 01:30:29 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:28 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 06/12] net: phylink: support late PCS provider attach Date: Tue, 1 Sep 2026 10:29:21 +0200 Message-ID: <20260901083001.8044-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for late PCS provider attachment to a phylink instance. Similar to FWNODE_PCS_PROVIDER_DEL, FWNODE_PCS_PROVIDER_ADD is added to address the case where a PCS provider is added after a phylink instance is created and started. The PCS notifier will emit the event FWNODE_PCS_PROVIDER_ADD every time a new PCS provider is added. If a related PCS is found, then such PCS is added to the phylink instance PCS list. Such PCS is then linked to the phylink instance and the supported interfaces of the phylink instance get refreshed. If we are in a major_config_failed scenario an interface reconfiguration is triggered in the next phylink resolve. In the example scenario where the link was previously torn down due to removal of PCS, the link will be established again as the PCS came back and is now available to phylink. Signed-off-by: Christian Marangi --- drivers/net/pcs/pcs.c | 22 +++++++++++ drivers/net/phy/phylink.c | 82 +++++++++++++++++++++++++++++++-------- include/linux/pcs/pcs.h | 31 +++++++++++++++ 3 files changed, 118 insertions(+), 17 deletions(-) diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c index 25b3248e8b93..fef560eddf2a 100644 --- a/drivers/net/pcs/pcs.c +++ b/drivers/net/pcs/pcs.c @@ -69,6 +69,10 @@ fwnode_pcs_add_provider(struct fwnode_handle *fwnode, =20 mutex_unlock(&fwnode_pcs_mutex); =20 + blocking_notifier_call_chain(&fwnode_pcs_notify_list, + FWNODE_PCS_PROVIDER_ADD, + pp); + pr_debug("Added pcs provider from %pfwf\n", fwnode); =20 return pp; @@ -201,6 +205,24 @@ struct phylink_pcs *fwnode_pcs_get(const struct fwnode= _handle *fwnode, unsigned } EXPORT_SYMBOL_GPL(fwnode_pcs_get); =20 +struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provide= r *provider, + const struct fwnode_handle *fwnode, + int index) +{ + struct fwnode_reference_args pcsspec; + struct phylink_pcs *pcs; + int ret; + + ret =3D fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec); + if (ret) + return ERR_PTR(ret); + + pcs =3D __fwnode_pcs_get_from_pcsspec_provider(&pcsspec, provider); + fwnode_handle_put(pcsspec.fwnode); + return pcs; +} +EXPORT_SYMBOL_GPL(fwnode_pcs_get_from_provider); + bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider, const struct fwnode_handle *fwnode, struct phylink_pcs *pl_pcs) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index e88c1effe880..a68d77ba5728 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1926,6 +1926,27 @@ int phylink_set_fixed_link(struct phylink *pl, } EXPORT_SYMBOL_GPL(phylink_set_fixed_link); =20 +static void phylink_add_pcs(struct phylink *pl, struct phylink_pcs *pcs) +{ + struct phylink_pcs *tmp; + + /* + * Make sure state mutex is locked to protect concurrent + * access to phylink instance PCS list from + * initial fill_available_pcs and late PCS attach + */ + lockdep_assert_held(&pl->state_mutex); + + list_for_each_entry(tmp, &pl->pcs_list, list) + if (tmp =3D=3D pcs) + return; + + list_add_tail(&pcs->list, &pl->pcs_list); + + /* Link PCS to phylink */ + pcs->phylink =3D pl; +} + static int phylink_fill_available_pcs(struct phylink *pl, struct phylink_config *config) { @@ -1958,7 +1979,7 @@ static int phylink_fill_available_pcs(struct phylink = *pl, if (!pcs) continue; =20 - list_add_tail(&pcs->list, &pl->pcs_list); + phylink_add_pcs(pl, pcs); } =20 out: @@ -2004,27 +2025,57 @@ static int pcs_provider_notify(struct notifier_bloc= k *self, struct fwnode_pcs_provider *pp =3D data; struct phylink_pcs *pcs, *tmp; bool resolve =3D false; + int count, i; =20 - rtnl_lock(); + /* + * On PCS provider deletion hold rtnl lock as one of + * PCS can be currently in use by the phylink instance + * and ethtool OPs can reference it. + */ + if (val =3D=3D FWNODE_PCS_PROVIDER_DEL) + rtnl_lock(); =20 mutex_lock(&pl->state_mutex); =20 - /* - * Loop all the PCS for phylink instance and check if - * this notification is relevant for some of them. - */ - list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) { - if (!fwnode_pcs_matches_provider(pp, pl->fwnode, pcs)) - continue; + switch (val) { + case FWNODE_PCS_PROVIDER_ADD: + count =3D fwnode_phylink_pcs_count(pl->fwnode); + for (i =3D 0; i < count; i++) { + pcs =3D fwnode_pcs_get_from_provider(pp, pl->fwnode, i); + if (IS_ERR(pcs)) + continue; + + phylink_add_pcs(pl, pcs); + resolve =3D true; + } + + /* Force an interface reconfig if major config fail */ + if (resolve && pl->major_config_failed) + pl->force_major_config =3D true; =20 - phylink_del_pcs(pl, pcs); - resolve =3D true; + break; + case FWNODE_PCS_PROVIDER_DEL: + /* + * Loop all the PCS for phylink instance and check if + * this notification is relevant for some of them. + */ + list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) { + if (!fwnode_pcs_matches_provider(pp, pl->fwnode, pcs)) + continue; + + phylink_del_pcs(pl, pcs); + resolve =3D true; + } + break; } =20 /* Exit early if nothing has changed */ if (!resolve) { mutex_unlock(&pl->state_mutex); - rtnl_unlock(); + + if (val =3D=3D FWNODE_PCS_PROVIDER_DEL) + rtnl_unlock(); + return NOTIFY_DONE; } =20 @@ -2038,7 +2089,8 @@ static int pcs_provider_notify(struct notifier_block = *self, =20 mutex_unlock(&pl->state_mutex); =20 - rtnl_unlock(); + if (val =3D=3D FWNODE_PCS_PROVIDER_DEL) + rtnl_unlock(); =20 phylink_run_resolve(pl); =20 @@ -2146,10 +2198,6 @@ struct phylink *phylink_create(struct phylink_config= *config, =20 mutex_lock(&pl->state_mutex); =20 - /* Link available PCS to phylink */ - list_for_each_entry(pcs, &pl->pcs_list, list) - pcs->phylink =3D pl; - phy_interface_copy(pl->supported_interfaces, pl->config->supported_interfaces); =20 diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h index 83e0a2ad4b09..00a636c82c65 100644 --- a/include/linux/pcs/pcs.h +++ b/include/linux/pcs/pcs.h @@ -5,6 +5,7 @@ #include =20 enum fwnode_pcs_notify_event { + FWNODE_PCS_PROVIDER_ADD, FWNODE_PCS_PROVIDER_DEL, }; =20 @@ -50,6 +51,28 @@ int unregister_fwnode_pcs_notifier(struct notifier_block= *nb); struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode, unsigned int index); =20 +/** + * fwnode_pcs_get_from_provider() - Retrieve a PCS from a specific provider + * @provider: PCS provider to use + * @fwnode: firmware node + * @index: index fwnode PCS handle in firmware node + * + * Get a PCS from the firmware node at index specifically provided by + * passed PCS provider. + * + * Unlike fwnode_pcs_get(), this function does not search the global list = of + * PCS providers. The caller must provide the provider responsible for the + * referenced PCS. + * + * Returns: a pointer to the phylink_pcs or a negative error pointer. Can + * return -ENODEV if the PCS is not present in global providers list (eith= er + * due to driver still needs to be probed or it failed to probe/removed) or + * can return -EINVAL if the PCS provider doesn't expose any PCS for the f= wnode. + */ +struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provide= r *provider, + const struct fwnode_handle *fwnode, + int index); + /** * fwnode_pcs_matches_provider() - Check whether a PCS belongs to a provid= er * @provider: PCS provider to check @@ -120,6 +143,14 @@ static inline struct phylink_pcs *fwnode_pcs_get(const= struct fwnode_handle *fwn return ERR_PTR(-ENOENT); } =20 +static inline struct phylink_pcs * +fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider, + const struct fwnode_handle *fwnode, + int index) +{ + return ERR_PTR(-ENOENT); +} + static inline bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider = *provider, const struct fwnode_handle *fwnode, struct phylink_pcs *pl_pcs) --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4E05474268 for ; Tue, 1 Sep 2026 08:30:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251437; cv=none; b=RSp+DV0m9qt+Qe4pMYQOzlPkZDDNx1VIdQtwsBxxmoDeUaduPSrUBfUzqTHWYa8qXoMa0Duqy/uNFM4UlNUcUwm6rWMDauyJAWWcwBnwy66gaDViodeD5GEuKPMPxaE1Apsvki6uq5yjbjMkDov1uhXup8dlgVMZ7NzHbjl21ts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251437; c=relaxed/simple; bh=ZorFQpVLqd70tRHeIpI5fLy2Qe7FkuHBADwIJX7pmAc=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P72+BQRjL4HqG3TBT8BZDmbpm58JowVhjhL/G8oe55F8H+ziLZcw9PZiN91KaRvVqCQMGkS+6tGeUNLOaMlhe2OpjnlDDLs7wqiAWmJ98KSdq1TPpXP4BAIsOi/sWrN5Ngs31FZH2KmMd9Xd6VlRYFV47dWKQrdZHZl+/RF/sC8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QTinHPiy; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QTinHPiy" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-49b8f86c6deso26070305e9.0 for ; Tue, 01 Sep 2026 01:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251433; x=1788856233; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=mgNAwW2BlGq0AAA4/ZvTmXt/lRmj3RQ9RMbCqvsLCVY=; b=QTinHPiynXAlqVBfpexqlTa35d/fng5y9tphlgCID0oniPZUljKwnIybKfRo7rngEj BevvY5J4Q/XTt79wiKn9n3T33Pb9QLM31lwr+QfvQKAy88byjFms/GoAwTDgIiiyqRWM HdkbAZxaxmJZnlvgwAIm/FQdSQ5dFba3/rpr8JN7LYSrSiAXZniPTfIFKmHwpR7dGTaV SZkT4JwwNkAIfkzs5iQuL3Gxq+mUboNpSXlISwh8u+jAZuCYgumvNPmNOF0pdT8yY/p/ FU+ruhG9fGdIPAW/G9ws0nqwWjMB1AfZi1Viq5m/2Dio/Dpr8VemSKhT3AebT1Z7upeh 1BtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251433; x=1788856233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=mgNAwW2BlGq0AAA4/ZvTmXt/lRmj3RQ9RMbCqvsLCVY=; b=rpMtqUgI33MQF6okm/54Sw6Ri6M7JXzC1tztiBLNTETlh0JcWswVNCNajG774VjKcr zCtyxPYJAG3NIs6YNv24MvBYfdAktTpylQU/wZCiJObq/h5Yv6jZmG2vHVCG3ImJhJ9z wpdKeMU9FBwjKU1Hul5P4oYQF5w9Yp6o57FdM5HtZ5vw3W6Pw3x7XjKHRSSrKABZlKIO n4A9gRS3VcPfc2qvsieXkev0D+VDiXMMhL9dYtzZIcnbRU6hOwLBOMXfJL3xth17FO3O 4gD2z1CQ13aOl14udapprALJVRV0lh+MrI6yBySO4qXMARBB35acPFxt3k9ExBf9zLQ/ iJIw== X-Forwarded-Encrypted: i=1; AHgh+Rr9efHktOH+FajT0wWPnZdUJ9h980oytjA/ES4kP8HlG6UpmpI/xdfqbNviJapo/WbfYVeL8Go4jb8HJu4=@vger.kernel.org X-Gm-Message-State: AFuF++nV6+bd/DTXU2p5h+/K+1UG2zU/O5s/QdTKRikkDT4Tiv+stwyn 4sG4CF6sh/mP4W5kJ+Q1fuutcfk+IqwKp6/DsQbPKsi/XdeNWHbXmZZV X-Gm-Gg: AR+sD11BIqJd8nZvBtEkwYXQhPv8JQQOgY4mbmKiRN8Bn1fK7auIQLRAgrYlK1fopys FzX6laFp5yTpRvVZcPoG574aGyWnDryab99y5kCB9nLZfqNtgbR4i+X5WDpSCSv2VX68o5nP5Gv yh3ST89sJOnBqZpMA9KYjvh2rRGP277LOzyUlBezDK6nhlUS7lQG56nuB+lCBcMasryauhzQae/ OEyAoCES68YstSX6fm+RKEtwTlzJ6PERRJcE91C03239ZrSIjHWfcwskTjy+4akoo7Tg6I1nKzr Xx2QVM6Ng+4MfTPtgqsL0/G0Jiq9Mcb+Oto6/CIWu8l4WmjIi4k4/qFrPk362HskHABM7hYAQsV MDVNv36gjDGBbE+UVClcI9QjHWoaZxIy1TYATtfgPjYsAA/VOlm1S3IaxTZbqxdY6G0VKFsXVje +HLdeqBuiH/zLrJMS7GajsWsuX1WAu1MAL7PEB9J857ykRSgBpUCUATHso4PyYzMoaleTEB1ArY yUq68i8MXskfSh9tpxbRS3lOA3JyGcM9exYYhV/DEyRm7JS8g66 X-Received: by 2002:a05:600c:3f10:b0:49c:d019:70c5 with SMTP id 5b1f17b1804b1-49cd01972c9mr330795615e9.0.1788251432530; Tue, 01 Sep 2026 01:30:32 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:31 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 07/12] net: Document PCS subsystem Date: Tue, 1 Sep 2026 10:29:22 +0200 Message-ID: <20260901083001.8044-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add extensive documentation of the new PCS subsystem and the fwnode implementation with producer/consumer API. Also update the sfp-phylink migration guide. Signed-off-by: Christian Marangi --- Documentation/networking/index.rst | 1 + Documentation/networking/pcs.rst | 234 +++++++++++++++++++++++ Documentation/networking/sfp-phylink.rst | 35 ++-- 3 files changed, 246 insertions(+), 24 deletions(-) create mode 100644 Documentation/networking/pcs.rst diff --git a/Documentation/networking/index.rst b/Documentation/networking/= index.rst index 44a422ad3b05..3fce8f6ac089 100644 --- a/Documentation/networking/index.rst +++ b/Documentation/networking/index.rst @@ -28,6 +28,7 @@ Contents: net_failover page_pool phy + pcs sfp-phylink alias bridge diff --git a/Documentation/networking/pcs.rst b/Documentation/networking/pc= s.rst new file mode 100644 index 000000000000..2cae70231948 --- /dev/null +++ b/Documentation/networking/pcs.rst @@ -0,0 +1,234 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PCS Subsystem +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The PCS (Physical Coding Sublayer) subsystem handles the registration and = lookup +of PCS devices. These devices contain the upper sublayers of the Ethernet +physical layer, generally handling framing, scrambling, and encoding tasks= . PCS +devices may also include PMA (Physical Medium Attachment) components. PCS +devices transfer data between the Link-layer MAC device, and the rest of t= he +physical layer, typically via a serdes. The output of the serdes may be +connected more-or-less directly to the medium when using fiber-optic or +backplane connections (1000BASE-SX, 1000BASE-KX, etc). It may also communi= cate +with a separate PHY (such as over SGMII) which handles the connection to t= he +medium (such as 1000BASE-T). + +Remark on usage of .mac_select_pcs and fw_node PCS +-------------------------------------------------- + +There are generally two ways to look up a PCS device. + +1. MAC OP struct .mac_select_pcs (considered deprecated) +2. Internal PCS handling with ``num_possible_pcs`` and ``fill_available_pc= s`` + +Implementation 1 leaves the entire handling of the PCS to the MAC +driver with the selection of the PCS driven by .mac_select_pcs. +Custom implementations are required if the PCS is external to the MAC +and needs to be handled by a separate driver. + +Implementation 2 makes the phylink core code to select the PCS +provided by ``num_possible_pcs`` and ``fill_available_pcs`` either +via internal MAC handling or firmware node (fwnode) + +Implementation 1 is considered deprecated and it's suggested to +switch to implementation 2 and where possible switch to firmware +node design. + +.. _pcs_fwnode: + +Looking up PCS Devices (fwnode implementation) +----------------------------------------------- + +The lookup of a PCS device follows the common producer/consumer implementa= tion +used by similar subsystems with a ``#pcs-cells`` on the producer and a +``pcs-handle`` property on the consumer:: + + pcs: pcs { + // ... + #pcs-cells =3D <0>; + }; + + ethernet-controller { + // ... + pcs-handle =3D <&pcs>; + }; + +On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs`` +value and ``fill_available_pcs`` helper function in +:c:struct:`phylink_config` to compose the list of available PCS that can be +used for the phylink instance. + +Phylink will then internally handle the selection of the correct PCS for +the requested interface mode based on the interface modes configured in +``pcs_interfaces`` in :c:struct:`phylink_config` struct and +``supported_interfaces`` in :c:struct:`phylink_pcs` struct. + +A PCS is considered eligible when the requested interface mode is present +in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and +``supported_interfaces`` in :c:struct:`phylink_pcs` struct. + +``supported_interfaces`` describes all interface modes supported by the MA= C, +whereas ``pcs_interfaces`` identifies the subset that require PCS selectio= n. + +For the special implementation where the PCS is internal or part of the MAC +and a dedicated driver is not needed, it's possible to leave the implement= ation +of the PCS to the MAC driver and just implement the ``num_possible_pcs`` +value and ``fill_available_pcs`` helper function in +:c:struct:`phylink_config` referencing the local :c:struct:`phylink_pcs` +struct allocated from the MAC driver. + +.. _pcs_consumer: + +Using PCS Devices +----------------- + +It's mandatory to either implement the ``mac_select_pcs`` callback +of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_availabl= e_pcs`` +of :c:struct:`phylink_config` to use a PCS for a MAC. + +The fwnode implementation exposes simple helpers to parse the PCS from +the fwnode :c:func:`fwnode_phylink_pcs_count` and +:c:func:`fwnode_phylink_pcs_parse`. The :c:func:`fwnode_phylink_pcs_count`= helper +takes the fwnode where the ``pcs-handle`` should be parsed and return the +number of PCS entries described in the fwnode. +The :c:func:`fwnode_phylink_pcs_parse` helper takes three arguments, +the fwnode where the ``pcs-handle`` should be parsed, an allocated array +of :c:struct:`phylink_pcs` pointer where to put the parsed PCS from the fw= node +and the maximum number of PCS to parse. +Contrary to :c:func:`fwnode_phylink_pcs_count`, :c:func:`fwnode_phylink_pc= s_parse` +helper fills the allocated array with ONLY the available PCS and return the +number of available PCS found. PCS that returns -ENODEV will be skipped and +won't be inserted in the allocated array. + +A phylink instance may use multiple PCS devices. The maximum number is rep= orted +through ``num_possible_pcs``. + +It's mandatory to specify for what interface a PCS is needed. This can be = done +by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct. +If the requested interface mode is not present in this bitmask, phylink do= es +not search for a PCS for that specific mode. (example MAC doesn't need a = PCS +for SGMII but require one for USXGMII) + +With the use of the :c:func:`fwnode_phylink_pcs_parse` a common implementa= tion +is the following:: + + static int mac_fill_available_pcs(struct phylink_config *config, + struct phylink_pcs **available_pcs, + unsigned int num_possible_pcs) + { + struct device *dev =3D config->dev; + + return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs, + num_possible_pcs); + } + + static int mac_setup_phylink(struct net_device *netdev) + { + struct phylink_config *config; + + // ... + + config->dev =3D &netdev->dev; + + // ... + + // Parse possible PCS and fill num_possible_pcs. + config->num_possible_pcs =3D fwnode_phylink_pcs_count(dev_fwnode(&ne= tdev->dev)); + config->fill_available_pcs =3D mac_fill_available_pcs; + + __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces= ); + __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces); + + // PCS required only for USXGMII + __set_bit(PHY_INTERFACE_MODE_USXGMII, config->pcs_interfaces); + + phylink =3D phylink_create(config, //... + +It's worth to mention that it's phylink code that takes care of allocating +the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs`` +callback based on the value set in ``num_possible_pcs`` for +:c:struct:`phylink_config` struct. + +The ``fill_available_pcs`` callback must not write more than +``num_possible_pcs`` entries. The third argument may be used to validate +that there is enough space to fill all the available PCS in the passed arr= ay +of :c:struct:`phylink_pcs` pointer. + +The ``fill_available_pcs`` callback is called only on :c:func:`phylink_cre= ate` +and is used only to compose the initial available PCS list. Ownership of P= CS +is held by phylink. + +.. _pcs_producer: + +Writing PCS Drivers +------------------- + +To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then, +register your PCS in your probe function using :c:func:`fwnode_pcs_add_pro= vider`. +The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode wh= ere +the PCS provider should be registered to, a xlate function to return the r= equested +PCS based on ``#pcs-cells`` and a pointer to reference private data for th= e xlate +function. + +The PCS will then be registered to a global list of PCS provider that the +PCS fwnode implementation will use to parse it. + +For the simple case where the PCS driver expose a single PCS, +:c:func:`fwnode_pcs_simple_xlate` can be used as the xlate function. + +You must call :c:func:`fwnode_pcs_del_provider` from your remove function +on driver detach. + +A devm variant, :c:func:`devm_fwnode_pcs_add_provider`, is available to +automatically release the PCS provider on driver detach. + +It's worth to mention that xlate function MUST reference already allocated +:c:struct:`phylink_pcs` pointer and MUST NOT dynamically allocate new PCS. +The returned pointer is used to identify the PCS across provider lookup and +removal notifications. + +Late PCS registration handling +------------------------------ + +It's possible that a PCS becomes available after the MAC finished probing. +Contrary to the usual producer/consumer implementation, when a PCS is not +registered and can't be found, the fwnode parser helper returns ``-ENODEV`` +instead of ``-EPROBE_DEFER``. + +This is to prevent race condition with particular devices that register +MAC and PCS with USB or PCIe and require the MAC to be registered before +the PCS. + +The phylink logic correctly handle this special case and keep the phylink +instance in a fail condition. + +The PCS fwnode implementation provides a notifier to which each phylink +instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config` +registers. When a new PCS provider is registered, the notifier is called +triggering the :c:func:`pcs_provider_notify` function. + +Function :c:func:`pcs_provider_notify` will check if the just added PCS +should be used by the phylink instance. If it should be used then, +it's added to the internal list of available PCS and a phylink major +config is forced. + +If a phylink instance was in a failure state, with the just added PCS +now part of the available PCS internal phylink list, provided all other +conditions are satisfied, the configuration is retried and the failure +condition is cleared. + +API Reference +------------- + +.. kernel-doc:: include/linux/phylink.h + :identifiers: phylink_pcs + +.. kernel-doc:: include/linux/pcs/pcs.h + :internal: + +.. kernel-doc:: include/linux/pcs/pcs-provider.h + :internal: diff --git a/Documentation/networking/sfp-phylink.rst b/Documentation/netwo= rking/sfp-phylink.rst index 5bf285d73e8a..306505118eba 100644 --- a/Documentation/networking/sfp-phylink.rst +++ b/Documentation/networking/sfp-phylink.rst @@ -311,33 +311,20 @@ this documentation. =20 priv->pcs =3D lynx_pcs_create_mdiodev(bus, 0); =20 - Some PCS can be recovered based on firmware information: + PCS that should be recovered based on firmware information should impl= ement + the external PCS as a :ref:`PCS provider ` and reference= it + with the use of PCS fwnode helper :ref:`PCS fwnode helper = `. =20 - .. code-block:: c - - priv->pcs =3D lynx_pcs_create_fwnode(of_fwnode_handle(node)); - -12. Populate the :c:func:`mac_select_pcs` callback and add it to your - :c:type:`struct phylink_mac_ops ` set of ops. This fu= nction - must return a pointer to the relevant :c:type:`struct phylink_pcs ` - that will be used for the requested link configuration: - - .. code-block:: c - - static struct phylink_pcs *foo_select_pcs(struct phylink_config *c= onfig, - phy_interface_t interfac= e) - { - struct foo_priv *priv =3D container_of(config, struct foo_= priv, - phylink_config); - - if ( /* 'interface' needs a PCS to function */ ) - return priv->pcs; +12. Populate the :c:var:`num_possible_pcs` value and + :c:func:`fill_available_pcs` callback and add it to your + :c:type:`struct phylink_config `. =20 - return NULL; - } + Refer to :ref:`Documentation/networking/pcs.rst ` for + further details and examples. =20 - See :c:func:`mvpp2_select_pcs` for an example of a driver that has mul= tiple - internal PCS. + Notice that the previous implementation of populating + :c:func:`mac_select_pcs` is considered deprecated in favor of the new + described above. =20 13. Fill-in all the :c:type:`phy_interface_t ` (i.e. all = MAC to PHY link modes) that your MAC can output. The following example shows a --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F021474274 for ; Tue, 1 Sep 2026 08:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251439; cv=none; b=TBhYFyzOK5oOZ5VDrggTKiGcsEaInxWyxzqpJd6d/6X1XO4Vio2y5vFxj2GN9BPlmEzYxvqDoBaaD+8HOHLGDqkzaaRAATNH46THQvEf8hvZEA0rSZ/x8C4PH1WIcDCSSyl2J4eVOK4+X6LhScKkQWoJGlKP+kR4OHIl/WLBxN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251439; c=relaxed/simple; bh=DlPWvl7VPmpyoxjPLEXDDFgGlZBGBcqWJsRTiZvvGGY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hv4HchU8uxOYtQW1BtoMTT9H8UDDpvrS84et5LYVHwkr43tVLwT4eNFolovs2Y53eB0d8bnpzJHVI28fpfrAIBbSzBjkdHp11P+mAd5ujFibq1jGC2xJpRuVglq9gEZXxkajIoojCrImGBxZw/uaVvFrrFRkMShB33hjJBZnftc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jNALetWt; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jNALetWt" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-49ccfbe062eso23056505e9.3 for ; Tue, 01 Sep 2026 01:30:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251435; x=1788856235; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=winUkNgWZKpQ2EAEJkwIhIBpCcK8DMcWRELm0nMiNB0=; b=jNALetWtYGBgk4UmMQ3NXZNE2x5Ewkx4DpUYN5vLTrdK8qmV7H7m2F5RKtdfbKX59T vbCu0l6wjvVTMjzlr7bW6W5iMnXX2POAcQZ3Hum4Hwr4FyqL0wlfmz+R7HL5h45xaVv2 23LtcWRWR7FgGrFSwllD5QFlmwQTw6LBEe2zW6vfesk1KhI2vVdrCJalRIGZXEvtxtxA Rv/+/LrC7kKb2SX4bEZdjY+q+GdWaas0hOgwYBqAnHoIsX9EBrRt5Pi2hb1Yg5tNSZQ1 v+AEnlhIfr4zCpVwx81TuDdiW11DZN0h4dAHPS19eKxVV8YyhlZgyyRbZSUfHbErU6Xd m88w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251435; x=1788856235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=winUkNgWZKpQ2EAEJkwIhIBpCcK8DMcWRELm0nMiNB0=; b=lMLOWb85s+9QU0ZIY6mfFDiREi+ic/nEMdNfg0OXhM0ha4ch1IqSO3ltt9H06vyaDS yXHpQfpsFBD40XjmBtfJmjqY3fXZg+CzySG2mgLljUaGhlzxbnZ9lY6nH7Cox93uTGcV t8RAZ0PvLtgEG9ZVC1o8wHTVX1LdJM1f/wANi7NLt7AIdb5+pkWCrXEQnmg9UbjXprss dDof8+kV/7knk9PHAOG6qJksEzw2I7KAyNksG3uyYT8aJxhAxtaNbcJHCuT+TCiY6tUS 3MVk1xhIz0L5Y7hYZNqS/zI0CyEF5Wk5/be3UAcsiQLAhrePvIXm5rP1g812lzDFrPNb jXFA== X-Forwarded-Encrypted: i=1; AHgh+RqyxtFTh6QibLWoIG+daOVsDrLmoE7oujlktWPY1ZQo3cqZZn/ua7CVZZxlcj7/G32HWw4sBF8R4rUOBgI=@vger.kernel.org X-Gm-Message-State: AFuF++kWfxZDuovbgljcHTID8dCJ/AxvS+qW/9YCp6AKKLm5pHlBz5aJ ovCjGAriWqE2ZSusf6PNMW0/EII5MuS2K1h3pkbT6G4yVTzI/JoEeBAh X-Gm-Gg: AR+sD12k/mFYpJ2x76IrRrScWjq6GTxr20BX59D4AL6KVLpDR2bCdhQfSM1dUj5+q1v iqVIkTRWJpqcJ+bS6jsEjALsfyBcCKcWQcvuSeawplpCSiG5MPkwU72cVJc7fUADY6ER9h0VboP TmbCKMYFBrmypQLQjPWERNGJ+Yq0zr+ZzINuZ4gKrPkviHjgT8nUDHktj9dqWrVjenxl11SLG2Y gG3mOwGRfQ7N97I392bsB1Kdwgsbq8hr78HyjUU63S/IE+ObyEcgrgS9sB0WBH5NXn5XyIWlhDd MfJ/PpP/5+d9Q9kFcapRbttAecXET+zyDVL5xNvPCclD/IqVodrwZ0SAV8lQMRxRvW2R8LJDlqW GYQ5DGUBGGMOJRTCM+1EAiqhE6iR1pa0HdfLz84gOzTuckBBxI5QwPVqyyjHxonQiHafit7fX9X OdZZ+lxCYV6N9Xcm0IH7Jig/j43KUCcRj31K9K4SMJgRrpEuMpvE9gy8Ct+GA5xXT38fgJ9uCQU EvDcXhhQu0qFUubZeG5rOD9Z31PzQ/VVglt2rpbPclHIs1yjfvr X-Received: by 2002:a05:600c:19c8:b0:49b:c8e:a211 with SMTP id 5b1f17b1804b1-49b91c20bfamr493430315e9.5.1788251434958; Tue, 01 Sep 2026 01:30:34 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:34 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 08/12] MAINTAINERS: add myself as PCS subsystem maintainer Date: Tue, 1 Sep 2026 10:29:23 +0200 Message-ID: <20260901083001.8044-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" List all the files of the Ethernet PCS subsystem and add myself as maintainer. Signed-off-by: Christian Marangi --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0b42e898f4d8..1b4f79be5e54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9757,6 +9757,15 @@ F: include/uapi/linux/if_bridge.h F: include/linux/netfilter_bridge/ F: net/bridge/ =20 +ETHERNET PCS SUBSYSTEM +M: Christian Marangi +L: netdev@vger.kernel.org +S: Maintained +F: Documentation/networking/pcs.rst +F: drivers/net/pcs/pcs.c +F: include/linux/pcs/pcs-provider.h +F: include/linux/pcs/pcs.h + ETHERNET PHY LIBRARY M: Andrew Lunn M: Heiner Kallweit --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26BCE4749C6 for ; Tue, 1 Sep 2026 08:30:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251441; cv=none; b=sVZvBUTB+Tn6GoNIy8NjEZA8EebSkCb03rlB+LThQc1iacEsSbyBQTkjMUAZIKMO+Gb+yY+BvjIgm3n8bHkBToRwr1tRilhpgo6sfO+uJGyOvOLQT7466EDw5nYCZKKsmdU9ZdrRuG71nhGMVVpqjDRyme+a7Z6L8lc6+rtmR3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251441; c=relaxed/simple; bh=A+KcmemH3pMaAVs3lMVfxapvO9ST6yn6NewQtddz0kY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N73u0Sy6WrjxzXnw09UXd1QaPaDWor8zR1pLIAPea/AEDBZ/Xxw5OZ0yhDQKRk5btM5OIrgSGWBiophIArpMzHgccXDDkrIzi4CQfD55w4+5eyQenC1ALZ8ESbNHpIZFoYCT53k+E8ATo2CypxK/PkVd92X4ealzp+46EpI6GyQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=m/uPYQ/O; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="m/uPYQ/O" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-49b0d8bc2aaso6894585e9.0 for ; Tue, 01 Sep 2026 01:30:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251437; x=1788856237; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=1bFwMN34t/laBcuJvUM/XSHQIvcTBfIZ9zeEVi8dxW8=; b=m/uPYQ/ORunukT6fcky54EqVzE2Fsy+v2PILLZzk9hNYWq+ytMHxJMkT+eE01PZJx1 aeE/3zbRwv2N12mnnCPpxeQnbwZ3f9Br2XLnm4V0/QuSJuyryB1qm2by4NLac4nXUIay IkEyMZwYy+6hwmOj+07W3MvTc25YqBXq50Pj8+zAnpB0PROiWo5+ree7MhXdey2cjFij 5zLfxe3xOug1PbMkO7GDUCp8kkhSr7VSI4jM3E9EY4ImE/Hh06ZQkvLJZ48IV2NnMyT7 RsjTYsmO2Zq/bNzYbKjinC0+fsPg4SsvdXKMhs2qph7PpPAft/0jiRwhCtyW5A/DAYYr HDcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251437; x=1788856237; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=1bFwMN34t/laBcuJvUM/XSHQIvcTBfIZ9zeEVi8dxW8=; b=LWWPXx6cbAP6lOXsTf2CXD2eMEhFh6JB70ZTFl03qg60GEryzJdPVeeJ8XCdl7rt3H wsLoNKVGDOBVm/gqiM/VYGE57QPTk3ty69YfjwHCmUiimOfFvvFQ2G38fr4nAJ+vATIZ vLLHU9a3DqRh853QZYbERXS0+iNMathbD2ICEL8h3I4e2HF5DuMo1PaNki7zVUO1fNDt OANf/68gDocuWYqlCmFBs9gkH6b+CXDbZljHElaW3oqul/2RzO90B/LxLYK1SCvZakx3 kaGzzzKTKVhsJMi0C9n02zwLErl4kVhUnHvCQD+iKWxEFCfF7meTJxRfWDtzzwRu/aaY AvEg== X-Forwarded-Encrypted: i=1; AHgh+RpuKOAy0QqtWAA/Gv4aE03wO7CaSw0+OIwxU9alJxtV9+Z0Vs6WNUNRWWCcbS0UT1ZKFDqEzxYZH1mlb9Q=@vger.kernel.org X-Gm-Message-State: AFuF++nRnDOBBjG75THRs5l2bFn3cNHPa95xt8td2vgQ7MFhr/EFikbw 6ahW9o2O4lOZDr9yt7xhfq1VoiG8i6T73L9Q/C0ag2RL62iDYuCGg0U0 X-Gm-Gg: AR+sD13h1sQy86BuGNDmKtyejwkyRTmydFlPdId7JhwB/GhVAu3s04GM+VdF3BA6i9v c5kq8RSFfYJbXwyyocSK6ZVdCc8VbX1AAA07F/HVl0pvjcD0MvcItoa6BsfMUQAsTWDP5zNml4y mrGCUkafa9xn6Ma0Qv54ZvNFy/JTnd9b0jBfEgHXhdPfGsPiVcwuHgKJ8Oh3CZSCovKmS9H22S4 MOCQxFIqWTBYh7PynsdYDPoaHF6vpc8/rB+JPaUTId5ab/tzYScTV9m5mLNlA52WV8j784FGOas H6LZoEiwnVQ1tYL8H22+338olzEylPFulUB6y0ulFuQPN2hFRS/7qNVPKP928uq3+hiP6uF9EeR WhpIkEsSxi1bn2ly4m66IUvcSwh8hwIyyZd6dlDgfkMt31F5QS3RAEJf5YRXH+eYvkRRP6G4Drc WNK3kdAwS8QRBeH5Q87aU4X/BwLQTY73Q8nYZm9mDgnkoM9uRqKd5PQxwgk55Gav404Um1PzsBS lswF/j8rTk1CVol4wYnfCNTqjK8UNkzIzXK+fuAG/u9u58AoYVt X-Received: by 2002:a05:600c:529a:b0:49c:cedc:3c36 with SMTP id 5b1f17b1804b1-49ccedc3cafmr333314475e9.16.1788251437016; Tue, 01 Sep 2026 01:30:37 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:36 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 09/12] net: phylink: add .pcs_link_down PCS OP Date: Tue, 1 Sep 2026 10:29:24 +0200 Message-ID: <20260901083001.8044-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Permit for PCS driver to define specific operation to tear down the link between the MAC and the PCS. This might be needed for some PCS that reset counter or require special reset to correctly work if the link needs to be restored later. On phylink_link_down() call, the additional phylink_pcs_link_down() will be called after .mac_link_down to tear down the link. PCS driver will need to define .pcs_link_down to make use of this. Signed-off-by: Christian Marangi Reviewed-by: Maxime Chevallier --- drivers/net/phy/phylink.c | 9 +++++++++ include/linux/phylink.h | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index a68d77ba5728..e5706b008b39 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -989,6 +989,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pc= s, unsigned int neg_mode, pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex); } =20 +static void phylink_pcs_link_down(struct phylink_pcs *pcs) +{ + if (pcs && pcs->ops->pcs_link_down) + pcs->ops->pcs_link_down(pcs); +} + static void phylink_pcs_disable_eee(struct phylink_pcs *pcs) { if (pcs && pcs->ops->pcs_disable_eee) @@ -1701,6 +1707,9 @@ static void phylink_link_down(struct phylink *pl) =20 pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode, pl->cur_interface); + + phylink_pcs_link_down(pl->pcs); + phylink_info(pl, "Link is Down\n"); } =20 diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 2c647238c7ce..87dc0f27dfc0 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -528,6 +528,7 @@ struct phylink_pcs { * @pcs_an_restart: restart 802.3z BaseX autonegotiation. * @pcs_link_up: program the PCS for the resolved link configuration * (where necessary). + * @pcs_link_down: tear down link between MAC and PCS. * @pcs_disable_eee: optional notification to PCS that EEE has been disabl= ed * at the MAC. * @pcs_enable_eee: optional notification to PCS that EEE will be enabled = at @@ -555,6 +556,7 @@ struct phylink_pcs_ops { void (*pcs_an_restart)(struct phylink_pcs *pcs); void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode, phy_interface_t interface, int speed, int duplex); + void (*pcs_link_down)(struct phylink_pcs *pcs); void (*pcs_disable_eee)(struct phylink_pcs *pcs); void (*pcs_enable_eee)(struct phylink_pcs *pcs); int (*pcs_pre_init)(struct phylink_pcs *pcs); @@ -690,6 +692,16 @@ void pcs_an_restart(struct phylink_pcs *pcs); void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, phy_interface_t interface, int speed, int duplex); =20 +/** + * pcs_link_down() - tear down link between MAC and PCS + * @pcs: a pointer to a &struct phylink_pcs. + * + * This call will be made just after mac_link_down() to inform the PCS the + * link has gone down. PCS should be configured to stop processing packets + * for transmission and reception. + */ +void pcs_link_down(struct phylink_pcs *pcs); + /** * pcs_disable_eee() - Disable EEE at the PCS * @pcs: a pointer to a &struct phylink_pcs --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA7674746AE for ; Tue, 1 Sep 2026 08:30:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251444; cv=none; b=j5LpKA0cHp+e7cK+Ao6fMi+g728N7aKFo3DsEbAfb3MlvmhyHs+ifheTXi8GD/1lme3hCd4PZy59l6RTmC5aCjqzG08lhq0O2qtjQO21vI37pe6OrGjxtdUMe+XOjwVI+kF2KF3kN780ZSjmXoXbdzUBlGFjMREwDud4hmprfd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251444; c=relaxed/simple; bh=q8erQ5YercewkjFj31D9or1Mr6d1F3WoS0ksnOd7MtM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KpogiVu/ZnMbSTDoypZPkg0j9Jr8hJBhAJ1fkv2HD8W0OAFnn564J0gCzfWL/W3dWtUGQmWXmzLteJ3p0dBYczbCAxqqxEE4Gm40F4yUWJMnIOUgfGxkqog1aaOfL9VjVIa9COIAGDGBHt7VNIWKxv1FegYfmpnApiyCQ0k1WnE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ElFpoRca; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ElFpoRca" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-48442ea8f59so347252f8f.1 for ; Tue, 01 Sep 2026 01:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251440; x=1788856240; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=FLNBnsANrTUMdnBcC9IapvMl8huqE7Ah/L99fobP8RQ=; b=ElFpoRcaE2Gips4xzcDVkVIgniYTfcL4gzSkviW+U9afZZUJxY2SaH+9wIjP3jRCQH QLboUTK+KPgYahP4twwJqMXk0Rmyvr7716LjAczFtzOMCo0rdN5OySJLu+wYPu861NK9 rl/LmMcSuR3cr4QHHUqaYWmUIspcY9PVuQ8zKOV0JfbLtdE/TI3g8vrpHbHM7S+ILkPZ pMeDPp2wtwTqSdiwSEyT7Wt6CaU5wPG3vPYZhtvLNImcTZeGevmwz6NVnHEeWnVc29bd 9LJM82nHtNWijF7X/8MXXTtwdZSGmSIwuSlg089H9o1zFSAQpD4wB5Gu/6ceO2s99JD5 Z3KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251440; x=1788856240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=FLNBnsANrTUMdnBcC9IapvMl8huqE7Ah/L99fobP8RQ=; b=oE10lr27el9M98l69xDKZmVrUP3F53BpwV7aV7hudz+XcMYDOWybJib2a/+hXspB5s 0eWBSAQXjxLH+boQR9Kwe4KQvaT5xTCt1zBJ476qjvN4J+WqD4lMwIn9W2S+INTr28UG 4DQbiClE17eoMweUkThmCJkL9bbeIETDT0TuEYf8S2kjyS+gwXbIG54bNw8e/I7exzbR T/ZGe144lytv23PX8pqVsADYO3TKU0bzNvFrXzb1h0J4if0boRkWswAOnDyxHkeU+KCZ IV3HaOnTMrA/JhZKtMH8UoCDqlb+WNPFbRXCgK4Lp1HiBb38iq3mH2LecuJC2ZJblzA5 /ISA== X-Forwarded-Encrypted: i=1; AHgh+RrQssbqVr6BrfR09s1pJLNNhuwJ+dJbXIwG2V+gKJ+Khe93K5Qu9izRdgslJ9b9WrW9Q1gNoa+GOLkuLok=@vger.kernel.org X-Gm-Message-State: AFuF++kWZK1oaC251FBa+hoB1M4Musb4kh59UZie3soFrhNIm79UY7AE RP9BkOtV7hBv/Tqhko7ATrSSWKJxBcHYtVXBLIYQfMG85vRgKfJSoRnZ X-Gm-Gg: AR+sD11qnLM7eT/d74AGinprIsAitSdK6dpG8IiDqtjTycQENkGmzi8PfbgqdIPZl05 OyUfC6hxAghFIwPQZflfBHkBRYdFZXEp4iLYFx44WBQUt39ObbjUe/H9CqgpAVWObYQMrUm8ukO zFyTgYOaC1aj4GVUSdkkjk7x/mb0cRVB9mRDIe4kklA91VobdEF3wUseB+1cGT/J+e396kYCCgx JA9AM1R4523gcCxfUbRMsnMHi1/4DB2K+LTut6ws1Yl436N1GmRcnZPRss4rzRRXnz+3AqCh/zT OGUtaSpF0rFle2ddt/T2LclZAL1OtReDFv4f1j9Ya0ywtAHhnjhaw8s+WRq+dAKWR2bhXhgwvNv 6PIVsfulKQcIHz9RKEPFujBbkhvZZzmznxzLafGAF6IhtXKjqtfbADcILpE0jUWnF7ZqfLzitaW pYGdtywPbK533yKfB5H/Gq8SR30X7Yy7BHIWgD4XnoVwgEK6ak1SOip1yGIAONu25K6GeqhlqGJ SobxXGWDniyAu7uwfYrPKF/FXcz6pJeW+6TvY7wI1mM+yg36b+7 X-Received: by 2002:a05:600c:4e4c:b0:49b:e22:4ee4 with SMTP id 5b1f17b1804b1-49cdd416ef1mr58000585e9.4.1788251439577; Tue, 01 Sep 2026 01:30:39 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:38 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 10/12] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Date: Tue, 1 Sep 2026 10:29:25 +0200 Message-ID: <20260901083001.8044-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Airoha Ethernet PCS for AN7581 SoC. Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for the various Serdes port supporting different Media Independent Interface (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII). This follow the new PCS provider with the use of #pcs-cells property. Signed-off-by: Christian Marangi --- .../bindings/net/pcs/airoha,pcs.yaml | 261 ++++++++++++++++++ 1 file changed, 261 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.ya= ml diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Do= cumentation/devicetree/bindings/net/pcs/airoha,pcs.yaml new file mode 100644 index 000000000000..9c1d116c1b01 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml @@ -0,0 +1,261 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Ethernet PCS and Serdes + +maintainers: + - Christian Marangi + +description: + Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for + the various Serdes port supporting different Media Independent Interface + (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII). + +properties: + compatible: + enum: + - airoha,an7581-pcs-eth + - airoha,an7581-pcs-pon + - airoha,an7581-pcs-pcie + - airoha,an7581-pcs-usb + + reg: + minItems: 6 + maxItems: 15 + + reg-names: + minItems: 6 + maxItems: 15 + + airoha,scu: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the SCU node required to configure + the serdes line to the correct interface mode. + + phys: + maxItems: 1 + + "#pcs-cells": true + +required: + - compatible + - reg + - reg-names + - "#pcs-cells" + +allOf: + - if: + properties: + compatible: + contains: + enum: + - airoha,an7581-pcs-eth + - airoha,an7581-pcs-pon + + then: + properties: + reg: + items: + - description: PCS MAC reg + - description: HSGMII AN reg + - description: HSGMII PCS reg + - description: MULTI SGMII reg + - description: USXGMII reg + - description: HSGMII rate adaption reg + - description: PCS Analog register + - description: PCS PMA (Physical Medium Attachment) register + + reg-names: + items: + - const: pcs_mac + - const: hsgmii_an + - const: hsgmii_pcs + - const: multi_sgmii + - const: usxgmii + - const: hsgmii_rate_adp + - const: pcs_ana + - const: pcs_pma + + phys: false + + "#pcs-cells": + const: 0 + + required: + - airoha,scu + + - if: + properties: + compatible: + contains: + const: airoha,an7581-pcs-pcie + + then: + properties: + reg: + items: + - description: PCS MAC 0 reg + - description: HSGMII AN 0 reg + - description: HSGMII PCS 0 reg + - description: MULTI SGMII 0 reg + - description: USXGMII 0 reg + - description: HSGMII rate adaption 0 reg + - description: PCS MAC 1 reg + - description: HSGMII AN 1 reg + - description: HSGMII PCS 1 reg + - description: MULTI SGMII 1 reg + - description: USXGMII 1 reg + - description: HSGMII rate adaption 1 reg + - description: PCS Analog register + - description: PCS PMA (Physical Medium Attachment) 0 register + - description: PCS PMA (Physical Medium Attachment) 1 register + + reg-names: + items: + - const: pcs_mac0 + - const: hsgmii_an0 + - const: hsgmii_pcs0 + - const: multi_sgmii0 + - const: usxgmii0 + - const: hsgmii_rate_adp0 + - const: pcs_mac1 + - const: hsgmii_an1 + - const: hsgmii_pcs1 + - const: multi_sgmii1 + - const: usxgmii1 + - const: hsgmii_rate_adp1 + - const: pcs_ana + - const: pcs_pma0 + - const: pcs_pma1 + + phys: false + + "#pcs-cells": + const: 1 + + required: + - airoha,scu + + - if: + properties: + compatible: + contains: + const: airoha,an7581-pcs-usb + + then: + properties: + reg: + items: + - description: PCS MAC reg + - description: HSGMII AN reg + - description: HSGMII PCS reg + - description: MULTI SGMII reg + - description: HSGMII rate adaption reg + - description: PCS Analog register + + reg-names: + items: + - const: pcs_mac + - const: hsgmii_an + - const: hsgmii_pcs + - const: multi_sgmii + - const: hsgmii_rate_adp + - const: pcs_ana + + airoha,scu: false + + "#pcs-cells": + const: 0 + + required: + - phys + +additionalProperties: false + +examples: + - | + #include + + pcs@1fa08000 { + compatible =3D "airoha,an7581-pcs-pon"; + reg =3D <0x1fa08000 0x1000>, + <0x1fa80000 0x60>, + <0x1fa80a00 0x164>, + <0x1fa84000 0x450>, + <0x1fa85900 0x338>, + <0x1fa86000 0x300>, + <0x1fa8a000 0x1000>, + <0x1fa8b000 0x1000>; + reg-names =3D "pcs_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "pcs_ana", "pcs_pma"; + + airoha,scu =3D <&scuclk>; + #pcs-cells =3D <0>; + }; + + pcs@1fa09000 { + compatible =3D "airoha,an7581-pcs-eth"; + reg =3D <0x1fa09000 0x1000>, + <0x1fa70000 0x60>, + <0x1fa70a00 0x164>, + <0x1fa74000 0x450>, + <0x1fa75900 0x338>, + <0x1fa76000 0x300>, + <0x1fa7a000 0x1000>, + <0x1fa7b000 0x1000>; + reg-names =3D "pcs_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "pcs_ana", "pcs_pma"; + + airoha,scu =3D <&scuclk>; + #pcs-cells =3D <0>; + }; + + pcs@1fa04000 { + compatible =3D "airoha,an7581-pcs-pcie"; + reg =3D <0x1fa04000 0x1000>, + <0x1fa50000 0x60>, + <0x1fa50a00 0x164>, + <0x1fa54000 0x450>, + <0x1fa55900 0x338>, + <0x1fa56000 0x300>, + <0x1fa05000 0x1000>, + <0x1fa60000 0x60>, + <0x1fa60a00 0x164>, + <0x1fa64000 0x450>, + <0x1fa65900 0x338>, + <0x1fa66000 0x300>, + <0x1fa5a000 0x1000>, + <0x1fa5b000 0x1000>, + <0x1fa5c000 0x1000>; + reg-names =3D "pcs_mac0", "hsgmii_an0", "hsgmii_pcs0", + "multi_sgmii0", "usxgmii0", + "hsgmii_rate_adp0", + "pcs_mac1", "hsgmii_an1", "hsgmii_pcs1", + "multi_sgmii1", "usxgmii1", + "hsgmii_rate_adp1", + "pcs_ana", "pcs_pma0", "pcs_pma1"; + + airoha,scu =3D <&scuclk>; + #pcs-cells =3D <1>; + }; + + pcs@1fa07000 { + compatible =3D "airoha,an7581-pcs-usb"; + reg =3D <0x1fa07000 0x1000>, + <0x1fa90000 0x60>, + <0x1fa90a00 0x164>, + <0x1fa94000 0x450>, + <0x1fa96000 0x300>, + <0x1fa9a000 0x600>; + reg-names =3D "pcs_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "hsgmii_rate_adp","pcs_ana"; + + phys =3D <&usb0_phy PHY_TYPE_USB3>; + + #pcs-cells =3D <0>; + }; --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20F9A47208F for ; Tue, 1 Sep 2026 08:30:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251457; cv=none; b=p6R4FmO0bj+542DBP2IOj00IYdvuR3hF9lXOzSrICn+1fDtnCSUhYe7bZL2P9qXjCFaKIHg3mbhhzxMvvSwFypESK+CJDlUaoQJ4J/kwJr28sz6vJo4yRvF+D6GtIKO0Bo+J1FJbW62KbMLmZIx2GzGIqJAWdn0J8I7gXsKVapM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251457; c=relaxed/simple; bh=QefjnYuy85Z8rbyYLO2IRmCF3LITecHztc9upE9bceI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oOUOxQQPpCWTz9dLDuMg3mnj0GCcS/U8kYJCbEMFLayeWHPmB4bwu5bJMJHq+1bYULIt7NfRnyZPnwuUgtI5tofuZyaYy2QW4UkUZ83+zdNTCI/y8aelkcxQjE5yJwAIHxh6J18FvV1/vkDcG+OiBx98tG43OBKI37eZx4pkeRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Gp6lJMbP; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Gp6lJMbP" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-49557167508so47698755e9.1 for ; Tue, 01 Sep 2026 01:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251444; x=1788856244; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=xaRUaSSkDf8Xr5Xzf+EME9APYOOSbcSP3a70XDxPN4I=; b=Gp6lJMbPliOczrKoa8xM5DE0fcJZEIxQjVKb1di6lULyY3ZnGESA/vjhYn6U2lnN6c Uns3XpWQO7Kq/ldS2QFGkMr+9u/8/qxeEyKhjYU5oIx5rxMS+jgqJjqjW+gB/nZ326r5 JmEGPuaY97XcZXTOn0U2jvuaii13myLprt9RuvJuH/G74uYBRO+EERE/sR3M7HDVFNK/ ySSXhBWhYajkuRiLxkPufe7sZy4ORFkc4LGAVC9RXmepIbabcVl+ffImbZ4EqD2D//3v K4ydpCPi1TzpGVRl1IHT1/aB2bF/GKf429ZbZXXFHFkcKurhR6TLqiI+Hfn7/KH4/RpH IIBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251444; x=1788856244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=xaRUaSSkDf8Xr5Xzf+EME9APYOOSbcSP3a70XDxPN4I=; b=XJ3xUkawv43AabZX2oiOQyc1t/dGnxFmcMSZO5YQZCu2kooSTmTv/vIt29uAnjiS1g 1rC06qGkdl/j5hlUL6J+CE5u97Zpb2v02iiLJsMLoqJ8na8U/AAlSsTVD852r8VYA9ra Ll9av4FaHUZN9oXEDPEk9TTQSmfhhONFj7OB/Qdh+17dJEQ5gCsXdvEIarrbQ4fKuM52 7mVpTkWtpGWC6iFbtVVsAAPZzz39SV7OUwJaMcmmkwwrwB2phRqCJi8cFKxuO4zBf3LK de9Q/KBnaCZFC7+ZexU/tA0p1Q0k5W9k/XHPpbqfkBq8ekKq3+E7jDOMztVeH6e8u3BF 3maQ== X-Forwarded-Encrypted: i=1; AHgh+RrN7P8+Gg5595mvQaXp7UFuJL3jQNjKP91DNih/CIG1PtUXgLEsKIUA0LbYmk+PO9LdCb0y0B9qXdzXHMk=@vger.kernel.org X-Gm-Message-State: AFuF++lYtxAcLSEwAr8iiSVjVwjaWSvdGoZYYoo0XyF87l6BEFknlbJo hMfnOEl7MXabwaIBFnrh0wNaVvhD0RFx2oXugdltIbXGrokNPNwjZbQt X-Gm-Gg: AR+sD10Gki1iz5tauo+5CWPGikzBb7ccga2METCkSRPQAoRt1z/LcO6sF0moBz6eyAW S0hMk1VD2PNNINQAYWCCFAbIsUzHkIGiwM0Kn/WhJAxfcZ+8fcn6a8Q7lU068D6r1zZqor61Utl RNJZsMtbnDo/Wv9XQxcb9Us7LfARSbBNi30Hh7jmsIuWOp85iuiqsqPBdqSLzzp4hQ8Wg1fj4eR npi1LUuYkIeEYZDQb0MUz27ixPzFiWvSm9guvK9Cfl8TIdwiIw+SG0sp97sMz2F+KOAHTW9rXpu x3cbZLndXzoc41l8LlNiSl6M+PWQVJQnTkbtIsyy+v+67M92PuGGOvg0itAkPF225y69E8basUf VxMv7pafBJ6PdGvn6Pej8o+dvfcpnEYgrnK/mVMr/nV8YseXD9ms1NbpDgcfrud2/TV/T7Uc1GP RUNlQKwysX5Zom17CjBMKeEVrpeTJk/d53tKryV1VAKqYAr92YoTwwT4ludPLSm2yw4NIRQnwnx yPrOYC7LoHrPNhcxjllvKG2tfKFVkpmMj5NGiYtFqN4xecFid0j X-Received: by 2002:a05:600c:3b2a:b0:49c:cee0:e7c1 with SMTP id 5b1f17b1804b1-49cdc57d1d1mr100892795e9.16.1788251442646; Tue, 01 Sep 2026 01:30:42 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:41 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 11/12] net: pcs: airoha: add PCS driver for Airoha AN7581 SoC Date: Tue, 1 Sep 2026 10:29:26 +0200 Message-ID: <20260901083001.8044-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCS driver for Airoha AN7581 SoC for Ethernet/PON/PCIe/USB SERDES and permit usage of external PHY or connected SFP cage. Supported modes are USXGMII, 10G-BASER, 2500BASE-X, 1000BASE-X and SGMII. The driver probe and register the various needed registers and register as a PCS provider for fwnode usage. Signed-off-by: Christian Marangi --- drivers/net/pcs/Kconfig | 2 + drivers/net/pcs/Makefile | 2 + drivers/net/pcs/airoha/Kconfig | 13 + drivers/net/pcs/airoha/Makefile | 7 + drivers/net/pcs/airoha/pcs-airoha-common.c | 1303 ++++++++++++ drivers/net/pcs/airoha/pcs-airoha.h | 1311 ++++++++++++ drivers/net/pcs/airoha/pcs-an7581.c | 2100 ++++++++++++++++++++ 7 files changed, 4738 insertions(+) create mode 100644 drivers/net/pcs/airoha/Kconfig create mode 100644 drivers/net/pcs/airoha/Makefile create mode 100644 drivers/net/pcs/airoha/pcs-airoha-common.c create mode 100644 drivers/net/pcs/airoha/pcs-airoha.h create mode 100644 drivers/net/pcs/airoha/pcs-an7581.c diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index ba2caec866a5..8fae619f2432 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -41,4 +41,6 @@ config PCS_RZN1_MIIC Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to RMII/RGMII, or can be set in pass-through mode for MII. =20 +source "drivers/net/pcs/airoha/Kconfig" + endmenu diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index 3005cdd89ab7..91593aa8d926 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -9,3 +9,5 @@ obj-$(CONFIG_PCS_XPCS) +=3D pcs_xpcs.o obj-$(CONFIG_PCS_LYNX) +=3D pcs-lynx.o obj-$(CONFIG_PCS_MTK_LYNXI) +=3D pcs-mtk-lynxi.o obj-$(CONFIG_PCS_RZN1_MIIC) +=3D pcs-rzn1-miic.o + +obj-$(CONFIG_PCS_AIROHA) +=3D airoha/ diff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig new file mode 100644 index 000000000000..1aa4c0d33b87 --- /dev/null +++ b/drivers/net/pcs/airoha/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PCS_AIROHA + tristate + select FWNODE_PCS + +config PCS_AIROHA_AN7581 + tristate "Airoha AN7581 PCS driver" + depends on ARCH_AIROHA || COMPILE_TEST + select PCS_AIROHA + help + This module provides helper to phylink for managing the Airoha + AN7581 PCS for SoC Ethernet and PON SERDES. diff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makef= ile new file mode 100644 index 000000000000..c5201d5cc356 --- /dev/null +++ b/drivers/net/pcs/airoha/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PCS_AIROHA) :=3D pcs-airoha.o +pcs-airoha-objs :=3D pcs-airoha-common.o +ifdef CONFIG_PCS_AIROHA_AN7581 +pcs-airoha-objs +=3D pcs-an7581.o +endif diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/a= iroha/pcs-airoha-common.c new file mode 100644 index 000000000000..d9ec0e97b746 --- /dev/null +++ b/drivers/net/pcs/airoha/pcs-airoha-common.c @@ -0,0 +1,1303 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcs-airoha.h" + +static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 xsi_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + xsi_sel =3D AIROHA_SCU_ETH_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + xsi_sel =3D AIROHA_SCU_ETH_XSI_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSR3, + AIROHA_SCU_ETH_XSI_SEL, + xsi_sel); +} + +static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 xsi_sel, wan_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + wan_sel =3D AIROHA_SCU_WAN_SEL_SGMII; + xsi_sel =3D AIROHA_SCU_PON_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_2500BASEX: + wan_sel =3D AIROHA_SCU_WAN_SEL_HSGMII; + xsi_sel =3D AIROHA_SCU_PON_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + wan_sel =3D AIROHA_SCU_WAN_SEL_USXGMII; + xsi_sel =3D AIROHA_SCU_PON_XSI_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSTR, + AIROHA_SCU_PON_XSI_SEL, + xsi_sel); + + regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF, + AIROHA_SCU_WAN_SEL, + wan_sel); +} + +static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + u32 xsi_sel; + + if (index =3D=3D 0) { + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + xsi_sel =3D AIROHA_SCU_PCIE_XSI0_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + xsi_sel =3D AIROHA_SCU_PCIE_XSI0_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSTR, + AIROHA_SCU_PCIE_XSI0_SEL, + xsi_sel); + } else { + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + xsi_sel =3D AIROHA_SCU_PCIE_XSI1_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + xsi_sel =3D AIROHA_SCU_PCIE_XSI1_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSTR, + AIROHA_SCU_PCIE_XSI1_SEL, + xsi_sel); + } +} + +static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + const struct airoha_pcs_match_data *data =3D priv->data; + int ret; + + switch (data->port_type) { + case AIROHA_PCS_ETH: + airoha_pcs_setup_scu_eth(priv, interface); + break; + case AIROHA_PCS_PON: + airoha_pcs_setup_scu_pon(priv, interface); + break; + case AIROHA_PCS_PCIE: + airoha_pcs_setup_scu_pcie(priv, index, interface); + break; + case AIROHA_PCS_USB: + break; + } + + ret =3D reset_control_bulk_assert(ARRAY_SIZE(priv->rsts), + priv->rsts); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts), + priv->rsts); + if (ret) + return ret; + + return 0; +} + +static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int inde= x) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + + regmap_set_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + /* Disable Hibernation */ + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1, + AIROHA_PCS_USXGMII_SPEED_SEL_H); + + /* FIXME: wait Airoha */ + /* Avoid PCS sending garbage to MAC in some HW revision (E0) */ + regmap_write(maps->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0); +} + +static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + + regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_TBI_10B_MODE, + priv->phy ? 0 : AIROHA_PCS_TBI_10B_MODE); +} + +static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv, int index) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + + regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_TBI_10B_MODE); + + regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CT= RL_6, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707)= ); + + regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CT= RL_8, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff)); +} + +static void airoha_pcs_init(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + airoha_pcs_init_sgmii(priv, index); + break; + case PHY_INTERFACE_MODE_2500BASEX: + airoha_pcs_init_hsgmii(priv, index); + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + airoha_pcs_init_usxgmii(priv, index); + break; + default: + return; + } +} + +static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv, + int index) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + + /* Disable every interrupt */ + regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INT= ERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT); + + /* Clear interrupt */ + regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTER= RUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR); + + regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INT= ERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR); +} + +static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv, + int index) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + + /* Disable every Interrupt */ + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0, + AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN); + + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1, + AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN | + AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN); + + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2, + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN); + + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3, + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN | + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN | + AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN | + AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN); + + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4, + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN); + + /* Clear any pending interrupt */ + regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2, + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT | + AIROHA_PCS_USXGMII_R_TYPE_E_INT | + AIROHA_PCS_USXGMII_R_TYPE_T_INT | + AIROHA_PCS_USXGMII_R_TYPE_D_INT); + + regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3, + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT | + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT | + AIROHA_PCS_USXGMII_LINK_UP_ST_INT | + AIROHA_PCS_USXGMII_HI_BER_ST_INT); + + regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4, + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT); + + /* Interrupt saddly seems to be not weel supported for Link Down. + * PCS Poll is a must to correctly read and react on Cable Deatch + * as only cable attach interrupt are fired and Link Down interrupt + * are fired only in special case like AN restart. + */ +} + +static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + return airoha_pcs_interrupt_init_sgmii(priv, index); + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + return airoha_pcs_interrupt_init_usxgmii(priv, index); + default: + return; + } +} + +static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv, + unsigned int neg_mode, int index, + struct phylink_link_state *state) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + u32 bmsr =3D 0, lpa =3D 0; + + regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1, + &bmsr); + regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5, + &lpa); + + bmsr =3D (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE | + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT | + AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY | + AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr; + lpa =3D AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa; + + phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa); +} + +static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int = index, + struct phylink_link_state *state) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + u32 bmsr =3D 0; + + regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1, + &bmsr); + + bmsr =3D (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE | + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT | + AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY | + AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr; + + state->link =3D !!(bmsr & BMSR_LSTATUS); + state->an_complete =3D !!(bmsr & BMSR_ANEGCOMPLETE); + state->speed =3D SPEED_2500; + state->duplex =3D DUPLEX_FULL; +} + +static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv, int= index, + struct phylink_link_state *state) +{ + const struct airoha_pcs_match_data *data =3D priv->data; + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + u32 an_done =3D 0, lpa =3D 0; + + /* Trigger HW workaround if needed. If an error is reported, + * consider link down and test again later. + */ + if (data->rxlock_workaround && data->rxlock_workaround(priv, index)) { + state->link =3D false; + return; + } + + /* Toggle AN Status */ + regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6, + AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS); + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6, + AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS); + + regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa); + regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_2, &an_don= e); + + state->link =3D !!(lpa & MDIO_USXGMII_LINK); + state->an_complete =3D !!(an_done & AIROHA_PCS_USXGMII_PCS_AN_COMPLETE); + + phylink_decode_usxgmii_word(state, lpa); +} + +static void airoha_pcs_get_state_10gbaser(struct airoha_pcs_priv *priv, in= t index, + struct phylink_link_state *state) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + u32 status =3D 0, curr_mode =3D 0; + + /* Toggle AN Status */ + regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6, + AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS); + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6, + AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS); + + regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_= 1, + &status); + regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &curr_m= ode); + + state->link =3D !!(status & AIROHA_PCS_USXGMII_RX_LINK_STUS); + + switch (curr_mode & AIROHA_PCS_USXGMII_CUR_USXGMII_MODE) { + case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G: + state->speed =3D SPEED_10000; + break; + case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G: + state->speed =3D SPEED_5000; + break; + case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G: + state->speed =3D SPEED_2500; + break; + default: + state->speed =3D SPEED_UNKNOWN; + return; + } + + state->duplex =3D DUPLEX_FULL; +} + +static void airoha_pcs_get_state(struct phylink_pcs *pcs, + unsigned int neg_mode, + struct phylink_link_state *state) +{ + struct airoha_pcs_port *port =3D to_airoha_pcs_port(pcs); + struct airoha_pcs_priv *priv =3D port->priv; + + switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + airoha_pcs_get_state_sgmii(priv, neg_mode, port->index, state); + break; + case PHY_INTERFACE_MODE_2500BASEX: + airoha_pcs_get_state_hsgmii(priv, port->index, state); + break; + case PHY_INTERFACE_MODE_USXGMII: + airoha_pcs_get_state_usxgmii(priv, port->index, state); + break; + case PHY_INTERFACE_MODE_10GBASER: + airoha_pcs_get_state_10gbaser(priv, port->index, state); + break; + default: + return; + } +} + +static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mod= e, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct airoha_pcs_port *port =3D to_airoha_pcs_port(pcs); + struct airoha_pcs_priv *priv =3D port->priv; + const struct airoha_pcs_match_data *data; + struct airoha_pcs_maps *maps; + int index =3D port->index; + u32 rate_adapt; + int ret; + + maps =3D &priv->maps[port->index]; + port->interface =3D interface; + data =3D priv->data; + + /* Apply Analog and Digital configuration for PCS */ + if (data->bringup) { + ret =3D data->bringup(priv, index, interface); + if (ret) + return ret; + } + + /* Set final configuration for various modes */ + airoha_pcs_init(priv, index, interface); + + /* Configure Interrupt for various modes */ + airoha_pcs_interrupt_init(priv, index, interface); + + rate_adapt =3D AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN; + + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) + rate_adapt |=3D AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS; + + /* AN Auto Settings (Rate Adaptation) */ + regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CT= RL_0, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt); + + if (interface =3D=3D PHY_INTERFACE_MODE_USXGMII || + interface =3D=3D PHY_INTERFACE_MODE_10GBASER) { + if (interface =3D=3D PHY_INTERFACE_MODE_USXGMII) { + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) + regmap_set_bits(maps->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_ENABLE); + else + regmap_clear_bits(maps->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_ENABLE); + + regmap_clear_bits(maps->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7, + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE); + } else { + regmap_clear_bits(maps->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_ENABLE); + + regmap_set_bits(maps->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7, + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE); + } + } + + /* Clear any force bit that my be set by bootloader */ + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII || + interface =3D=3D PHY_INTERFACE_MODE_1000BASEX || + interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) { + regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CT= RL_0, + AIROHA_PCS_LINK_MODE_P0 | + AIROHA_PCS_FORCE_SPD_MODE_P0 | + AIROHA_PCS_FORCE_LINKDOWN_P0 | + AIROHA_PCS_FORCE_LINKUP_P0); + } + + /* Toggle Rate Adaption for SGMII/HSGMII mode */ + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII || + interface =3D=3D PHY_INTERFACE_MODE_1000BASEX || + interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) { + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) + regmap_clear_bits(maps->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0, + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE); + else + regmap_set_bits(maps->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0, + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE); + } + + /* Setup AN Link Timer */ + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII || + interface =3D=3D PHY_INTERFACE_MODE_1000BASEX) { + u32 an_timer; + + an_timer =3D phylink_get_link_timer_ns(interface); + + /* Value needs to be shifted by 4, seems value is internally * 16 */ + regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11, + AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER, + FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER, + an_timer >> 4)); + + regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3, + AIROHA_PCS_HSGMII_PCS_LINK_STSTIME, + FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME, + an_timer >> 4)); + } + + /* Setup SGMII AN and advertisement in DEV_ABILITY */ + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + int advertise =3D phylink_mii_c22_pcs_encode_advertisement(interface, + advertising); + if (advertise < 0) + return advertise; + + regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4, + AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY, + FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY, + advertise)); + + regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + } else { + regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + } + } + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) { + regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + + regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_TX_ENABLE); + } + + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII || + interface =3D=3D PHY_INTERFACE_MODE_1000BASEX) { + u32 if_mode =3D AIROHA_PCS_HSGMII_AN_SIDEBAND_EN; + + /* Toggle SGMII or 1000base-x mode */ + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) + if_mode |=3D AIROHA_PCS_HSGMII_AN_SGMII_EN; + + if (neg_mode & PHYLINK_PCS_NEG_INBAND) + regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS); + else + regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS); + + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + /* Clear force speed bits and MAC mode */ + regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 | + AIROHA_PCS_HSGMII_PCS_MAC_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT); + } else { + /* Enable compatibility with MAC PCS Layer */ + if_mode |=3D AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN; + + /* AN off force rate adaption, speed is set later in Link Up */ + regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_MAC_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT); + } + + regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode); + + regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_TX_ENABLE | + AIROHA_PCS_HSGMII_PCS_MODE2_EN); + } + + if (interface =3D=3D PHY_INTERFACE_MODE_1000BASEX && + neg_mode !=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_SGMII_SEND_AN_ERR_EN); + + regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE= _CL37, + AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE); + } + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) { + regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY); + } + + /* Configure Flow Control on XFI */ + regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN, + permit_pause_to_mac ? + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN : + 0); + + return 0; +} + +static void airoha_pcs_an_restart(struct phylink_pcs *pcs) +{ + struct airoha_pcs_port *port =3D to_airoha_pcs_port(pcs); + struct airoha_pcs_priv *priv =3D port->priv; + struct airoha_pcs_maps *maps; + + maps =3D &priv->maps[port->index]; + + switch (port->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART); + udelay(3); + regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART); + break; + case PHY_INTERFACE_MODE_USXGMII: + regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_RESTART); + udelay(3); + regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_RESTART); + break; + default: + return; + } +} + +static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_m= ode, + phy_interface_t interface, int speed, int duplex) +{ + struct airoha_pcs_port *port =3D to_airoha_pcs_port(pcs); + struct airoha_pcs_priv *priv =3D port->priv; + const struct airoha_pcs_match_data *data; + struct airoha_pcs_maps *maps; + + maps =3D &priv->maps[port->index]; + data =3D priv->data; + + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + regmap_update_bits(maps->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) | + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0)); + udelay(1); + regmap_update_bits(maps->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) | + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5)); + } + } else { + if (interface =3D=3D PHY_INTERFACE_MODE_USXGMII || + interface =3D=3D PHY_INTERFACE_MODE_10GBASER) { + u32 mode; + u32 rate_adapt; + + switch (speed) { + case SPEED_10000: + rate_adapt =3D AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000; + mode =3D AIROHA_PCS_USXGMII_MODE_10000; + break; + case SPEED_5000: + rate_adapt =3D AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000; + mode =3D AIROHA_PCS_USXGMII_MODE_5000; + break; + case SPEED_2500: + rate_adapt =3D AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500; + mode =3D AIROHA_PCS_USXGMII_MODE_2500; + break; + case SPEED_1000: + rate_adapt =3D AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000; + mode =3D AIROHA_PCS_USXGMII_MODE_1000; + break; + case SPEED_100: + rate_adapt =3D AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100; + mode =3D AIROHA_PCS_USXGMII_MODE_100; + break; + default: + /* Not supported */ + return; + } + + /* Force USXGMII to selected speed */ + regmap_update_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL= _7, + AIROHA_PCS_USXGMII_MODE, mode); + + if (interface =3D=3D PHY_INTERFACE_MODE_10GBASER) + regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT= _CTRL_11, + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN | + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN | + rate_adapt); + } + + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII || + interface =3D=3D PHY_INTERFACE_MODE_1000BASEX) { + u32 force_speed; + u32 rate_adapt; + + switch (speed) { + case SPEED_1000: + force_speed =3D AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000; + rate_adapt =3D AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000; + break; + case SPEED_100: + force_speed =3D AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100; + rate_adapt =3D AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100; + break; + case SPEED_10: + force_speed =3D AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10; + rate_adapt =3D AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10; + break; + default: + /* Not supported */ + return; + } + + regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, + force_speed | rate_adapt); + } + + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII || + interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) { + u32 ck_gen_mode; + u32 speed_reg; + u32 if_mode; + + switch (speed) { + case SPEED_2500: + speed_reg =3D AIROHA_PCS_LINK_MODE_P0_2_5G; + break; + case SPEED_1000: + speed_reg =3D AIROHA_PCS_LINK_MODE_P0_1G; + if_mode =3D AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000; + ck_gen_mode =3D AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000; + break; + case SPEED_100: + speed_reg =3D AIROHA_PCS_LINK_MODE_P0_100M; + if_mode =3D AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100; + ck_gen_mode =3D AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100; + break; + case SPEED_10: + speed_reg =3D AIROHA_PCS_LINK_MODE_P0_10M; + if_mode =3D AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10; + ck_gen_mode =3D AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10; + break; + } + + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_= 13, + AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, + if_mode); + + regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MO= DE_FORCE, + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL, + ck_gen_mode | + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL); + } + + regmap_update_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_= CTRL_0, + AIROHA_PCS_LINK_MODE_P0 | + AIROHA_PCS_FORCE_SPD_MODE_P0, + speed_reg | + AIROHA_PCS_FORCE_SPD_MODE_P0); + } + } + + if (data->link_up) + data->link_up(priv, port->index); + + /* BPI BMI enable */ + regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); +} + +static void airoha_pcs_link_down(struct phylink_pcs *pcs) +{ + struct airoha_pcs_port *port =3D to_airoha_pcs_port(pcs); + struct airoha_pcs_priv *priv =3D port->priv; + struct airoha_pcs_maps *maps; + + maps =3D &priv->maps[port->index]; + + /* MPI MBI disable */ + regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); +} + +static void airoha_pcs_pre_config(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + struct airoha_pcs_port *port =3D to_airoha_pcs_port(pcs); + struct airoha_pcs_priv *priv =3D port->priv; + struct airoha_pcs_maps *maps; + + maps =3D &priv->maps[port->index]; + + /* Select HSGMII or USXGMII in SCU regs */ + airoha_pcs_setup_scu(priv, port->index, interface); + + /* MPI MBI disable */ + regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); + + /* Write 1 to trigger reset and clear */ + regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST, + AIROHA_PCS_XFI_MAC_LOGIC_RST); + regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST, + AIROHA_PCS_XFI_MAC_LOGIC_RST); + + usleep_range(1000, 2000); + + /* Clear XFI MAC counter */ + regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR, + AIROHA_PCS_XFI_GLB_CNT_CLR); +} + +static int airoha_pcs_post_config(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + struct airoha_pcs_port *port =3D to_airoha_pcs_port(pcs); + struct airoha_pcs_priv *priv =3D port->priv; + struct airoha_pcs_maps *maps; + + maps =3D &priv->maps[port->index]; + + /* Frag disable */ + regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RX_FRAG_LEN, + FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31)); + regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FRAG_LEN, + FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31)); + + /* IPG NUM */ + regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_IPG_NUM, + FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10)); + + return 0; +} + +static unsigned int airoha_pcs_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE; +} + +static const struct phylink_pcs_ops airoha_pcs_ops =3D { + .pcs_inband_caps =3D airoha_pcs_inband_caps, + .pcs_pre_config =3D airoha_pcs_pre_config, + .pcs_post_config =3D airoha_pcs_post_config, + .pcs_get_state =3D airoha_pcs_get_state, + .pcs_config =3D airoha_pcs_config, + .pcs_an_restart =3D airoha_pcs_an_restart, + .pcs_link_up =3D airoha_pcs_link_up, + .pcs_link_down =3D airoha_pcs_link_down, +}; + +static int airoha_pcs_init_named_regmap(struct platform_device *pdev, + const char *name, struct regmap **regmap) +{ + struct regmap_config config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + }; + void __iomem *base; + + base =3D devm_platform_ioremap_resource_byname(pdev, name); + if (IS_ERR(base)) + return PTR_ERR(base); + + config.name =3D name; + *regmap =3D devm_regmap_init_mmio(&pdev->dev, base, &config); + + return PTR_ERR_OR_ZERO(*regmap); +} + +static int airoha_pcs_alloc_maps(struct platform_device *pdev, + struct airoha_pcs_priv *priv) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[0]; + int ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pc= s); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgm= ii_rate_adp); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sg= mii); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "usxgmii", &maps->usxgmii_pcs); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "pcs_pma", &priv->pcs_pma[0]); + if (ret) + return ret; + + return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana); +} + +static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev, + struct airoha_pcs_priv *priv) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[0]; + int ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pc= s); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgm= ii_rate_adp); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sg= mii); + if (ret) + return ret; + + return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana); +} + +static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev, + struct airoha_pcs_priv *priv) +{ + struct airoha_pcs_maps *maps =3D priv->maps; + int ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "pcs_mac0", &maps[0].pcs_mac); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_an0", &maps[0].hsgmii_= an); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs0", &maps[0].hsgmii= _pcs); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp0", &maps[0].h= sgmii_rate_adp); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "multi_sgmii0", &maps[0].multi= _sgmii); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "usxgmii0", &maps[0].usxgmii_p= cs); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "pcs_mac1", &maps[1].pcs_mac); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_an1", &maps[1].hsgmii_= an); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs1", &maps[1].hsgmii= _pcs); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp1", &maps[1].h= sgmii_rate_adp); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "multi_sgmii1", &maps[1].multi= _sgmii); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "usxgmii1", &maps[1].usxgmii_p= cs); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "pcs_pma0", &priv->pcs_pma[0]); + if (ret) + return ret; + + ret =3D airoha_pcs_init_named_regmap(pdev, "pcs_pma1", &priv->pcs_pma[1]); + if (ret) + return ret; + + return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana); +} + +static struct phylink_pcs *airoha_pcs_xlate(struct fwnode_reference_args *= pcsspec, + void *data) +{ + struct airoha_pcs_priv *priv =3D data; + struct device *dev =3D priv->dev; + u64 index =3D 0; + + switch (priv->data->port_type) { + case AIROHA_PCS_ETH: + case AIROHA_PCS_PON: + case AIROHA_PCS_USB: + if (pcsspec->nargs) { + dev_err(dev, "invalid number of cells in 'pcs-handle' property\n"); + return ERR_PTR(-EINVAL); + } + + break; + case AIROHA_PCS_PCIE: + if (pcsspec->nargs !=3D 1) { + dev_err(dev, "invalid number of cells in 'pcs-handle' property\n"); + return ERR_PTR(-EINVAL); + } + + break; + } + + if (pcsspec->nargs) + index =3D pcsspec->args[0]; + + if (index >=3D priv->data->num_port) { + dev_err(dev, "invalid index cell in 'pcs-handle' property\n"); + return ERR_PTR(-EINVAL); + } + + return &priv->ports[index].pcs; +} + +static int airoha_pcs_probe(struct platform_device *pdev) +{ + const struct airoha_pcs_match_data *data; + struct fwnode_pcs_provider *pcs_provider; + struct device *dev =3D &pdev->dev; + struct airoha_pcs_priv *priv; + int index, ret; + + data =3D of_device_get_match_data(dev); + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ports =3D devm_kcalloc(dev, data->num_port, + sizeof(*priv->ports), GFP_KERNEL); + if (!priv->ports) + return -ENOMEM; + + priv->dev =3D dev; + priv->data =3D data; + + if (data->port_type =3D=3D AIROHA_PCS_USB) { + struct phy *phy; + + phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "failed to get phy\n"); + + priv->phy =3D phy; + } + + switch (data->port_type) { + case AIROHA_PCS_ETH: + case AIROHA_PCS_PON: + ret =3D airoha_pcs_alloc_maps(pdev, priv); + if (ret) + return ret; + + break; + case AIROHA_PCS_PCIE: + ret =3D airoha_pcs_pcie_alloc_maps(pdev, priv); + if (ret) + return ret; + + break; + case AIROHA_PCS_USB: + ret =3D airoha_pcs_usb_alloc_maps(pdev, priv); + if (ret) + return ret; + + break; + } + + if (data->alloc_regmap_fields) { + ret =3D data->alloc_regmap_fields(priv); + if (ret) + return ret; + } + + /* SCU is used to toggle XFI or HSGMII in global SoC registers */ + if (!priv->phy) { + priv->scu =3D syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu"= ); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + } + + priv->rsts[0].id =3D "mac"; + priv->rsts[1].id =3D "phy"; + ret =3D devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(pr= iv->rsts), + priv->rsts); + if (ret) + return dev_err_probe(dev, ret, "failed to get bulk reset lines\n"); + + /* For Ethernet PCS, read the AN7581 SoC revision to check if + * manual rx calibration is needed. This is only limited to + * any SoC revision before E2. + */ + if (device_is_compatible(dev, "airoha,an7581-pcs-eth")) { + u32 val; + + ret =3D regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val); + if (ret) + return ret; + + if (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) < 0x2) + priv->manual_rx_calib =3D true; + } + + for (index =3D 0; index < data->num_port; index++) { + struct airoha_pcs_port *port =3D &priv->ports[index]; + + port->priv =3D priv; + port->index =3D index; + port->pcs.poll =3D true; + port->pcs.ops =3D &airoha_pcs_ops; + + switch (data->port_type) { + case AIROHA_PCS_ETH: + case AIROHA_PCS_PON: + case AIROHA_PCS_PCIE: + __set_bit(PHY_INTERFACE_MODE_10GBASER, + port->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_USXGMII, + port->pcs.supported_interfaces); + fallthrough; + case AIROHA_PCS_USB: + __set_bit(PHY_INTERFACE_MODE_SGMII, + port->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, + port->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + port->pcs.supported_interfaces); + break; + } + } + + platform_set_drvdata(pdev, priv); + + pcs_provider =3D devm_fwnode_pcs_add_provider(dev, dev_fwnode(dev), + airoha_pcs_xlate, priv); + if (IS_ERR(pcs_provider)) + return PTR_ERR(pcs_provider); + + return 0; +} + +static const struct airoha_pcs_match_data an7581_pcs_eth =3D { + .num_port =3D 1, + .port_type =3D AIROHA_PCS_ETH, + .alloc_regmap_fields =3D an7581_pcs_alloc_regmap_fields, + .bringup =3D an7581_pcs_bringup, + .link_up =3D an7581_pcs_phya_link_up, + .rxlock_workaround =3D an7581_pcs_rxlock_workaround, +}; + +static const struct airoha_pcs_match_data an7581_pcs_pon =3D { + .num_port =3D 1, + .port_type =3D AIROHA_PCS_PON, + .alloc_regmap_fields =3D an7581_pcs_alloc_regmap_fields, + .bringup =3D an7581_pcs_bringup, + .link_up =3D an7581_pcs_phya_link_up, +}; + +static const struct airoha_pcs_match_data an7581_pcs_pcie =3D { + .num_port =3D 2, + .port_type =3D AIROHA_PCS_PCIE, + .alloc_regmap_fields =3D an7581_pcs_pcie_alloc_regmap_fields, + .bringup =3D an7581_pcs_bringup, + .link_up =3D an7581_pcs_phya_link_up, +}; + +static const struct airoha_pcs_match_data an7581_pcs_usb =3D { + .num_port =3D 1, + .port_type =3D AIROHA_PCS_USB, + .bringup =3D an7581_pcs_usb_bringup, +}; + +static const struct of_device_id airoha_pcs_of_table[] =3D { + { .compatible =3D "airoha,an7581-pcs-eth", .data =3D &an7581_pcs_eth }, + { .compatible =3D "airoha,an7581-pcs-pon", .data =3D &an7581_pcs_pon }, + { .compatible =3D "airoha,an7581-pcs-pcie", .data =3D &an7581_pcs_pcie }, + { .compatible =3D "airoha,an7581-pcs-usb", .data =3D &an7581_pcs_usb }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, airoha_pcs_of_table); + +static struct platform_driver airoha_pcs_driver =3D { + .driver =3D { + .name =3D "airoha-pcs", + .of_match_table =3D airoha_pcs_of_table, + }, + .probe =3D airoha_pcs_probe, +}; +module_platform_driver(airoha_pcs_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Airoha PCS driver"); +MODULE_AUTHOR("Christian Marangi "); diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/p= cs-airoha.h new file mode 100644 index 000000000000..8a76d51b5d2c --- /dev/null +++ b/drivers/net/pcs/airoha/pcs-airoha.h @@ -0,0 +1,1311 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include + +/* SCU*/ +#define AIROHA_SCU_PDIDR 0x5c +#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0) +#define AIROHA_SCU_WAN_CONF 0x70 +#define AIROHA_SCU_WAN_SEL GENMASK(7, 0) +#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0= x10) +#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, = 0x11) +#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL,= 0x12) +#define AIROHA_SCU_SSR3 0x94 +#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13) +#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_= SEL, 0x1) +#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_S= EL, 0x2) +#define AIROHA_SCU_SSTR 0x9c +#define AIROHA_SCU_PCIE_XSI0_SEL GENMASK(14, 13) +#define AIROHA_SCU_PCIE_XSI0_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_X= SI0_SEL, 0x1) +#define AIROHA_SCU_PCIE_XSI0_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XS= I0_SEL, 0x2) +#define AIROHA_SCU_PCIE_XSI1_SEL GENMASK(12, 11) +#define AIROHA_SCU_PCIE_XSI1_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_X= SI1_SEL, 0x1) +#define AIROHA_SCU_PCIE_XSI1_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XS= I1_SEL, 0x2) +#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9) +#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_= SEL, 0x1) +#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_S= EL, 0x2) + +/* XFI_MAC */ +#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0 +#define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22) +#define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17) +#define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10) +#define AIROHA_PCS_XFI_TX_FC_EN BIT(5) +#define AIROHA_PCS_XFI_RX_FC_EN BIT(4) +#define AIROHA_PCS_XFI_RXMPI_STOP BIT(3) +#define AIROHA_PCS_XFI_RXMBI_STOP BIT(2) +#define AIROHA_PCS_XFI_TXMPI_STOP BIT(1) +#define AIROHA_PCS_XFI_TXMBI_STOP BIT(0) +#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10 +#define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0) +#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60 +#define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0) +#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64 +#define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0) +#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100 +#define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0) + +/* HSGMII_AN */ +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0 +#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY BIT(15) +#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */ +#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5) +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3) +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10 +#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */ +#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34 +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8) +#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5) +#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AI= ROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIR= OHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIRO= HA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0) +#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1) +#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60 +#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0) + +/* HSGMII_PCS */ +#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0 +#define AIROHA_PCS_TBI_10B_MODE BIT(30) +#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24) +#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12) +#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8 +#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0) +#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14 +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14) +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13) +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12) +#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8) +#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(= AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(A= IROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AI= ROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1) +#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0) +#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20 +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11) +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10) +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9) +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8) +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5) +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4) +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3) +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2) +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1) +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0) +#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24 +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST= (AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(= AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(A= IROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0) +#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104 +#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5) +#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0) +#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c +#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2) +#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0) + +/* HSGMII_ANA */ +#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6 0x18 +#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC BIT(20) +#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8 0x20 +#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0) +#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11 0x2c +#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED GENMASK(3, 2) +#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_P= CS_HSGMII_ANA_TPHY_SPEED, 0x0) +#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_= PCS_HSGMII_ANA_TPHY_SPEED, 0x1) +#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE GENMASK(1, 0) +#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18 0x48 +#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV GENMASK(28, 27) +#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19 0x4c +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK= (2, 0) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PRE= P_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK = FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK = FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK = FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSP= LL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONC= KBG, 0x4) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSP= LL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MO= NCKBG, 0x5) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIE= LD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_= 250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCK= BG, 0x7) +#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24 0x60 +#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24) +#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26 0x68 +#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(= AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(= AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST= (AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2) +#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST= (AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3) + +/* MULTI_SGMII */ +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14 +#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0) +#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18 +#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4) +#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_M= ODE_P0, 0x3) +#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MOD= E_P0, 0x2) +#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_M= ODE_P0, 0x1) +#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MO= DE_P0, 0x0) +#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2) +#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1) +#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100 +#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28) +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c +#define AIROHA_PCS_HSGMII_PCS_INT BIT(0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c +#define AIROHA_PCS_LINK_STS_P0 BIT(3) +#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0) +#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_ST= S_P0, 0x2) +#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_= STS_P0, 0x1) +#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_S= TS_P0, 0x0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448 +#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2) +#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1) +#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0) + +/* HSGMII_RATE_ADP */ +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6) +#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100 +#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31) + +/* USXGMII */ +#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0 +#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13) +#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x4 +#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS BIT(2) +#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP \ + FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x1) +#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_DOWN \ + FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x0) +#define AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1 0x30 +#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12) +#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3) +#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2) +#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0) +#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c +#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0 +#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4 +#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8 +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8 +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16) +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8) +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24) +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16) +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8) +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0 +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4 +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8 +#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8) +#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310 +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_= PCS_USXGMII_CUR_USXGMII_MODE, 0x0) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_P= CS_USXGMII_CUR_USXGMII_MODE, 0x1) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA= _PCS_USXGMII_CUR_USXGMII_MODE, 0x2) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_P= CS_USXGMII_CUR_USXGMII_MODE, 0x3) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA= _PCS_USXGMII_CUR_USXGMII_MODE, 0x4) +#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318 +#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c +#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320 +#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12) +#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8) +#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGM= II_MODE, 0x0) +#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMI= I_MODE, 0x1) +#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMI= I_MODE, 0x2) +#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMI= I_MODE, 0x3) +#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII= _MODE, 0x4) + +/* PMA_PHYA */ +#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0 +#define AIROHA_PCS_ANA_CMN_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4 +#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24) +#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16) +#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8) +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8 +#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24) +#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16) +#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8) +#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc +#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16) +#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8) +#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10 +#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16) +#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14 +#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 0x0 +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 0x1 +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 0x2 +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 0x3 +#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 0x0 +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 0x1 +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 0x2 +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 0x3 +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 0x1 +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 0x2 +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 0x3 +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 0x4 +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 0x5 +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 0x6 +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20 +#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT 0x0 +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM 0x1 +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM 0x2 +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM 0x3 +#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 0x0 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 0x1 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 0x2 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 0x3 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 0x4 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8) +#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 0x0 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 0x1 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 0x2 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 0x3 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 0x4 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 0x6 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16) +#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c +#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0) +#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 0x0 +#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 0x1 +#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30 +#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17) +#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8) +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3) +#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34 +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8) +#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38 +#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16) +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48 +#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16) +#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8) +#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO BIT(5) +#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50 +#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24) +#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16) +#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8) +#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54 +#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24) +#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16) +#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8) +#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58 +#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 0x0 +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 0x1 +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 0x2 +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3 +#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8) +#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64 +#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24) +#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 0x0 +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 0x1 +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 0x2 +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 0x3 +#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68 +#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 0x0 +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 0x1 +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 0x2 +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 0x3 +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24) +#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT 0x0 +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM 0x1 +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM 0x2 +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM 0x3 +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70 +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 0x0 +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 0x1 +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 0x2 +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 0x3 +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 0x4 +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74 +#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 0x0 +#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 0x1 +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 0x0 +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 0x1 +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 0x2 +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 0x3 +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 0x4 +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 0x6 +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78 +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27) +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24) +#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16) +#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c +#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8) +#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80 +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16) +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84 +#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94 +#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4 +#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24) +#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0 +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1 +#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4 +#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16) +#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28) +#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24) +#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20) +#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18) +#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16) +#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8 +#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24) +#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16) +#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8) +#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc +#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8) +#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0) +#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8 +#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8) +#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4 +#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24) +#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8 +#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16) +#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8) +#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc +#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16) +#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8) +#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c +#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24) +#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19) +#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16) +#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2) +#define AIROHA_PCS_ANA_CDR_PR_MONPI_EN BIT(1) +#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110 +#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24) +#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114 +#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16) +#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8) +#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118 +#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24) +#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16) +#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8) +#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c +#define AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120 +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS BIT(0) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS BIT(1) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS BIT(2) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS BIT(3) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS BIT(4) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS BIT(5) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS BIT(6) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS BIT(7) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH BIT(8) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS BIT(9) +#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c +#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8) +#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS BIT(0) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 BIT(1) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 BIT(2) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 BIT(3) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 BIT(4) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 BIT(5) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 BIT(6) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 BIT(7) +#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA BIT(8) +#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE BIT(9) +#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT BIT(10) +#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144 +#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148 +#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16) +#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8) +#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0) + +/* PMA_PHYA 2L */ +#define AIROHA_PCS_ANA_PXP_2L_CMN_EN 0x0 +#define AIROHA_PCS_ANA_2L_CMN_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN 0x4 +#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IOFST GENMASK(29, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IBIAS GENMASK(21, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_LPF_SHCK_EN BIT(8) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR 0x8 +#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWR GENMASK(28, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BP GENMASK(20, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BC GENMASK(12, 8) +#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BR GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC 0xc +#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_CODE GENMASK(23, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_OPTION BIT(8) +#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWC GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC 0x10 +#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KS GENMASK(17, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KF GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KFC GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE 0x14 +#define AIROHA_PCS_ANA_2L_JCPLL_POSTDIV_D5 BIT(24) +#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0) +#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_2 0x0 +#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_3 0x1 +#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_4 0x2 +#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_1 0x3 +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY 0x1c +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS GENMASK(25, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_23 0x0 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_21 0x1 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_19 0x2 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_15 0x3 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_EN BIT(16) +#define AIROHA_PCS_ANA_2L_JCPLL_PLL_RSTB BIT(8) +#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY GENMASK(2, 0) +#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_20_25 0x1 +#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_40_50 0x2 +#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_80_100 0x3 +#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_150_200 0x4 +#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_300_400 0x5 +#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_600_800 0x6 +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM 0x20 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_OUT BIT(24) +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD GENMASK(17, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_INT 0x0 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_1SDM 0x1 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_2SDM 0x2 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_3SDM 0x3 +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_MODE GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_IFM BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN 0x24 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_VREF GENMASK(28, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN GENMASK(18, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_2 0x0 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_4 0x1 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_6 0x2 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_8 0x3 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_10 0x4 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_EN BIT(8) +#define AIROHA_PCS_ANA_2L_JCPLL_SDM_HREN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN 0x28 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_0_5 0x0 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_1 0x1 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_2 0x2 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_4 0x3 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_8 0x4 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_16 0x6 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_EN BIT(16) +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV 0x2c +#define AIROHA_PCS_ANA_2L_JCPLL_VCO_SCAPWR GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_VCO_HALFLSB_EN BIT(16) +#define AIROHA_PCS_ANA_2L_JCPLL_VCO_CFIX GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV GENMASK(1, 0) +#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_1 0x0 +#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_2 0x1 +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR 0x30 +#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(18, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(10, 8) +#define AIROHA_PCS_ANA_2L_JCPLL_VCO_TCLVAR GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN 0x38 +#define AIROHA_PCS_ANA_2L_JCPLL_SSC_TRI_EN BIT(16) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1 0x3c +#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA GENMASK(31, 16) +#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA1 GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD 0x40 +#define AIROHA_PCS_ANA_2L_JCPLL_SSC_PERIOD GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN 0x4c +#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L GENMASK(31, 24) +#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PC= S_ANA_JCPLL_SPARE_L, BIT(5)) +#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF 0x50 +#define AIROHA_PCS_ANA_2L_JCPLL_TCL_KBAND_VREF GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN 0x54 +#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IBIAS GENMASK(29, 24) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST 0x58 +#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BP GENMASK(28, 24) +#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BC GENMASK(20, 16) +#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BR GENMASK(12, 8) +#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IOFST GENMASK(5, 0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR 0x5c +#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_CODE GENMASK(31, 24) +#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_OPTION BIT(16) +#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWC GENMASK(12, 8) +#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWR GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV 0x60 +#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KS GENMASK(25, 24) +#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KF GENMASK(17, 16) +#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KFC GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_DIV GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN 0x64 +#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_2 0x0 +#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_3 0x1 +#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_4 0x2 +#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_1 0x3 +#define AIROHA_PCS_ANA_2L_TXPLL_POSTDIV_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN 0x68 +#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_INTERNAL BIT(24) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV 0x6c +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_EN BIT(24) +#define AIROHA_PCS_ANA_2L_TXPLL_PLL_RSTB BIT(16) +#define AIROHA_PCS_ANA_2L_TXPLL_RST_DLY GENMASK(10, 8) +#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV GENMASK(1, 0) +#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_1 0x0 +#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_2 0x1 +#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_3 0x2 +#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_4 0x3 +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS 0x70 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD GENMASK(25, 24) +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_INT 0x0 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_1SDM 0x1 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_2SDM 0x2 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_3SDM 0x3 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_MODE GENMASK(17, 16) +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_IFM BIT(8) +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS GENMASK(1, 0) +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_23 0x0 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_21 0x1 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_19 0x2 +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_15 0x3 +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT 0x74 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2 0x0 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2_5 0x1 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_3 0x2 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_4 0x3 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_6 0x4 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_EN BIT(16) +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_HREN BIT(8) +#define AIROHA_PCS_ANA_2L_TXPLL_SDM_OUT BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF 0x78 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_EN BIT(24) +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_VREF GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW 0x7c +#define AIROHA_PCS_ANA_2L_TXPLL_VCO_HALFLSB_EN BIT(24) +#define AIROHA_PCS_ANA_2L_TXPLL_VCO_CFIX GENMASK(17, 16) +#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_1 0x0 +#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_2 0x1 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW GENMASK(2, 0) +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_0_5 0x0 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_1 0x1 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_2 0x2 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_4 0x3 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_8 0x4 +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_16 0x6 +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR 0x80 +#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(18, 16) +#define AIROHA_PCS_ANA_2L_TXPLL_VCO_TCLVAR GENMASK(10, 8) +#define AIROHA_PCS_ANA_2L_TXPLL_VCO_SCAPWR GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN 0x84 +#define AIROHA_PCS_ANA_2L_TXPLL_SSC_TRI_EN BIT(16) +#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PHASE_INI BIT(8) +#define AIROHA_PCS_ANA_2L_TXPLL_SSC_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1 0x88 +#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA GENMASK(31, 16) +#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA1 GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD 0x8c +#define AIROHA_PCS_ANA_2L_TXPLL_LDO_VCO_OUT GENMASK(25, 24) +#define AIROHA_PCS_ANA_2L_TXPLL_LDO_OUT GENMASK(17, 16) +#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PERIOD GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF 0x9c +#define AIROHA_PCS_ANA_2L_TXPLL_TCL_KBAND_VREF GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN 0xcc +#define AIROHA_PCS_ANA_2L_TX0_DMEDGEGEN_EN BIT(24) +#define AIROHA_PCS_ANA_2L_TX0_CKLDO_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN 0xe8 +#define AIROHA_PCS_ANA_2L_TX1_DMEDGEGEN_EN BIT(24) +#define AIROHA_PCS_ANA_2L_TX1_CKLDO_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL 0xf4 +#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FORCE BIT(24) +#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL BIT(16) +#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0 +#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1 +#define AIROHA_PCS_ANA_PXP_2L_RX0_REV_0 0xfc +#define AIROHA_PCS_ANA_2L_RX0_REV_1 GENMASK(31, 16) +#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28) +#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20) +#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18) +#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16) +#define AIROHA_PCS_ANA_2L_RX0_REV_0 GENMASK(15, 0) +#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12) +#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11) +#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10) +#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6) +#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4) +#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2) +#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1) +#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV 0x100 +#define AIROHA_PCS_ANA_2L_RX0_TDC_CK_SEL BIT(24) +#define AIROHA_PCS_ANA_2L_RX0_PHYCK_RSTB BIT(16) +#define AIROHA_PCS_ANA_2L_RX0_PHYCK_SEL GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_RX0_PHYCK_DIV GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV 0x104 +#define AIROHA_PCS_ANA_2L_CDR0_PD_EDGE_DIS BIT(8) +#define AIROHA_PCS_ANA_2L_CDR0_PD_PICAL_CKD8_INV BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO 0x110 +#define AIROHA_PCS_ANA_2L_CDR0_LPF_TOP_LIM GENMASK(26, 8) +#define AIROHA_PCS_ANA_2L_CDR0_LPF_RATIO GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE 0x11c +#define AIROHA_PCS_ANA_2L_CDR0_PR_INJ_FORCE_OFF BIT(24) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC 0x120 +#define AIROHA_PCS_ANA_2L_CDR0_PR_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_SEL GENMASK(19, 16) +#define AIROHA_PCS_ANA_2L_CDR0_PR_VCOADC_OS GENMASK(11, 8) +#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_DAC GENMASK(6, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL 0x124 +#define AIROHA_PCS_ANA_2L_CDR0_PR_FBKSEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_2L_CDR0_PR_DAC_BAND GENMASK(20, 16) +#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_CKBUF_VAL GENMASK(10, 8) +#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_IBAND_VAL GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN 0x130 +#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPR_EN BIT(24) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN 0x134 +#define AIROHA_PCS_ANA_2L_CDR0_PR_XFICK_EN BIT(8) +#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR 0x138 +#define AIROHA_PCS_ANA_2L_CDR0_PR_CAP_EN BIT(8) +#define AIROHA_PCS_ANA_2L_CDR0_PR_BUF_IN_SR GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON 0x13c +#define AIROHA_PCS_ANA_2L_RX0_DAC_MON GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN 0x140 +#define AIROHA_PCS_ANA_2L_RX0_SIGDET_PEAK GENMASK(25, 24) +#define AIROHA_PCS_ANA_2L_RX0_SIGDET_LPF_CTRL GENMASK(9, 8) +#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL 0x144 +#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ1_EN BIT(24) +#define AIROHA_PCS_ANA_2L_RX0_FE_EQ_HZEN BIT(16) +#define AIROHA_PCS_ANA_2L_RX0_SIGDET_VTH_SEL GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN 0x148 +#define AIROHA_PCS_ANA_2L_RX0_FE_VCM_GEN_PWDB BIT(16) +#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ3_EN BIT(8) +#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ2_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE 0x150 +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE GENMASK(17, 8) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2VOS BIT(0) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2IOS BIT(1) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1VOS BIT(2) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1IOS BIT(3) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2VOS BIT(4) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2IOS BIT(5) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1VOS BIT(6) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1IOS BIT(7) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_LVSH BIT(8) +#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_COMPOS BIT(9) +#define AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE 0x170 +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE GENMASK(19, 8) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_SAOS BIT(0) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP1 BIT(1) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP2 BIT(2) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP3 BIT(3) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP4 BIT(4) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP5 BIT(5) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP6 BIT(6) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP7 BIT(7) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_VGA BIT(8) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_CTLE BIT(9) +#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_ATT BIT(10) +#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ 0x17c +#define AIROHA_PCS_ANA_2L_RX0_DAC_E1_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_2L_RX0_DAC_E0_BYPASS_AEQ BIT(16) +#define AIROHA_PCS_ANA_2L_RX0_DAC_D1_BYPASS_AEQ BIT(8) +#define AIROHA_PCS_ANA_2L_RX0_DAC_D0_BYPASS_AEQ BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ 0x180 +#define AIROHA_PCS_ANA_2L_RX0_DAC_EYE_BYPASS_AEQ BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB 0x234 +#define AIROHA_PCS_ANA_2L_RX1_DAC_D0_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL 0x1ac +#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL_FORCE BIT(24) +#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL BIT(16) +#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0 +#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1 +#define AIROHA_PCS_ANA_PXP_2L_RX1_REV_0 0x1b4 +#define AIROHA_PCS_ANA_2L_RX1_REV_1 GENMASK(31, 16) +#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28) +#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20) +#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18) +#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16) +#define AIROHA_PCS_ANA_2L_RX1_REV_0 GENMASK(15, 0) +#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12) +#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11) +#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10) +#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6) +#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4) +#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2) +#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1) +#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV 0x1b8 +#define AIROHA_PCS_ANA_2L_RX1_TDC_CK_SEL BIT(24) +#define AIROHA_PCS_ANA_2L_RX1_PHYCK_RSTB BIT(16) +#define AIROHA_PCS_ANA_2L_RX1_PHYCK_SEL GENMASK(9, 8) +#define AIROHA_PCS_ANA_2L_RX1_PHYCK_DIV GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV 0x1bc +#define AIROHA_PCS_ANA_2L_CDR1_PD_EDGE_DIS BIT(8) +#define AIROHA_PCS_ANA_2L_CDR1_PD_PICAL_CKD8_INV BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO 0x1c8 +#define AIROHA_PCS_ANA_2L_CDR1_LPF_TOP_LIM GENMASK(26, 8) +#define AIROHA_PCS_ANA_2L_CDR1_LPF_RATIO GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE 0x1d4 +#define AIROHA_PCS_ANA_2L_CDR1_PR_INJ_FORCE_OFF BIT(24) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC 0x1d8 +#define AIROHA_PCS_ANA_2L_CDR1_PR_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_SEL GENMASK(19, 16) +#define AIROHA_PCS_ANA_2L_CDR1_PR_VCOADC_OS GENMASK(11, 8) +#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_DAC GENMASK(6, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL 0x1dc +#define AIROHA_PCS_ANA_2L_CDR1_PR_FBKSEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_2L_CDR1_PR_DAC_BAND GENMASK(20, 16) +#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_CKBUF_VAL GENMASK(10, 8) +#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_IBAND_VAL GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN 0x1e8 +#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPR_EN BIT(24) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN 0x1ec +#define AIROHA_PCS_ANA_2L_CDR1_PR_XFICK_EN BIT(8) +#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR 0x1f0 +#define AIROHA_PCS_ANA_2L_RX1_DAC_MON GENMASK(20, 16) +#define AIROHA_PCS_ANA_2L_CDR1_PR_CAP_EN BIT(8) +#define AIROHA_PCS_ANA_2L_CDR1_PR_BUF_IN_SR GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE 0x1f4 +#define AIROHA_PCS_ANA_2L_RX1_SIGDET_LPF_CTRL GENMASK(25, 24) +#define AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH 0x1f8 +#define AIROHA_PCS_ANA_2L_RX1_SIGDET_VTH_SEL GENMASK(20, 16) +#define AIROHA_PCS_ANA_2L_RX1_SIGDET_PEAK GENMASK(9, 8) +#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL 0x1fc +#define AIROHA_PCS_ANA_2L_RX1_FE_EQ_HZEN BIT(24) +#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN 0x200 +#define AIROHA_PCS_ANA_2L_RX1_FE_VCM_GEN_PWDB BIT(24) +#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ3_EN BIT(16) +#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ2_EN BIT(8) +#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ1_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW 0x208 +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE GENMASK(25, 16) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2VOS BIT(0) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2IOS BIT(1) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1VOS BIT(2) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1IOS BIT(3) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2VOS BIT(4) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2IOS BIT(5) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1VOS BIT(6) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1IOS BIT(7) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_LVSH BIT(8) +#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_COMPOS BIT(9) +#define AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE 0x228 +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE GENMASK(27, 16) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_SAOS BIT(0) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP1 BIT(1) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP2 BIT(2) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP3 BIT(3) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP4 BIT(4) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP5 BIT(5) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP6 BIT(6) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP7 BIT(7) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_VGA BIT(8) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_CTLE BIT(9) +#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_ATT BIT(10) +#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ 0x238 +#define AIROHA_PCS_ANA_2L_RX1_DAC_EYE_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_2L_RX1_DAC_E1_BYPASS_AEQ BIT(16) +#define AIROHA_PCS_ANA_2L_RX1_DAC_E0_BYPASS_AEQ BIT(8) +#define AIROHA_PCS_ANA_2L_RX1_DAC_D1_BYPASS_AEQ BIT(0) + +/* PMA_PHYD */ +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0 +#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24) +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4 +#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88 +#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8) +#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c +#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PM= A_OSC_SPEED_OPT, 0x0) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA= _OSC_SPEED_OPT, 0x1) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA= _OSC_SPEED_OPT, 0x2) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA= _OSC_SPEED_OPT, 0x3) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA= _OSC_SPEED_OPT, 0x4) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA= _OSC_SPEED_OPT, 0x5) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA= _OSC_SPEED_OPT, 0x6) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA= _OSC_SPEED_OPT, 0x7) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90 +#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94 +#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98 +#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c +#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100 +#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104 +#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c +#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114 +#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24) +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120 +#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16) +#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8) +#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c +#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16) +#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150 +#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154 +#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158 +#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12) +#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_P= CS_PMA_FREQLOCK_DET_EN, 0x0) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_P= CS_PMA_FREQLOCK_DET_EN, 0x1) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_= PMA_FREQLOCK_DET_EN, 0x2) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PC= S_PMA_FREQLOCK_DET_EN, 0x3) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_= PCS_PMA_FREQLOCK_DET_EN, 0x7) +#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c +#define AIROHA_PCS_PMA_SIGDET_EN BIT(0) +#define AIROHA_PCS_PMA_RX_FLL_1 0x174 +#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_FLL_2 0x178 +#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16) +#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RA= TE, 0x0) +#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RA= TE, 0x1) +#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RAT= E, 0x2) +#define AIROHA_PCS_PMA_RX_FLL_5 0x184 +#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16) +#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_FLL_B 0x19c +#define AIROHA_PCS_PMA_LOAD_EN BIT(0) +#define AIROHA_PCS_PMA_RX_RESET_1 0x208 +#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8) +#define AIROHA_PCS_PMA_TX_RST_B 0x260 +#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8) +#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320 +#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330 +#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c +#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c +#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24) +#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16) +#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8) +#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0) +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350 +#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360 +#define AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN GENMASK(17, 16) +#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374 +#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2 0x380 +#define AIROHA_PCS_RX_SIGDET BIT(8) +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390 +#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394 +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c +#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8) +#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414 +#define AIROHA_PCS_PMA_XFI_RX_MODE GENMASK(11, 9) +#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_RX_MODE, 0x0) +#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_RX_MODE, 0x1) +#define AIROHA_PCS_PMA_XFI_RX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_RX_MODE, 0x2) +#define AIROHA_PCS_PMA_XFI_RX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_RX_MODE, 0x3) +#define AIROHA_PCS_PMA_XFI_RX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_RX_MODE, 0x4) +#define AIROHA_PCS_PMA_XFI_RX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_RX_MODE, 0x5) +#define AIROHA_PCS_PMA_R2T_MODE BIT(8) +#define AIROHA_PCS_PMA_XFI_TX_MODE GENMASK(5, 3) +#define AIROHA_PCS_PMA_XFI_TX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_TX_MODE, 0x0) +#define AIROHA_PCS_PMA_XFI_TX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_TX_MODE, 0x1) +#define AIROHA_PCS_PMA_XFI_TX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_TX_MODE, 0x2) +#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_TX_MODE, 0x3) +#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_TX_MODE, 0x4) +#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_= XFI_TX_MODE, 0x5) +#define AIROHA_PCS_PMA_SW_RST_SET 0x460 +#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11) +#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10) +#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9) +#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8) +#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7) +#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6) +#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5) +#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4) +#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3) +#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2) +#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1) +#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0) +#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474 +#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16) +#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c +#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16) +#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c +#define AIROHA_PCS_PMA_DISB_LEQ BIT(0) +#define AIROHA_PCS_PMA_RX_FREQDET 0x530 +#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16) +#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580 +#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16) +#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16) +#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0) +#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16) +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0) +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8) +#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798 +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0) +#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800 +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0) +#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16) +#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16) +#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0) +#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16) +#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_29 0x910 +#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL GENMASK(5, 4) + +#define AIROHA_PCS_MAX_CALIBRATION_TRY 50 +#define AIROHA_PCS_MAX_RX_SIGDET_TRY 6 +#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT 4 +#define AIROHA_PCS_MAX_NUM_RSTS 2 + +enum xfi_port_type { + AIROHA_PCS_ETH, + AIROHA_PCS_PON, + AIROHA_PCS_USB, + AIROHA_PCS_PCIE, +}; + +struct airoha_pcs_maps { + struct regmap *pcs_mac; + struct regmap *hsgmii_an; + struct regmap *hsgmii_pcs; + struct regmap *hsgmii_rate_adp; + struct regmap *multi_sgmii; + struct regmap *usxgmii_pcs; +}; + +struct airoha_pcs_priv { + struct device *dev; + const struct airoha_pcs_match_data *data; + + struct airoha_pcs_port *ports; + + struct regmap *scu; + + struct airoha_pcs_maps maps[2]; + + struct regmap *pcs_pma[2]; + struct regmap *pcs_ana; + struct regmap_field **pcs_ana_fields[2]; + + struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS]; + + struct phy *phy; + + bool manual_rx_calib; +}; + +struct airoha_pcs_port { + struct airoha_pcs_priv *priv; + phy_interface_t interface; + int index; + + struct phylink_pcs pcs; +}; + +struct airoha_pcs_match_data { + int num_port; + enum xfi_port_type port_type; + + int (*alloc_regmap_fields)(struct airoha_pcs_priv *priv); + int (*bringup)(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface); + void (*link_up)(struct airoha_pcs_priv *priv, int index); + int (*rxlock_workaround)(struct airoha_pcs_priv *priv, int index); +}; + +#define to_airoha_pcs_port(n) container_of(n, struct airoha_pcs_port, pcs) + +#if IS_ENABLED(CONFIG_PCS_AIROHA_AN7581) +int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv); +int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv); +int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface); +int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface); + +void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index); +int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index); +#else +static inline int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *p= riv) +{ + return -EOPNOTSUPP; +} + +static inline int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_pr= iv *priv) +{ + return -EOPNOTSUPP; +} + +static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + return -EOPNOTSUPP; +} + +static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + return -EOPNOTSUPP; +} + +static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, + int index) +{ +} + +static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *pri= v, + int index) +{ + return 0; +} +#endif diff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/p= cs-an7581.c new file mode 100644 index 000000000000..a98e004a5cae --- /dev/null +++ b/drivers/net/pcs/airoha/pcs-an7581.c @@ -0,0 +1,2100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ +#include +#include +#include +#include + +#include "pcs-airoha.h" + +#include + +enum { + AN7581_PCS_CMN_EN, + + AN7581_PCS_JCPLL_SPARE_L, + AN7581_PCS_JCPLL_RST_DLY, + AN7581_PCS_JCPLL_PLL_RSTB, + AN7581_PCS_JCPLL_SDM_DI_EN, + AN7581_PCS_JCPLL_SDM_DI_LS, + + AN7581_PCS_JCPLL_SDM_OUT, + AN7581_PCS_JCPLL_SDM_ORD, + AN7581_PCS_JCPLL_SDM_MODE, + AN7581_PCS_JCPLL_SDM_IFM, + AN7581_PCS_JCPLL_SDM_HREN, + + AN7581_PCS_JCPLL_CHP_IOFST, + AN7581_PCS_JCPLL_CHP_IBIAS, + AN7581_PCS_JCPLL_LPF_SHCK_EN, + + AN7581_PCS_JCPLL_LPF_BWR, + AN7581_PCS_JCPLL_LPF_BP, + AN7581_PCS_JCPLL_LPF_BC, + AN7581_PCS_JCPLL_LPF_BR, + AN7581_PCS_JCPLL_LPF_BWC, + + AN7581_PCS_JCPLL_VCO_SCAPWR, + AN7581_PCS_JCPLL_VCO_HALFLSB_EN, + AN7581_PCS_JCPLL_VCO_CFIX, + AN7581_PCS_JCPLL_VCODIV, + AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L, + AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H, + AN7581_PCS_JCPLL_VCO_TCLVAR, + + AN7581_PCS_JCPLL_POSTDIV_D5, + AN7581_PCS_JCPLL_MMD_PREDIV_MODE, + + AN7581_PCS_JCPLL_KBAND_KS, + AN7581_PCS_JCPLL_KBAND_KF, + AN7581_PCS_JCPLL_KBAND_KFC, + AN7581_PCS_JCPLL_KBAND_DIV, + AN7581_PCS_JCPLL_KBAND_CODE, + AN7581_PCS_JCPLL_KBAND_OPTION, + + AN7581_PCS_JCPLL_TCL_AMP_VREF, + AN7581_PCS_JCPLL_TCL_AMP_GAIN, + AN7581_PCS_JCPLL_TCL_AMP_EN, + + AN7581_PCS_JCPLL_TCL_LPF_BW, + AN7581_PCS_JCPLL_TCL_LPF_EN, + + AN7581_PCS_JCPLL_SSC_DELTA, + AN7581_PCS_JCPLL_SSC_DELTA1, + AN7581_PCS_JCPLL_SSC_PERIOD, + AN7581_PCS_JCPLL_SSC_TRI_EN, + AN7581_PCS_JCPLL_SSC_EN, + AN7581_PCS_JCPLL_SSC_PHASE_INI, + AN7581_PCS_JCPLL_TCL_KBAND_VREF, + + AN7581_PCS_TXPLL_LDO_VCO_OUT, + AN7581_PCS_TXPLL_LDO_OUT, + AN7581_PCS_TXPLL_PLL_RSTB, + AN7581_PCS_TXPLL_RST_DLY, + AN7581_PCS_TXPLL_REFIN_DIV, + AN7581_PCS_TXPLL_REFIN_INTERNAL, + AN7581_PCS_TXPLL_SDM_MODE, + AN7581_PCS_TXPLL_SDM_IFM, + AN7581_PCS_TXPLL_SDM_DI_LS, + AN7581_PCS_TXPLL_SDM_DI_EN, + AN7581_PCS_TXPLL_SDM_HREN, + AN7581_PCS_TXPLL_SDM_ORD, + AN7581_PCS_TXPLL_SDM_OUT, + AN7581_PCS_TXPLL_SSC_DELTA1, + AN7581_PCS_TXPLL_SSC_DELTA, + AN7581_PCS_TXPLL_SSC_TRI_EN, + AN7581_PCS_TXPLL_SSC_PHASE_INI, + AN7581_PCS_TXPLL_SSC_EN, + AN7581_PCS_TXPLL_SSC_PERIOD, + AN7581_PCS_TXPLL_LPF_BC, + AN7581_PCS_TXPLL_LPF_BR, + AN7581_PCS_TXPLL_LPF_BP, + AN7581_PCS_TXPLL_LPF_BWC, + AN7581_PCS_TXPLL_LPF_BWR, + AN7581_PCS_TXPLL_CHP_IOFST, + AN7581_PCS_TXPLL_CHP_IBIAS, + AN7581_PCS_TXPLL_VCO_CFIX, + AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L, + AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H, + AN7581_PCS_TXPLL_VCO_TCLVAR, + AN7581_PCS_TXPLL_VCO_SCAPWR, + AN7581_PCS_TXPLL_VCO_HALFLSB_EN, + AN7581_PCS_TXPLL_KBAND_CODE, + AN7581_PCS_TXPLL_KBAND_OPTION, + AN7581_PCS_TXPLL_KBAND_KS, + AN7581_PCS_TXPLL_KBAND_KF, + AN7581_PCS_TXPLL_KBAND_KFC, + AN7581_PCS_TXPLL_KBAND_DIV, + AN7581_PCS_TXPLL_MMD_PREDIV_MODE, + AN7581_PCS_TXPLL_POSTDIV_EN, + AN7581_PCS_TXPLL_VCODIV, + AN7581_PCS_TXPLL_TCL_KBAND_VREF, + AN7581_PCS_TXPLL_TCL_AMP_GAIN, + AN7581_PCS_TXPLL_TCL_AMP_VREF, + AN7581_PCS_TXPLL_TCL_LPF_BW, + AN7581_PCS_TXPLL_TCL_LPF_EN, + AN7581_PCS_TXPLL_TCL_AMP_EN, + + AN7581_PCS_TX_DMEDGEGEN_EN, + AN7581_PCS_TX_CKLDO_EN, + + AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ, + AN7581_PCS_RX_DAC_E1_BYPASS_AEQ, + AN7581_PCS_RX_DAC_E0_BYPASS_AEQ, + AN7581_PCS_RX_DAC_D1_BYPASS_AEQ, + AN7581_PCS_RX_DAC_D0_BYPASS_AEQ, + AN7581_PCS_RX_FE_VCM_GEN_PWDB, + AN7581_PCS_RX_OSCAL_FORCE, + AN7581_PCS_RX_DAC_MON, + AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL, + AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL, + AN7581_PCS_RX_REV_1_SIGDET_ILEAK, + AN7581_PCS_RX_FE_VB_EQ3_EN, + AN7581_PCS_RX_FE_VB_EQ2_EN, + AN7581_PCS_RX_FE_VB_EQ1_EN, + AN7581_PCS_RX_FE_EQ_HZEN, + AN7581_PCS_RX_SIGDET_VTH_SEL, + AN7581_PCS_RX_SIGDET_PEAK, + AN7581_PCS_RX_SIGDET_LPF_CTRL, + AN7581_PCS_RX_TDC_CK_SEL, + AN7581_PCS_RX_PHYCK_RSTB, + AN7581_PCS_RX_PHYCK_SEL, + AN7581_PCS_RX_PHYCK_DIV, + AN7581_PCS_RX_PHY_CK_SEL_FORCE, + AN7581_PCS_RX_PHY_CK_SEL, + + AN7581_PCS_AEQ_OFORCE, + + AN7581_PCS_CDR_PD_EDGE_DIS, + AN7581_PCS_CDR_PD_PICAL_CKD8_INV, + + AN7581_PCS_CDR_PR_XFICK_EN, + AN7581_PCS_CDR_PR_MONPI_EN, + AN7581_PCS_CDR_PR_MONPR_EN, + AN7581_PCS_CDR_PR_KBAND_DIV, + AN7581_PCS_CDR_PR_BETA_SEL, + AN7581_PCS_CDR_PR_VCOADC_OS, + AN7581_PCS_CDR_PR_BETA_DAC, + AN7581_PCS_CDR_PR_FBKSEL, + AN7581_PCS_CDR_PR_DAC_BAND, + AN7581_PCS_CDR_PR_VREG_CKBUF_VAL, + AN7581_PCS_CDR_PR_VREG_IBAND_VAL, + AN7581_PCS_CDR_PR_CAP_EN, + AN7581_PCS_CDR_PR_INJ_FORCE_OFF, + + AN7581_PCS_CDR_BUF_IN_SR, + + AN7581_PCS_CDR_LPF_TOP_LIM, + AN7581_PCS_CDR_LPF_RATIO, + + AN7581_PCS_FIELDS_MAX, +}; + +static const struct reg_field an7581_pcs_fields[AN7581_PCS_FIELDS_MAX] =3D= { + [AN7581_PCS_CMN_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CMN_EN, 0, 0), + + [AN7581_PCS_JCPLL_SPARE_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H= , 8, 15), + + [AN7581_PCS_JCPLL_RST_DLY] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY= , 0, 2), + [AN7581_PCS_JCPLL_PLL_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DL= Y, 8, 8), + [AN7581_PCS_JCPLL_SDM_DI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_D= LY, 16, 16), + [AN7581_PCS_JCPLL_SDM_DI_LS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_D= LY, 24, 25), + + [AN7581_PCS_JCPLL_SDM_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM= , 24, 24), + [AN7581_PCS_JCPLL_SDM_ORD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM= , 16, 17), + [AN7581_PCS_JCPLL_SDM_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IF= M, 8, 9), + [AN7581_PCS_JCPLL_SDM_IFM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM= , 0, 0), + [AN7581_PCS_JCPLL_SDM_HREN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HR= EN, 0, 0), + + [AN7581_PCS_JCPLL_SSC_PERIOD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_= DELTA, 16, 31), + [AN7581_PCS_JCPLL_SSC_DELTA] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_D= ELTA, 0, 15), + [AN7581_PCS_JCPLL_SSC_DELTA1] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_= TRI_EN, 8, 23), + [AN7581_PCS_JCPLL_SSC_TRI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_= TRI_EN, 0, 0), + [AN7581_PCS_JCPLL_SSC_PHASE_INI] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_V= CO_TCLVAR, 17, 17), + [AN7581_PCS_JCPLL_SSC_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLV= AR, 16, 16), + [AN7581_PCS_JCPLL_TCL_KBAND_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_= SPARE_H, 16, 20), + + [AN7581_PCS_JCPLL_CHP_IOFST] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EX= T_EN, 24, 29), + [AN7581_PCS_JCPLL_CHP_IBIAS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EX= T_EN, 16, 21), + [AN7581_PCS_JCPLL_LPF_SHCK_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_= EXT_EN, 8, 8), + + [AN7581_PCS_JCPLL_LPF_BWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR,= 24, 28), + [AN7581_PCS_JCPLL_LPF_BP] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, = 16, 20), + [AN7581_PCS_JCPLL_LPF_BC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, = 8, 12), + [AN7581_PCS_JCPLL_LPF_BR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, = 0, 4), + [AN7581_PCS_JCPLL_LPF_BWC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC= , 0, 4), + + [AN7581_PCS_JCPLL_VCO_SCAPWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCOD= IV, 24, 26), + [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_= VCODIV, 16, 16), + [AN7581_PCS_JCPLL_VCO_CFIX] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV= , 8, 9), + [AN7581_PCS_JCPLL_VCODIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, = 0, 1), + [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCP= LL_VCO_TCLVAR, 8, 10), + [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCP= LL_VCO_TCLVAR, 3, 5), + [AN7581_PCS_JCPLL_VCO_TCLVAR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_= TCLVAR, 0, 2), + + [AN7581_PCS_JCPLL_POSTDIV_D5] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_= PREDIV_MODE, 24, 24), + [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL= _MMD_PREDIV_MODE, 0, 1), + + [AN7581_PCS_JCPLL_KBAND_KS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_= KFC, 16, 17), + [AN7581_PCS_JCPLL_KBAND_KF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_= KFC, 8, 9), + [AN7581_PCS_JCPLL_KBAND_KFC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND= _KFC, 0, 1), + [AN7581_PCS_JCPLL_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_B= WC, 24, 26), + [AN7581_PCS_JCPLL_KBAND_CODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_= BWC, 16, 23), + [AN7581_PCS_JCPLL_KBAND_OPTION] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LP= F_BWC, 8, 8), + + [AN7581_PCS_JCPLL_TCL_AMP_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SD= M_HREN, 24, 28), + [AN7581_PCS_JCPLL_TCL_AMP_GAIN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SD= M_HREN, 16, 18), + [AN7581_PCS_JCPLL_TCL_AMP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_= HREN, 8, 8), + + [AN7581_PCS_JCPLL_TCL_LPF_BW] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_= CMP_EN, 24, 26), + [AN7581_PCS_JCPLL_TCL_LPF_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_= CMP_EN, 16, 16), + + [AN7581_PCS_TXPLL_LDO_VCO_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC= _PERIOD, 24, 25), + [AN7581_PCS_TXPLL_LDO_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PER= IOD, 16, 17), + [AN7581_PCS_TXPLL_PLL_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_= INTERNAL, 24, 24), + [AN7581_PCS_TXPLL_RST_DLY] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_I= NTERNAL, 16, 18), + [AN7581_PCS_TXPLL_REFIN_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN= _INTERNAL, 8, 9), + [AN7581_PCS_TXPLL_REFIN_INTERNAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_= REFIN_INTERNAL, 0, 0), + [AN7581_PCS_TXPLL_SDM_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI= _EN, 24, 25), + [AN7581_PCS_TXPLL_SDM_IFM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_= EN, 16, 16), + [AN7581_PCS_TXPLL_SDM_DI_LS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_D= I_EN, 8, 9), + [AN7581_PCS_TXPLL_SDM_DI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_D= I_EN, 0, 0), + [AN7581_PCS_TXPLL_SDM_HREN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_OR= D, 16, 16), + [AN7581_PCS_TXPLL_SDM_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD= , 8, 8), + [AN7581_PCS_TXPLL_SDM_ORD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD= , 0, 1), + [AN7581_PCS_TXPLL_SSC_DELTA1] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_= DELTA1, 16, 31), + [AN7581_PCS_TXPLL_SSC_DELTA] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_D= ELTA1, 0, 15), + [AN7581_PCS_TXPLL_SSC_TRI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_= EN, 16, 16), + [AN7581_PCS_TXPLL_SSC_PHASE_INI] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_S= SC_EN, 8, 8), + [AN7581_PCS_TXPLL_SSC_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, = 0, 0), + [AN7581_PCS_TXPLL_SSC_PERIOD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_= PERIOD, 0, 15), + [AN7581_PCS_TXPLL_LPF_BC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIA= S, 24, 28), + [AN7581_PCS_TXPLL_LPF_BR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIA= S, 16, 20), + [AN7581_PCS_TXPLL_CHP_IOFST] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_I= BIAS, 8, 13), + [AN7581_PCS_TXPLL_CHP_IBIAS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_I= BIAS, 0, 5), + [AN7581_PCS_TXPLL_LPF_BWC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,= 16, 20), + [AN7581_PCS_TXPLL_LPF_BWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,= 8, 12), + [AN7581_PCS_TXPLL_LPF_BP] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, = 0, 4), + [AN7581_PCS_TXPLL_VCO_CFIX] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LP= F_EN, 24, 25), + [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXP= LL_VCO_HALFLSB_EN, 27, 29), + [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXP= LL_VCO_HALFLSB_EN, 24, 26), + [AN7581_PCS_TXPLL_VCO_TCLVAR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_= HALFLSB_EN, 16, 18), + [AN7581_PCS_TXPLL_VCO_SCAPWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_= HALFLSB_EN, 8, 10), + [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_= VCO_HALFLSB_EN, 0, 0), + [AN7581_PCS_TXPLL_KBAND_CODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAN= D_CODE, 0, 7), + [AN7581_PCS_TXPLL_KBAND_OPTION] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LP= F_BP, 24, 24), + [AN7581_PCS_TXPLL_KBAND_KS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_= KS, 0, 1), + [AN7581_PCS_TXPLL_KBAND_KF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_= CODE, 24, 25), + [AN7581_PCS_TXPLL_KBAND_KFC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND= _CODE, 16, 17), + [AN7581_PCS_TXPLL_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND= _CODE, 8, 10), + [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL= _KBAND_KS, 16, 17), + [AN7581_PCS_TXPLL_POSTDIV_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAN= D_KS, 8, 8), + [AN7581_PCS_TXPLL_VCODIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_= EN, 16, 17), + [AN7581_PCS_TXPLL_TCL_KBAND_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_= TCL_KBAND_VREF, 0, 4), + [AN7581_PCS_TXPLL_TCL_AMP_GAIN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TC= L_AMP_GAIN, 0, 2), + [AN7581_PCS_TXPLL_TCL_AMP_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TC= L_AMP_GAIN, 8, 12), + [AN7581_PCS_TXPLL_TCL_LPF_BW] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_= LPF_EN, 8, 10), + [AN7581_PCS_TXPLL_TCL_LPF_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_= LPF_EN, 0, 0), + [AN7581_PCS_TXPLL_TCL_AMP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_= ORD, 24, 24), + + [AN7581_PCS_TX_DMEDGEGEN_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN= , 24, 24), + [AN7581_PCS_TX_CKLDO_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 0,= 0), + + [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DA= C_D1_BYPASS_AEQ, 24, 24), + [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC= _D1_BYPASS_AEQ, 16, 16), + [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC= _D1_BYPASS_AEQ, 8, 8), + [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC= _D1_BYPASS_AEQ, 0, 0), + [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_= PEAKING_CTRL_MSB, 24, 24), + [AN7581_PCS_RX_FE_VCM_GEN_PWDB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_VC= M_GEN_PWDB, 0, 0), + + [AN7581_PCS_AEQ_OFORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_AEQ_CFORCE, 8, 1= 9), + [AN7581_PCS_RX_OSCAL_FORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_OSCAL_WAT= CH_WNDW, 8, 17), + + [AN7581_PCS_CDR_PD_EDGE_DIS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICA= L_CKD8_INV, 8, 8), + [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_P= D_PICAL_CKD8_INV, 0, 0), + + [AN7581_PCS_RX_DAC_MON] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,= 24, 28), + [AN7581_PCS_CDR_PR_XFICK_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONP= R_EN, 2, 2), + [AN7581_PCS_CDR_PR_MONPI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONP= R_EN, 1, 1), + [AN7581_PCS_CDR_PR_MONPR_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONP= R_EN, 0, 0), + + [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_= RX_REV_0, 24, 26), + [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_= RX_REV_0, 20, 22), + [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_RE= V_0, 18, 19), + + [AN7581_PCS_CDR_LPF_TOP_LIM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RAT= IO, 8, 26), + [AN7581_PCS_CDR_LPF_RATIO] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO= , 0, 1), + + [AN7581_PCS_CDR_PR_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BET= A_DAC, 24, 26), + [AN7581_PCS_CDR_PR_BETA_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA= _DAC, 16, 19), + [AN7581_PCS_CDR_PR_VCOADC_OS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BET= A_DAC, 8, 11), + [AN7581_PCS_CDR_PR_BETA_DAC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA= _DAC, 0, 6), + [AN7581_PCS_CDR_PR_FBKSEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_I= BAND_VAL, 24, 25), + [AN7581_PCS_CDR_PR_DAC_BAND] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG= _IBAND_VAL, 16, 20), + [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_P= R_VREG_IBAND_VAL, 8, 10), + [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_P= R_VREG_IBAND_VAL, 0, 2), + + [AN7581_PCS_RX_FE_VB_EQ3_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZ= EN, 24, 24), + [AN7581_PCS_RX_FE_VB_EQ2_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZ= EN, 16, 16), + [AN7581_PCS_RX_FE_VB_EQ1_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZ= EN, 8, 8), + [AN7581_PCS_RX_FE_EQ_HZEN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN= , 0, 0), + + [AN7581_PCS_CDR_PR_CAP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_= EN, 19, 19), + [AN7581_PCS_CDR_BUF_IN_SR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_= EN, 16, 18), + + [AN7581_PCS_RX_SIGDET_VTH_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET= _NOVTH, 16, 20), + [AN7581_PCS_RX_SIGDET_PEAK] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NO= VTH, 8, 9), + [AN7581_PCS_RX_SIGDET_LPF_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_R= ANGE, 24, 25), + + [AN7581_PCS_RX_TDC_CK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,= 24, 24), + [AN7581_PCS_RX_PHYCK_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,= 16, 16), + [AN7581_PCS_RX_PHYCK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, = 8, 9), + [AN7581_PCS_RX_PHYCK_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, = 0, 7), + [AN7581_PCS_RX_PHY_CK_SEL_FORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSB= IT_SEL, 24, 24), + [AN7581_PCS_RX_PHY_CK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL= , 16, 16), + + [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR= _INJ_MODE, 24, 24), +}; + +static const struct reg_field an7581_pcs_pcie0_fields[AN7581_PCS_FIELDS_MA= X] =3D { + [AN7581_PCS_CMN_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0), + + [AN7581_PCS_JCPLL_SPARE_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_= VTP_EN, 24, 31), + + [AN7581_PCS_JCPLL_RST_DLY] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_= DLY, 0, 2), + [AN7581_PCS_JCPLL_PLL_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST= _DLY, 8, 8), + [AN7581_PCS_JCPLL_SDM_DI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RS= T_DLY, 16, 16), + [AN7581_PCS_JCPLL_SDM_DI_LS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RS= T_DLY, 24, 25), + + [AN7581_PCS_JCPLL_SDM_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_= IFM, 24, 24), + [AN7581_PCS_JCPLL_SDM_ORD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_= IFM, 16, 17), + [AN7581_PCS_JCPLL_SDM_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM= _IFM, 8, 9), + [AN7581_PCS_JCPLL_SDM_IFM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_= IFM, 0, 0), + [AN7581_PCS_JCPLL_SDM_HREN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM= _HREN, 0, 0), + + [AN7581_PCS_JCPLL_CHP_IOFST] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB= _EXT_EN, 24, 29), + [AN7581_PCS_JCPLL_CHP_IBIAS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB= _EXT_EN, 16, 21), + [AN7581_PCS_JCPLL_LPF_SHCK_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_= IB_EXT_EN, 8, 8), + + [AN7581_PCS_JCPLL_LPF_BWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_= BR, 24, 28), + [AN7581_PCS_JCPLL_LPF_BP] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_B= R, 16, 20), + [AN7581_PCS_JCPLL_LPF_BC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_B= R, 8, 12), + [AN7581_PCS_JCPLL_LPF_BR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_B= R, 0, 4), + [AN7581_PCS_JCPLL_LPF_BWC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_= BWC, 0, 4), + + [AN7581_PCS_JCPLL_VCO_SCAPWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_V= CODIV, 24, 26), + [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCP= LL_VCODIV, 16, 16), + [AN7581_PCS_JCPLL_VCO_CFIX] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO= DIV, 8, 9), + [AN7581_PCS_JCPLL_VCODIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODI= V, 0, 1), + [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= JCPLL_VCO_TCLVAR, 16, 18), + [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= JCPLL_VCO_TCLVAR, 8, 10), + [AN7581_PCS_JCPLL_VCO_TCLVAR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_V= CO_TCLVAR, 0, 2), + + [AN7581_PCS_JCPLL_SSC_DELTA] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SS= C_DELTA1, 16, 31), + [AN7581_PCS_JCPLL_SSC_DELTA1] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= SC_DELTA1, 0, 15), + [AN7581_PCS_JCPLL_SSC_PERIOD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= SC_PERIOD, 0, 15), + [AN7581_PCS_JCPLL_SSC_TRI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= SC_EN, 16, 16), + [AN7581_PCS_JCPLL_SSC_PHASE_INI] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPL= L_SSC_EN, 8, 8), + [AN7581_PCS_JCPLL_SSC_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_E= N, 0, 0), + [AN7581_PCS_JCPLL_TCL_KBAND_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCP= LL_TCL_KBAND_VREF, 0, 4), + + [AN7581_PCS_JCPLL_POSTDIV_D5] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_M= MD_PREDIV_MODE, 24, 24), + [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JC= PLL_MMD_PREDIV_MODE, 0, 1), + + [AN7581_PCS_JCPLL_KBAND_KS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBA= ND_KFC, 16, 17), + [AN7581_PCS_JCPLL_KBAND_KF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBA= ND_KFC, 8, 9), + [AN7581_PCS_JCPLL_KBAND_KFC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KB= AND_KFC, 0, 1), + [AN7581_PCS_JCPLL_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LP= F_BWC, 24, 26), + [AN7581_PCS_JCPLL_KBAND_CODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_L= PF_BWC, 16, 23), + [AN7581_PCS_JCPLL_KBAND_OPTION] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL= _LPF_BWC, 8, 8), + + [AN7581_PCS_JCPLL_TCL_AMP_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL= _SDM_HREN, 24, 28), + [AN7581_PCS_JCPLL_TCL_AMP_GAIN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL= _SDM_HREN, 16, 18), + [AN7581_PCS_JCPLL_TCL_AMP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= DM_HREN, 8, 8), + + [AN7581_PCS_JCPLL_TCL_LPF_BW] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_T= CL_CMP_EN, 24, 26), + [AN7581_PCS_JCPLL_TCL_LPF_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_T= CL_CMP_EN, 16, 16), + + [AN7581_PCS_TXPLL_LDO_VCO_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_= SSC_PERIOD, 24, 25), + [AN7581_PCS_TXPLL_LDO_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_= PERIOD, 16, 17), + [AN7581_PCS_TXPLL_PLL_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REF= IN_DIV, 16, 16), + [AN7581_PCS_TXPLL_RST_DLY] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFI= N_DIV, 8, 10), + [AN7581_PCS_TXPLL_REFIN_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_RE= FIN_DIV, 0, 1), + [AN7581_PCS_TXPLL_REFIN_INTERNAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXP= LL_PHY_CK2_EN, 24, 24), + [AN7581_PCS_TXPLL_SDM_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM= _DI_LS, 16, 17), + [AN7581_PCS_TXPLL_SDM_IFM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_= DI_LS, 8, 8), + [AN7581_PCS_TXPLL_SDM_DI_LS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SD= M_DI_LS, 0, 1), + [AN7581_PCS_TXPLL_SDM_DI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_RE= FIN_DIV, 24, 24), + [AN7581_PCS_TXPLL_SDM_HREN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM= _OUT, 8, 8), + [AN7581_PCS_TXPLL_SDM_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_= OUT, 0, 0), + [AN7581_PCS_TXPLL_SDM_ORD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_= DI_LS, 24, 25), + [AN7581_PCS_TXPLL_SSC_DELTA1] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= SC_DELTA1, 16, 31), + [AN7581_PCS_TXPLL_SSC_DELTA] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SS= C_DELTA1, 0, 15), + [AN7581_PCS_TXPLL_SSC_TRI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= SC_EN, 16, 16), + [AN7581_PCS_TXPLL_SSC_PHASE_INI] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPL= L_SSC_EN, 8, 8), + [AN7581_PCS_TXPLL_SSC_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_E= N, 0, 0), + [AN7581_PCS_TXPLL_SSC_PERIOD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= SC_PERIOD, 0, 15), + [AN7581_PCS_TXPLL_LPF_BC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_I= OFST, 16, 20), + [AN7581_PCS_TXPLL_LPF_BR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_I= OFST, 8, 12), + [AN7581_PCS_TXPLL_CHP_IOFST] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CH= P_IOFST, 0, 5), + [AN7581_PCS_TXPLL_CHP_IBIAS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS= _CK_EN, 24, 29), + [AN7581_PCS_TXPLL_LPF_BWC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_= BWR, 8, 12), + [AN7581_PCS_TXPLL_LPF_BWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_= BWR, 0, 4), + [AN7581_PCS_TXPLL_LPF_BP] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_I= OFST, 24, 28), + [AN7581_PCS_TXPLL_VCO_CFIX] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL= _LPF_BW, 16, 17), + [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= TXPLL_VCO_SCAPWR, 24, 26), + [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= TXPLL_VCO_SCAPWR, 16, 18), + [AN7581_PCS_TXPLL_VCO_TCLVAR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_V= CO_SCAPWR, 8, 10), + [AN7581_PCS_TXPLL_VCO_SCAPWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_V= CO_SCAPWR, 0, 2), + [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXP= LL_TCL_LPF_BW, 24, 24), + [AN7581_PCS_TXPLL_KBAND_CODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_L= PF_BWR, 24, 31), + [AN7581_PCS_TXPLL_KBAND_OPTION] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL= _LPF_BWR, 16, 16), + [AN7581_PCS_TXPLL_KBAND_KS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBA= ND_DIV, 24, 25), + [AN7581_PCS_TXPLL_KBAND_KF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBA= ND_DIV, 16, 17), + [AN7581_PCS_TXPLL_KBAND_KFC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KB= AND_DIV, 8, 9), + [AN7581_PCS_TXPLL_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KB= AND_DIV, 0, 2), + [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX= PLL_POSTDIV_EN, 8, 9), + [AN7581_PCS_TXPLL_POSTDIV_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_P= OSTDIV_EN, 0, 0), + [AN7581_PCS_TXPLL_VCODIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_L= PF_BW, 8, 9), + [AN7581_PCS_TXPLL_TCL_KBAND_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXP= LL_TCL_KBAND_VREF, 0, 4), + [AN7581_PCS_TXPLL_TCL_AMP_GAIN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL= _SDM_OUT, 24, 26), + [AN7581_PCS_TXPLL_TCL_AMP_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL= _TCL_AMP_VREF, 0, 4), + [AN7581_PCS_TXPLL_TCL_LPF_BW] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_T= CL_LPF_BW, 0, 2), + [AN7581_PCS_TXPLL_TCL_LPF_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_T= CL_AMP_VREF, 24, 24), + [AN7581_PCS_TXPLL_TCL_AMP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= DM_OUT, 16, 16), + + [AN7581_PCS_TX_DMEDGEGEN_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLD= O_EN, 24, 24), + [AN7581_PCS_TX_CKLDO_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN= , 0, 0), + + [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX= 0_DAC_EYE_BYPASS_AEQ, 0, 0), + [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0= _DAC_D0_BYPASS_AEQ, 24, 24), + [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0= _DAC_D0_BYPASS_AEQ, 16, 16), + [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0= _DAC_D0_BYPASS_AEQ, 8, 8), + [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0= _DAC_D0_BYPASS_AEQ, 0, 0), + [AN7581_PCS_RX_FE_VCM_GEN_PWDB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_F= E_VB_EQ2_EN, 16, 16), + + [AN7581_PCS_AEQ_OFORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE, = 8, 19), + [AN7581_PCS_RX_OSCAL_FORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL= _FORCE, 8, 17), + + [AN7581_PCS_CDR_PD_EDGE_DIS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_= PICAL_CKD8_INV, 8, 8), + [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CD= R0_PD_PICAL_CKD8_INV, 0, 0), + + [AN7581_PCS_RX_DAC_MON] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON, = 0, 4), + [AN7581_PCS_CDR_PR_XFICK_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_= MONPI_EN, 8, 8), + [AN7581_PCS_CDR_PR_MONPI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_= MONPI_EN, 0, 0), + [AN7581_PCS_CDR_PR_MONPR_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_= COR_HBW_EN, 24, 24), + + [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_= 2L_RX0_REV_0, 24, 26), + [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_= 2L_RX0_REV_0, 20, 22), + [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX= 0_REV_0, 18, 19), + + [AN7581_PCS_CDR_LPF_TOP_LIM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF= _RATIO, 8, 26), + [AN7581_PCS_CDR_LPF_RATIO] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_R= ATIO, 0, 1), + + [AN7581_PCS_CDR_PR_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR= _BETA_DAC, 24, 26), + [AN7581_PCS_CDR_PR_BETA_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_= BETA_DAC, 16, 19), + [AN7581_PCS_CDR_PR_VCOADC_OS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR= _BETA_DAC, 8, 11), + [AN7581_PCS_CDR_PR_BETA_DAC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_= BETA_DAC, 0, 6), + [AN7581_PCS_CDR_PR_FBKSEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VR= EG_IBAND_VAL, 24, 25), + [AN7581_PCS_CDR_PR_DAC_BAND] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_= VREG_IBAND_VAL, 16, 20), + [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CD= R0_PR_VREG_IBAND_VAL, 8, 10), + [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CD= R0_PR_VREG_IBAND_VAL, 0, 2), + + [AN7581_PCS_RX_FE_VB_EQ3_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_V= B_EQ2_EN, 8, 8), + [AN7581_PCS_RX_FE_VB_EQ2_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_V= B_EQ2_EN, 0, 0), + [AN7581_PCS_RX_FE_VB_EQ1_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGD= ET_VTH_SEL, 24, 24), + [AN7581_PCS_RX_FE_EQ_HZEN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET= _VTH_SEL, 16, 16), + + [AN7581_PCS_CDR_PR_CAP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BU= F_IN_SR, 8, 8), + [AN7581_PCS_CDR_BUF_IN_SR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BU= F_IN_SR, 0, 2), + + [AN7581_PCS_RX_SIGDET_VTH_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SI= GDET_VTH_SEL, 0, 4), + [AN7581_PCS_RX_SIGDET_PEAK] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDE= T_DCTEST_EN, 24, 25), + [AN7581_PCS_RX_SIGDET_LPF_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_S= IGDET_DCTEST_EN, 8, 9), + + [AN7581_PCS_RX_TDC_CK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_= DIV, 24, 24), + [AN7581_PCS_RX_PHYCK_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_= DIV, 16, 16), + [AN7581_PCS_RX_PHYCK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_D= IV, 8, 9), + [AN7581_PCS_RX_PHYCK_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_D= IV, 0, 7), + [AN7581_PCS_RX_PHY_CK_SEL_FORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_= BUSBIT_SEL, 24, 24), + [AN7581_PCS_RX_PHY_CK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT= _SEL, 16, 16), + + [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR= 0_PR_INJ_MODE, 24, 24), +}; + +static const struct reg_field an7581_pcs_pcie1_fields[AN7581_PCS_FIELDS_MA= X] =3D { + [AN7581_PCS_CMN_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0), + + [AN7581_PCS_JCPLL_SPARE_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_= VTP_EN, 24, 31), + + [AN7581_PCS_JCPLL_RST_DLY] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_= DLY, 0, 2), + [AN7581_PCS_JCPLL_PLL_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST= _DLY, 8, 8), + [AN7581_PCS_JCPLL_SDM_DI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RS= T_DLY, 16, 16), + [AN7581_PCS_JCPLL_SDM_DI_LS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RS= T_DLY, 24, 25), + + [AN7581_PCS_JCPLL_SDM_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_= IFM, 24, 24), + [AN7581_PCS_JCPLL_SDM_ORD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_= IFM, 16, 17), + [AN7581_PCS_JCPLL_SDM_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM= _IFM, 8, 9), + [AN7581_PCS_JCPLL_SDM_IFM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_= IFM, 0, 0), + [AN7581_PCS_JCPLL_SDM_HREN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM= _HREN, 0, 0), + + [AN7581_PCS_JCPLL_CHP_IOFST] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB= _EXT_EN, 24, 29), + [AN7581_PCS_JCPLL_CHP_IBIAS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB= _EXT_EN, 16, 21), + [AN7581_PCS_JCPLL_LPF_SHCK_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_= IB_EXT_EN, 8, 8), + + [AN7581_PCS_JCPLL_LPF_BWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_= BR, 24, 28), + [AN7581_PCS_JCPLL_LPF_BP] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_B= R, 16, 20), + [AN7581_PCS_JCPLL_LPF_BC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_B= R, 8, 12), + [AN7581_PCS_JCPLL_LPF_BR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_B= R, 0, 4), + [AN7581_PCS_JCPLL_LPF_BWC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_= BWC, 0, 4), + + [AN7581_PCS_JCPLL_VCO_SCAPWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_V= CODIV, 24, 26), + [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCP= LL_VCODIV, 16, 16), + [AN7581_PCS_JCPLL_VCO_CFIX] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO= DIV, 8, 9), + [AN7581_PCS_JCPLL_VCODIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODI= V, 0, 1), + [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= JCPLL_VCO_TCLVAR, 16, 18), + [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= JCPLL_VCO_TCLVAR, 8, 10), + [AN7581_PCS_JCPLL_VCO_TCLVAR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_V= CO_TCLVAR, 0, 2), + + [AN7581_PCS_JCPLL_SSC_DELTA] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SS= C_DELTA1, 16, 31), + [AN7581_PCS_JCPLL_SSC_DELTA1] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= SC_DELTA1, 0, 15), + [AN7581_PCS_JCPLL_SSC_PERIOD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= SC_PERIOD, 0, 15), + [AN7581_PCS_JCPLL_SSC_TRI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= SC_EN, 16, 16), + [AN7581_PCS_JCPLL_SSC_PHASE_INI] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPL= L_SSC_EN, 8, 8), + [AN7581_PCS_JCPLL_SSC_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_E= N, 0, 0), + [AN7581_PCS_JCPLL_TCL_KBAND_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCP= LL_TCL_KBAND_VREF, 0, 4), + + [AN7581_PCS_JCPLL_POSTDIV_D5] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_M= MD_PREDIV_MODE, 24, 24), + [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JC= PLL_MMD_PREDIV_MODE, 0, 1), + + [AN7581_PCS_JCPLL_KBAND_KS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBA= ND_KFC, 16, 17), + [AN7581_PCS_JCPLL_KBAND_KF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBA= ND_KFC, 8, 9), + [AN7581_PCS_JCPLL_KBAND_KFC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KB= AND_KFC, 0, 1), + [AN7581_PCS_JCPLL_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LP= F_BWC, 24, 26), + [AN7581_PCS_JCPLL_KBAND_CODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_L= PF_BWC, 16, 23), + [AN7581_PCS_JCPLL_KBAND_OPTION] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL= _LPF_BWC, 8, 8), + + [AN7581_PCS_JCPLL_TCL_AMP_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL= _SDM_HREN, 24, 28), + [AN7581_PCS_JCPLL_TCL_AMP_GAIN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL= _SDM_HREN, 16, 18), + [AN7581_PCS_JCPLL_TCL_AMP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_S= DM_HREN, 8, 8), + + [AN7581_PCS_JCPLL_TCL_LPF_BW] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_T= CL_CMP_EN, 24, 26), + [AN7581_PCS_JCPLL_TCL_LPF_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_T= CL_CMP_EN, 16, 16), + + [AN7581_PCS_TXPLL_LDO_VCO_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_= SSC_PERIOD, 24, 25), + [AN7581_PCS_TXPLL_LDO_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_= PERIOD, 16, 17), + [AN7581_PCS_TXPLL_PLL_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REF= IN_DIV, 16, 16), + [AN7581_PCS_TXPLL_RST_DLY] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFI= N_DIV, 8, 10), + [AN7581_PCS_TXPLL_REFIN_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_RE= FIN_DIV, 0, 1), + [AN7581_PCS_TXPLL_REFIN_INTERNAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXP= LL_PHY_CK2_EN, 24, 24), + [AN7581_PCS_TXPLL_SDM_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM= _DI_LS, 16, 17), + [AN7581_PCS_TXPLL_SDM_IFM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_= DI_LS, 8, 8), + [AN7581_PCS_TXPLL_SDM_DI_LS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SD= M_DI_LS, 0, 1), + [AN7581_PCS_TXPLL_SDM_DI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_RE= FIN_DIV, 24, 24), + [AN7581_PCS_TXPLL_SDM_HREN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM= _OUT, 8, 8), + [AN7581_PCS_TXPLL_SDM_OUT] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_= OUT, 0, 0), + [AN7581_PCS_TXPLL_SDM_ORD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_= DI_LS, 24, 25), + [AN7581_PCS_TXPLL_SSC_DELTA1] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= SC_DELTA1, 16, 31), + [AN7581_PCS_TXPLL_SSC_DELTA] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SS= C_DELTA1, 0, 15), + [AN7581_PCS_TXPLL_SSC_TRI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= SC_EN, 16, 16), + [AN7581_PCS_TXPLL_SSC_PHASE_INI] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPL= L_SSC_EN, 8, 8), + [AN7581_PCS_TXPLL_SSC_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_E= N, 0, 0), + [AN7581_PCS_TXPLL_SSC_PERIOD] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= SC_PERIOD, 0, 15), + [AN7581_PCS_TXPLL_LPF_BC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_I= OFST, 16, 20), + [AN7581_PCS_TXPLL_LPF_BR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_I= OFST, 8, 12), + [AN7581_PCS_TXPLL_CHP_IOFST] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CH= P_IOFST, 0, 5), + [AN7581_PCS_TXPLL_CHP_IBIAS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS= _CK_EN, 24, 29), + [AN7581_PCS_TXPLL_LPF_BWC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_= BWR, 8, 12), + [AN7581_PCS_TXPLL_LPF_BWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_= BWR, 0, 4), + [AN7581_PCS_TXPLL_LPF_BP] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_I= OFST, 24, 28), + [AN7581_PCS_TXPLL_VCO_CFIX] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL= _LPF_BW, 16, 17), + [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= TXPLL_VCO_SCAPWR, 24, 26), + [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_= TXPLL_VCO_SCAPWR, 16, 18), + [AN7581_PCS_TXPLL_VCO_TCLVAR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_V= CO_SCAPWR, 8, 10), + [AN7581_PCS_TXPLL_VCO_SCAPWR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_V= CO_SCAPWR, 0, 2), + [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXP= LL_TCL_LPF_BW, 24, 24), + [AN7581_PCS_TXPLL_KBAND_CODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_L= PF_BWR, 24, 31), + [AN7581_PCS_TXPLL_KBAND_OPTION] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL= _LPF_BWR, 16, 16), + [AN7581_PCS_TXPLL_KBAND_KS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBA= ND_DIV, 24, 25), + [AN7581_PCS_TXPLL_KBAND_KF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBA= ND_DIV, 16, 17), + [AN7581_PCS_TXPLL_KBAND_KFC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KB= AND_DIV, 8, 9), + [AN7581_PCS_TXPLL_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KB= AND_DIV, 0, 2), + [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX= PLL_POSTDIV_EN, 8, 9), + [AN7581_PCS_TXPLL_POSTDIV_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_P= OSTDIV_EN, 0, 0), + [AN7581_PCS_TXPLL_VCODIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_L= PF_BW, 8, 9), + [AN7581_PCS_TXPLL_TCL_KBAND_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXP= LL_TCL_KBAND_VREF, 0, 4), + [AN7581_PCS_TXPLL_TCL_AMP_GAIN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL= _SDM_OUT, 24, 26), + [AN7581_PCS_TXPLL_TCL_AMP_VREF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL= _TCL_AMP_VREF, 0, 4), + [AN7581_PCS_TXPLL_TCL_LPF_BW] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_T= CL_LPF_BW, 0, 2), + [AN7581_PCS_TXPLL_TCL_LPF_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_T= CL_AMP_VREF, 24, 24), + [AN7581_PCS_TXPLL_TCL_AMP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_S= DM_OUT, 16, 16), + + [AN7581_PCS_TX_DMEDGEGEN_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLD= O_EN, 24, 24), + [AN7581_PCS_TX_CKLDO_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN= , 0, 0), + + [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX= 1_DAC_D1_BYPASS_AEQ, 24, 24), + [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1= _DAC_D1_BYPASS_AEQ, 16, 16), + [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1= _DAC_D1_BYPASS_AEQ, 8, 8), + [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1= _DAC_D1_BYPASS_AEQ, 0, 0), + [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1= _FE_PEACKING_CTRL_LSB, 24, 24), + [AN7581_PCS_RX_FE_VCM_GEN_PWDB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_F= E_VB_EQ1_EN, 24, 24), + + [AN7581_PCS_AEQ_OFORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE, = 16, 27), + [AN7581_PCS_RX_OSCAL_FORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL= _WATCH_WNDW, 16, 25), + + [AN7581_PCS_CDR_PD_EDGE_DIS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_= PICAL_CKD8_INV, 8, 8), + [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CD= R1_PD_PICAL_CKD8_INV, 0, 0), + + [AN7581_PCS_RX_DAC_MON] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_I= N_SR, 16, 20), + [AN7581_PCS_CDR_PR_XFICK_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_= MONPI_EN, 8, 8), + [AN7581_PCS_CDR_PR_MONPI_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_= MONPI_EN, 0, 0), + [AN7581_PCS_CDR_PR_MONPR_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_= COR_HBW_EN, 24, 24), + + [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_= 2L_RX1_REV_0, 24, 26), + [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_= 2L_RX1_REV_0, 20, 22), + [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX= 1_REV_0, 18, 19), + + [AN7581_PCS_CDR_LPF_TOP_LIM] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF= _RATIO, 8, 26), + [AN7581_PCS_CDR_LPF_RATIO] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_R= ATIO, 0, 1), + + [AN7581_PCS_CDR_PR_KBAND_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR= _BETA_DAC, 24, 26), + [AN7581_PCS_CDR_PR_BETA_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_= BETA_DAC, 16, 19), + [AN7581_PCS_CDR_PR_VCOADC_OS] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR= _BETA_DAC, 8, 11), + [AN7581_PCS_CDR_PR_BETA_DAC] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_= BETA_DAC, 0, 6), + [AN7581_PCS_CDR_PR_FBKSEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VR= EG_IBAND_VAL, 24, 25), + [AN7581_PCS_CDR_PR_DAC_BAND] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_= VREG_IBAND_VAL, 16, 20), + [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CD= R1_PR_VREG_IBAND_VAL, 8, 10), + [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CD= R1_PR_VREG_IBAND_VAL, 0, 2), + + [AN7581_PCS_RX_FE_VB_EQ3_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_V= B_EQ1_EN, 16, 16), + [AN7581_PCS_RX_FE_VB_EQ2_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_V= B_EQ1_EN, 8, 8), + [AN7581_PCS_RX_FE_VB_EQ1_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_V= B_EQ1_EN, 0, 0), + [AN7581_PCS_RX_FE_EQ_HZEN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_50O= HMS_SEL, 24, 24), + + [AN7581_PCS_CDR_PR_CAP_EN] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BU= F_IN_SR, 8, 8), + [AN7581_PCS_CDR_BUF_IN_SR] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BU= F_IN_SR, 0, 2), + + [AN7581_PCS_RX_SIGDET_VTH_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SI= GDET_NOVTH, 16, 20), + [AN7581_PCS_RX_SIGDET_PEAK] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDE= T_NOVTH, 8, 9), + [AN7581_PCS_RX_SIGDET_LPF_CTRL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_D= AC_RANGE_EYE, 24, 25), + + [AN7581_PCS_RX_TDC_CK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_= DIV, 24, 24), + [AN7581_PCS_RX_PHYCK_RSTB] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_= DIV, 16, 16), + [AN7581_PCS_RX_PHYCK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_D= IV, 8, 9), + [AN7581_PCS_RX_PHYCK_DIV] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_D= IV, 0, 7), + [AN7581_PCS_RX_PHY_CK_SEL_FORCE] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_= BUSBIT_SEL, 24, 24), + [AN7581_PCS_RX_PHY_CK_SEL] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT= _SEL, 16, 16), + + [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] =3D REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR= 1_PR_INJ_MODE, 24, 24), +}; + +static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + struct regmap_field **pcs_ana_fields =3D priv->pcs_ana_fields[index]; + struct regmap *pcs_pma; + u32 kband_vref; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + kband_vref =3D 0x10; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + kband_vref =3D 0xf; + break; + default: + return; + } + + /* This comment only apply to Serdes PCIe that expose + * 2 PCS. + * + * The Serdes PCIe expose 2 PCS but always require + * the PMA for the first PCS to be configured + * for correct functionality for JCPLL. + */ + pcs_pma =3D priv->pcs_pma[0]; + + /* Setup LDO */ + usleep_range(200, 300); + + regmap_field_set_bits(pcs_ana_fields[AN7581_PCS_JCPLL_SPARE_L], + AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO); + + /* Setup RSTB */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_RST_DLY], + AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_PLL_RSTB], 0x1); + + /* Enable PLL force selection and Force Disable */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN | + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN); + + /* Setup SDM */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_LS], + AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_EN], 0x0); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_OUT], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_ORD], + AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_MODE], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_IFM], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_HREN], 0x0); + + /* Setup SSC */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA], 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA1], 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PERIOD], 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_TRI_EN], 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_EN], 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PHASE_INI], 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0); + + /* Setup LPF */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IOFST], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IBIAS], 0x18); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_SHCK_EN], 0); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWR], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BP], 0x10); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BC], 0x1f); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BR], BIT(3) | BIT(= 1)); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWC], 0x0); + + /* Setup VCO */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_SCAPWR], 0x4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_HALFLSB_EN], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_CFIX], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0x= 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H], 0x= 3); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x3); + + /* Setup PCW */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW, + AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000)); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW); + + /* Setup DIV */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_POSTDIV_D5], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_MMD_PREDIV_MODE], + AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCODIV], + AIROHA_PCS_ANA_JCPLL_VCODIV_1); + + /* Setup KBand */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KS], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KF], 0x3); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KFC], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_DIV], 0x2); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_CODE], 0xe4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_OPTION], 0x0); + + /* Setup TCL */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_KBAND_VREF], + kband_vref); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_VREF], 0x5); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_GAIN], + AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_EN], 0x1); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_BW], + AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_EN], 0x1); + + /* Enable PLL */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN); + + /* Enale PLL Output */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN | + AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN); +} + +static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + struct regmap_field **pcs_ana_fields =3D priv->pcs_ana_fields[index]; + u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc; + struct regmap *pcs_pma; + u32 tcl_amp_vref; + bool sdm_hren; + u32 vco_cfix; + bool vcodiv; + u32 pcw; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + lpf_chp_ibias =3D 0xf; + lpf_bp =3D BIT(1); + lpf_bwr =3D BIT(3) | BIT(1) | BIT(0); + lpf_bwc =3D BIT(4) | BIT(3); + vco_cfix =3D BIT(1) | BIT(0); + pcw =3D BIT(27); + tcl_amp_vref =3D BIT(3) | BIT(1) | BIT(0); + vcodiv =3D false; + sdm_hren =3D false; + break; + case PHY_INTERFACE_MODE_2500BASEX: + lpf_chp_ibias =3D 0xa; + lpf_bp =3D BIT(2) | BIT(0); + lpf_bwr =3D 0; + lpf_bwc =3D 0; + vco_cfix =3D 0; + pcw =3D BIT(27) | BIT(25); + tcl_amp_vref =3D BIT(3) | BIT(2) | BIT(0); + vcodiv =3D true; + sdm_hren =3D false; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + lpf_chp_ibias =3D 0xf; + lpf_bp =3D BIT(1); + lpf_bwr =3D BIT(3) | BIT(1) | BIT(0); + lpf_bwc =3D BIT(4) | BIT(3); + vco_cfix =3D BIT(0); + pcw =3D BIT(27) | BIT(22); + tcl_amp_vref =3D BIT(3) | BIT(1) | BIT(0); + vcodiv =3D false; + sdm_hren =3D true; + break; + default: + return; + } + + /* This comment only apply to Serdes PCIe that expose + * 2 PCS. + * + * The Serdes PCIe expose 2 PCS but always require + * the PMA for the first PCS to be configured + * for correct functionality for TXPLL. + */ + pcs_pma =3D priv->pcs_pma[0]; + + /* Setup VCO LDO Output */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_VCO_OUT], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_OUT], 0x1); + + /* Setup RSTB */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_PLL_RSTB], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_RST_DLY], 0x4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_DIV], + AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_INTERNAL], 0x1); + + /* Enable PLL force selection and Force Disable */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN | + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN); + + /* Setup SDM */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_MODE], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_IFM], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_LS], + AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_EN], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_HREN], sdm_hren); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_OUT], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_ORD], + AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM); + + /* Setup SSC */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA1], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_TRI_EN], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PHASE_INI], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_EN], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PERIOD], 0x0); + + /* Setup LPF */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IBIAS], + lpf_chp_ibias); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IOFST], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BC], 0x1f); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BR], 0x5); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWC], lpf_bwc); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWR], lpf_bwr); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BP], lpf_bp); + + /* Setup VCO */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_CFIX], vco_cfix); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L], 0x= 0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H], 0x= 4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_TCLVAR], 0x4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_SCAPWR], 0x7); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_HALFLSB_EN], 0x1); + + /* Setup PCW */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW, + AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW); + + /* Setup KBand */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_CODE], 0xe4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_OPTION], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KS], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KF], 0x3); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KFC], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_DIV], 0x4); + + /* Setup DIV */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_POSTDIV_EN], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_MMD_PREDIV_MODE], + AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCODIV], + vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 : + AIROHA_PCS_ANA_TXPLL_VCODIV_1); + + /* Setup TCL */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_KBAND_VREF], 0xf); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_VREF], + tcl_amp_vref); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_GAIN], + AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_BW], + AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_EN], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_EN], 0x1); + + /* Enable PLL */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN); + + /* Enale PLL Output */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN | + AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN); +} + +static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + struct regmap_field **pcs_ana_fields =3D priv->pcs_ana_fields[index]; + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + u32 fir_cn1, fir_c0b, fir_c1; + u32 tx_rate_ctrl; + u32 ckin_divisor; + u32 xfi_tx_mode; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + ckin_divisor =3D BIT(1); + tx_rate_ctrl =3D BIT(0); + fir_cn1 =3D 0; + fir_c0b =3D 12; + fir_c1 =3D 0; + xfi_tx_mode =3D AIROHA_PCS_PMA_XFI_TX_MODE_1G25; + break; + case PHY_INTERFACE_MODE_2500BASEX: + ckin_divisor =3D BIT(2); + tx_rate_ctrl =3D BIT(0); + fir_cn1 =3D 0; + fir_c0b =3D 11; + fir_c1 =3D 1; + xfi_tx_mode =3D AIROHA_PCS_PMA_XFI_TX_MODE_3G12; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + ckin_divisor =3D BIT(2) | BIT(0); + tx_rate_ctrl =3D BIT(1); + fir_cn1 =3D 1; + fir_c0b =3D 1; + fir_c1 =3D 11; + xfi_tx_mode =3D AIROHA_PCS_PMA_XFI_TX_MODE_10G3; + break; + default: + return; + } + + /* Set TX rate ctrl */ + if (priv->data->port_type =3D=3D AIROHA_PCS_PCIE) { + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29, + AIROHA_PCS_PMA_2L_TX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_2L_TX_RATE_CTRL, + tx_rate_ctrl)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1, + AIROHA_PCS_PMA_XFI_TX_MODE, + xfi_tx_mode); + } else { + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL, + AIROHA_PCS_PMA_PON_TX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL, + tx_rate_ctrl)); + } + + /* Setup TX Config */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_DMEDGEGEN_EN], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_CKLDO_EN], 0x1); + + udelay(1); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL | + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL); + + /* FIXME: Ask Airoha TX term is OK to reset? */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR | + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL | + AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR, + ckin_divisor)); + + if (priv->data->port_type !=3D AIROHA_PCS_PCIE) { + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL | + AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL, + tx_rate_ctrl)); + } + + /* Setup TX FIR Load Parameters (Reference 660mV) */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1)); + + /* Reset TX Bar */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B, + AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B); +} + +static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + struct regmap_field **pcs_ana_fields =3D priv->pcs_ana_fields[index]; + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + u32 phyck_div, phyck_sel; + u32 pr_cdr_beta_dac; + u32 cdr_pr_buf_in_sr; + bool cdr_pr_cap_en; + u32 sigdet_vth_sel; + u32 rx_rate_ctrl; + u32 xfi_rx_mode; + u32 osr; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + osr =3D BIT(1) | BIT(0); /* 1.25G */ + pr_cdr_beta_dac =3D BIT(3); + rx_rate_ctrl =3D 0; + cdr_pr_cap_en =3D false; + cdr_pr_buf_in_sr =3D BIT(2) | BIT(1) | BIT(0); + sigdet_vth_sel =3D BIT(2) | BIT(1); + phyck_div =3D BIT(5) | BIT(3) | BIT(0); + phyck_sel =3D BIT(0); + xfi_rx_mode =3D AIROHA_PCS_PMA_XFI_RX_MODE_1G25; + break; + case PHY_INTERFACE_MODE_2500BASEX: + osr =3D BIT(0); /* 2.5G */ + pr_cdr_beta_dac =3D BIT(2) | BIT(1); + rx_rate_ctrl =3D 0; + cdr_pr_cap_en =3D true; + cdr_pr_buf_in_sr =3D BIT(2) | BIT(1); + sigdet_vth_sel =3D BIT(2) | BIT(1); + phyck_div =3D BIT(3) | BIT(1) | BIT(0); + phyck_sel =3D BIT(0); + xfi_rx_mode =3D AIROHA_PCS_PMA_XFI_RX_MODE_3G12; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + osr =3D 0; /* 10G */ + cdr_pr_cap_en =3D false; + pr_cdr_beta_dac =3D BIT(3); + rx_rate_ctrl =3D BIT(1); + cdr_pr_buf_in_sr =3D BIT(2) | BIT(1) | BIT(0); + sigdet_vth_sel =3D BIT(1); + phyck_div =3D BIT(6) | BIT(1); + phyck_sel =3D BIT(1); + xfi_rx_mode =3D AIROHA_PCS_PMA_XFI_RX_MODE_10G3; + break; + default: + return; + } + + /* Set RX rate ctrl */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2, + AIROHA_PCS_PMA_CK_RATE, + AIROHA_PCS_PMA_CK_RATE_10); + + if (priv->data->port_type =3D=3D AIROHA_PCS_PCIE) { + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29, + AIROHA_PCS_PMA_2L_RX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_2L_RX_RATE_CTRL, + rx_rate_ctrl)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1, + AIROHA_PCS_PMA_XFI_RX_MODE, + xfi_rx_mode); + } else { + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1, + AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, + rx_rate_ctrl)); + } + + /* Setup RX Path */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5, + AIROHA_PCS_PMA_FLL_IDAC_MIN | + AIROHA_PCS_PMA_FLL_IDAC_MAX, + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) | + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff)); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VCM_GEN_PWDB], 0x1); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1, + AIROHA_PCS_PMA_LCPLL_MAN_PWDB); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_AEQ_OFORCE], + AIROHA_PCS_ANA_AEQ_OFORCE_CTLE); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_OSCAL_FORCE], + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4, + AIROHA_PCS_PMA_DISB_BLWC_OFFSET); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL, + AIROHA_PCS_PMA_DISB_LEQ); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_PICAL_CKD8_INV], 0x0); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS, + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON | + AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON, + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL | + AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_MON], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_XFICK_EN], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPI_EN], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPR_EN], 0x0); + + /* Setup FE Gain and FE Peacking */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0)); + + /* Setup FE VOS */ + if (interface !=3D PHY_INTERFACE_MODE_USXGMII && + interface !=3D PHY_INTERFACE_MODE_10GBASER) + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS | + AIROHA_PCS_PMA_FORCE_DA_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0)); + + /* Setup FLL PR FMeter (no bypass mode)*/ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0, + AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1, + AIROHA_PCS_PMA_PLL_LOCK_TARGET_END | + AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) | + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3, + AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1)); + + /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */ + /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a t= ypo */ + /* Setup REV */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL], + BIT(2)); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL], + BIT(2)); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_SIGDET_ILEAK], 0x0); + + /* Setup Rdy Timeout */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5, + AIROHA_PCS_PMA_RX_RDY | + AIROHA_PCS_PMA_RX_BLWC_RDY_EN, + FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) | + FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5)); + + /* Setup CaBoundry Init */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0, + AIROHA_PCS_PMA_RX_OS_START | + AIROHA_PCS_PMA_OSC_SPEED_OPT, + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) | + AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6, + AIROHA_PCS_PMA_RX_OS_END, + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1, + AIROHA_PCS_PMA_RX_PICAL_END | + AIROHA_PCS_PMA_RX_PICAL_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4, + AIROHA_PCS_PMA_RX_SDCAL_END | + AIROHA_PCS_PMA_RX_SDCAL_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2, + AIROHA_PCS_PMA_RX_PDOS_END | + AIROHA_PCS_PMA_RX_PDOS_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3, + AIROHA_PCS_PMA_RX_FEOS_END | + AIROHA_PCS_PMA_RX_FEOS_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2)); + + /* Setup By Serdes*/ + /* Setup RX OSR */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED, + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL | + AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr)); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], !!osr); + + /* Setup CDR LPF Ratio */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_TOP_LIM], 0x20000); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_RATIO], osr); + + /* Setup CDR PR */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_KBAND_DIV], 0x4); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_SEL], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VCOADC_OS], 0x8); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_DAC], + pr_cdr_beta_dac); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_FBKSEL], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_DAC_BAND], + pr_cdr_beta_dac); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL], 0x6); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_IBAND_VAL], 0x6); + + /* Setup Eye Mon */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2, + AIROHA_PCS_PMA_EQ_DEBUG_SEL | + AIROHA_PCS_PMA_FOM_NUM_ORDER | + AIROHA_PCS_PMA_A_SEL, + FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) | + FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) | + FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2, + AIROHA_PCS_PMA_DATA_SHIFT | + AIROHA_PCS_PMA_EYECNT_FAST, + AIROHA_PCS_PMA_EYECNT_FAST); + + /* Calibration Start */ + + /* Enable SYS */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0, + AIROHA_PCS_PMA_RX_SYS_EN_SEL, + FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1)); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0, + AIROHA_PCS_PMA_SW_LCPLL_EN); + + usleep_range(500, 600); + + /* Setup FLL PR FMeter (bypass mode)*/ + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8, + AIROHA_PCS_PMA_DISB_FBCK_LOCK); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9, + AIROHA_PCS_PMA_FORCE_FBCK_LOCK); + + /* Enable CMLEQ */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_EQ_HZEN], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ3_EN], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ2_EN], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ1_EN], 0x1); + + /* Setup CDR PR */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_CAP_EN], + cdr_pr_cap_en); + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_BUF_IN_SR], + cdr_pr_buf_in_sr); + + /* Setup CDR xxx Pwdb, set force and disable */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN | + AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB | + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B | + AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0, + AIROHA_PCS_PMA_XPON_CDR_PD_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB | + AIROHA_PCS_PMA_XPON_RX_FE_PWDB); + + /* FIXME: Ask Airoha WHY it's cleared? */ + /* regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, + * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL); + */ + + /* Setup SigDet */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_VTH_SEL], + sigdet_vth_sel); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_PEAK], + BIT(1)); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_LPF_CTRL], + BIT(1) | BIT(0)); + + /* Disable SigDet Pwdb */ + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1, + AIROHA_PCS_PMA_RX_SIDGET_PWDB); + + /* Setup PHYCK */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_TDC_CK_SEL], 0x0); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_RSTB], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_SEL], + phyck_sel); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_DIV], + phyck_div); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL_FORCE], 0x1); + regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL], 0x0); + + usleep_range(100, 200); + + /* Enable CDR xxx Pwdb */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0, + AIROHA_PCS_PMA_XPON_CDR_PD_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB | + AIROHA_PCS_PMA_XPON_RX_FE_PWDB); + + /* Enable SigDet Pwdb */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1, + AIROHA_PCS_PMA_RX_SIDGET_PWDB); +} + +static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *p= riv, + int index, u32 cdr_pr_idac) +{ + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + u32 val =3D UINT_MAX; + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC, + cdr_pr_idac)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_FREQLOCK_DET_EN, + AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_FREQLOCK_DET_EN, + AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL); + + usleep_range(5000, 7000); + + regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val); + + return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val); +} + +static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv, + int index, u32 target_fl_out) +{ + unsigned int fl_out_diff =3D UINT_MAX; + unsigned int prcal_search; + u32 cdr_pr_idac =3D 0; + + for (prcal_search =3D 0; prcal_search < 8 ; prcal_search++) { + unsigned int fl_out_diff_new; + unsigned int fl_out; + u32 cdr_pr_idac_tmp; + + /* try to find the upper value by setting the last 3 bit */ + cdr_pr_idac_tmp =3D FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + prcal_search); + fl_out =3D an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new =3D abs_diff(fl_out, target_fl_out); + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new < fl_out_diff) { + cdr_pr_idac =3D cdr_pr_idac_tmp; + fl_out_diff =3D fl_out_diff_new; + } + } + + return cdr_pr_idac; +} + +static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, in= t index, + u32 target_fl_out, u32 cdr_pr_idac_major) +{ + unsigned int remaining_prcal_search_bits =3D 0; + u32 cdr_pr_idac =3D cdr_pr_idac_major; + unsigned int fl_out, fl_out_diff; + int best_prcal_search_bit =3D -1; + int prcal_search_bit; + + fl_out =3D an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac); + fl_out_diff =3D abs_diff(fl_out, target_fl_out); + + /* Deadline search part. + * We start from top bits to bottom as we progressively decrease the + * signal. + */ + for (prcal_search_bit =3D 7; prcal_search_bit >=3D 0; prcal_search_bit--)= { + unsigned int fl_out_diff_new; + u32 cdr_pr_idac_tmp; + + cdr_pr_idac_tmp =3D cdr_pr_idac | BIT(prcal_search_bit); + fl_out =3D an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new =3D abs_diff(fl_out, target_fl_out); + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new < fl_out_diff) { + best_prcal_search_bit =3D prcal_search_bit; + fl_out_diff =3D fl_out_diff_new; + } + } + + /* Set the idac with the best value we found and + * reset the search bit to start from bottom to top. + */ + if (best_prcal_search_bit >=3D 0) { + cdr_pr_idac |=3D BIT(best_prcal_search_bit); + remaining_prcal_search_bits =3D best_prcal_search_bit; + prcal_search_bit =3D 0; + } + + /* Fine tune part. + * Test remaining bits to find an even closer signal level to target + * by increasing the signal. + */ + while (remaining_prcal_search_bits) { + unsigned int fl_out_diff_new; + u32 cdr_pr_idac_tmp; + + cdr_pr_idac_tmp =3D cdr_pr_idac | BIT(prcal_search_bit); + fl_out =3D an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new =3D abs_diff(fl_out, target_fl_out); + /* Assume we found the deadline when the new absolue signal difference + * from target is greater than the previous and the difference is at + * least 10% greater between the old and new value. + * This is to account for signal detection level tollerance making + * sure we are actually over a deadline (AKA we are getting farther + * from target) + */ + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + + /* Exact match, set the bit and exit */ + if (!fl_out_diff_new) { + cdr_pr_idac |=3D BIT(prcal_search_bit); + break; + } + + if (fl_out_diff && fl_out_diff_new > fl_out_diff && + (abs_diff(fl_out_diff_new, fl_out_diff) * 100) / fl_out_diff > 10) { + /* Exit early if we are already at the deadline */ + if (prcal_search_bit =3D=3D 0) + break; + + /* We found the deadline, set the value to the previous + * bit, and reset the loop to fine tune with the + * remaining values. + */ + cdr_pr_idac |=3D BIT(prcal_search_bit - 1); + remaining_prcal_search_bits =3D prcal_search_bit - 1; + prcal_search_bit =3D 0; + } else { + /* Update the signal level diff and try the next bit */ + fl_out_diff =3D fl_out_diff_new; + + /* If we didn't found the deadline, set the last bit + * and reset the loop to fine tune with the remainig + * values. + */ + if (prcal_search_bit =3D=3D remaining_prcal_search_bits - 1) { + cdr_pr_idac |=3D BIT(prcal_search_bit); + remaining_prcal_search_bits =3D prcal_search_bit; + prcal_search_bit =3D 0; + } else { + prcal_search_bit++; + } + } + } + + return cdr_pr_idac; +} + +static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + struct regmap_field **pcs_ana_fields =3D priv->pcs_ana_fields[index]; + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + u32 cdr_pr_idac_major, cdr_pr_idac; + unsigned int fl_out, fl_out_diff; + + u32 target_fl_out; + u32 cyclecnt; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */ + case PHY_INTERFACE_MODE_1000BASEX: + target_fl_out =3D 0xa3d6; + cyclecnt =3D 32767; + break; + case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */ + target_fl_out =3D 0xa000; + cyclecnt =3D 20000; + break; + case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */ + case PHY_INTERFACE_MODE_10GBASER: + target_fl_out =3D 0x9edf; + cyclecnt =3D 32767; + break; + default: + return; + } + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_REF_RST_N); + + usleep_range(100, 200); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2, + AIROHA_PCS_PMA_LOCK_TARGET_END | + AIROHA_PCS_PMA_LOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1, + AIROHA_PCS_PMA_UNLOCK_CYCLECNT | + AIROHA_PCS_PMA_LOCK_CYCLECNT, + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_LOCK_UNLOCKTH | + AIROHA_PCS_PMA_LOCK_LOCKTH, + FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3)); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3, + AIROHA_PCS_PMA_UNLOCK_TARGET_END | + AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) | + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100)); + + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x1); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + /* Calibration logic: + * First check the major value by looping with every + * value in the last 3 bit of CDR_PR_IDAC. + * Get the signal level and save the value that is closer to + * the target. + * + * Then check each remaining 7 bits in search of the deadline + * where the signal gets farther than signal target. + * + * Finally fine tune for the remaining bits to find the one that + * produce the closest signal level. + */ + cdr_pr_idac_major =3D an7581_pcs_rx_prcal_idac_major(priv, index, target_= fl_out); + + cdr_pr_idac =3D an7581_pcs_rx_prcal_idac_minor(priv, index, + target_fl_out, cdr_pr_idac_major); + + fl_out =3D an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac); + fl_out_diff =3D abs_diff(fl_out, target_fl_out); + if (fl_out_diff > 100) { + u32 pr_idac_major =3D FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + cdr_pr_idac_major); + unsigned int fl_out_tmp, fl_out_diff_tmp; + u32 cdr_pr_idac_tmp; + + if (pr_idac_major > 0) { + cdr_pr_idac_tmp =3D FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + pr_idac_major - 1); + + dev_dbg(priv->dev, "Fl Out is %d far from target %d with Pr Idac %x. Tr= ying with Pr Idac %x.\n", + fl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp); + + cdr_pr_idac_tmp =3D an7581_pcs_rx_prcal_idac_minor(priv, index, + target_fl_out, + cdr_pr_idac_tmp); + + fl_out_tmp =3D an7581_pcs_apply_cdr_pr_idac(priv, index, + cdr_pr_idac_tmp); + fl_out_diff_tmp =3D abs_diff(fl_out_tmp, target_fl_out); + if (fl_out_diff_tmp < fl_out_diff) { + fl_out =3D fl_out_tmp; + fl_out_diff =3D fl_out_diff_tmp; + cdr_pr_idac =3D cdr_pr_idac_tmp; + } + } + } + dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, = fl_out); + if (fl_out_diff > 100) + dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate cali= bration.\n", + fl_out_diff, target_fl_out); + + /* Setup Load Band */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x0); + + /* Disable force of LPF C previously enabled */ + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_B, + AIROHA_PCS_PMA_LOAD_EN); + + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1, + AIROHA_PCS_PMA_LPATH_IDAC, + FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac)); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB); + + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_REF_RST_N); + + usleep_range(100, 200); +} + +/* This is used to both calibrate and lock to signal (after a previous + * calibration) after a global reset. + */ +static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, int index, + phy_interface_t interface, bool calibrate) +{ + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + + /* Setup LPF L2D force and disable */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA | + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA); + + /* Calibrate IDAC and setup Load Band */ + if (calibrate) + an7581_pcs_rx_prcal(priv, index, interface); + + /* Setup LPF RSTB force and disable */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB | + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB); + + usleep_range(700, 1000); + + /* Force Enable LPF RSTB */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB); + + usleep_range(100, 200); + + /* Force Enable LPF L2D */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA); + + /* Disable LPF RSTB force bit */ + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB); + + /* Disable LPF L2D force bit */ + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA); +} + +static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + int calibration_try =3D 0; + u32 val =3D 0; + + an7581_pcs_tx_bringup(priv, index, interface); + an7581_pcs_rx_bringup(priv, index, interface); + + usleep_range(100, 200); + +retry_calibration: + an7581_pcs_cdr_reset(priv, index, interface, priv->manual_rx_calib); + + /* Global reset clear */ + regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N | + AIROHA_PCS_PMA_SW_REF_RST_N | + AIROHA_PCS_PMA_SW_ALLPCS_RST_N | + AIROHA_PCS_PMA_SW_PMA_RST_N | + AIROHA_PCS_PMA_SW_TX_RST_N | + AIROHA_PCS_PMA_SW_RX_RST_N | + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N, + AIROHA_PCS_PMA_SW_REF_RST_N); + + usleep_range(100, 200); + + /* Global reset */ + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N | + AIROHA_PCS_PMA_SW_REF_RST_N | + AIROHA_PCS_PMA_SW_ALLPCS_RST_N | + AIROHA_PCS_PMA_SW_PMA_RST_N | + AIROHA_PCS_PMA_SW_TX_RST_N | + AIROHA_PCS_PMA_SW_RX_RST_N | + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N); + + usleep_range(5000, 7000); + + an7581_pcs_cdr_reset(priv, index, interface, false); + + /* Manual RX calibration is required only for SoC before E2 + * revision. E2+ SoC autocalibrate RX and only CDR reset is needed. + */ + if (!priv->manual_rx_calib) + return 0; + + /* It was discovered that after a global reset and auto mode gets + * actually enabled, the fl_out from calibration might change and + * might deviates a lot from the expected value it was calibrated for. + * To correctly work, the PCS FreqDet module needs to Lock to the fl_out + * (frequency level output) or no signal can correctly be transmitted. + * This is detected by checking the FreqDet module Lock bit. + * + * If it's detected that the FreqDet module is not locked, retry + * calibration. From observation on real hardware with a 10g SFP module, + * it required a maximum of an additional calibration to actually make + * the FreqDet module to lock. Try 10 times before failing to handle + * really strange case. + */ + regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val); + if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) { + if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) { + dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibrati= on try. PCS won't work.\n", + AIROHA_PCS_MAX_CALIBRATION_TRY); + return -EIO; + } + + calibration_try++; + + dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.= \n"); + goto retry_calibration; + } + + return 0; +} + +static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + an7581_pcs_jcpll_bringup(priv, index, interface); + + usleep_range(200, 300); + + an7581_pcs_txpll_bringup(priv, index, interface); + + usleep_range(200, 300); +} + +int an7581_pcs_bringup(struct airoha_pcs_priv *priv, int index, + phy_interface_t interface) +{ + struct regmap_field **pcs_ana_fields =3D priv->pcs_ana_fields[index]; + + /* Enable Analog Common Lane */ + regmap_field_write(pcs_ana_fields[AN7581_PCS_CMN_EN], 0x1); + + /* Setup PLL */ + an7581_pcs_pll_bringup(priv, index, interface); + + msleep(100); + + /* Setup PHYA */ + return an7581_pcs_phya_bringup(priv, index, interface); +} + +int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv, + int index, phy_interface_t interface) +{ + int ret; + + ret =3D phy_set_mode_ext(priv->phy, PHY_MODE_ETHERNET, interface); + if (ret) + return ret; + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) { + regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8, + AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR | + AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 | + AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, + FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) | + FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) | + FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3)); + + regmap_set_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6, + AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC); + } else { + regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6, + AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC); + } + + regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26, + AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, + AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32); + + regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24, + AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE); + + regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18, + AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, + FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1)); + + regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19, + AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE, + FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE, + FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV, + AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK))); + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11, + AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, + AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII); + else + regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11, + AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, + AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII); + + return 0; +} + +void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index) +{ + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + + /* Reset TXPCS on link up */ + regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N); + + usleep_range(100, 200); + + regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N); +} + +static int __an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv, = int index, + const struct reg_field *fields) +{ + struct device *dev =3D priv->dev; + int i; + + priv->pcs_ana_fields[index] =3D devm_kcalloc(dev, AN7581_PCS_FIELDS_MAX, + sizeof(*priv->pcs_ana_fields[index]), + GFP_KERNEL); + if (!priv->pcs_ana_fields[index]) + return -ENOMEM; + + for (i =3D 0; i < AN7581_PCS_FIELDS_MAX; i++) { + struct regmap_field *field; + + field =3D devm_regmap_field_alloc(dev, priv->pcs_ana, + fields[i]); + if (IS_ERR(field)) + return PTR_ERR(field); + + priv->pcs_ana_fields[index][i] =3D field; + } + + return 0; +} + +int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv) +{ + return __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_fields); +} + +int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv) +{ + int ret; + + ret =3D __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_pcie0_fields= ); + if (ret) + return ret; + + return __an7581_pcs_alloc_regmap_fields(priv, 1, an7581_pcs_pcie1_fields); +} + +static bool an7581_pcs_have_rx_signal(struct airoha_pcs_priv *priv, int in= dex) +{ + struct regmap *pcs_pma =3D priv->pcs_pma[index]; + unsigned int count =3D 0; + u32 val =3D 0; + int i; + + regmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0, + AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN); + + /* Scan 6 times for RX sigdet module to detect RX signal */ + for (i =3D 0; i < AIROHA_PCS_MAX_RX_SIGDET_TRY; i++) { + regmap_read(pcs_pma, AIROHA_PCS_PMA_DIG_RO_RESERVE_2, + &val); + if (val & AIROHA_PCS_RX_SIGDET) + count++; + } + + /* Consider signal presence if we detect signal at least 4 times */ + return count >=3D AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT; +} + +int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index) +{ + struct airoha_pcs_maps *maps =3D &priv->maps[index]; + u32 val =3D 0; + + /* Check if PCS is UP or Down */ + regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_STUS_1, &val); + if (val & AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP) + return 0; + + /* Validate if this is consistent with RX SigDet module */ + if (!an7581_pcs_have_rx_signal(priv, index)) + return 0; + + /* If PCS is down but RX SigDet module detected signal, + * trigger CDR reset. + */ + an7581_pcs_cdr_reset(priv, index, PHY_INTERFACE_MODE_NA, false); + + /* Report there is an error with Link Detection and we + * should test again later. + */ + return -EINVAL; +} --=20 2.53.0 From nobody Sat Sep 26 13:08:14 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77F344766A9 for ; Tue, 1 Sep 2026 08:30:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251450; cv=none; b=lg8Sn7jxn0EyTEuS8uvY0b7MuL6VuUh9LXWYX5/UdkmRnq8oVmNndbN0qnw1Bk+uKl9MAXj/OFPiut9mK0eZ40SihG94m15ze1NFuAOoC5n1SvKdGI0bniFTYRaqwB7nxCvEY3ezfUCpYcUfy1p3x1ZVbOOqKv4TXxSfmL7lm0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788251450; c=relaxed/simple; bh=1H2gh4N34JGclhfnudJ+lMU2aFBG3EaWcj6BA+jNZag=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=psPV8O/NpiQmihVRgfv+c3sYo7Zo4egrgd7TD8oez8NdeoeLJ4cOfzzJ/F4Fl+TN2qocHVDu3M7EglO6l5umnOwaMhtARL7MF5Rq/mi7h6yj/spQVIvwbJ6tCM7CTTV6ekGlG90AxinTj0g3kTZKLOT5lx3hAikCS3bHUEJyiB8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HoBm9R4L; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HoBm9R4L" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-49b9320423cso44162395e9.0 for ; Tue, 01 Sep 2026 01:30:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788251446; x=1788856246; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=Ux55P/eUqyNIOwazmon9Wlp3z9i89MIzAhLzSAAm5IY=; b=HoBm9R4LUbbr6MNLz95Cv+6VAYgxVptTUfXShk553UsfmMX9glvgZyC1aA7aWLdfwN Bpb2RWLFx/vjoJ/GbSbUc2TTQBPcMkqCUOr55KEcnQIIJdQ/bhWzXhz7mWwgxE59LaYF 0TRuwFBzq5eM5tMqozRCMdzAVDlpEa3ESJ5U8V/d/E0rY+1p0tfEKiF0VCZK87iogRDP oTTxLLXxmQHx6r6Ks8YkN4kvPlB3l2y4yfpbGIlEFM4+D27/ea7ZRaf8k37Ut1kwsZ4s 4MVeHKs+5vUm9iFKcn3Q53d3eeg3j5Ii4QnEXoX2jZjCbK+v1gRXX76ttikbJxLHxKWY Rbeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788251446; x=1788856246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=Ux55P/eUqyNIOwazmon9Wlp3z9i89MIzAhLzSAAm5IY=; b=TVewygG0hsLrcE9JsX+8LJ4JlENPR8NlvUDmZ2qVpAqEPN6IO01FUP5DdtykSs4x/o zRq/oxC1D7bQjAJTzsmF5EkFklWg6KDrDeVlY8PYQBs+u6U6qDo6nu5DYJFD6b+E+4Xc MHvfF1ci7zA5VOg5zRv3pBu2AbInlZJZp9zFeIbKVNnxxYJ3SGf6/l9wL1Fb+V4+yfmZ 7hjx15ogCdKmHlWt3zRc2pSGI/5IZCnAK6wNJ4EvrXMeUrNorJXinPl1oxDZ4dOewVC1 SHw2xdCobPTRimacU2XnBkan2hE4AA7xIyPBApD8SeixNsojK6C/nBLSf/sQWsqEWunU muBw== X-Forwarded-Encrypted: i=1; AHgh+RpzdppsFRhHM84ZjUIhWXAXzbfoc5hyJm7Cfs8qVPfeFXlMbsfAVDkYFZVfH6aObcSE3rl5ZJZF9uOAtR8=@vger.kernel.org X-Gm-Message-State: AFuF++mk4pnn9q4XbzRsmAi1y3GWNVEqDfAotaQovYk3LttDLKzdL+By uKGB5l/47HE4KwtJT4t7CtP2OyYoUySe8sYxlsVNmp3vZOQFhv2lssMX X-Gm-Gg: AR+sD13DObJGsk7TFYXTw4TAh8+tXVSpmAZup82pg8oZrb1r6zuMNpPmmjOHOTu4zNu Kz884INVOcfk3Pv6GBqo8wE7UoeU8MbuZiHlyNe+KcPafP8IAUpOsCL8Khu+4liGY4grD+b53p3 ugB+ieHUSsA9RwXnjhDXYoQyE77Soj7WJTjcu1Ex1A9zrInnTYeePX3Md3MnD+zrXjjgCdJzNtb nPSxziCkFSyxYDAGyQwrP85KCTK7JSghW5wY1CNCmhzUNYTfE32wp8LgeNddEpf3i25MD0PJbfu 1H4G3gBWPSwR82mjoknG+MVu43/YQIuaHO+vP0STaf8V5ucPDGtoWeE1vKaJlH0JtMkjHvsRurN keDw2DRJmBHFzL3J86QkDtRgKkTRIu5bogcNBr1vKGM0V6tVWqqCUu31ID8VMYFblfyCZD1PBE0 CqeudvQD5kBM1mFRj0Wf8b7GtjBx0lQPib/rHXS2ycg0Qac1F+F+gLN6C771I5ODkI3CZaoHmqp SQhumQidBLgmUiUcA6d/YJaJ4LqNdmkoK36wpTZBJiQNF1vjj26 X-Received: by 2002:a05:600c:34ce:b0:49b:9205:45b3 with SMTP id 5b1f17b1804b1-49cdc572c7dmr124020605e9.15.1788251445310; Tue, 01 Sep 2026 01:30:45 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-79-26-252-140.retail.telecomitalia.it. [79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:44 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 12/12] net: airoha: add phylink support Date: Tue, 1 Sep 2026 10:29:27 +0200 Message-ID: <20260901083001.8044-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add phylink support for each GDM port. For GDM1 add the internal interface mode as the only supported mode. For GDM2/3/4 add the required configuration of the PCS to make the external PHY or attached SFP cage work. These needs to be defined in the GDM port node using the pcs-handle property. Update and provide a .get/set_link_ksettings function that use phylink for ethtool OPs now that we fully support phylink. Signed-off-by: Christian Marangi Acked-by: Lorenzo Bianconi Tested-by: Zhengping Zhang --- drivers/net/ethernet/airoha/Kconfig | 2 + drivers/net/ethernet/airoha/airoha_eth.c | 199 +++++++++++++++++++++- drivers/net/ethernet/airoha/airoha_eth.h | 5 + drivers/net/ethernet/airoha/airoha_regs.h | 12 ++ 4 files changed, 215 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/air= oha/Kconfig index 1f6640a15fc9..5c54a07d2a76 100644 --- a/drivers/net/ethernet/airoha/Kconfig +++ b/drivers/net/ethernet/airoha/Kconfig @@ -20,6 +20,8 @@ config NET_AIROHA depends on NET_DSA || !NET_DSA select NET_AIROHA_NPU select PAGE_POOL + select PCS_AIROHA + select PHYLINK help This driver supports the gigabit ethernet MACs in the Airoha SoC family. diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/etherne= t/airoha/airoha_eth.c index 64619e9a704d..c3827bf9791b 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.c +++ b/drivers/net/ethernet/airoha/airoha_eth.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1915,10 +1916,18 @@ static int airoha_dev_open(struct net_device *netde= v) struct airoha_qdma *qdma; int err; =20 + err =3D phylink_of_phy_connect(dev->phylink, netdev->dev.of_node, 0); + if (err) { + netdev_err(netdev, "could not attach PHY: %d\n", err); + return err; + } + + phylink_start(dev->phylink); + netif_tx_start_all_queues(netdev); err =3D airoha_set_vip_for_gdm_port(dev, true); if (err) - return err; + goto err_phy_stop; =20 qdma =3D airoha_qdma_deref(dev); if (netdev_uses_dsa(netdev)) @@ -1938,6 +1947,13 @@ static int airoha_dev_open(struct net_device *netdev) pse_port); =20 return 0; + +err_phy_stop: + netif_tx_stop_all_queues(netdev); + phylink_stop(dev->phylink); + phylink_disconnect_phy(dev->phylink); + + return err; } =20 static int airoha_dev_stop(struct net_device *netdev) @@ -1945,6 +1961,8 @@ static int airoha_dev_stop(struct net_device *netdev) struct airoha_gdm_dev *dev =3D netdev_priv(netdev); struct airoha_gdm_port *port =3D dev->port; =20 + phylink_stop(dev->phylink); + netif_tx_disable(netdev); airoha_set_vip_for_gdm_port(dev, false); =20 @@ -1954,6 +1972,9 @@ static int airoha_dev_stop(struct net_device *netdev) airoha_set_gdm_port_fwd_cfg(dev->eth, REG_GDM_FWD_CFG(port->id), FE_PSE_PORT_DROP); + + phylink_disconnect_phy(dev->phylink); + return 0; } =20 @@ -2509,6 +2530,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *net= dev, } while (u64_stats_fetch_retry(&dev->stats.syncp, start)); } =20 +static int +airoha_ethtool_get_link_ksettings(struct net_device *netdev, + struct ethtool_link_ksettings *cmd) +{ + struct airoha_gdm_dev *dev =3D netdev_priv(netdev); + + return phylink_ethtool_ksettings_get(dev->phylink, cmd); +} + +static int +airoha_ethtool_set_link_ksettings(struct net_device *netdev, + const struct ethtool_link_ksettings *cmd) +{ + struct airoha_gdm_dev *dev =3D netdev_priv(netdev); + + return phylink_ethtool_ksettings_set(dev->phylink, cmd); +} + static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev, int channel, enum tx_sched_mode mode, const u16 *weights, u8 n_weights) @@ -3353,7 +3392,8 @@ static const struct ethtool_ops airoha_ethtool_ops = =3D { .get_drvinfo =3D airoha_ethtool_get_drvinfo, .get_eth_mac_stats =3D airoha_ethtool_get_mac_stats, .get_rmon_stats =3D airoha_ethtool_get_rmon_stats, - .get_link_ksettings =3D phy_ethtool_get_link_ksettings, + .get_link_ksettings =3D airoha_ethtool_get_link_ksettings, + .set_link_ksettings =3D airoha_ethtool_set_link_ksettings, .get_link =3D ethtool_op_get_link, }; =20 @@ -3409,6 +3449,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth, return false; } =20 +/* Nothing to do in MAC, everything is handled in PCS */ +static void airoha_mac_config(struct phylink_config *config, unsigned int = mode, + const struct phylink_link_state *state) +{ +} + +static void airoha_mac_link_up(struct phylink_config *config, struct phy_d= evice *phy, + unsigned int mode, phy_interface_t interface, + int speed, int duplex, bool tx_pause, bool rx_pause) +{ + struct airoha_gdm_dev *dev =3D container_of(config, struct airoha_gdm_dev, + phylink_config); + struct airoha_gdm_port *port =3D dev->port; + struct airoha_eth *eth =3D dev->eth; + u32 frag_size_tx, frag_size_rx; + + /* TX/RX frag is configured only for GDM4 */ + if (port->id !=3D AIROHA_GDM4_IDX) + return; + + switch (speed) { + case SPEED_10000: + case SPEED_5000: + frag_size_tx =3D 8; + frag_size_rx =3D 8; + break; + case SPEED_2500: + frag_size_tx =3D 2; + frag_size_rx =3D 1; + break; + default: + frag_size_tx =3D 1; + frag_size_rx =3D 0; + break; + } + + mutex_lock(&port->link_lock); + + /* Configure TX/RX frag based on speed */ + if (dev->nbq =3D=3D 1) { + airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, + GDM4_SGMII1_TX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK, + frag_size_tx)); + + airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, + GDM4_SGMII1_RX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK, + frag_size_rx)); + } else { + airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, + GDM4_SGMII0_TX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK, + frag_size_tx)); + + airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, + GDM4_SGMII0_RX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK, + frag_size_rx)); + } + + mutex_unlock(&port->link_lock); +} + +/* Nothing to do in MAC, everything is handled in PCS */ +static void airoha_mac_link_down(struct phylink_config *config, unsigned i= nt mode, + phy_interface_t interface) +{ +} + +static const struct phylink_mac_ops airoha_phylink_ops =3D { + .mac_config =3D airoha_mac_config, + .mac_link_up =3D airoha_mac_link_up, + .mac_link_down =3D airoha_mac_link_down, +}; + +static int airoha_fill_available_pcs(struct phylink_config *config, + struct phylink_pcs **available_pcs, + unsigned int num_possible_pcs) +{ + struct device *dev =3D config->dev; + + return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs, + num_possible_pcs); +} + +static int airoha_setup_phylink(struct net_device *netdev) +{ + struct airoha_gdm_dev *dev =3D netdev_priv(netdev); + struct device_node *np =3D netdev->dev.of_node; + struct airoha_gdm_port *port =3D dev->port; + struct phylink_config *config; + phy_interface_t phy_mode; + struct phylink *phylink; + int err; + + err =3D of_get_phy_mode(np, &phy_mode); + if (err) { + dev_err(&netdev->dev, "incorrect phy-mode\n"); + return err; + } + + config =3D &dev->phylink_config; + config->dev =3D &netdev->dev; + config->type =3D PHYLINK_NETDEV; + + /* + * GDM1 only supports internal for Embedded Switch + * and doesn't require a PCS. + */ + if (port->id =3D=3D AIROHA_GDM1_IDX) { + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10000FD; + + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + } else { + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | + MAC_2500FD | MAC_5000FD | MAC_10000FD; + + config->num_possible_pcs =3D fwnode_phylink_pcs_count(dev_fwnode(config-= >dev)); + config->fill_available_pcs =3D airoha_fill_available_pcs; + + __set_bit(PHY_INTERFACE_MODE_SGMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_USXGMII, + config->supported_interfaces); + + phy_interface_copy(config->pcs_interfaces, + config->supported_interfaces); + } + + phylink =3D phylink_create(config, of_fwnode_handle(np), + phy_mode, &airoha_phylink_ops); + if (IS_ERR(phylink)) + return PTR_ERR(phylink); + + dev->phylink =3D phylink; + + return 0; +} + static int airoha_alloc_gdm_device(struct airoha_eth *eth, struct airoha_gdm_port *port, int nbq, struct device_node *np) @@ -3474,7 +3663,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth = *eth, dev->nbq =3D nbq; port->devs[index] =3D dev; =20 - return 0; + return airoha_setup_phylink(netdev); } =20 static int airoha_alloc_gdm_port(struct airoha_eth *eth, @@ -3510,6 +3699,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *e= th, =20 port->id =3D id; spin_lock_init(&port->stats_lock); + mutex_init(&port->link_lock); eth->ports[p] =3D port; =20 err =3D airoha_metadata_dst_alloc(port); @@ -3706,6 +3896,8 @@ static int airoha_probe(struct platform_device *pdev) netdev =3D netdev_from_priv(dev); if (netdev->reg_state =3D=3D NETREG_REGISTERED) unregister_netdev(netdev); + if (dev->phylink) + phylink_destroy(dev->phylink); of_node_put(netdev->dev.of_node); } airoha_metadata_dst_free(port); @@ -3744,6 +3936,7 @@ static void airoha_remove(struct platform_device *pde= v) =20 netdev =3D netdev_from_priv(dev); unregister_netdev(netdev); + phylink_destroy(dev->phylink); of_node_put(netdev->dev.of_node); } airoha_metadata_dst_free(port); diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/etherne= t/airoha/airoha_eth.h index fa9a8edce22f..83daec003257 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.h +++ b/drivers/net/ethernet/airoha/airoha_eth.h @@ -595,6 +595,9 @@ struct airoha_gdm_dev { * QDMA migration. */ spinlock_t txq_lock[AIROHA_NUM_NETDEV_TX_RINGS]; + + struct phylink *phylink; + struct phylink_config phylink_config; }; =20 struct airoha_gdm_port { @@ -604,6 +607,8 @@ struct airoha_gdm_port { =20 /* protect concurrent hw_stats accesses */ spinlock_t stats_lock; + /* protect concurrent GDM4 register access */ + struct mutex link_lock; =20 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; }; diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethern= et/airoha/airoha_regs.h index 442b48c9b991..4ea89057b560 100644 --- a/drivers/net/ethernet/airoha/airoha_regs.h +++ b/drivers/net/ethernet/airoha/airoha_regs.h @@ -357,6 +357,18 @@ #define IP_FRAGMENT_PORT_MASK GENMASK(8, 5) #define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0) =20 +#define REG_FE_GDM4_TMBI_FRAG 0x2028 +#define GDM4_SGMII1_TX_WEIGHT_MASK GENMASK(31, 26) +#define GDM4_SGMII1_TX_FRAG_SIZE_MASK GENMASK(25, 16) +#define GDM4_SGMII0_TX_WEIGHT_MASK GENMASK(15, 10) +#define GDM4_SGMII0_TX_FRAG_SIZE_MASK GENMASK(9, 0) + +#define REG_FE_GDM4_RMBI_FRAG 0x202c +#define GDM4_SGMII1_RX_WEIGHT_MASK GENMASK(31, 26) +#define GDM4_SGMII1_RX_FRAG_SIZE_MASK GENMASK(25, 16) +#define GDM4_SGMII0_RX_WEIGHT_MASK GENMASK(15, 10) +#define GDM4_SGMII0_RX_FRAG_SIZE_MASK GENMASK(9, 0) + #define REG_MC_VLAN_EN 0x2100 #define MC_VLAN_EN_MASK BIT(0) =20 --=20 2.53.0