From nobody Sat Sep 26 13:46:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68332309EE2 for ; Tue, 1 Sep 2026 05:00:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788238820; cv=none; b=DKGm3RoGzndH+GmvDPreAX7ChFkb1CSnytZzo6izoblCHyTtkp4oPHiB0cibTnIqu91ItVgJyA6apDWdFXALyNMx6C+T/fmSiGIeZvfn4987QAzz6dgWzjD4CBR1Rkt8ofXqRRblQ98rQr9qqqEh1UZOhp+vK8eI9KoMk+/anIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788238820; c=relaxed/simple; bh=QvvHlpNsMHZYg0o05xxg11E/+PQv6nRN4oyH5aP5cos=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WAiEKkdVAosWL5RiXmL/iQnJp1pybKuPcZJwEaoOUbLG0f7MWYz4AC56CiTBC6KoGbJScQG18STlUUFbdR/lYwYO3OXJBvAqxzXtNIhLCdn8p8rw/jLh5rNIfkhta+9R3oqeD/O3sOlX8Rdg9buu8aueMp7NkMQZEV77D9prsKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QOhP9NRN; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QOhP9NRN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B216E1F000E9; Tue, 1 Sep 2026 05:00:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788238819; bh=nhbTlysx2qcUVkxU6t4jsy3LwWNBM53UJ2WzMWwNbCA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QOhP9NRNLVTyN8idbFPMJhE/NPWL7xHmjXnR2lrn3EwaFNcfRU2PSR9D/baB32atB dEeyj/+bx7Wi96PJG2870Nngq8W/rtW2KO6lAAa+vEVTK0lxMNpyYE4sACUg2N1rpE tc2qqJ5GeTaOcMb9ScdpxHqm5qnJzKbNiiMqUGRPVUj3dNOexMG9yOGP8Yzb5ddZCl j82J0NRwuyGisdgf7a/wZawcil19xyrN6xyozqwQyT0lzR3WanCkqF8ls3oYFgRp/x qGuA7SqrBSTsj8VupY31IhjaB1ufeP0/sS/cwpcoxGHpUxsVJs3T4bF8sFi+WOiM/J vx5CdKs35trWw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 1/3] riscv: word-at-a-time: improve find_zero() for !RISCV_ISA_ZBB Date: Tue, 1 Sep 2026 12:40:29 +0800 Message-ID: <20260901044032.5635-2-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260901044032.5635-1-jszhang@kernel.org> References: <20260901044032.5635-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current find_zero() heavily depends on fls64() for calculation. This bring non-optimal code when !RISCV_ISA_ZBB. But in word-at-a-time case, we don't have to go with fls64() code path, instead, we can fallback to the generic word-at-a-time implementaion. What's more, the fls64() brings non-necessary zero bits couting for RV32. In fact, fls() is enough. Before the patch: 0000000000000000 : 0: c529 beqz a0,4a <.L1> 2: 577d li a4,-1 4: 9301 srli a4,a4,0x20 6: 03f00793 li a5,63 a: 00a76463 bltu a4,a0,12 <.L3> e: 1502 slli a0,a0,0x20 10: 47fd li a5,31 0000000000000012 <.L3>: 12: 577d li a4,-1 14: 8341 srli a4,a4,0x10 16: 00a76463 bltu a4,a0,1e <.L4> 1a: 37c1 addiw a5,a5,-16 1c: 0542 slli a0,a0,0x10 000000000000001e <.L4>: 1e: 577d li a4,-1 20: 8321 srli a4,a4,0x8 22: 00a76463 bltu a4,a0,2a <.L5> 26: 37e1 addiw a5,a5,-8 28: 0522 slli a0,a0,0x8 000000000000002a <.L5>: 2a: 577d li a4,-1 2c: 8311 srli a4,a4,0x4 2e: 00a76463 bltu a4,a0,36 <.L6> 32: 37f1 addiw a5,a5,-4 34: 0512 slli a0,a0,0x4 0000000000000036 <.L6>: 36: 577d li a4,-1 38: 8309 srli a4,a4,0x2 3a: 00a76463 bltu a4,a0,42 <.L7> 3e: 37f9 addiw a5,a5,-2 40: 050a slli a0,a0,0x2 0000000000000042 <.L7>: 42: 00054563 bltz a0,4c <.L12> 46: 4037d51b sraiw a0,a5,0x3 000000000000004a <.L1>: 4a: 8082 ret 000000000000004c <.L12>: 4c: 2785 addiw a5,a5,1 4e: 4037d51b sraiw a0,a5,0x3 52: 8082 ret After the patch: 0000000000000000 : 0: 102037b7 lui a5,0x10203 4: 0792 slli a5,a5,0x4 6: 40578793 addi a5,a5,1029 # 10203405 <.L4+0x102033c5> a: 07c2 slli a5,a5,0x10 c: 60878793 addi a5,a5,1544 10: 02f50533 mul a0,a0,a5 14: 9161 srli a0,a0,0x38 16: 8082 ret 33 instructions vs 8 instructions! And this kind of instructions reducing dramatically improves the performance of below micro-benchmark: $ cat tt.c #inlcude #inlcude "word-at-a-time.h" // copy and modify, eg. remove other headers int main() { int i; unsigned long ret =3D 0; for (i =3D 0; i < 100000000; i++) ret |=3D find_zero(0xabcd123 + i); printf("%ld\n", ret); } $ gcc -O tt.c $ time ./a.out Per my test, the above micro-benchmark is improved by about 1150%! Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/a= sm/word-at-a-time.h index 3802cda71ab7..0c8a9b337f93 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -13,6 +13,9 @@ #include #include =20 +#if !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) +#include +#else struct word_at_a_time { const unsigned long one_bits, high_bits; }; @@ -47,6 +50,8 @@ static inline unsigned long find_zero(unsigned long mask) /* The mask we created is directly usable as a bytemask */ #define zero_bytemask(mask) (mask) =20 +#endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_= ZBB)) */ + #ifdef CONFIG_DCACHE_WORD_ACCESS =20 /* --=20 2.51.0 From nobody Sat Sep 26 13:46:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9FD8376483 for ; Tue, 1 Sep 2026 05:00:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788238824; cv=none; b=mNF8m9f8lQ8vVKJF9nH6HfFYvG644X/6ZUSY0AIoxYiK+UDhK6MJ9OGCQmppy7VWs4WEe9vBczkD6bmq+mxJtB+5ietgmKXCn6N1aleQgSHAqmWMM7Vy9E4EeC45vRsuDMovY6UejMVlKciQEh6kIW32WVPbO/1s9RTF+A2xmVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788238824; c=relaxed/simple; bh=jy33/Tc52BzbW3MkRv/+6XiOGSKTPkOy55r39xq3KKA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZDq/tdnKGOt5xNoDpROTkwv9q/P12PRT57+cwupO5hJyVJJNSoCdeIlVMXZqDnelP86DcuOZ7ga01WrZlz/rA7yZKIOluBwqtTmohyLtCIfsXP0NRxilK3MTu6iG44lf8kKWQ1bedlziuH08l9evoKCrzXhvkEBUeFhivBlBB0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GhggRRq7; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GhggRRq7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B170B1F00A3F; Tue, 1 Sep 2026 05:00:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788238822; bh=n3Q8RF4M/hgya8VOSqKUVI4WBX6zl6C8eGltqGxQCpU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=GhggRRq7EsKH9sMWM8k2d1uwhxzAJSJ9aPSF4BJYxuRYt9xWdzISSPhs89uRS9m/I zFMw5vieOpZtlT/2km9PpRFzZi43/8MhQPQgDLc6kKndW0NPTQspq0HjaeDVm4kDty r7KvqKrS/QPIybbO58rC3bcvQKJzqSsgZr3pqSEuwnEXh3l+RoMugsXeRjShgskpNO cdrjp59786xLx9ShpJ11UcCYfEo9E2LqmE467u2xZaKvTVlpso1VloBR458X9e6hwF KfV0OXJe9M7jtIUu0uJOAncLYVZKBaokwoNRaUmQX5up0dTbpzVBvLT7LG+tmdETfu ooqEcrsq7CTQQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 2/3] riscv: word-at-a-time: improve find_zero() without Zbb Date: Tue, 1 Sep 2026 12:40:30 +0800 Message-ID: <20260901044032.5635-3-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260901044032.5635-1-jszhang@kernel.org> References: <20260901044032.5635-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previous commit improved the find_zero() performance for !RISCV_ISA_ZBB. What about RISCV_ISA_ZBB=3Dy but the HW doesn't support Zbb? We have the same heavy generic fls64() issue. Let's improve this situation by checking Zbb extension and fall back to generic count_masked_bytes() if Zbb isn't supported. To remove non-necessary zero bits couting on RV32, we also replace the 'fls64(mask) >> 3' with '!mask ? 0 : ((__fls(mask) + 1) >> 3);' We will get similar performance improvement as previous commit for RISCV_ISA_ZBB=3Dy but HW doesn't support Zbb. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 29 ++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/a= sm/word-at-a-time.h index 0c8a9b337f93..ca3d30741ed1 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -42,9 +42,36 @@ static inline unsigned long create_zero_mask(unsigned lo= ng bits) return bits >> 7; } =20 +#ifdef CONFIG_64BIT +/* + * Jan Achrenius on G+: microoptimized version of + * the simpler "(mask & ONEBYTES) * ONEBYTES >> 56" + * that works for the bytemasks without having to + * mask them first. + */ +static inline long count_masked_bytes(unsigned long mask) +{ + return mask*0x0001020304050608ul >> 56; +} + +#else /* 32-bit case */ + +/* Carl Chatfield / Jan Achrenius G+ version for 32-bit */ +static inline long count_masked_bytes(long mask) +{ + /* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */ + long a =3D (0x0ff0001+mask) >> 23; + /* Fix the 1 for 00 case */ + return a & mask; +} +#endif + static inline unsigned long find_zero(unsigned long mask) { - return fls64(mask) >> 3; + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return !mask ? 0 : ((__fls(mask) + 1) >> 3); + + return count_masked_bytes(mask); } =20 /* The mask we created is directly usable as a bytemask */ --=20 2.51.0 From nobody Sat Sep 26 13:46:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 402AF38D3F2 for ; Tue, 1 Sep 2026 05:00:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788238826; cv=none; b=LA6EWmXxzABvIw60/3leWq7Sn+bzUImL0aYWDBgbB3tJqLsrqqGFmO7tlWkbryaQBrnR5YEa8ZVYfsSVnmgx8DsFLO7GW4edwXgaYnhpz2HxwrPaG+tgG8w1vkjLQJvqOSZ1dV7KhW/pz7Q2RhFyMX8/M0cLCpKyeFhJGePxuFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788238826; c=relaxed/simple; bh=uVtGUyIWHyjoUK8L0H3DB3EX/vfhDouF0fbHo6dDlXk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sSf1VCn5jMa6a080dzTgyADCyvTgJTkqT05nuPXc5qEqqCvlzLXYhcYvAS7B9XeI7SwZSD16cS3hrU8A38CCCnzyEs+Ql9zC+R82TkgGX+Hm4Q3ruYhsNPAZkEhSVtDLrgtoCaFTm+ni6msX9fHwmx01FQK4IShwLXSd4tZzMdc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KOFSeLal; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KOFSeLal" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53BA21F000E9; Tue, 1 Sep 2026 05:00:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788238825; bh=Ut/plU37hD5FU0JK0VZhhjzCZo1toEUrT5tdJhQhLbc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KOFSeLalu7RlfBOOrdjKw1xHW46q6Ara4dLGnjFHb/y9LUPjl7w/jLIp7kBS5yPtt 6gW/wiwq4QnKqTIkYGPZWydFVktDxG9Hu12pz9BqXsauMQAUinU7ToI7lw61BzQ5y+ Nxc3p/VYo7m9ZLPxtOxMGKhhnSe91z35LY914jieSEOXf0Wa3cdGMeHgMgXnG2LA/n uwFRKpCc1nWk6QDF9Tk0XMWLMWbCi3FRxwop+gRYZx02Q22t2frUl6w3Ol6zRZuPpz dnMWikyT+yRflAk0taclfza+VByoaU5305sHJNvr4KVxWE1tTg1czpP/u/eccPIYSe P+4JGkbpF7ApQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 3/3] riscv: word-at-a-time: improve find_zero() for Zbb Date: Tue, 1 Sep 2026 12:40:31 +0800 Message-ID: <20260901044032.5635-4-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260901044032.5635-1-jszhang@kernel.org> References: <20260901044032.5635-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In commit f915a3e5b018 ("arm64: word-at-a-time: improve byte count calculations for LE"), Linus improved the find_zero() for arm64 LE. Do the same optimization as he did: "do __ffs() on the intermediate value that found whether there is a zero byte, before we've actually computed the final byte mask.", so that we share the similar improvements: "The difference between the old and the new implementation is that "count_zero()" ends up scheduling better because it is being done on a value that is available earlier (before the final mask). But more importantly, it can be implemented without the insane semantics of the standard bit finding helpers that have the off-by-one issue and have to special-case the zero mask situation." Before the patch: 0000000000000000 : 0: c909 beqz a0,12 <.L1> 2: 60051793 clz a5,a0 6: 03f00513 li a0,63 a: 8d1d sub a0,a0,a5 c: 2505 addiw a0,a0,1 e: 4035551b sraiw a0,a0,0x3 0000000000000012 <.L1>: 12: 8082 ret After the patch: 0000000000000000 : 0: 60151513 ctz a0,a0 4: 810d srli a0,a0,0x3 6: 8082 ret 7 instructions vs 3 instructions! As can be seen, on RV64 w/ Zbb, the new "find_zero()" ends up just "ctz" plus the shift right that then ends up being subsumed by the "add to final length". But I have no HW platform which supports Zbb, so I can't get the performance improvement numbers by the last patch, only built and tested the patch on QEMU. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/a= sm/word-at-a-time.h index ca3d30741ed1..8c5ac6a72f7f 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -38,6 +38,9 @@ static inline unsigned long prep_zero_mask(unsigned long = val, =20 static inline unsigned long create_zero_mask(unsigned long bits) { + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return bits; + bits =3D (bits - 1) & ~bits; return bits >> 7; } @@ -69,13 +72,19 @@ static inline long count_masked_bytes(long mask) static inline unsigned long find_zero(unsigned long mask) { if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) - return !mask ? 0 : ((__fls(mask) + 1) >> 3); + return __ffs(mask) >> 3; =20 return count_masked_bytes(mask); } =20 -/* The mask we created is directly usable as a bytemask */ -#define zero_bytemask(mask) (mask) +static inline unsigned long zero_bytemask(unsigned long bits) +{ + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return bits; + + bits =3D (bits - 1) & ~bits; + return bits >> 7; +} =20 #endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_= ZBB)) */ =20 --=20 2.51.0