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[2.51.220.108]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b91c5790csm314541845e9.0.2026.09.01.08.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 08:33:24 -0700 (PDT) From: Alexey Charkov Date: Tue, 01 Sep 2026 19:33:11 +0400 Subject: [PATCH 1/4] nvmem: rockchip-otp: Serialize reads Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-rk3576-otp-cpuid-mac-v1-1-ea9135270fc2@flipper.net> References: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> In-Reply-To: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Michael Walle , Miquel Raynal , Finley Xiao , Greg Kroah-Hartman Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Alexey Charkov , stable@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2712; i=alchark@flipper.net; h=from:subject:message-id; bh=amm6IB2QVHQmS41llynjCeEO9qHZu2xpesEVqtnd22I=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWRN+2C3xbXrK4OeZYvDjPdrr1mZbp/St7fnwfTot49W3 TD5HCSf3jGRhUGMi8FSTJFl7rcltlON+Gbt8vD4CjOHlQlkiLRIAwMQsDDw5SbmlRrpGOmZahvq GRrpGOsYMXBxCsBUx35iZNibP3We43yhXZ16Wn+qpl7LuCJ44ZzTmxzTjRy/HlSF/clg+GfIZX2 of9I/hUiz98vtfcUeTXiyUHIf56ZrjJturNqyaAEPAA== X-Developer-Key: i=alchark@flipper.net; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 The OTP controller is driven through a single set of registers holding a state machine which has to be stepped through for every word read, yet nothing keeps two readers out of each other's way. Concurrent reads interleave, and the outcome is either a reader bailing out: rockchip-otp 2a580000.otp: timeout during read setup or, worse, one of them silently taking delivery of the other's data. Reading two cells in parallel from userspace on RK3576 reproduces both within 150 iterations - 53 read errors and 9 corrupted results, the latter either losing their first word or, in one case, ending in the two bytes which belong to the other reader's cell - whereas the same reads issued sequentially never fail. Concurrency is not hypothetical here, as six thermal sensors source their trim values from the OTP and reach the driver straight from asynchronous driver probing. Guard the read path with a mutex. Reads are the only way into the hardware, as the driver registers no write callback, and they always run in process context, so a plain mutex spanning the whole clock-enable, read, clock-disable sequence is enough. Fixes: 755864feb729 ("nvmem: add Rockchip OTP driver") Cc: stable@vger.kernel.org Signed-off-by: Alexey Charkov Reviewed-by: Miquel Raynal --- drivers/nvmem/rockchip-otp.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 2c0feb036f3f..b034b7455016 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +81,8 @@ struct rockchip_otp { void __iomem *base; struct reset_control *rst; const struct rockchip_data *data; + /* Serializes access to the OTP controller state machine */ + struct mutex mutex; struct clk_bulk_data clks[]; }; =20 @@ -272,6 +275,8 @@ static int rockchip_otp_read(void *context, unsigned in= t offset, if (!otp->data || !otp->data->reg_read) return -EINVAL; =20 + guard(mutex)(&otp->mutex); + ret =3D clk_bulk_prepare_enable(otp->data->num_clks, otp->clks); if (ret < 0) { dev_err(otp->dev, "failed to prepare/enable clks\n"); @@ -431,6 +436,11 @@ static int rockchip_otp_probe(struct platform_device *= pdev) =20 otp->data =3D data; otp->dev =3D dev; + + ret =3D devm_mutex_init(dev, &otp->mutex); + if (ret) + return ret; + otp->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(otp->base)) return dev_err_probe(dev, PTR_ERR(otp->base), --=20 2.54.0 From nobody Sat Sep 26 12:30:54 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC6D8436BEA for ; Tue, 1 Sep 2026 15:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788276811; cv=none; b=RqAqzIoO+JWmBqn8aPh6QujM4PPKgcSKAUpyN0UknN8TvbA5L08IwitNddLBeGu4btSbkWzu2/uylU2QkBhfsS/D3Rk5ch1qzTqnhN+bQIY9/dkou9klbsIuWqMm3eQ65KjdKYMKJLv+AAU6GFOvrw/kHRUys50m9LvsbIRbuZk= ARC-Message-Signature: i=1; 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[2.51.220.108]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b91c5790csm314541845e9.0.2026.09.01.08.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 08:33:27 -0700 (PDT) From: Alexey Charkov Date: Tue, 01 Sep 2026 19:33:12 +0400 Subject: [PATCH 2/4] dt-bindings: nvmem: layouts: Add Rockchip OTP CPUID layout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-rk3576-otp-cpuid-mac-v1-2-ea9135270fc2@flipper.net> References: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> In-Reply-To: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Michael Walle , Miquel Raynal , Finley Xiao , Greg Kroah-Hartman Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Alexey Charkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4722; i=alchark@flipper.net; h=from:subject:message-id; bh=gbqk612bcsgInYoFXSfKuUjKXJIWg/fCJSQ1WjRdZrs=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWRN+2D3v1K22fvkdJVbDxKZnF9mnVq/kkvolMicZTaX7 QIyz85f2TGRhUGMi8FSTJFl7rcltlON+Gbt8vD4CjOHlQlkiLRIAwMQsDDw5SbmlRrpGOmZahvq GRrpGOsYMXBxCsBU33nJ8D989rzHab8Fn9z54BMt9Uc94njWGqs9CbaFRes+XlHyaUtk+F+2+1e mt2/TpsJLnq5vdR7P/BB8z3CehuKO3MK4D/+aKhkA X-Developer-Key: i=alchark@flipper.net; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 Rockchip SoCs ship with a unique CPU ID programmed into their internal OTP memory, and Rockchip bootloaders derive Ethernet MAC addresses from it so that boards with no dedicated storage for one still get a stable address. Describe that derivation as an NVMEM layout, so that the resulting addresses become available through the standard nvmem "mac-address" cell whether or not the firmware got a chance to patch them into the device tree. Keep the compatible SoC specific, as the location of the CPU ID within the OTP memory differs between SoCs. Signed-off-by: Alexey Charkov --- .../bindings/nvmem/layouts/nvmem-layout.yaml | 1 + .../nvmem/layouts/rockchip,rk3576-otp-cpuid.yaml | 73 ++++++++++++++++++= ++++ MAINTAINERS | 6 ++ 3 files changed, 80 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.y= aml b/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml index 382507060651..ab94dbb41aac 100644 --- a/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml +++ b/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml @@ -21,6 +21,7 @@ oneOf: - $ref: fixed-layout.yaml - $ref: kontron,sl28-vpd.yaml - $ref: onie,tlv-layout.yaml + - $ref: rockchip,rk3576-otp-cpuid.yaml - $ref: u-boot,env.yaml =20 properties: diff --git a/Documentation/devicetree/bindings/nvmem/layouts/rockchip,rk357= 6-otp-cpuid.yaml b/Documentation/devicetree/bindings/nvmem/layouts/rockchip= ,rk3576-otp-cpuid.yaml new file mode 100644 index 000000000000..85153d480950 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/layouts/rockchip,rk3576-otp-c= puid.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/layouts/rockchip,rk3576-otp-cpuid= .yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVMEM layout of the CPU ID in Rockchip OTP memory + +maintainers: + - Alexey Charkov + +description: | + Rockchip SoCs are shipped with a unique CPU ID programmed into their + internal OTP memory. Rockchip bootloaders derive Ethernet MAC addresses + from it, so that boards which have no dedicated storage for a MAC address + still get a stable one. The addresses are computed by hashing the lowerc= ase + hexadecimal representation of the CPU ID with SHA-256 and taking the fir= st + six octets of the digest, with the multicast bit cleared and the locally + administered bit set. + + The location of the CPU ID within the OTP memory differs between SoCs, + hence the SoC specific compatible. + +select: false + +properties: + compatible: + const: rockchip,rk3576-otp-cpuid + + mac-address: + type: object + description: + MAC address derived from the CPU ID. The first argument of the phand= le + selects one of the two addresses that can be derived (can be 0 or 1). + + properties: + "#nvmem-cell-cells": + const: 1 + + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + otp@2a580000 { + compatible =3D "rockchip,rk3576-otp"; + reg =3D <0x0 0x2a580000 0x0 0x400>; + clocks =3D <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>; + clock-names =3D "otp", "apb_pclk", "phy"; + resets =3D <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; + reset-names =3D "otp", "apb"; + + nvmem-layout { + compatible =3D "rockchip,rk3576-otp-cpuid"; + + otp_mac_address: mac-address { + #nvmem-cell-cells =3D <1>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index b91655b34f0e..b35b3677bf0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23713,6 +23713,12 @@ F: Documentation/userspace-api/media/v4l/metafmt-r= kisp1.rst F: drivers/media/platform/rockchip/rkisp1 F: include/uapi/linux/rkisp1-config.h =20 +ROCKCHIP OTP CPUID NVMEM LAYOUT DRIVER +M: Alexey Charkov +L: linux-rockchip@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/nvmem/layouts/rockchip,rk3576-otp-cpu= id.yaml + ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT M: Daniel Golle M: Aurelien Jarno --=20 2.54.0 From nobody Sat Sep 26 12:30:54 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12D0D4398FD for ; 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[2.51.220.108]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b91c5790csm314541845e9.0.2026.09.01.08.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 08:33:30 -0700 (PDT) From: Alexey Charkov Date: Tue, 01 Sep 2026 19:33:13 +0400 Subject: [PATCH 3/4] nvmem: layouts: Add Rockchip OTP CPUID layout driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-rk3576-otp-cpuid-mac-v1-3-ea9135270fc2@flipper.net> References: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> In-Reply-To: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Michael Walle , Miquel Raynal , Finley Xiao , Greg Kroah-Hartman Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Alexey Charkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6571; i=alchark@flipper.net; h=from:subject:message-id; bh=d4EylAch0HWQDbh+CNZzCOo23MHWD8MSNDYCBCvHebw=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWRN+2C3Zn96lfC2ddusjhzeHOBsUORaZmnpK16kE6g0Z +mxD2usOiayMIhxMViKKbLM/bbEdqoR36xdHh5fYeawMoEMkRZpYAACFga+3MS8UiMdIz1TbUM9 QyMdYx0jBi5OAZjqwD6G//EB7Gmyp/qmnLr/U/nvXiVxvrbi6TXLfphyL7NdYiexvYXhn72f8gP bLZ1nlmj+vZ138NICg4lzq6KfXbKWZwzweK5/jRsA X-Developer-Key: i=alchark@flipper.net; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 Rockchip SoCs customarily use the CPU ID programmed into their on-chip OTP memory to derive stable Ethernet MAC addresses even when a board doesn't otherwise have dedicated storage for those. The derivation depends on the particular bootloader implementation (e.g. it is done by upstream U-Boot, which patches the derived MAC addresses at runtime into the device tree it hands to the kernel). Using less featureful bootloaders, such as direct boot to Linux from SPL, leaves the kernel with only a random MAC address instead, even though everything required for the derivation is equally available to Linux as it is to U-Boot. Reproduce the same derivation in the kernel and expose the result as an nvmem cell named "mac-address", so that of_get_mac_address() picks it up through its standard nvmem fallback. The address index comes from the DT phandle argument, which lets both interfaces of a dual Ethernet board share a single cell. Enable the layout by default on Rockchip, as consumers of its cells would otherwise defer their probe indefinitely. Signed-off-by: Alexey Charkov Reviewed-by: Miquel Raynal --- MAINTAINERS | 1 + drivers/nvmem/layouts/Kconfig | 13 ++++ drivers/nvmem/layouts/Makefile | 1 + drivers/nvmem/layouts/rockchip-otp-cpuid.c | 119 +++++++++++++++++++++++++= ++++ 4 files changed, 134 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b35b3677bf0b..ae98e1fc6121 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23718,6 +23718,7 @@ M: Alexey Charkov L: linux-rockchip@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/nvmem/layouts/rockchip,rk3576-otp-cpu= id.yaml +F: drivers/nvmem/layouts/rockchip-otp-cpuid.c =20 ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT M: Daniel Golle diff --git a/drivers/nvmem/layouts/Kconfig b/drivers/nvmem/layouts/Kconfig index 5e586dfebe47..6e2511ac6f7e 100644 --- a/drivers/nvmem/layouts/Kconfig +++ b/drivers/nvmem/layouts/Kconfig @@ -26,6 +26,19 @@ config NVMEM_LAYOUT_ONIE_TLV =20 If unsure, say N. =20 +config NVMEM_LAYOUT_ROCKCHIP_OTP_CPUID + tristate "Rockchip OTP CPU ID layout support" + default ARCH_ROCKCHIP + select CRYPTO_LIB_SHA256 + help + Say Y here if you want to expose the MAC addresses that Rockchip + bootloaders derive from the CPU ID programmed into the OTP memory of + Rockchip SoCs. Boards which have no other source of MAC addresses + need this to get stable ones when the bootloader does not patch them + into the device tree. + + If unsure, say N. + config NVMEM_LAYOUT_U_BOOT_ENV tristate "U-Boot environment variables layout" select CRC32 diff --git a/drivers/nvmem/layouts/Makefile b/drivers/nvmem/layouts/Makefile index dd6c6c70b1a9..a0ade4c22c79 100644 --- a/drivers/nvmem/layouts/Makefile +++ b/drivers/nvmem/layouts/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_NVMEM_LAYOUTS) +=3D fixed-layout.o obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) +=3D sl28vpd.o obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) +=3D onie-tlv.o +obj-$(CONFIG_NVMEM_LAYOUT_ROCKCHIP_OTP_CPUID) +=3D rockchip-otp-cpuid.o obj-$(CONFIG_NVMEM_LAYOUT_U_BOOT_ENV) +=3D u-boot-env.o diff --git a/drivers/nvmem/layouts/rockchip-otp-cpuid.c b/drivers/nvmem/lay= outs/rockchip-otp-cpuid.c new file mode 100644 index 000000000000..61f509c4a8cf --- /dev/null +++ b/drivers/nvmem/layouts/rockchip-otp-cpuid.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: 2026 Flipper FZCO +/* + * NVMEM layout for the CPU ID in Rockchip OTP memory + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ROCKCHIP_CPUID_LEN 16 + +struct rockchip_cpuid_data { + unsigned int offset; +}; + +static int rockchip_cpuid_mac_pp(void *priv, const char *id, int index, + unsigned int offset, void *buf, size_t bytes) +{ + char cpuid[ROCKCHIP_CPUID_LEN * 2]; + u8 digest[SHA256_DIGEST_SIZE]; + u8 *mac =3D buf; + + if (bytes !=3D ROCKCHIP_CPUID_LEN) + return -EINVAL; + + if (index < 0 || index > 1) + return -EINVAL; + + /* The buffer still holds the raw CPU ID at this point */ + bin2hex(cpuid, mac, ROCKCHIP_CPUID_LEN); + + sha256(cpuid, sizeof(cpuid), digest); + + memcpy(mac, digest, ETH_ALEN); + mac[0] &=3D 0xfe; /* clear the multicast bit */ + mac[0] |=3D 0x02; /* set the locally administered bit */ + mac[5] ^=3D index; + + if (!is_valid_ether_addr(mac)) + return -EINVAL; + + return 0; +} + +static int rockchip_cpuid_add_cells(struct nvmem_layout *layout) +{ + const struct rockchip_cpuid_data *data; + struct nvmem_cell_info info =3D {0}; + struct device_node *layout_np; + int ret; + + data =3D of_device_get_match_data(&layout->dev); + if (!data) + return -EINVAL; + + layout_np =3D of_nvmem_layout_get_container(layout->nvmem); + if (!layout_np) + return -ENOENT; + + info.name =3D "mac-address"; + info.offset =3D data->offset; + info.raw_len =3D ROCKCHIP_CPUID_LEN; + info.bytes =3D ETH_ALEN; + info.read_post_process =3D rockchip_cpuid_mac_pp; + info.np =3D of_get_child_by_name(layout_np, info.name); + + of_node_put(layout_np); + + ret =3D nvmem_add_one_cell(layout->nvmem, &info); + if (ret) + of_node_put(info.np); + + return ret; +} + +static int rockchip_cpuid_probe(struct nvmem_layout *layout) +{ + layout->add_cells =3D rockchip_cpuid_add_cells; + + return nvmem_layout_register(layout); +} + +static void rockchip_cpuid_remove(struct nvmem_layout *layout) +{ + nvmem_layout_unregister(layout); +} + +static const struct rockchip_cpuid_data rk3576_cpuid_data =3D { + .offset =3D 0x0a, +}; + +static const struct of_device_id rockchip_cpuid_of_match_table[] =3D { + { + .compatible =3D "rockchip,rk3576-otp-cpuid", + .data =3D &rk3576_cpuid_data, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, rockchip_cpuid_of_match_table); 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[2.51.220.108]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b91c5790csm314541845e9.0.2026.09.01.08.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 08:33:33 -0700 (PDT) From: Alexey Charkov Date: Tue, 01 Sep 2026 19:33:14 +0400 Subject: [PATCH 4/4] arm64: dts: rockchip: Derive GMAC MAC addresses from OTP on RK3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-rk3576-otp-cpuid-mac-v1-4-ea9135270fc2@flipper.net> References: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> In-Reply-To: <20260901-rk3576-otp-cpuid-mac-v1-0-ea9135270fc2@flipper.net> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Michael Walle , Miquel Raynal , Finley Xiao , Greg Kroah-Hartman Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Alexey Charkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2071; i=alchark@flipper.net; h=from:subject:message-id; bh=7ScGxa+8+RlYUQcbDyTy3K6G/E2mZ7i4yB4b0QAxXtI=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWRN+2Bn0+oxU6P3qU/7I7eGFXnGf49KT7dMO7uyUF1W6 rxyqMHyjoksDGJcDJZiiixzvy2xnWrEN2uXh8dXmDmsTCBDpEUaGICAhYEvNzGv1EjHSM9U21DP 0EjHWMeIgYtTAKa6W5zhn97ro1tSdDtDJG4wGubZej43tPqwU1bkr0wH95UzN2IYrzEyPHz0dy2 bQNfGDaf/3zEQnXryvurGjW8ropd8La2Y5dtUwAkA X-Developer-Key: i=alchark@flipper.net; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 Rockchip SoCs derive stable MAC addresses from the CPU ID in OTP memory, which a bootloader would normally process and patch the live device tree based on it. This depends on the particular bootloader implementation though, and the derivation itself is not described in the device tree. Add explicit nvmem layout for the CPU ID derived MAC addresses on RK3576, so that any OS can implement the same derivation without depending on the bootloader used. Boards which store a MAC address of their own can override the reference with a cell of their choosing. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index b0c0d3c8b1b1..0012b45ef426 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1845,6 +1845,8 @@ gmac0: ethernet@2a220000 { interrupts =3D , ; interrupt-names =3D "macirq", "eth_wake_irq"; + nvmem-cells =3D <&otp_mac_address 0>; + nvmem-cell-names =3D "mac-address"; power-domains =3D <&power RK3576_PD_SDGMAC>; resets =3D <&cru SRST_A_GMAC0>; reset-names =3D "stmmaceth"; @@ -1893,6 +1895,8 @@ gmac1: ethernet@2a230000 { interrupts =3D , ; interrupt-names =3D "macirq", "eth_wake_irq"; + nvmem-cells =3D <&otp_mac_address 1>; + nvmem-cell-names =3D "mac-address"; power-domains =3D <&power RK3576_PD_SDGMAC>; resets =3D <&cru SRST_A_GMAC1>; reset-names =3D "stmmaceth"; @@ -2131,6 +2135,14 @@ soc_tsadc_trim: soc-tsadc-trim@64 { reg =3D <0x64 0x2>; bits =3D <0 10>; }; + + nvmem-layout { + compatible =3D "rockchip,rk3576-otp-cpuid"; + + otp_mac_address: mac-address { + #nvmem-cell-cells =3D <1>; + }; + }; }; =20 sai0: sai@2a600000 { --=20 2.54.0