From nobody Sat Sep 26 13:18:34 2026 Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DD5F472795; Tue, 1 Sep 2026 08:48:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.206.16.166 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788252523; cv=none; b=N64Am0A14FavS7YFQe+ITQkGbHcEvDNGV50ntr76zpXF+slWdbfmUv65fELFOX7d5hq1wsiEvRD5etS/kNQv/UBJMh8kWwq8sKnVzPRdpYokgbdcTXzaojLdvAYIDwEn+KwrbA5SneD3SPSnTih6vorCQqrRKj8ZVwbC3blUEKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788252523; c=relaxed/simple; bh=Wk5sEMb9LINLsnrda5qnSjDz5LAieS2TldfVF54QzsA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dhx1NW9U7iskw37xKAaCQtY/LOiEQlo5wKjFf3LKUleDY+SEH+GZpd5I+o+1K9yP5z7MkrzXt7AR75Bv8KPhy0Nkv2oyRvZ8099dEf2FPT/Rbt59GR8ckezNnQnUVvbFDN/QrRrnnXuxIByViTj1hZmlOkJ92PK67bX2+KdMh1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.206.16.166 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip4t1788252492teff1807c X-QQ-Originating-IP: +RBFOTE4CvCvzCH75wZfmQq0Q2Rd0B2ygPN1I/8A7oo= Received: from [192.168.30.32] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 01 Sep 2026 16:48:09 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 12533345009795839515 EX-QQ-RecipientCnt: 29 From: Xilin Wu Date: Tue, 01 Sep 2026 16:47:54 +0800 Subject: [PATCH 1/6] PCI: of: Avoid config reads for disabled bridge nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-q8b-dts-v1-1-7de0b6a73d08@radxa.com> References: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> In-Reply-To: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> To: Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4411; i=sophon@radxa.com; h=from:subject:message-id; bh=Wk5sEMb9LINLsnrda5qnSjDz5LAieS2TldfVF54QzsA=; b=owGbwMvMwCVmdFg0fe08Iz/G02pJDFnTJjo35nxOY5ev1n+y+NXrkm8hi9RnvnNdnPRzwx72r sPFoWl2HaUsDGJcDLJiiiwK8Qxz2Stzrz0VK9WDmcPKBDKEgYtTACayIpLhv5vUeZPda9f1/b7Z FhYWWN3b9PFxYtj9lys/+H+4zLYjJpqR4ZTrcymxBRJ9dbVxESuYNBWnnNykN9mub8PjT78OH5n zmg8A X-Developer-Key: i=sophon@radxa.com; a=openpgp; fpr=205F009D07796DD6E516752E32C31567AD9E324E X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpip:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: NcVNg4YzPDc1xazVUX7u7R2D/hjsw+p7gtXqp1Yp0D8gsMLJM0ynnDmM lPWRmsH5fcE1/7K8dgx6KQvrv55kIaSLJI1CHnTvi3W7fk2x6gon6N0/CUfuUy9i6GqOgEk o1HH08rR7tt32TLyec9gG3zi5v3rzWG4oCjV+GS30fOWrORQEiTFAa29s0Zjkms68Q0DSTB bW3duGeky4rHRzdKaPOMvoy/SLwHIHAQCYuYONTk8NeSWoBKRIw4PqmirqxpdL/dM2OWz93 IydQHBW/4psIv+412e83lnimt8zyJ9WTsauc0/8QPrA4XiyP0bmF8zE4p0O7cmw7jo/lrdi TiIyKzXLil+qbajJkhr1ZYMbR9r5AfOjFEDAyoIx2Kxcg75ioAnZRTYnAsrHUZq2TXnRvfM Tyw81KBGqFAZvB6qJhl2Eb6IOyHG9UfbvtkCBpLi+diPLr/hFFPNwL2pwL/bTSwKOb/BB44 +eRbqZyUrKWx8xXmHNfYNslJjjxCvPF02mUA500rHLp+BkazFY9WzQ0n/rQSdddafyQvTO5 ZSUAcF+pz9hJO8kPMyi6sWhOLWuZron18J5ihw8fHwufDHrD2mkcBhtsDRe/TfW0PQJgMB5 hTBrhoKtBSNQCUf8E9Gc4ECU97+WWyjUbyC1QUAQOWyCUd+ODbO3kPoElk4XwXInAwYveCs n9Utj/NaJP9liRcwWpTVnGMnH9CKTVCth23JNIXnfHRdqn+fqqyVqZIEsAkkf5lVDC6Bmrw VCCGTWLfzB7uNdMii90g0ZDqSSMAaI5oZk75JjpKWg/nlVyjQcTBOiRNt/3vgFVEtLYhKH+ BNUUCvT8yd2LjVPRVDBymMQ7wBZ0CrOsBPSoz2gFYo7KH77kQnlepGvRsVmbinROFnSbHsG ULSdsNQT3It2bi/wUVeDw1SlO4DS9I0PJDHGDWn7Afuh7/93dLCPYjt4RiN/FZnx4sq78eC FvmSPeMBMfCXB1ciloD6NEpW7Mg0Ofqn2a7qCgWtNXYqdKA7ICO9SSFDHYYSdpa0n6PNjLx rborTfA0Tt9o7A8M1QPf0g1FIHHQWSRCJbJZbMHCLPOAXMqxOMSd9Tgjp2xDi+0hNoP3qxA f3HqozXluzgdNbt38AvIfY= X-QQ-XMRINFO: NyFYKkN4Ny6FuXrnB5Ye7Aabb3ujjtK+gg== X-QQ-RECHKSPAM: 0 The TC9563 PCI power-control driver powers off external downstream ports whose device tree nodes have status =3D "disabled". On the Radxa Dragon Q8B, reading the Vendor ID from one of these powered-off port functions during PCI enumeration raises an Arm SError instead of returning an all-ones PCI error response. This prevents the board from completing boot. Commit 1a8c251cff20 ("PCI: move OF status =3D "disabled" detection to dev->match_driver") made disabled PCI functions remain discoverable so PCI fixups can still be applied, while suppressing driver binding later. Preserve that behavior for endpoint functions. For an unavailable node describing a PCI-to-PCI bridge, however, the node also represents a subordinate bus that must not be enumerated. Check the device tree node before reading the Vendor ID and return a PCI error response without accessing config space when such a bridge is disabled. Functions not described by device tree and disabled endpoint functions remain discoverable. Signed-off-by: Xilin Wu Acked-by: Manivannan Sadhasivam Tested-by: Daniele Briguglio --- drivers/pci/of.c | 27 +++++++++++++++++++++++++-- drivers/pci/pci.h | 5 +++++ drivers/pci/probe.c | 5 +++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index a51dff91b196..37e9062065d7 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -24,8 +24,8 @@ * pci_set_of_node - Find and set device's DT device_node * @dev: the PCI device structure to fill * - * Returns 0 on success with of_node set or when no device is described in= the - * DT. Returns -ENODEV if the device is present, but disabled in the DT. + * Return: 0 on success with of_node set or when no device is described in= the + * DT. */ int pci_set_of_node(struct pci_dev *dev) { @@ -46,6 +46,29 @@ int pci_set_of_node(struct pci_dev *dev) return 0; } =20 +/** + * pci_of_device_skip_config_read - check whether to skip probing a PCI de= vice + * @bus: PCI bus to scan + * @devfn: device/function number to check + * + * Return: true only when firmware explicitly describes an unavailable PCI + * bridge/port node. Disabled endpoints remain discoverable so fixups stil= l run, + * while driver binding is suppressed later in pci_bus_add_device(). + */ +bool pci_of_device_skip_config_read(struct pci_bus *bus, unsigned int devf= n) +{ + if (!bus->dev.of_node) + return false; + + struct device_node *node __free(device_node) =3D + of_pci_find_child_device(bus->dev.of_node, devfn); + + if (!node || of_device_is_available(node)) + return false; + + return of_node_is_type(node, "pci"); +} + void pci_release_of_node(struct pci_dev *dev) { of_node_put(dev->dev.of_node); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index ba3c3fddddc2..7cb1d04d947d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1244,6 +1244,7 @@ u32 of_pci_get_slot_power_limit(struct device_node *n= ode, u8 *slot_power_limit_scale); bool of_pci_preserve_config(struct device_node *node); int pci_set_of_node(struct pci_dev *dev); +bool pci_of_device_skip_config_read(struct pci_bus *bus, unsigned int devf= n); void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); @@ -1284,6 +1285,10 @@ static inline bool of_pci_preserve_config(struct dev= ice_node *node) } =20 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } +static inline bool pci_of_device_skip_config_read(struct pci_bus *bus, uns= igned int devfn) +{ + return false; +} static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { } static inline void pci_release_bus_of_node(struct pci_bus *bus) { } diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 27008e2ea5af..ce29bf78a6f7 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2586,6 +2586,11 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_b= us *bus, int devfn, u32 *l, bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, int timeout) { + if (pci_of_device_skip_config_read(bus, devfn)) { + PCI_SET_ERROR_RESPONSE(l); + return false; + } + return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); } EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); --=20 2.55.0 From nobody Sat Sep 26 13:18:34 2026 Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D349642AFAC; Tue, 1 Sep 2026 08:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.254.200.92 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788252524; cv=none; b=fWeC0rGxmTLY5v+J/NSX2CsB0+iyDKkFXX+ZCYoJsVcIH8wurupNFIisAhBBV5fU0KAMIWjDNVEqp9gjRyM1BZDQd414V8hw4nn/gYruS26XFajUHUHTkNFBXW8q8u3jXzT3eWWfqGammc9C763btQw/mJyCShBK5tK3k7Fiim4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788252524; c=relaxed/simple; bh=P3ecEwYp+pJD3fXjF69gnodv/MTSj8RHD4NMUnKFiTY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=APZhnjeuW8PElJjFXR1eyS00ebHEFo3vHT9TYCtaAihM3niRdudHHFpJudOIlHTduViyd3RNnOfdJZGOUKpSUg7jQYNBSP/aGLvw+5caOO1+Vcvx4kwdUl9GYyvfdMkDF4jkxG5Vo5nilR/qaaPYdZ1EW3WNrh25bdwbSjjNg/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.254.200.92 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip4t1788252496tc46f9645 X-QQ-Originating-IP: jAnARFYDdwVi32JHsYFw7EMsDCDcE2uzlE6/Bqeumrw= Received: from [192.168.30.32] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 01 Sep 2026 16:48:13 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 12420683238229624417 EX-QQ-RecipientCnt: 29 From: Xilin Wu Date: Tue, 01 Sep 2026 16:47:55 +0800 Subject: [PATCH 2/6] dt-bindings: display: bridge: simple: document Chrontel CH7218A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-q8b-dts-v1-2-7de0b6a73d08@radxa.com> References: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> In-Reply-To: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> To: Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1112; i=sophon@radxa.com; h=from:subject:message-id; bh=P3ecEwYp+pJD3fXjF69gnodv/MTSj8RHD4NMUnKFiTY=; b=owGbwMvMwCVmdFg0fe08Iz/G02pJDFnTJjqrR7AfSJUq63m/46MtbyfjrqBA3RJ1i5436+P7X zzrCD7XUcrCIMbFICumyKIQzzCXvTL32lOxUj2YOaxMIEMYuDgFYCKmpxgZTk3XVrj9d8+Ohe1R f3lPdVcH9574uP6diM3a/ze//y84LMvwV/aDOFu6avDN2KbTmzV8L6bzmmucncLNxTn3Z5iR9VQ 1BgA= X-Developer-Key: i=sophon@radxa.com; a=openpgp; fpr=205F009D07796DD6E516752E32C31567AD9E324E X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpip:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: OVJbsmpLzkvU+Q5zV8GvobH99npAwRLgWGjh8KR84TVil4V/FItqOoOR ccBCfwdxwVsiBNyi5fONNdVrwWASv5F/LKEIJmLRXuDJ8/kuljvQfzaQ688OVpeOjWGpltG l7Yos5Kne1GEWBkXSvmMHz7/8YOgiCWlFJjBndYFAoW0Npb4nLJrOQNr2CNqdeFH7ILdNyn tJHcXIp9y7PsGpF8hads3sapzuY+i18+WQg9pUNOk0LpD5kCBwAjf8lNYJgkwz6GyRMm3tS rvGT/kYmyK11JWZuf82mXZvipqruxWlZjwWoOZAXTlDLdnZCY0GPccp5Dr4rA9Bb8A66Nf4 hHfRo6OYBUM9gt0Gjc9mflJ//QosEnM+K7LxFKwWG7iADaTHFBrWpt7euotQmgOwFWDWs9q TO1Ob0RXMw/gvnt2otQigXkBsMQtNyckfdPsEYFJxkuZqhUaDNdDF/6/c8Gu556sTt8ahjs IQVbrfYWtUPhiM7yRRSMGjOmPjte/davWuywEPC56hy76Mf9OnaQuwQtmqXyi4Q+I/DmlYn +TfytXFRloZGHNe+gN4VKxteOKj5rrqOH+jvwRYzyV9wbx26SokvkAEjTqvXDmb1lRGC52I M8Q7DdMMDuljPYuGjW+TaByUn5OBwNvMunuJmUGLl5WMPHhvQh9Lz7wcjXrNyFs81D7kmt2 Hp67c4GD3FbfnuF7+a1JD1nMRvHWPGS5nYooI7EsNC47nJ+L06+iOM5gHKooHIraKPUSnrI osYq1J46aI1H020jwkgrLnZIqb1jMAQQxNtQNSgpEHog5w81FIVAhlNiCaK+DcP5xR98Li5 4E/aa4EbGgWhObYULU8Uo9GR8m8XFxBTemKwFWprSrj9rPONH97sFvcCvsNensodvcmbM1F BIq7HTfyCWw6ZXBdaLRVrR+WrZDvRiOrFCJyDLaUUGwmvAwVP5zGphpicNU2pV2DOrA3n2B k+jgH8mUI0U7tYEYJtAmpaVeFxCmwY8WO7R2t2moXaywXg7Rr7yxPPNlmPM9mTxQ6QrivlE WZ3HUPJNrQ5WToO1wH4dnAK2GuAkj9akEZYtdDTwZnocaklc8DfHd55KjNyrwkHRZYjP2Bu 1nWl3cvPX5K X-QQ-XMRINFO: NS+P29fieYNwqS3WCnRCOn9D1NpZuCnCRA== X-QQ-RECHKSPAM: 0 The Chrontel CH7218A is a DisplayPort 1.4 to HDMI 2.1 protocol converter. The device contains an embedded microcontroller and on-chip flash. It automatically boots its firmware and requires no host-side configuration for the on-board use case, so it can be represented by the simple bridge binding. Document the chrontel,ch7218a compatible. Signed-off-by: Xilin Wu Acked-by: Krzysztof Kozlowski Tested-by: Daniele Briguglio --- Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge= .yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index 7636c24906ba..9e0e7e09774e 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -29,6 +29,7 @@ properties: - adi,adv7123 - algoltek,ag6311 - asl-tek,cs5263 + - chrontel,ch7218a - dumb-vga-dac - mstar,tsumu88adt3-lf-1 - parade,ps185hdm --=20 2.55.0 From nobody Sat Sep 26 13:18:34 2026 Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A78A47253F; Tue, 1 Sep 2026 08:48:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip4t1788252501teb53240c X-QQ-Originating-IP: 0mYgCpomsnDKbD+h2k+lHMBtEyjIbP0NaGhFxfccFrA= Received: from [192.168.30.32] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 01 Sep 2026 16:48:18 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 3973929460923786869 EX-QQ-RecipientCnt: 29 From: Xilin Wu Date: Tue, 01 Sep 2026 16:47:56 +0800 Subject: [PATCH 3/6] drm/bridge: simple: add Chrontel CH7218A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-q8b-dts-v1-3-7de0b6a73d08@radxa.com> References: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> In-Reply-To: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> To: Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Add the CH7218A to the simple bridge driver and expose its output as an HDMI Type-A connector. Signed-off-by: Xilin Wu Tested-by: Daniele Briguglio --- drivers/gpu/drm/bridge/simple-bridge.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/bridge/simple-bridge.c b/drivers/gpu/drm/bridg= e/simple-bridge.c index 3fba7002322e..fab793fb12b5 100644 --- a/drivers/gpu/drm/bridge/simple-bridge.c +++ b/drivers/gpu/drm/bridge/simple-bridge.c @@ -275,6 +275,11 @@ static const struct of_device_id simple_bridge_match[]= =3D { .data =3D &(const struct simple_bridge_info) { .connector_type =3D DRM_MODE_CONNECTOR_HDMIA, }, + }, { + .compatible =3D "chrontel,ch7218a", + .data =3D &(const struct simple_bridge_info) { + .connector_type =3D DRM_MODE_CONNECTOR_HDMIA, + }, }, { .compatible =3D "mstar,tsumu88adt3-lf-1", .data =3D &(const struct simple_bridge_info) { --=20 2.55.0 From nobody Sat Sep 26 13:18:34 2026 Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C71704766B6; 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dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip4t1788252505te49710af X-QQ-Originating-IP: j0zn8JV8YG2Na5F1kBXtTpcNGNwxlSCLn2r/eXAtkZE= Received: from [192.168.30.32] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 01 Sep 2026 16:48:22 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 8002565544933552914 EX-QQ-RecipientCnt: 29 From: Xilin Wu Date: Tue, 01 Sep 2026 16:47:57 +0800 Subject: [PATCH 4/6] dt-bindings: arm: qcom: document Radxa Dragon Q8B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-q8b-dts-v1-4-7de0b6a73d08@radxa.com> References: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> In-Reply-To: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> To: Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Document its radxa,dragon-q8b compatible. Signed-off-by: Xilin Wu Acked-by: Krzysztof Kozlowski Tested-by: Daniele Briguglio --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index ff8a35df7862..4341bb04f912 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -902,6 +902,7 @@ properties: - microsoft,blackrock - qcom,sc8280xp-crd - qcom,sc8280xp-qrd + - radxa,dragon-q8b - const: qcom,sc8280xp =20 - items: --=20 2.55.0 From nobody Sat Sep 26 13:18:34 2026 Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C13E6473C86; Tue, 1 Sep 2026 08:48:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.254.200.92 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip4t1788252509t94851027 X-QQ-Originating-IP: lIvP1GpVQQqw+C7jJ6FIpBcVY6xKxry0TN9Yl3JnFvM= Received: from [192.168.30.32] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 01 Sep 2026 16:48:27 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 16756156345845701689 EX-QQ-RecipientCnt: 29 From: Xilin Wu Date: Tue, 01 Sep 2026 16:47:58 +0800 Subject: [PATCH 5/6] dt-bindings: pinctrl: qcom,sc8280xp-tlmm: allow gpio-line-names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-q8b-dts-v1-5-7de0b6a73d08@radxa.com> References: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> In-Reply-To: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> To: Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Allow boards to provide descriptive names for these lines and constrain the list to the number of GPIOs exposed by the controller. Signed-off-by: Xilin Wu Acked-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Linus Walleij Tested-by: Daniele Briguglio --- Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.y= aml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml index ed344deaf8b9..ebc3a8b34a4c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml @@ -27,6 +27,9 @@ properties: =20 gpio-reserved-ranges: true =20 + gpio-line-names: + maxItems: 230 + patternProperties: "-state$": oneOf: --=20 2.55.0 From nobody Sat Sep 26 13:18:34 2026 Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F38947277C; 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dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip4t1788252514t4a4e009b X-QQ-Originating-IP: RPLr4mZy/4rlTXzR1f5gn5xScXRfE6qJM5MajJqaFE8= Received: from [192.168.30.32] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 01 Sep 2026 16:48:31 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 15032415479306263874 EX-QQ-RecipientCnt: 29 From: Xilin Wu Date: Tue, 01 Sep 2026 16:47:59 +0800 Subject: [PATCH 6/6] arm64: dts: qcom: sc8280xp: add Radxa Dragon Q8B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-q8b-dts-v1-6-7de0b6a73d08@radxa.com> References: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> In-Reply-To: <20260901-q8b-dts-v1-0-7de0b6a73d08@radxa.com> To: Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Describe the following hardware: - UFS and microSD storage - Two M.2 M-key PCIe connectors - An M.2 E-key connector for Wi-Fi and Bluetooth - The QPS615 PCIe switch and its downstream topology - Two USB-C ports with DisplayPort alternate mode - USB Type-A ports - HDMI 2.1 output through the Chrontel CH7218A bridge - WCD9385 headset audio - GPU, video, ADSP and CDSP remote processors - RTC, EEPROM, thermal sensors and the 40-pin expansion header Co-developed-by: Stephen Chen Signed-off-by: Stephen Chen Co-developed-by: Junhao Xie Signed-off-by: Junhao Xie Signed-off-by: Xilin Wu Tested-by: Daniele Briguglio --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts | 2097 ++++++++++++++++= ++++ 2 files changed, 2099 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 1c86e7e98f55..34244354ba75 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -299,6 +299,8 @@ sc8280xp-microsoft-arcata-el2-dtbs :=3D sc8280xp-micros= oft-arcata.dtb sc8280xp-el2 dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-microsoft-arcata.dtb sc8280xp-micros= oft-arcata-el2.dtb sc8280xp-microsoft-blackrock-el2-dtbs :=3D sc8280xp-microsoft-blackrock.dt= b sc8280xp-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-microsoft-blackrock.dtb sc8280xp-mic= rosoft-blackrock-el2.dtb +sc8280xp-radxa-dragon-q8b-el2-dtbs :=3D sc8280xp-radxa-dragon-q8b.dtb sc82= 80xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-radxa-dragon-q8b.dtb sc8280xp-radxa-= dragon-q8b-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm450-lenovo-tbx605f.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm450-motorola-ali.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts b/arch/= arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts new file mode 100644 index 000000000000..1c0e94bba4d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts @@ -0,0 +1,2097 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include + +#include "sc8280xp.dtsi" +#include "sc8280xp-pmics.dtsi" + +/delete-node/ &pil_video_mem; +/delete-node/ &pil_nsp1_mem; +/delete-node/ &remoteproc_nsp1; + +/ { + model =3D "Radxa Dragon Q8B"; + compatible =3D "radxa,dragon-q8b", "qcom,sc8280xp"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart17; + serial1 =3D &uart2; + }; + + wcd938x: audio-codec { + compatible =3D "qcom,wcd9385-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + reset-gpios =3D <&tlmm 106 GPIO_ACTIVE_LOW>; + + vdd-buck-supply =3D <&vreg_s10b>; + vdd-rxtx-supply =3D <&vreg_s10b>; + vdd-io-supply =3D <&vreg_s10b>; + vdd-mic-bias-supply =3D <&vreg_bob>; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + qcom,hphl-jack-type-normally-closed; + + #sound-dai-cells =3D <1>; + }; + + hdmi-bridge { + compatible =3D "chrontel,ch7218a"; + + vdd-supply =3D <&vcc_5v_s>; + + pinctrl-0 =3D <&dp_hpd_default>; + pinctrl-names =3D "default"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint =3D <&mdss0_dp2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + hdmi_bridge_frl_out: endpoint { + remote-endpoint =3D <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con: endpoint { + remote-endpoint =3D <&hdmi_bridge_frl_out>; + }; + }; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adp12v_voltage 0>; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-0 =3D <&user_led>; + pinctrl-names =3D "default"; + + user-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + nvme-connector { + compatible =3D "pcie-m2-m-connector"; + vpcie3v3-supply =3D <&vcc_nvme_3v3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nvme_pcie_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie2a_ep>; + }; + }; + }; + }; + + nvme2-connector { + compatible =3D "pcie-m2-m-connector"; + vpcie3v3-supply =3D <&vcc_nvme2_3v3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nvme2_pcie_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie3b_ep>; + }; + }; + }; + }; + + pmic-glink { + compatible =3D "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 166 GPIO_ACTIVE_HIGH>, + <&tlmm 49 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint =3D <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_con0_ss: endpoint { + remote-endpoint =3D <&usb_0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_con0_sbu: endpoint { + remote-endpoint =3D <&usb0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + + pmic_glink_con1_hs: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_con1_ss: endpoint { + remote-endpoint =3D <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_con1_sbu: endpoint { + remote-endpoint =3D <&usb1_sbu_mux>; + }; + }; + }; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vcc_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8a>; + + gpio =3D <&tlmm 161 GPIO_ACTIVE_HIGH>; + enable-active-high; + + /* Longer delay for I2C pull-up to stabilize */ + startup-delay-us =3D <50000>; + + pinctrl-0 =3D <&vcc_1v8_reg_en>; + pinctrl-names =3D "default"; + }; + + vcc_1v8a: regulator-vcc-1v8a { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vcc_1v8a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pmc8280c_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us =3D <1000>; + + pinctrl-0 =3D <ð_phy_pwr_en>; + pinctrl-names =3D "default"; + }; + + vcc_3v3_ekey: regulator-vcc-3v3-ekey { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vcc_3v3_ekey"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <3000>; + + pinctrl-0 =3D <&hastings_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vcc_5v_s: regulator-vcc-5v-s { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vcc_5v_s"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpio =3D <&tlmm 159 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <250000>; + off-on-delay-us =3D <150000>; + + pinctrl-0 =3D <&vcc_5v_s_reg_en>; + pinctrl-names =3D "default"; + + /* CH7218A needs to be powered on for HPD logic to work */ + regulator-always-on; + }; + + vcc_nvme_3v3: regulator-vcc-nvme-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vcc_nvme_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 135 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <1500>; + + pinctrl-0 =3D <&nvme_reg_en>; + pinctrl-names =3D "default"; + }; + + vcc_nvme2_3v3: regulator-vcc-nvme2-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vcc_nvme2_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 158 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <1500>; + + pinctrl-0 =3D <&nvme2_reg_en>; + pinctrl-names =3D "default"; + }; + + /* This regulator is actually part of the UFS module */ + vcc_ufs: regulator-vcc-ufs { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_ufs"; + regulator-min-microvolt =3D <2480000>; + regulator-max-microvolt =3D <2480000>; + vin-supply =3D <&vreg_l7d>; + }; + + vdd_ntn_core_0p9: regulator-vdd-ntn-core-0p9 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vdd_ntn_core_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + gpio =3D <&tlmm 160 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <1000>; + + pinctrl-0 =3D <&ntn_0p9_en>; + pinctrl-names =3D "default"; + }; + + vdd_usb2: regulator-vdd-usb2 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vdd_usb2"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpio =3D <&pmc8280c_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <700>; + + pinctrl-0 =3D <&usb2_reg_en>; + pinctrl-names =3D "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vdd_usb3: regulator-vdd-usb3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vdd_usb3"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpio =3D <&pmc8280c_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <700>; + + pinctrl-0 =3D <&usb3_reg_en>; + pinctrl-names =3D "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + + pil_video_mem: video-region@8c600000 { + reg =3D <0 0x8c600000 0 0x700000>; + no-map; + }; + }; + + thermal-zones { + eeprom-thermal { + thermal-sensors =3D <&pmk8280_adc_tm 2>; + }; + + led-thermal { + thermal-sensors =3D <&pmk8280_adc_tm 6>; + }; + + left-edge-thermal { + thermal-sensors =3D <&pmk8280_adc_tm 5>; + }; + + left-edge-2-thermal { + thermal-sensors =3D <&pmk8280_adc_tm 7>; + }; + + pmc8280c-thermal { + cooling-maps { + map0 { + trip =3D <&pmc8280c_alert0>; + /* Throttle X1C cores to 2496MHz at 105C */ + cooling-device =3D <&cpu4 5 5>, + <&cpu5 5 5>, + <&cpu6 5 5>, + <&cpu7 5 5>; + }; + }; + + trips { + pmc8280c_alert0: trip2 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + }; + }; + + smb2351-thermal { + thermal-sensors =3D <&pmk8280_adc_tm 3>; + }; + + top-left-thermal { + thermal-sensors =3D <&pmk8280_adc_tm 0>; + }; + + top-right-thermal { + thermal-sensors =3D <&pmk8280_adc_tm 1>; + }; + + vbat-thermal { + polling-delay-passive =3D <250>; + thermal-sensors =3D <&pmk8280_adc_tm 4>; + + cooling-maps { + map0 { + trip =3D <&vbat_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + vbat_alert0: trip-point0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + vbat_alert1: trip-point1 { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + vbat_crit: vbat-crit { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + + usb0-sbu-mux { + compatible =3D "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; + select-gpios =3D <&tlmm 164 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&usb0_sbu_default>; + pinctrl-names =3D "default"; + + mode-switch; + orientation-switch; + + port { + usb0_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_con0_sbu>; + }; + }; + }; + + usb1-sbu-mux { + compatible =3D "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios =3D <&tlmm 48 GPIO_ACTIVE_LOW>; + select-gpios =3D <&tlmm 47 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&usb1_sbu_default>; + pinctrl-names =3D "default"; + + mode-switch; + orientation-switch; + + port { + usb1_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_con1_sbu>; + }; + }; + }; + + adp12v_voltage: voltage-divider-adp12v { + compatible =3D "voltage-divider"; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM5(1)>; + #io-channel-cells =3D <1>; + + /* R470 (110K) in series with R471 (10K) to ground. */ + full-ohms =3D <120000>; + output-ohms =3D <10000>; + }; + + wlan-connector { + compatible =3D "pcie-m2-e-connector"; + + vpcie3v3-supply =3D <&vcc_3v3_ekey>; + vpcie1v8-supply =3D <&vreg_s10b>; + w-disable1-gpios =3D <&tlmm 134 GPIO_ACTIVE_LOW>; + w-disable2-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + uart-wake-gpios =3D <&tlmm 130 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&wcn_wlan_bt_en>; + pinctrl-names =3D "default"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* PCIe interface for Wi-Fi */ + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + wlan_pcie_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie4_ep>; + }; + }; + + /* USB interface for BT */ + port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + wlan_usb_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usb_hub_m2_ep>; + }; + }; + + /* UART interface for BT */ + port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + wlan_uart_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&uart2_ep>; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-l1-l4-supply =3D <&vreg_s12b>; + vdd-l2-l7-supply =3D <&vreg_bob>; + vdd-l3-l5-supply =3D <&vreg_s11b>; + vdd-l6-l9-l10-supply =3D <&vreg_s12b>; + vdd-l8-supply =3D <&vreg_s12b>; + + vreg_s10b: smps10 { + regulator-name =3D "vreg_s10b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s11b: smps11 { + regulator-name =3D "vreg_s11b"; + regulator-min-microvolt =3D <1272000>; + regulator-max-microvolt =3D <1272000>; + regulator-initial-mode =3D ; + }; + + vreg_s12b: smps12 { + regulator-name =3D "vreg_s12b"; + regulator-min-microvolt =3D <984000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b: ldo1 { + regulator-name =3D "vreg_l1b"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3b: ldo3 { + regulator-name =3D "vreg_l3b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4b: ldo4 { + regulator-name =3D "vreg_l4b"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b: ldo6 { + regulator-name =3D "vreg_l6b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-bob-supply =3D <&vph_pwr>; + vdd-l1-l12-supply =3D <&vreg_s1c>; + vdd-l2-l8-supply =3D <&vreg_s1c>; + vdd-l3-l4-l5-l7-l13-supply =3D <&vreg_bob>; + vdd-l6-l9-l11-supply =3D <&vreg_bob>; + vdd-l10-supply =3D <&vreg_s11b>; + + vreg_s1c: smps1 { + regulator-name =3D "vreg_s1c"; + regulator-min-microvolt =3D <1888000>; + regulator-max-microvolt =3D <1888000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8c: ldo8 { + regulator-name =3D "vreg_l8c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c: ldo9 { + regulator-name =3D "vreg_l9c"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13c: ldo13 { + regulator-name =3D "vreg_l13c"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_bob: bob { + regulator-name =3D "vreg_bob"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + regulator-always-on; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-l4-supply =3D <&vreg_s11b>; + vdd-l2-l7-supply =3D <&vreg_bob>; + vdd-l3-l5-supply =3D <&vreg_s11b>; + vdd-l6-l9-l10-supply =3D <&vreg_s12b>; + vdd-l8-supply =3D <&vreg_s12b>; + + vreg_l2d: ldo2 { + regulator-name =3D "vreg_l2d"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3d: ldo3 { + regulator-name =3D "vreg_l3d"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4d: ldo4 { + regulator-name =3D "vreg_l4d"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6d: ldo6 { + regulator-name =3D "vreg_l6d"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7d: ldo7 { + regulator-name =3D "vreg_l7d"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l8d: ldo8 { + regulator-name =3D "vreg_l8d"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9d: ldo9 { + regulator-name =3D "vreg_l9d"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10d: ldo10 { + regulator-name =3D "vreg_l10d"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&dispcc0 { + status =3D "okay"; +}; + +&gpi_dma0 { + dma-channel-mask =3D <0x3f>; + status =3D "okay"; +}; + +&gpi_dma1 { + dma-channel-mask =3D <0x3f>; + status =3D "okay"; +}; + +&gpi_dma2 { + dma-channel-mask =3D <0x3f>; + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + /* Reuse firmware from x13s as the SoC is unfused */ + firmware-name =3D "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; +}; + +&i2c12 { + clock-frequency =3D <400000>; + + pinctrl-0 =3D <&qup_i2c12_data_clk>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + eeprom@50 { + compatible =3D "belling,bl24c16f", "atmel,24c16"; + reg =3D <0x50>; + pagesize =3D <16>; + vcc-supply =3D <&vreg_s10b>; + wp-gpios =3D <&tlmm 3 GPIO_ACTIVE_LOW>; + read-only; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mac_addr0: mac-address@9e { + reg =3D <0x9e 0x6>; + }; + + mac_addr1: mac-address@a4 { + reg =3D <0xa4 0x6>; + }; + }; + }; + + rtc@68 { + compatible =3D "st,m41t11"; + reg =3D <0x68>; + }; +}; + +/* QPS615 PCIe Switch */ +&i2c21 { + pinctrl-0 =3D <&qup_i2c21_data_clk>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&iris { + firmware-name =3D "qcom/vpu/vpu20_p4_gen2_s6.mbn"; + + status =3D "okay"; +}; + +&lpass_tlmm { + status =3D "okay"; +}; + +&mdss0 { + status =3D "okay"; +}; + +&mdss0_dp0 { + status =3D "okay"; +}; + +&mdss0_dp0_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + + remote-endpoint =3D <&usb_0_qmpphy_dp_in>; +}; + +&mdss0_dp1 { + status =3D "okay"; +}; + +&mdss0_dp1_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + + remote-endpoint =3D <&usb_1_qmpphy_dp_in>; +}; + +&mdss0_dp2 { + status =3D "okay"; +}; + +&mdss0_dp2_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + + remote-endpoint =3D <&hdmi_bridge_dp_in>; +}; + +&mdss0_dp2_phy { + vdda-phy-supply =3D <&vreg_l3b>; + vdda-pll-supply =3D <&vreg_l6b>; + + status =3D "okay"; +}; + +/* M-key Gen3 x4 */ +&pcie2a { + /* Place ECAM and BAR space above 4 GiB to accommodate large BARs. */ + reg =3D <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x5 0x00000000 0x0 0x10000000>, /* ECAM config */ + <0x0 0x01c23000 0x0 0x1000>; + + ranges =3D /* IO (1 MiB) */ + <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, + /* 32-bit non-prefetchable memory (256 MiB) */ + <0x02000000 0x0 0x40000000 0x5 0x10000000 0x0 0x10000000>, + /* 64-bit non-prefetchable memory (3.5 GiB) */ + <0x03000000 0x5 0x20000000 0x5 0x20000000 0x0 0xe0000000>; + + pinctrl-0 =3D <&pcie2a_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie2a_port0 { + compatible =3D "pciclass,0604"; + + reset-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; + + port { + pcie2a_ep: endpoint { + remote-endpoint =3D <&nvme_pcie_ep>; + }; + }; +}; + +&pcie2a_phy { + vdda-phy-supply =3D <&vreg_l6d>; + vdda-pll-supply =3D <&vreg_l4d>; + + status =3D "okay"; +}; + +/* QPS615 */ +&pcie3a { + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x34000000 0x0 0xf1d>, + <0x0 0x34000f20 0x0 0xa8>, + <0x0 0x34001000 0x0 0x1000>, + <0x4 0x80000000 0x0 0x10000000>, /* ECAM config */ + <0x0 0x01c13000 0x0 0x1000>; + + ranges =3D /* IO (1 MiB) */ + <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, + /* 32-bit non-prefetchable memory (256 MiB) */ + <0x02000000 0x0 0x40000000 0x4 0x90000000 0x0 0x10000000>, + /* 64-bit non-prefetchable memory (512 MiB) */ + <0x03000000 0x4 0xa0000000 0x4 0xa0000000 0x0 0x20000000>; + + num-lanes =3D <2>; + + pinctrl-0 =3D <&pcie3a_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3a_phy { + vdda-phy-supply =3D <&vreg_l6d>; + vdda-pll-supply =3D <&vreg_l4d>; + + status =3D "okay"; +}; + +&pcie3a_port0 { + reset-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vdd_ntn_core_0p9>; + vdd18-supply =3D <&vcc_1v8>; + vdd09-supply =3D <&vdd_ntn_core_0p9>; + vddio1-supply =3D <&vcc_1v8>; + vddio2-supply =3D <&vcc_1v8>; + vddio18-supply =3D <&vcc_1v8>; + + i2c-parent =3D <&i2c21 0x77>; + + resx-gpios =3D <&tlmm 108 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&tc9563_resx_n>; + pinctrl-names =3D "default"; + + /* I-PEX BTB Connector */ + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + + /* Disable by default for power saving */ + status =3D "disabled"; + }; + + /* FPC Connector */ + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + + status =3D "disabled"; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + ethernet@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + + nvmem-cells =3D <&mac_addr0>; + nvmem-cell-names =3D "mac-address"; + }; + + ethernet@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + + nvmem-cells =3D <&mac_addr1>; + nvmem-cell-names =3D "mac-address"; + }; + }; + }; +}; + +/* M-key Gen3 x2 */ +&pcie3b { + reg =3D <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x32000000 0x0 0xf1d>, + <0x0 0x32000f20 0x0 0xa8>, + <0x0 0x32001000 0x0 0x1000>, + <0x4 0x40000000 0x0 0x10000000>, /* ECAM config */ + <0x0 0x01c0b000 0x0 0x1000>; + + ranges =3D /* IO (1 MiB) */ + <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, + /* 32-bit non-prefetchable memory (256 MiB) */ + <0x02000000 0x0 0x40000000 0x4 0x50000000 0x0 0x10000000>, + /* 64-bit non-prefetchable memory (512 MiB) */ + <0x03000000 0x4 0x60000000 0x4 0x60000000 0x0 0x20000000>; + + pinctrl-0 =3D <&pcie3b_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3b_port0 { + compatible =3D "pciclass,0604"; + + reset-gpios =3D <&tlmm 153 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + + port { + pcie3b_ep: endpoint { + remote-endpoint =3D <&nvme2_pcie_ep>; + }; + }; +}; + +&pcie3b_phy { + vdda-phy-supply =3D <&vreg_l6d>; + vdda-pll-supply =3D <&vreg_l4d>; + + status =3D "okay"; +}; + +/* E-key Gen2 x1 */ +&pcie4 { + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x30000000 0x0 0xf1d>, + <0x0 0x30000f20 0x0 0xa8>, + <0x0 0x30001000 0x0 0x1000>, + <0x4 0x00000000 0x0 0x10000000>, /* ECAM config */ + <0x0 0x01c03000 0x0 0x1000>; + + ranges =3D /* IO (1 MiB) */ + <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, + /* 32-bit non-prefetchable memory (256 MiB) */ + <0x02000000 0x0 0x40000000 0x4 0x10000000 0x0 0x10000000>, + /* 64-bit non-prefetchable memory (512 MiB) */ + <0x03000000 0x4 0x20000000 0x4 0x20000000 0x0 0x20000000>; + + max-link-speed =3D <2>; + + pinctrl-0 =3D <&pcie4_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie4_port0 { + compatible =3D "pciclass,0604"; + + reset-gpios =3D <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 139 GPIO_ACTIVE_LOW>; + + port { + pcie4_ep: endpoint { + remote-endpoint =3D <&wlan_pcie_ep>; + }; + }; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l6d>; + vdda-pll-supply =3D <&vreg_l4d>; + + status =3D "okay"; +}; + +&pmc8280c_gpios { + eth_phy_pwr_en: eth-phy-pwr-en-state { + pins =3D "gpio4"; + function =3D "normal"; + }; + + usb2_reg_en: usb2-reg-en-state { + pins =3D "gpio5"; + function =3D "normal"; + }; + + usb3_reg_en: usb3-reg-en-state { + pins =3D "gpio6"; + function =3D "normal"; + }; +}; + +&pmk8280_adc_tm { + status =3D "okay"; + + sys-therm@0 { + reg =3D <0>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; + + sys-therm@1 { + reg =3D <1>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; + + sys-therm@2 { + reg =3D <2>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; + + sys-therm@3 { + reg =3D <3>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; + + sys-therm@4 { + reg =3D <4>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; + + sys-therm@5 { + reg =3D <5>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; + + sys-therm@6 { + reg =3D <6>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; + + sys-therm@7 { + reg =3D <7>; + io-channels =3D <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>; + qcom,hw-settle-time-us =3D <200>; + qcom,avg-samples =3D <2>; + qcom,ratiometric; + }; +}; + +&pmk8280_pon_pwrkey { + status =3D "okay"; +}; + +&pmk8280_vadc { + channel@108 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + label =3D "adp12v_det"; + }; + + channel@144 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm1"; + }; + + channel@145 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm2"; + }; + + channel@146 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm3"; + }; + + channel@147 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm4"; + }; + + channel@344 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm5"; + }; + + channel@345 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm6"; + }; + + channel@346 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm7"; + }; + + channel@347 { + reg =3D ; + qcom,hw-settle-time =3D <200>; + qcom,ratiometric; + label =3D "sys_therm8"; + }; +}; + +&pmr735a_gpios { + hastings_reg_en: hastings-reg-en-state { + pins =3D "gpio1"; + function =3D "normal"; + }; +}; + +&qup0 { + firmware-name =3D "qcom/sc8280xp/qupv3fw.elf"; + status =3D "okay"; +}; + +&qup1 { + firmware-name =3D "qcom/sc8280xp/qupv3fw.elf"; + status =3D "okay"; +}; + +&qup2 { + firmware-name =3D "qcom/sc8280xp/qupv3fw.elf"; + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sc8280xp/radxa/dragon-q8b/qcadsp8280.mbn"; + status =3D "okay"; +}; + +&remoteproc_nsp0 { + firmware-name =3D "qcom/sc8280xp/qccdsp8280.mbn"; + status =3D "okay"; +}; + +&rxmacro { + status =3D "okay"; +}; + +&sdc2 { + pinctrl-0 =3D <&sdc2_default_state>; + pinctrl-1 =3D <&sdc2_sleep_state>; + pinctrl-names =3D "default", "sleep"; + + full-pwr-cycle; + + vmmc-supply =3D <&vreg_l9c>; + vqmmc-supply =3D <&vreg_l6c>; + + cd-gpios =3D <&tlmm 131 GPIO_ACTIVE_LOW>; + + status =3D "okay"; +}; + +&sound { + compatible =3D "qcom,sc8280xp-sndcard"; + model =3D "SC8280XP-Radxa-Dragon-Q8B"; + + audio-routing =3D + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + dp0-dai-link { + link-name =3D "DP0 Playback"; + + codec { + sound-dai =3D <&mdss0_dp0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + dp1-dai-link { + link-name =3D "DP1 Playback"; + + codec { + sound-dai =3D <&mdss0_dp1>; + }; + + cpu { + sound-dai =3D <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + dp2-dai-link { + link-name =3D "DP2 Playback"; + + codec { + sound-dai =3D <&mdss0_dp2>; + }; + + cpu { + sound-dai =3D <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + codec { + sound-dai =3D <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + codec { + sound-dai =3D <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; +}; + +&swr1 { + status =3D "okay"; + + wcd_rx: wcd9380-rx@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + qcom,rx-port-mapping =3D <1 2 3 4 5>; + }; +}; + +&swr2 { + status =3D "okay"; + + wcd_tx: wcd9380-tx@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + qcom,tx-port-mapping =3D <1 1 2 3>; + }; +}; + +&txmacro { + status =3D "okay"; +}; + +/* E-key Bluetooth */ +&uart2 { + uart-has-rtscts; + status =3D "okay"; + + port { + uart2_ep: endpoint { + remote-endpoint =3D <&wlan_uart_ep>; + }; + }; +}; + +&uart17 { + compatible =3D "qcom,geni-debug-uart"; + + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vcc_ufs>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l3d>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l6b>; + vdda-pll-supply =3D <&vreg_l3b>; + + status =3D "okay"; +}; + +&usb_0 { + status =3D "okay"; +}; + +&usb_0_dwc3 { + dr_mode =3D "host"; +}; + +&usb_0_dwc3_hs { + remote-endpoint =3D <&pmic_glink_con0_hs>; +}; + +&usb_0_hsphy { + vdda-pll-supply =3D <&vreg_l9d>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l7d>; + + status =3D "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply =3D <&vreg_l9d>; + vdda-pll-supply =3D <&vreg_l4d>; + + mode-switch; + orientation-switch; + + status =3D "okay"; +}; + +&usb_0_qmpphy_dp_in { + remote-endpoint =3D <&mdss0_dp0_out>; +}; + +&usb_0_qmpphy_out { + remote-endpoint =3D <&pmic_glink_con0_ss>; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_con1_hs>; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l4b>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l13c>; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l4b>; + vdda-pll-supply =3D <&vreg_l3b>; + + mode-switch; + orientation-switch; + + status =3D "okay"; +}; + +&usb_1_qmpphy_dp_in { + remote-endpoint =3D <&mdss0_dp1_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint =3D <&pmic_glink_con1_ss>; +}; + +&usb_2 { + status =3D "okay"; +}; + +&usb_2_dwc3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_hub_m2: hub@3 { + compatible =3D "usb1a86,8091"; + reg =3D <3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + usb_hub_m2_ep: endpoint { + remote-endpoint =3D <&wlan_usb_ep>; + }; + }; + }; + }; +}; + +&usb_2_hsphy0 { + vdda-pll-supply =3D <&vreg_l1b>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l7d>; + + status =3D "okay"; +}; + +&usb_2_hsphy1 { + vdda-pll-supply =3D <&vreg_l8d>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l7d>; + + status =3D "okay"; +}; + +&usb_2_hsphy2 { + vdda-pll-supply =3D <&vreg_l10d>; + vdda18-supply =3D <&vreg_l8c>; + vdda33-supply =3D <&vreg_l2d>; + + status =3D "okay"; +}; + +&usb_2_hsphy3 { + vdda-pll-supply =3D <&vreg_l10d>; + vdda18-supply =3D <&vreg_l8c>; + vdda33-supply =3D <&vreg_l2d>; + + status =3D "okay"; +}; + +&usb_2_qmpphy0 { + vdda-phy-supply =3D <&vreg_l1b>; + vdda-pll-supply =3D <&vreg_l4d>; + + status =3D "okay"; +}; + +&usb_2_qmpphy1 { + vdda-phy-supply =3D <&vreg_l8d>; + vdda-pll-supply =3D <&vreg_l4d>; + + status =3D "okay"; +}; + +&vamacro { + vdd-micb-supply =3D <&vreg_s10b>; + + qcom,dmic-sample-rate =3D <4800000>; + + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; + +/* PINCTRL - additions to nodes defined in sc8280xp.dtsi */ + +&qup_i2c12_data_clk { + drive-strength =3D <2>; + bias-disable; +}; + +&qup_i2c21_data_clk { + drive-strength =3D <2>; + bias-disable; +}; + +&tlmm { + gpio-reserved-ranges =3D <74 6>, /* QSPI Flash */ + <125 5>; /* SPI (TPM) */ + gpio-line-names =3D + /* GPIO_0 ~ GPIO_3 */ + "", "", "", "", + /* GPIO_4 ~ GPIO_7 */ + "", "", "", "", + /* GPIO_8 ~ GPIO_11 */ + "", "", "", "", + /* GPIO_12 ~ GPIO_15 */ + "", "", "", "", + /* GPIO_16 ~ GPIO_19 */ + "", "", "", "", + /* GPIO_20 ~ GPIO_23 */ + "", "", "", "", + /* GPIO_24 ~ GPIO_27 */ + "", "", "", "", + /* GPIO_28 ~ GPIO_31 */ + "", "", "", "", + /* GPIO_32 ~ GPIO_35 */ + "", "", "", "", + /* GPIO_36 ~ GPIO_39 */ + "", "", "", "", + /* GPIO_40 ~ GPIO_43 */ + "", "PIN_3", "PIN_5", "PIN_27", + /* GPIO_44 ~ GPIO_47 */ + "PIN_28", "", "", "", + /* GPIO_48 ~ GPIO_51 */ + "", "", "", "", + /* GPIO_52 ~ GPIO_55 */ + "", "", "", "", + /* GPIO_56 ~ GPIO_59 */ + "", "", "", "", + /* GPIO_60 ~ GPIO_63 */ + "", "", "", "PIN_8", + /* GPIO_64 ~ GPIO_67 */ + "PIN_10", "", "PIN_13", "PIN_15", + /* GPIO_68 ~ GPIO_71 */ + "PIN_16", "PIN_37", "", "", + /* GPIO_72 ~ GPIO_75 */ + "", "", "", "", + /* GPIO_76 ~ GPIO_79 */ + "", "", "", "", + /* GPIO_80 ~ GPIO_83 */ + "", "", "", "", + /* GPIO_84 ~ GPIO_87 */ + "", "", "", "PIN_21", + /* GPIO_88 ~ GPIO_91 */ + "PIN_19", "PIN_23", "PIN_24", "PIN_26", + /* GPIO_92 ~ GPIO_95 */ + "PIN_22", "", "", "", + /* GPIO_96 ~ GPIO_99 */ + "", "", "", "", + /* GPIO_100 ~ GPIO_103 */ + "", "", "", "", + /* GPIO_104 ~ GPIO_107 */ + "", "", "", "", + /* GPIO_108 ~ GPIO_111 */ + "", "", "PIN_18", "PIN_11", + /* GPIO_112 ~ GPIO_115 */ + "PIN_36", "", "PIN_32", "PIN_33", + /* GPIO_116 ~ GPIO_119 */ + "", "", "", "", + /* GPIO_120 ~ GPIO_123 */ + "", "", "", "", + /* GPIO_124 ~ GPIO_127 */ + "", "", "", "", + /* GPIO_128 ~ GPIO_131 */ + "", "", "", "", + /* GPIO_132 ~ GPIO_135 */ + "", "", "", "", + /* GPIO_136 ~ GPIO_139 */ + "", "", "", "", + /* GPIO_140 ~ GPIO_143 */ + "", "", "", "", + /* GPIO_144 ~ GPIO_147 */ + "", "", "", "", + /* GPIO_148 ~ GPIO_151 */ + "", "", "", "", + /* GPIO_152 ~ GPIO_155 */ + "", "", "", "", + /* GPIO_156 ~ GPIO_159 */ + "PIN_31", "PIN_29", "", "", + /* GPIO_160 ~ GPIO_163 */ + "", "", "", "", + /* GPIO_164 ~ GPIO_167 */ + "", "", "", "", + /* GPIO_168 ~ GPIO_171 */ + "", "", "", "PIN_35", + /* GPIO_172 ~ GPIO_175 */ + "PIN_38", "PIN_40", "PIN_12", "PIN_7", + /* GPIO_176 ~ GPIO_179 */ + "", "", "", ""; + + dp_hpd_default: dp-hpd-default-state { + pins =3D "gpio2"; + function =3D "edp_hot"; + bias-disable; + }; + + ntn_0p9_en: ntn-0p9-en-state { + pins =3D "gpio160"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio135"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + nvme2_reg_en: nvme2-reg-en-state { + pins =3D "gpio158"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie2a_default: pcie2a-default-state { + clkreq-n-pins { + pins =3D "gpio142"; + function =3D "pcie2a_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio143"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio145"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie3a_default: pcie3a-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie3a_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins =3D "gpio152"; + function =3D "pcie3b_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio153"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-n-pins { + pins =3D "gpio149"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio140"; + function =3D "pcie4_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio141"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio139"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <16>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <16>; + bias-pull-up; + }; + + card-detect-pins { + pins =3D "gpio131"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + card-detect-pins { + pins =3D "gpio131"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + tc9563_resx_n: tc9563-resx-state { + pins =3D "gpio108"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb0_sbu_default: usb0-sbu-state { + oe-n-pins { + pins =3D "gpio101"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + output-high; + }; + + sel-pins { + pins =3D "gpio164"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + }; + }; + + usb1_sbu_default: usb1-sbu-state { + oe-n-pins { + pins =3D "gpio48"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + output-high; + }; + + sel-pins { + pins =3D "gpio47"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + }; + }; + + vcc_1v8_reg_en: vcc-1v8-reg-en-state { + pins =3D "gpio161"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + vcc_5v_s_reg_en: vcc-5v-s-reg-en-state { + pins =3D "gpio159"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wcd_default: wcd-default-state { + reset-pins { + pins =3D "gpio106"; + function =3D "gpio"; + bias-disable; + }; + }; + + wcn_wlan_bt_en: wcn-wlan-en-state { + pins =3D "gpio133", "gpio134"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + user_led: user-led-state { + pins =3D "gpio4"; + function =3D "gpio"; + bias-pull-up; + }; +}; --=20 2.55.0