From nobody Sat Sep 26 11:47:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96ACB44A3E6 for ; Tue, 1 Sep 2026 19:57:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788292647; cv=none; b=S4FDtqAcp7ERroQ5SZOnVS3iETwceebe/hI946SwBqPGWzxadEmUGUQM3DhhtdOxKEaB3w7SEZZtiS4E9IWIwX2YwU6940XDW5QJfhAPn45dcCAtE+tR6Qh+H5EKyVMUdKD1HLskHGrTLv33b07NVOsCIDfkEsHdJFlgviIKy+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788292647; c=relaxed/simple; bh=rCvlPknLGM17Xc/ny1wY7xGWECwsix65LrYdnOlW7MI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fg8yL7XqftYa6A2VRIqAb9Z6F90N1QvZo4ckdD6jnQ1NbBWG9HI8+B/t2gszcTG7mVwCv9+9O99FqAUB5UJoHG520Yu9oj83baSkJyRn4/mcVaKCq9zRw13xHa5nO0tupv3rLodKG49IrufAkMF2wPMrkgj2qkhRxGxyMeSIvww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=AwQldk14; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="AwQldk14" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788292644; bh=rCvlPknLGM17Xc/ny1wY7xGWECwsix65LrYdnOlW7MI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AwQldk14HlTia8gWljufFe9X4XuwnSW57CSg9aaW+5JdeAR+5+ozFGd0heCPgzSo2 RxZGkaf9GGbshx0tdL3CgIVLSgj30Olup4PdpJV+KgMlNZAyB35Rj8vZm/HI27nLDr OVA1rbLs0N9hU3Jdy/lyWlZe7RnMlGXdG2jL79pql5qhP81yXd0nYsUqIhx9AQ05qR JDftH1nkqLACGA1lPBz/zAKFPoyOHHS6HUcr1oa+UMgmIK0JBHN8QGLTpViIOcFlH3 JERZWsJjC7jiuwLCehnbJSXM+B4VRWq7Emhk6dCeSo2IxV6mcSAeghJRpznwNHWTEI YRtvE3auxXyHA== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id D24E517E057E; Tue, 01 Sep 2026 21:57:23 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 01 Sep 2026 22:55:13 +0300 Subject: [PATCH v2 1/3] phy: hdmi: Add optional FRL TxFFE config options Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-hdptx-ffe-v2-1-3a5922c76fc5@collabora.com> References: <20260901-hdptx-ffe-v2-0-3a5922c76fc5@collabora.com> In-Reply-To: <20260901-hdptx-ffe-v2-0-3a5922c76fc5@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Andy Yan Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.15.2 During HDMI 2.1 FRL link training, the source and sink can negotiate a Transmitter Feed-Forward Equalization (TxFFE) level to improve the signal quality. Starting from zero, the source may increment the TxFFE level up to a maximum agreed during the LTS3 stage if the sink keeps reporting FLT failures. TxFFE adjustment is optional and only attempted when both the source and the connected sink support it. Since the existing HDMI PHY configuration API covers the FRL rate/lane selection only, provide the following fields to the frl sub-struct of phy_configure_opts_hdmi: * ffe_level: the TxFFE level to apply, only meaningful when set_ffe_level is set. * set_ffe_level: a 1-bit flag that changes the semantics of the phy_configure() call, i.e. when set, the PHY driver must apply the new ffe_level and ignore the other frl related fields. The flag-based approach reflects an important invariant in the link training process: whenever the FRL rate or lane count changes, the TxFFE level must be reset to zero. A separate phy_configure() call with set_ffe_level can only follow after the rate has been established, making the two operations deliberately distinct. Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index d4cf4430ee8f..1d4b62475079 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -19,6 +19,10 @@ enum phy_hdmi_mode { * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. * @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps. * @frl.lanes: HDMI FRL lanes count. + * @frl.ffe_level: Transmitter Feed Forward Equalizer Level. + * Optional, only meaningful when set_ffe_level flag is on. + * @frl.set_ffe_level: Flag indicating whether or not to reconfigure ffe_l= evel. + * All the other struct fields must be ignored when this is used. * * This structure is used to represent the configuration state of a HDMI p= hy. */ @@ -29,6 +33,8 @@ struct phy_configure_opts_hdmi { struct { u8 rate_per_lane; u8 lanes; + u8 ffe_level; + u8 set_ffe_level : 1; } frl; }; }; --=20 2.55.0 From nobody Sat Sep 26 11:47:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 879B644A3F4 for ; Tue, 1 Sep 2026 19:57:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788292648; cv=none; b=HdOevfwOO6hD3oiTb/qwCQ1ZNe0N09eUMtwSoIf+e+R2VkLQAAbjFPy/KkvVPRYAg78GDmWvVitIzG1XnvhMRrdd/IO8IAJxoZ/e59G6TnB1hVZ4x0jvtxtUWYj6+ESr0u24SQ0K5jZheuClBcY31aHpDMxz6INyp7Jj2JH4sug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788292648; c=relaxed/simple; bh=4lP0oLI8PNKCXZUuWv4Wfm8oJux9jtJXdUCFqHxCj9c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cAlCRt7A9xF4G4sTaen5cfoNXYQu+fPEtiPxLrEdPpKfsjmfqekAQR+vP3aGVw3HVLWKeuIeFzp1T1oJdta6umeWk3DBCz8XK0rfe+PAiFs07BhNGCdcPBnVENHVmbzz13LfP9sV5LzkUFGnE9AT/GC78Ue+oDKUtnYruk0HGT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=VD77AgkL; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="VD77AgkL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788292644; bh=4lP0oLI8PNKCXZUuWv4Wfm8oJux9jtJXdUCFqHxCj9c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VD77AgkLO3N+rBCDKILwJT5zdr3N8Kx5DlgfAo7s3wk6Xms4WM1LhZGcHKaOfVpJ4 tejKkjfkD7zMWNSC97ZIQIUuaL1+ka3VAKhtKmSfy8oVnzpqIG91KAy0SwyBpWnKqI doEmiDBUYUPObmPTSOgPDx0N+phyX6BXPXpwXaFJRiEyxQRbjwUo1eLEJHakZu0+pi WleV4dBV3lZP+2u59VpYuIR+AoMcbDsecRvUDflIFZEYjcX8wwM6Qw/GlP/sQEzorU ZkuZev4lxYmYNaABksOkPao2M/FHrQ10JvDlxJqQsrkFB6k/sHgVHQAvAkH6suCW3z ki+k26F+s0T3g== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 98ACD17E0934; Tue, 01 Sep 2026 21:57:24 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 01 Sep 2026 22:55:14 +0300 Subject: [PATCH v2 2/3] phy: rockchip: samsung-hdptx: Handle PHY config after module reload Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-hdptx-ffe-v2-2-3a5922c76fc5@collabora.com> References: <20260901-hdptx-ffe-v2-0-3a5922c76fc5@collabora.com> In-Reply-To: <20260901-hdptx-ffe-v2-0-3a5922c76fc5@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Andy Yan Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.15.2 The pll_config_dirty mechanism introduced in commit aec3e4ce25da ("phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes") invalidates the clock rate in determine_rate() by resetting req->rate to zero, ensuring CCF will invoke set_rate() to program pending PLL configuration changes into hardware. However, after a module reload cycle the PHY PLL clock gets re-registered with CCF, which causes the framework's cached rate to also be zero. Setting req->rate to zero then has no effect, since CCF sees no difference between the requested and current rates and skips calling set_rate(), leaving the PLL unconfigured. Address this by first computing the actual target rate from the HDMI link configuration, and only then invalidating it when it matches the CCF cached rate. Fixes: aec3e4ce25da ("phy: rockchip: samsung-hdptx: Handle uncommitted PHY = config changes") Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 24ed0d7eb6f8..b03042ec9a84 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -2346,14 +2346,16 @@ static int rk_hdptx_phy_clk_determine_rate(struct c= lk_hw *hw, * to ensure rk_hdptx_phy_clk_set_rate() will be always invoked. * Otherwise, restrict the rate according to the PHY link setup. */ - if (hdptx->pll_config_dirty) - req->rate =3D 0; - else if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) + + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) req->rate =3D hdptx->hdmi_cfg.rate; else req->rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.rate * 8, hdptx->hdmi_cfg.bpc); =20 + if (hdptx->pll_config_dirty && req->rate =3D=3D clk_hw_get_rate(hw)) + req->rate =3D 0; + return 0; } =20 --=20 2.55.0 From nobody Sat Sep 26 11:47:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E8E44A400 for ; Tue, 1 Sep 2026 19:57:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788292648; cv=none; b=YplRW3Y77qPw81bS7QGA82LMqjir5nSN3ww9NKPdBH897uGNeCKcONelOQeYueBdegEKh5/h7Cr1H2QW/JTdt8EOObpJLbC+v/hULSgF3aOpQ1iEbZUJaBJVoMFC7mXusY9S8Kn4xr6aloTNK0VvzRrKGZZy1E2j4j+qMbAKtvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788292648; c=relaxed/simple; bh=5+//jJMis2DTE/0hiz65W/T5XYb9Lv/1gpdVa6A5mio=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tp8cmBLLdvYJ1tL7+ghlOqj+HkyxWd0X4PIxEizk4PdvqVxb5mUPIedLEZNpaXbs2Aw91em37l3AzxZw8sGbn+xzRIiVEaJuMqr8ejjOFCQi9/ZXmWKMDEpEeLC7Bp+3qyie4bnOa3mUSQJLEyciLI4FlSiJ93hlaPFEjxpr5rE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=GFvon9g7; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="GFvon9g7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788292645; bh=5+//jJMis2DTE/0hiz65W/T5XYb9Lv/1gpdVa6A5mio=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GFvon9g7x4fUT1VdcNt3Q86mI6IjNsKMXP9weCH+QkYRnbOfgR9P/udvfiMcn5iG7 vIMq3SXs6B9rOHW2gVUHmbEEOwOaE13lMhsemKCjfhXlsDCIMRlm6pAODM0fel4l/b Z7etHCzlPiAWpiCZko5cGLSNz/KNIuFxC3MMZ9U25qflATwbHueNh7YbL+JCW8FAc/ XLHR7QKJbTrxKwVoCNo7iPvtLrm9VhOIuZ04BFdJK4g8gUg6TGlTVvws9TrVMBRSbn +4o60HMDJRgUPhZD4QQWUMtVBMvX2P1KaOsS91J3q8o7QiFE4xzxSNy5AgPZyGGpXq V9XzkX+/b45cQ== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5D14917E0CAB; Tue, 01 Sep 2026 21:57:25 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 01 Sep 2026 22:55:15 +0300 Subject: [PATCH v2 3/3] phy: rockchip: samsung-hdptx: Add support for FRL TxFFE level control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-hdptx-ffe-v2-3-3a5922c76fc5@collabora.com> References: <20260901-hdptx-ffe-v2-0-3a5922c76fc5@collabora.com> In-Reply-To: <20260901-hdptx-ffe-v2-0-3a5922c76fc5@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Andy Yan Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.15.2 During HDMI 2.1 FRL link training, the source may need to incrementally raise the TxFFE level in response to persistent link failures reported by the sink during LTS3. The phy_configure_opts_hdmi struct now carries ffe_level and set_ffe_level fields to convey such an update independently of a full rate reconfiguration. Wire up the optional TxFFE control in the Samsung HDPTX PHY driver. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 72 +++++++++++++++++++= ++-- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index b03042ec9a84..6879eecc5a9f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -333,6 +333,7 @@ #define FRL_3G3L_RATE 900000000 #define FRL_6G3L_RATE 1800000000 #define FRL_8G4L_RATE 3200000000 +#define FRL_FFE_MAX_LEVEL 3 =20 enum dp_link_rate { DP_BW_RBR, @@ -466,6 +467,16 @@ static const struct ropll_config rk_hdptx_tmds_ropll_c= fg[] =3D { { 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, = 1, 1, }, }; =20 +static const struct ffe_config { + u8 pre_shoot; + u8 de_emphasis; +} rk_hdptx_frl_ffe_cfg[FRL_FFE_MAX_LEVEL + 1] =3D { + { 0x3, 0x4 }, + { 0x3, 0x6 }, + { 0x3, 0x8 }, + { 0x3, 0x9 }, +}; + static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0009), 0x0c), REG_SEQ0(CMN_REG(000a), 0x83), @@ -1321,6 +1332,45 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk= _hdptx_phy *hdptx) return rk_hdptx_post_enable_lane(hdptx); } =20 +static int rk_hdptx_frl_ffe_config(struct rk_hdptx_phy *hdptx, u8 ffe_leve= l) +{ + u8 val; + + if (ffe_level > FRL_FFE_MAX_LEVEL) + return -EINVAL; + + val =3D rk_hdptx_frl_ffe_cfg[ffe_level].pre_shoot; + + regmap_update_bits(hdptx->regmap, LANE_REG(0305), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0405), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0505), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0605), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + + val =3D rk_hdptx_frl_ffe_cfg[ffe_level].de_emphasis; + + regmap_update_bits(hdptx->regmap, LANE_REG(0304), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0404), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0504), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0604), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + return 0; +} + static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx) { reset_control_assert(hdptx->rsts[RST_LANE].rstc); @@ -1735,6 +1785,13 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, unsigned long long frl_rate =3D 100000000ULL * hdmi_in->frl.lanes * hdmi_in->frl.rate_per_lane; =20 + if (hdmi_in->frl.set_ffe_level) { + if (hdmi_in->frl.ffe_level > FRL_FFE_MAX_LEVEL) + return -EINVAL; + + return 0; + } + switch (hdmi_in->frl.rate_per_lane) { case 3: case 6: @@ -2081,11 +2138,18 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->pll_config_dirty =3D true; + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL && + opts->hdmi.frl.set_ffe_level) { + dev_dbg(hdptx->dev, "%s ffe_level=3D%u\n", __func__, + opts->hdmi.frl.ffe_level); + ret =3D rk_hdptx_frl_ffe_config(hdptx, opts->hdmi.frl.ffe_level); + } else { + hdptx->pll_config_dirty =3D true; =20 - dev_dbg(hdptx->dev, "%s %s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.mode ? "FRL" : "TMDS", - hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); + dev_dbg(hdptx->dev, "%s %s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.mode ? "FRL" : "TMDS", + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); + } } =20 return ret; --=20 2.55.0