From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC95A388385; Tue, 1 Sep 2026 21:50:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299444; cv=none; b=tXlkm8FKrf1aN1UVDEqGiRHwiODvtQx3PwplTBYhTLumgOhXIzwcJ2BqRobb9bSdmNXEIPgLtAoVjzJrWvZH4Yo3x0JkIQ4e8DNRIiTAFdl5Wi18/kTyWa6fnSP2aKMyjLFP8Lga7XpMf5Mm38VDbc1UwCc1BJ9zao/d+1+zyeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299444; c=relaxed/simple; bh=YKCiV3JRnowlUYP4gZAvFvJ+clFyUJvl2G9cB2ncGS4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NBhlqk+45grTWN8/rgtnOi87u17XcCdhy3Tc6GLDLPrwnGAf4fSMEAa4qd0NFOalBCH7tIHZg9r+hO2dZWMvoVTtjTi8OiOWDKz3WEvcXWv1wCztww4rUaTkZHvYCqEhtBdcDGuLO3LHs9KnD/IbA1zIdNG5Q0ErpVal3MMH3vY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O1tXmJQX; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O1tXmJQX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA0341F00A3A; Tue, 1 Sep 2026 21:50:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299440; bh=B5W37ayUUTp9OcZ1NvZJyL332jGmKa7++7rGX5259fQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=O1tXmJQXdWbHBUSj0QyD/dvMCJh0uMI39ko23jLxCFXoTGrENSFz1UlAfuI9YUjuc nUhT0OHwlouVyx7ci6Bvt6/CAE0Xjap399URkibWTCg8aQ9YIqhWQUoA9vkTyiaMPf MR0Ik6aTSjpDbMaBsvaiZ9geURMncNkCHtfJc34ybgg28JQY0SZbTC5Y8wpCFN2iaY pSwnQybHNe62KCRKMV3ucyrtwFwHyGg885H0ILS6FmCd+nwSO6UyZaggHxQxm8k7Rz oOyOf1/aY1o6PcSynyuikf5PcW3isdYMuiqtIIB4zHVfRrGeIUPoZyo3MI6tH1TLYo 8cXDpPuC5wR+w== From: Mark Brown Date: Tue, 01 Sep 2026 22:46:59 +0100 Subject: [PATCH v20 01/14] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-1-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=953; i=broonie@kernel.org; h=from:subject:message-id; bh=YKCiV3JRnowlUYP4gZAvFvJ+clFyUJvl2G9cB2ncGS4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0idB4DcdKlt7wJVbB6ROntsyQAta8YhETgGb uPxSopq6guJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdInQAKCRAk1otyXVSH 0NtVB/9mh/8qaJIgJBmwYxhtuRck4ae6qKEoj6g+12jBJAM9deBCHC2GZtOn9jE2Z7vuin2xq85 3ILDGkDY13HakK2mBhbm+J3OI59twTVJL8325yrcuL2uQpdk2nbGMeHVX6Ugf6dnervIaRcGy3G QY/IPBVZL6161pO02IwcLqVE2oyD4ko6+gF7d8nBmPiCGbThC1orRYaXXrGxycYaVmr30CPzPru r2M/1x8t5l88fNN89tNdNPjZDI7sczsDoKdDhwPBie51aqMxO02kKPFmPVj41MZOeXHcg3IjZwD dvXXlZjQqhY9BsFNeIcyfXp0C1mixuaSokOUzvHcKYAOo8QF X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The initial EL2 setup for GCS did not include disabling of EL1 usage of GCS instructions, also disable these traps. Fixes: ff5181d8a2a8 ("arm64/gcs: Provide basic EL2 setup to allow GCS usage= at EL0 and EL1") Reviewed-by: Leonardo Bras Signed-off-by: Mark Brown Reviewed-by: Lorenzo Stoakes (ARM) --- arch/arm64/include/asm/el2_setup.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index aa8ec9df8024..d308c6e6757d 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -393,6 +393,11 @@ orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK =20 + /* Disable traps of GCS instructions at EL1 */ + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK + .Lskip_gce_fgt_\@: =20 .Lset_fgt_\@: --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 213821E1A17; Tue, 1 Sep 2026 21:50:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299447; cv=none; b=BO1SqzsLo+hcC4/XKVG48IQ3pYa0TwZ7DhDJnrMuZUr9OE70XVCAVe74sL7YEFOUqClHnnoE9/Adr1BSxG5r9YFhuK+Hv7lJUNzsoHpKplEijMkl7KrxszccAYLwxHkkB3mQe7Utocr4+C6eAC/UMKqszZRgxvltTOua6a7u6fY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299447; c=relaxed/simple; bh=03IFzhMIe86O1tDUwMFTAH2bc2Wf2e5ofSlKnmvMwps=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a3XiqCTPh49tPJLsp1+GgVk3fNnAXP11btzgbwCofXDD4f4hZyM6wEliqfbAWMvx/t+tGdEiqcjJQJdYEgO1xp9iRyUUBKdi/9CQHjXhahOtCilf5NKtcdq7sbgm5Lfag/f7ikSD2G+Zc/OJ7+Zac5AIL6kuzRJ9BetwPY3drHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Bk0TvFDC; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Bk0TvFDC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4769B1F00A3D; Tue, 1 Sep 2026 21:50:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299444; bh=7S1u1NUBMcaYrnhlVutGEefRSHacesekDiD9O9QWeIU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Bk0TvFDCwLVa+GQJHJYn2g7CLDqrNRx0t0IqP5iFtYv5KihthFDWcW0rmSuMhehPG kfXiXGAd/yykMQof/0C0cr4A8wJfmJtIA8HIgC+myjcg2xaTjBYyqNTchxDeNSmvNo YfupBRL2gUXAQ6dVCG2eOx4TRdW8tjWYv14EfKzRWnJm/G9Qm2aJCg/FYToS8A9VNi Dr1KSsaG5FDn0Jcf7wSLmViLAY0XqT6wHFEZVqMp8WRTfj64jajrhysMzqrvYim9lF iKrBAWaH4f+JkkFy7aM3AIprw3LZTNy53cuLJr/4d6k7j3T1jfn7g4x50R+ib/l/Vo 5qqyOR47O+jKw== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:00 +0100 Subject: [PATCH v20 02/14] KVM: arm64: Fix FGT mapping for HFGITR_EL2.nGCSEPP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-2-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1231; i=broonie@kernel.org; h=from:subject:message-id; bh=03IFzhMIe86O1tDUwMFTAH2bc2Wf2e5ofSlKnmvMwps=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0ieJtASYG9gKhKYFZFR2q7jGqYsV3vGZdvtf ZfQo6jxSpaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIngAKCRAk1otyXVSH 0P/hB/92IeSeCJYmi34v1rDavY+z6TcZkqhldqLJ87GeFsA+t4Lqg2T/3+OggmtRPI3DvRwVthB fEr9uV/PDr9mBoEBBfDqNB0O0NwfGFh0DhuB5YiyJEdNe0F901O06pO/kVL5RHnn+0RSIpeeCKr HqYPVcsRCsgcpgvIow19RMoSzDQLo6hPKWgtPITjYOiOFadtUquVw5O3xQxEoBkImMXr2CPPat3 zf4+6V4KXWcU1eW7nQjMePPdTUBUpz83W74CH82ePiMRt8s/RUDwojdqbMywWJrc7AG+8HQ7+55 uq6ZUfAE+VZoEkHHMMCzQnHsFoR+SECdmjnPA0oN7BjdILIY X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The encoding to trap mapping currently maps a FGT on OP_GCSPOPX to HFGITR_EL2.nGCSEPP but as per DDI0601 2026-06 this FGT controls trapping of GCSPUSHX and GCSPOPCX, and not the separate GCSPOPX instruction. Update the mapping to reflect the architecture. Fixes: 863ac38984a82 ("KVM: arm64: Add missing HFGITR_EL2 FGT entries to ne= sted virt") Reviewed-by: Leonardo Bras Signed-off-by: Mark Brown Reviewed-by: Lorenzo Stoakes (ARM) --- arch/arm64/kvm/emulate-nested.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 625604019fb3..3806ff0920fe 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -1445,7 +1445,7 @@ static const struct encoding_to_trap_config encoding_= to_fgt[] __initconst =3D { SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1), SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1), SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0), - SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0), + SR_FGT(OP_GCSPOPCX, HFGITR, nGCSEPP, 0), SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0), SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0), SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0), --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 283D5263F4A; Tue, 1 Sep 2026 21:50:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299449; cv=none; b=doECjMmtjt5Q/pdzqAGAsdJIOntkqUrb9GiXD9shYHTqO/iuKYg+xq5Wa1PPnUwj2/nssH5adkUEcdKK30SuWT1VkoC2CzNV/VnM+72FjLl94Ot0Tbl/dAQAwUfs9sHhc4sXQtoJ0CB97LeTcNvQ8WSV8vymUZxqGpaCsXx4CIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299449; c=relaxed/simple; bh=m9Y5i7FdxhbgarHpEdv5O9O+IvLpM7gYqzuqvKiJFaY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u8OSuD7Y/eAaYl/qPqo/TZK4OFEMeaY3E8yvPQwQvI3dIu4kQthk6i9ecspyiTOjtWHHMmjUyuVqqPoCOZ6qHqAW8tj3LPcKNZJpqXFhp818MQEGubJHiMooML6ILKcqwheG0h7SIMuyOIqZ51fs+Gw2kpV/6m8QNa5nckmyito= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K77cNbtl; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K77cNbtl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BADDE1F00A3F; Tue, 1 Sep 2026 21:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299447; bh=eJqGPr5rbQ4tkoXXjq4502u6xcz5r67vyKX0+Mx/Oeo=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=K77cNbtlS6mcYIif+NY0Yp4M371WCG4dFQGisty61M1nFpabzSzPrVGXBVb9yZzTQ ccNxozOCjSjadsoaotk+0z69ebtoRy/7VGzpoulDLDbWIV3CPZJPXpcjEVO+nilgpt EPxW5tF71utgc9eRkTIcI7lLqemJZhogPVRdN67Nsb/lZTrckGj8OznYMJMvTv4TZg 85VzfRrL5WRCZ2zsegHRV5L3jVZ6UHEDhZX2vBuZqWlKit58DekTFH6g+JSkxFtlzh jkVA/btPjEZeGe0Lfld2psuLwnjsKh0EzSf5WfG38wtx8GJX6HCa5ghkvVbzPHQDWc RXYtu6/J3/XEg== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:01 +0100 Subject: [PATCH v20 03/14] KVM: arm64: Manage GCS access and registers for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-3-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=13040; i=broonie@kernel.org; h=from:subject:message-id; bh=m9Y5i7FdxhbgarHpEdv5O9O+IvLpM7gYqzuqvKiJFaY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0iesuUD2SCfh40Z3K5aNL1NncfxhiWCMN9oL vhcyFbnTjOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIngAKCRAk1otyXVSH 0D1nB/wPVcdyGLEdvV1R/+MNiWtebP7ig1AI3I9pxh+jJpIH0VYuxscbo8LgO9+ZDdi4SVePfOb 4NHkrMH8OZ2kdxSfX1zb2pOb13LxHwL8KNQS/Ymu6UFOlea9tg0i3+/1AzyYr1f5YGksGJO20bo b0ppvKcGOr0FqJUdDI60iB/+X8cISlaVj3aiuROr1ffa0qlSB2vgcAFUG5VlQ0bVXddvXIWfLBV Hs5MT0CDzuI7FJSJXd/UVa4vDcGnGBquF/+waGpqkslxh0adIQgq8RT3qzzRRuygv0JVPi2Z68h ekZQ+UyxmP3Jw3meodGZXogrpcIDRYy7a5XtSeCwgFD3Te6j X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS introduces a number of system registers, on systems with GCS we need to context switch them and expose them to VMMs to allow guests to use GCS. In order to allow guests to use GCS we also need to configure HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and CHKFEAT will report GCS as disabled. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- arch/arm64/include/asm/kvm_emulate.h | 3 +++ arch/arm64/include/asm/kvm_host.h | 14 ++++++++++ arch/arm64/include/asm/vncr_mapping.h | 2 ++ arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 28 ++++++++++++++++++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 11 ++++++++ arch/arm64/kvm/sys_regs.c | 42 ++++++++++++++++++++++++++= ++++ 6 files changed, 100 insertions(+) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index a3c1928bdf74..0cd91b3d6c82 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -712,6 +712,9 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) if (kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V)) vcpu->arch.hcrx_el2 |=3D HCRX_EL2_EnASR; =20 + if (kvm_has_gcs(kvm)) + vcpu->arch.hcrx_el2 |=3D HCRX_EL2_GCSEn; + /* * NV3 is a host-specific extension, and we always use * it when present and that the guest uses NV. It may diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 27fe0cd5b2d7..6aba1bcb8ee7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -500,6 +500,10 @@ enum vcpu_sysreg { =20 POR_EL0, /* Permission Overlay Register 0 (EL0) */ =20 + /* Guarded Control Stack registers */ + GCSCRE0_EL1, /* Guarded Control Stack Control (EL0) */ + GCSPR_EL0, /* Guarded Control Stack Pointer (EL0) */ + /* FP/SIMD/SVE */ SVCR, FPMR, @@ -520,6 +524,8 @@ enum vcpu_sysreg { PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ PIR_EL2, /* Permission Indirection Register 1 (EL2) */ POR_EL2, /* Permission Overlay Register 2 (EL2) */ + GCSCR_EL2, /* Guarded Control Stack Control Register (EL2) */ + GCSPR_EL2, /* Guarded Control Stack Pointer Register (EL2) */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ @@ -592,6 +598,10 @@ enum vcpu_sysreg { VNCR(VDISR_EL2), VNCR(VSESR_EL2), =20 + /* Guarded Control Stack registers */ + VNCR(GCSPR_EL1), /* Guarded Control Stack Pointer (EL1) */ + VNCR(GCSCR_EL1), /* Guarded Control Stack Control (EL1) */ + VNCR(HFGRTR_EL2), VNCR(HFGWTR_EL2), VNCR(HFGITR_EL2), @@ -1654,6 +1664,10 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64= val); #define kvm_has_sctlr2(k) \ (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) =20 +#define kvm_has_gcs(k) \ + (system_supports_gcs() && \ + kvm_has_feat((k), ID_AA64PFR1_EL1, GCS, IMP)) + static inline bool kvm_arch_has_irq_bypass(void) { return true; diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index 9e8a49fa8b63..e589adccc2f3 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -97,6 +97,8 @@ #define VNCR_PMSNEVFR_EL1 0x850 #define VNCR_PMSDSFR_EL1 0x858 #define VNCR_TRFCR_EL1 0x880 +#define VNCR_GCSPR_EL1 0x8C0 +#define VNCR_GCSCR_EL1 0x8D0 #define VNCR_MPAM1_EL1 0x900 #define VNCR_MPAMHCR_EL2 0x930 #define VNCR_MPAMVPMV_EL2 0x938 diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index c382848d3194..d26802aa455e 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -17,6 +17,7 @@ #include =20 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt); +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt); =20 static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt) { @@ -67,6 +68,11 @@ static inline void __sysreg_save_user_state(struct kvm_c= pu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); + + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL0) =3D read_sysreg_s(SYS_GCSPR_EL0); + ctxt_sys_reg(ctxt, GCSCRE0_EL1) =3D read_sysreg_s(SYS_GCSCRE0_EL1); + } } =20 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt) @@ -131,6 +137,14 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_cont= ext *ctxt) return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu =3D ctxt_to_vcpu(ctxt); + + return kvm_has_gcs(kern_hyp_va(vcpu->kvm)); + +} + static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); @@ -144,6 +158,10 @@ static inline void __sysreg_save_el1_state(struct kvm_= cpu_context *ctxt) if (ctxt_has_s1pie(ctxt)) { ctxt_sys_reg(ctxt, PIR_EL1) =3D read_sysreg_el1(SYS_PIR); ctxt_sys_reg(ctxt, PIRE0_EL1) =3D read_sysreg_el1(SYS_PIRE0); + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL1) =3D read_sysreg_el1(SYS_GCSPR); + ctxt_sys_reg(ctxt, GCSCR_EL1) =3D read_sysreg_el1(SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) @@ -210,6 +228,11 @@ static inline void __sysreg_restore_user_state(struct = kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_gcs(ctxt)) { + write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0); + write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1), + SYS_GCSCRE0_EL1); + } } =20 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, @@ -243,6 +266,11 @@ static inline void __sysreg_restore_el1_state(struct k= vm_cpu_context *ctxt, if (ctxt_has_s1pie(ctxt)) { write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR); write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0); + + if (ctxt_has_gcs(ctxt)) { + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1), SYS_GCSPR); + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1), SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sy= sreg-sr.c index 0c4ef1ce32ae..08b5d939a6c5 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -59,10 +59,14 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *v= cpu) if (ctxt_has_s1pie(&vcpu->arch.ctxt)) { __vcpu_assign_sys_reg(vcpu, PIRE0_EL2, read_sysreg_el1(SYS_PIRE0)); __vcpu_assign_sys_reg(vcpu, PIR_EL2, read_sysreg_el1(SYS_PIR)); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) + __vcpu_assign_sys_reg(vcpu, GCSCR_EL2, read_sysreg_el1(SYS_GCSCR)); } =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) __vcpu_assign_sys_reg(vcpu, POR_EL2, read_sysreg_el1(SYS_POR)); + } =20 /* @@ -86,6 +90,8 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcp= u) __vcpu_assign_sys_reg(vcpu, SP_EL2, read_sysreg(sp_el1)); __vcpu_assign_sys_reg(vcpu, ELR_EL2, read_sysreg_el1(SYS_ELR)); __vcpu_assign_sys_reg(vcpu, SPSR_EL2, read_sysreg_el1(SYS_SPSR)); + if (ctxt_has_gcs(&vcpu->arch.ctxt)) + __vcpu_assign_sys_reg(vcpu, GCSPR_EL2, read_sysreg_el1(SYS_GCSPR)); =20 if (ctxt_has_sctlr2(&vcpu->arch.ctxt)) __vcpu_assign_sys_reg(vcpu, SCTLR2_EL2, read_sysreg_el1(SYS_SCTLR2)); @@ -138,6 +144,11 @@ static void __sysreg_restore_vel2_state(struct kvm_vcp= u *vcpu) if (ctxt_has_s1pie(&vcpu->arch.ctxt)) { write_sysreg_el1(__vcpu_sys_reg(vcpu, PIR_EL2), SYS_PIR); write_sysreg_el1(__vcpu_sys_reg(vcpu, PIRE0_EL2), SYS_PIRE0); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) { + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSCR_EL2), SYS_GCSCR); + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSPR_EL2), SYS_GCSPR); + } } =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 44aae52c473d..c5ce18b3f7d8 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -109,6 +109,8 @@ static enum sr_loc_attr locate_direct_register(const st= ruct kvm_vcpu *vcpu, case PIR_EL1: case PIRE0_EL1: case POR_EL1: + case GCSCR_EL1: + case GCSPR_EL1: case ESR_EL1: case AFSR0_EL1: case AFSR1_EL1: @@ -135,6 +137,8 @@ static enum sr_loc_attr locate_direct_register(const st= ruct kvm_vcpu *vcpu, case DACR32_EL2: case IFSR32_EL2: case DBGVCR32_EL2: + case GCSCRE0_EL1: + case GCSPR_EL0: /* These registers are always loaded, no matter what */ return SR_LOC_LOADED; =20 @@ -198,6 +202,8 @@ static void locate_register(const struct kvm_vcpu *vcpu= , enum vcpu_sysreg reg, MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSCR_EL2, GCSCR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSPR_EL2, GCSPR_EL1, NULL ); MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); @@ -253,6 +259,10 @@ static u64 read_sr_from_cpu(enum vcpu_sysreg reg) case TCR2_EL1: val =3D read_sysreg_s(SYS_TCR2_EL12); break; case PIR_EL1: val =3D read_sysreg_s(SYS_PIR_EL12); break; case PIRE0_EL1: val =3D read_sysreg_s(SYS_PIRE0_EL12); break; + case GCSPR_EL0: val =3D read_sysreg_s(SYS_GCSPR_EL0); break; + case GCSCRE0_EL1: val =3D read_sysreg_s(SYS_GCSCRE0_EL1); break; + case GCSCR_EL1: val =3D read_sysreg_s(SYS_GCSCR_EL12); break; + case GCSPR_EL1: val =3D read_sysreg_s(SYS_GCSPR_EL12); break; case POR_EL1: val =3D read_sysreg_s(SYS_POR_EL12); break; case ESR_EL1: val =3D read_sysreg_s(SYS_ESR_EL12); break; case AFSR0_EL1: val =3D read_sysreg_s(SYS_AFSR0_EL12); break; @@ -293,6 +303,10 @@ static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 = val) case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; + case GCSCRE0_EL1: write_sysreg_s(val, SYS_GCSCRE0_EL1); break; + case GCSPR_EL0: write_sysreg_s(val, SYS_GCSPR_EL0); break; + case GCSCR_EL1: write_sysreg_s(val, SYS_GCSCR_EL12); break; + case GCSPR_EL1: write_sysreg_s(val, SYS_GCSPR_EL12); break; case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; @@ -3089,6 +3103,21 @@ static unsigned int cnthv_visibility(const struct kv= m_vcpu *vcpu, return REG_HIDDEN; } =20 +static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + if (kvm_has_gcs(vcpu->kvm)) + return 0; + + return REG_HIDDEN; +} + +static unsigned int gcs_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + return __el2_visibility(vcpu, rd, gcs_visibility); +} + static bool access_mdcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3493,6 +3522,13 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { PTRAUTH_KEY(APDB), PTRAUTH_KEY(APGA), =20 + { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSPR_EL1), NULL, reset_unknown, GCSPR_EL1, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSCRE0_EL1), NULL, reset_val, GCSCRE0_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_SPSR_EL1), access_spsr}, { SYS_DESC(SYS_ELR_EL1), access_elr}, =20 @@ -3618,6 +3654,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | CTR_EL0_IminLine_MASK), + { SYS_DESC(SYS_GCSPR_EL0), NULL, reset_unknown, GCSPR_EL0, + .visibility =3D gcs_visibility }, { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility =3D f= p8_visibility }, =20 @@ -3861,6 +3899,10 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, vncr_el2_visibility), =20 + EL2_REG_FILTERED(GCSCR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), + EL2_REG_FILTERED(GCSPR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8F2E329E5D; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-4-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1878; i=broonie@kernel.org; h=from:subject:message-id; bh=LwMT3EVZoWU5eNa5DiJ2GGvvTQFQp0oHfZnwyQfQBTQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0ifKxbOLVWORa3S4gy8SI5WMrDaK9fxgLlXc /ggZP58ZZeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdInwAKCRAk1otyXVSH 0FPFB/9+UT3nttgf5in3uZHBX+a83G4M3mzsPxIAtI5dFCKihmUZJYyUl3Hrv2Pd8Srnlv5oUYs u5z+FAemxHbTL0wxShYystY3zBLfLuTHn6buak8cKPgI/aA6oPQ0i85ugxkCnzGctkADLwTgkZA /OW7ciq7enmv/DA8vyEO2OzCVbb7gV7td7MlGizbWKKPFKjHa+QSOBm0PZXMDbcwCsL4YKiIotp i1tO2KR43yiB+lUUF23XcMt1/saoH+eO6ol9c8kLApMCgZCfL6YSm+h1M9S1TxsqeD8x7cvWCWs TIo8UFvc6YXlVB1Qj0Rz7oqtZtn4fkJnCRcZIaurEzPoE1ei X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In order to allow efficient implementation of GCS implementations are permitted to do GCS specific caching, with barriers implicit in stack switch operations and GCSB DSYNC as an explicit barrier. Since we do not use GCS in the hypervisor or host kernel the hypervisor cannot rely on any barriers being present in vCPU context switches other than those it explicitly inserts. Add explicit barriers when loading and saving vCPU state. Signed-off-by: Mark Brown Reviewed-by: Yuan Yao Reviewed-by: Leonardo Bras Reviewed-by: Lorenzo Stoakes (ARM) --- arch/arm64/kvm/arm.c | 7 +++++++ arch/arm64/kvm/hyp/nvhe/hyp-main.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 8b080804bc90..52f53f682e6a 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -755,6 +755,13 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY); } =20 + /* + * Ensure any GCS memory effects from the outgoing vCPU are + * visible elsewhere. + */ + if (kvm_has_gcs(vcpu->kvm)) + gcsb_dsync(); + kvm_vcpu_put_debug(vcpu); kvm_arch_vcpu_put_fp(vcpu); if (has_vhe()) diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/h= yp-main.c index 9a3b92e626ad..534db037c5f6 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -261,6 +261,13 @@ static void sync_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vc= pu) fpsimd_sve_sync(&hyp_vcpu->vcpu); sync_debug_state(hyp_vcpu); =20 + /* + * Ensure any GCS memory effects from the outgoing vCPU are + * visible elsewhere even if the host skips syncing. + */ + if (kvm_has_gcs(hyp_vcpu->vcpu.kvm)) + gcsb_dsync(); + if (pkvm_hyp_vcpu_is_protected(hyp_vcpu)) { host_vcpu->arch.ctxt =3D hyp_vcpu->vcpu.arch.ctxt; } else { --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38F5F397E89; Tue, 1 Sep 2026 21:50:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299456; cv=none; b=ss9dw5ANo2uM5Ba23+6CqqatGDErQ6zdKv6MaCYSD/IA4kACblNeixjwCLIGzgFY5nf8wL77zorV8dg9St3QvCC+jFxJc79Xcy6FMlKCNjD3+yqduEFYO1Hi4sH/y9qadppLcqBgj8ri+wLtE84DPVa7fv/jlag4364AzAOat8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299456; c=relaxed/simple; bh=3iH+1nUhsEJN00Qw463PdcsZjZP8Q5hktNUuslTMlxM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZmC9kkQRTLE93Hw4YR2pKymzVsL7YiPDwsh1YVz4W2YKCmfynErYUAJ7LBstzIWmPCAP0cNdKQa9YdTJ9NiClOeGvon1W5/DMRa/zvr9pu24+79gieVH3TKbwHklfKXs1B+2sB7akjQyODwBww3Xs8eBD//7qsMl/OaNcXrTgVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I2FmYZZM; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I2FmYZZM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B056F1F00A3E; Tue, 1 Sep 2026 21:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299454; bh=lBA+J448Iua93g/qbLnqNUoqyaKmMk0WVYNGvf6vR94=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=I2FmYZZMBKjKRsiG89p1iHHkHB7EVMZWBb8uxGs6+81oUK3ZwPon5F7nKEhaYVXdu WodzHb5fF9HjI+DliUmDTnwPxsKlwHdu+NZW8WpwU424aadbWzc7/NnbdNH7bfzpML XgZCGrO/4+y+BUR6ENXnS/tIS0TUG1vmJLGmczC71m5IK1ocJ4eCoyhqiGVMzTkE8/ 0IJiPezXUcx9r2wrNqUfS+GRgLEM6Avm1y5p+vWO/J2BGEg6d9cp+CIxXmCOBTPlvz 6U/VwYeUZvQcx8+l2/W27z4wkxRlaQGn7MkzXNDs3HTg05JKbydgSri2U8odGTlD2D 2w3iMZ2WDqWHw== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:03 +0100 Subject: [PATCH v20 05/14] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-5-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2743; i=broonie@kernel.org; h=from:subject:message-id; bh=3iH+1nUhsEJN00Qw463PdcsZjZP8Q5hktNUuslTMlxM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0igEXcjS1jffnwhPl/7D+f19Fp5b7boxQo5U EPFTqc+3kWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIoAAKCRAk1otyXVSH 0AvTB/sEU0gXvVDV7maD6BHIZmkQiZN3btgN5V+6+jmhJOL5LRfIRKLutr6BlKwWwhfRCMZ/0BN pzsc8DcNc3Wd2/IS/kHpyEP4MPXsvwL9vyLngsyFpBgL8RqRWh3Yadu68IuDLC8mQ49RvTAoiVk h4Np6Smsjk717sR1A3p4/u3jqBbJtg01K20IDEjPTVOwZvqP/9jfsqXE7fUJ/vVHEMw5DV9NjxB fBehd7s9H7+af3YfxeZ8FHoGGhXDmkMKSwxqkBjuwJGglPuJXNXDuIp6e8M3ALhgVHOREgd2QqZ UN3I8dme2tFsI+2CYBv0P3M9AD4omM/dl4PqyoaqygH3gT3u X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI 0487 R_WTXBY we need to manage PSTATE.EXLOCK when entering an exception, when the exception is entered from a lower EL the bit is cleared while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN. Implement this behaviour in enter_exception64(). Reviewed-by: Yuan Yao Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras Reviewed-by: Lorenzo Stoakes (ARM) --- arch/arm64/include/uapi/asm/ptrace.h | 1 + arch/arm64/kvm/hyp/exception.c | 37 ++++++++++++++++++++++++++++++++= ++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi= /asm/ptrace.h index 15649a253a57..eed7f1226be6 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -56,6 +56,7 @@ #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 #define PSR_N_BIT 0x80000000 +#define PSR_EXLOCK_BIT 0x400000000 =20 #define PSR_BTYPE_SHIFT 10 =20 diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index 754e2dc1df54..85c873644fe9 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c @@ -49,6 +49,38 @@ static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu,= u64 val) vcpu->arch.ctxt.spsr_und =3D val; } =20 +static unsigned long compute_exlock(struct kvm_vcpu *vcpu, + unsigned long mode, + unsigned long target_mode) +{ + u64 gcscr; + + if (!kvm_has_gcs(kern_hyp_va(vcpu->kvm))) + return 0; + + /* GCS can't be enabled for 32 bit */ + if (mode & PSR_MODE32_BIT) + return 0; + + /* When taking an exception to a higher EL EXLOCK is cleared. */ + if ((mode | PSR_MODE_THREAD_BIT) !=3D target_mode) + return 0; + + /* + * When taking an exception to the same EL EXLOCK is set to + * the effective value of GCSR_ELx.EXLOCKEN. + */ + if (is_hyp_ctxt(vcpu)) + gcscr =3D vcpu_read_sys_reg(vcpu, GCSCR_EL2); + else + gcscr =3D vcpu_read_sys_reg(vcpu, GCSCR_EL1); + + if (gcscr & GCSCR_ELx_EXLOCKEN) + return PSR_EXLOCK_BIT; + + return 0; +} + /* * This performs the exception entry at a given EL (@target_mode), stashin= g PC * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTAT= E. @@ -138,6 +170,11 @@ static void enter_exception64(struct kvm_vcpu *vcpu, u= nsigned long target_mode, // PSTATE.BTYPE is set to zero upon any exception to AArch64 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. =20 + // PSTATE.EXLOCK is set to 0 upon any exception to a higher + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same + // exception level. See ARM DDI 0487 R_WTXBY. + new |=3D compute_exlock(vcpu, mode, target_mode); + new |=3D PSR_D_BIT; new |=3D PSR_A_BIT; new |=3D PSR_I_BIT; --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9A642D0C89; Tue, 1 Sep 2026 21:50:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299462; cv=none; b=G+eAaiXA6676iVXLhyJAqP/yArbJk+ceMrpRktzRO0GPsqFejthJCspDYR8yUtSAmBkXYefJI083U0kWEo7TppRFXaxCM8j4kGt3/f26NJE03Kj9zjMBHP6voXyJHafaRa0vRvWjcEW9hlU4KpNIRdLKahaE34Tktu3n2j8nKmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299462; c=relaxed/simple; bh=bxVsB4rskIKiN1PVeIRuoZGQxKFGSMyZpayUqX7OE88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZLPtPQSv9HnEwCv2nve0I3YecbNDVG+PXuk4Y2ZrNQGEg44OPNsGYdGsDAxaC1J50f4xUYiUOxD3lxDyoUVlGMxha+bIgHp7W6/ndik6+/GYHogn+heoScmdXtFJarsBtCTuPrtpuylA51ebr8floRFrD3UuHFv5mde0Vbb6Rmc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=id4kALbJ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="id4kALbJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E88B1F00A3A; Tue, 1 Sep 2026 21:50:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299458; bh=KHnPZg/net7a+AQdOjT36JOU7VGnbjYxcvxeIjCtLNc=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=id4kALbJSvCv3lQfPGhvN2kJZaoPf1b9Y30ySDtXKHwI8CBLWJrLqw71t5KrAW8En MXMd0nPS9VgdXjm1LPqiTki2NRk5zyiyUabs+2LkJlPwX1wnnY42ZTD/U1ovl2XHgI oqflOJDkmFA2MEEkUuezZ5m+kP2T7JMu3dlAstk1TLnxFxKaMod2DRiCYSjmJRozhp QgsfhsNhTUlXDhY/dasYVlwlM6e51s/g4BQf82zOVbRXukYM4uBnwSqvPkd259NS2d MngVOrAlXXV0QSCf87w2X00anCV4JlF0vw3eUmc4L/uhyknGEDehVy/KCvYqa5zZwn zYmwvJMClFdSQ== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:04 +0100 Subject: [PATCH v20 06/14] KVM: arm64: Validate GCS exception lock when emulating ERET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-6-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3807; i=broonie@kernel.org; h=from:subject:message-id; bh=bxVsB4rskIKiN1PVeIRuoZGQxKFGSMyZpayUqX7OE88=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0ih5Tuxm01Ccs5r23+rEkMvOu6q3wxrigZEO HcQ18QxVZaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIoQAKCRAk1otyXVSH 0Pf4B/4nRi9ComSxb4Ck0ja/JaqjMy3dr/ZrdhDUUElLzcIr+Awkq/MO2hMBdUksVXV8aYMr/jC iAuBZTEkxvHHKDVp9lok7PS/ViOGfl1uY5hqCghgJdZvCWf4klKP/ZjRHpWisLzYFJfpWgvI68M 1Zz7ovId5SDzC9o/bSo4TWXknAZCMxcQ2XlnfzcDVg/wGf8LhL8ltGxEiPhdoIpmnFLRjN1+L4b FwPMqzqDFGB0Jqt/tZMdMdNEN2jYRVcKQ1RnZ/uwAL8AZi4Rqkd1nIuO51S/N5wbnmjIwIguafk 0NxH70532VXwp4po2XVZQYQD0dupQjkKhC2qb1AeBV2jRo1j X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI0487 R_TYTWB GCS adds an additional case where an illegal exception return can be generated. If all of: - PSTATE.EXLOCK is 0. - The EL is not being changed by the ERET. - GCSCR_ELx.EXLOCKEN is 1. are true then the return is illegal. Emulate this behaviour when emulating ERET for nested guests, while we're at it using the symbolic definition for EXLOCK in SPSR. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- arch/arm64/include/asm/kvm_nested.h | 32 ++++++++++++++++++++++++++++++++ arch/arm64/kvm/emulate-nested.c | 5 ++++- arch/arm64/kvm/hyp/vhe/switch.c | 4 ++++ 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/k= vm_nested.h index 1ed708335809..9e595e8e7642 100644 --- a/arch/arm64/include/asm/kvm_nested.h +++ b/arch/arm64/include/asm/kvm_nested.h @@ -240,6 +240,38 @@ static inline bool kvm_auth_eretax(struct kvm_vcpu *vc= pu, u64 *elr) } #endif =20 +#ifdef CONFIG_ARM64_GCS +/* See IllegalExceptionReturn() pseudocode */ +static inline bool kvm_check_illegal_exlock_return(struct kvm_vcpu *vcpu, + u64 spsr) +{ + u64 pstate, cur_mode, target_mode; + + if (!kvm_has_gcs(vcpu->kvm)) + return false; + + if (vcpu->arch.ctxt.regs.pstate & PSR_EXLOCK_BIT) + return false; + + /* Check the EL only, ignore thread mode */ + pstate =3D vcpu->arch.ctxt.regs.pstate; + cur_mode =3D (pstate & PSR_MODE_MASK) | PSR_MODE_THREAD_BIT; + target_mode =3D (spsr & PSR_MODE_MASK) | PSR_MODE_THREAD_BIT; + + if (cur_mode !=3D target_mode) + return false; + + return vcpu_read_sys_reg(vcpu, GCSCR_EL2) & GCSCR_ELx_EXLOCKEN; +} + +#else +static inline bool kvm_check_illegal_exlock_return(struct kvm_vcpu *vcpu, + u64 spsr) +{ + return false; +} +#endif + #define KVM_NV_GUEST_MAP_SZ (KVM_PGTABLE_PROT_SW1 | KVM_PGTABLE_PROT_SW0) =20 static inline u64 kvm_encode_nested_level(struct kvm_s2_trans *trans) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 3806ff0920fe..170c0c521f22 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2748,10 +2748,13 @@ static u64 kvm_check_illegal_exception_return(struc= t kvm_vcpu *vcpu, u64 spsr) * - trying to return to an illegal M value * - trying to return to a 32bit EL * - trying to return to EL1 with HCR_EL2.TGE set + * - GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK is 0 when attempting + * to return from ELx the same EL. */ if (mode =3D=3D PSR_MODE_EL3t || mode =3D=3D PSR_MODE_EL3h || mode =3D=3D 0b00001 || (mode & BIT(1)) || (spsr & PSR_MODE32_BIT) || + kvm_check_illegal_exlock_return(vcpu, spsr) || (vcpu_el2_tge_is_set(vcpu) && (mode =3D=3D PSR_MODE_EL1t || mode =3D=3D PSR_MODE_EL1h))) { u64 mask; @@ -2778,7 +2781,7 @@ static u64 kvm_check_illegal_exception_return(struct = kvm_vcpu *vcpu, u64 spsr) =20 mask =3D PSR_MODE_MASK | PSR_MODE32_BIT; if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) - mask |=3D BIT_ULL(34); /* PSTATE.EXLOCK */ + mask |=3D PSR_EXLOCK_BIT; =20 spsr |=3D *vcpu_cpsr(vcpu) & mask; spsr |=3D PSR_IL_BIT; diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switc= h.c index 7875911c0506..af59d1bf51ad 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -383,6 +383,10 @@ static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu,= u64 *exit_code) return false; } =20 + /* Push GCS exception lock failures into the slow path */ + if (kvm_check_illegal_exlock_return(vcpu, spsr)) + return false; + /* If ERETAx fails, take the slow path */ if (esr_iss_is_eretax(esr)) { if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr))) --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50D023806AD; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-7-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1286; i=broonie@kernel.org; h=from:subject:message-id; bh=ybZ3Kdn/7X6FtbChfk8rW3p585sYuKBjGuFuBHbmNzA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0ih715I7fTQ8ImR5pPuXiL5bjJV6Yt6xQaij m17Hr7PAbCJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIoQAKCRAk1otyXVSH 0DAfB/9WzE5SnoA6xrOiQ6faxAotAUN5O1BpWGY3P1Q3uA8gLLr83/moWCnFRRb9cYMAaiKck+T jZUpsFk1gtgdF7SiIrcCbRgPv5l144hBm/Fc8KKEpuS7p2WmNg3O6YN7+x1PXZULD1vxkKAyLS+ L3iDSWXv4Ytu8SLiczzTC81ioPGMyqLMblIJQ/YBpzZMxN8+4lqAf4nkqxWwBLe+L6LExTl+Oj8 +ZmmzqRYFl9iruvA4K+jpOWzhh2gmbgo9V/ERWPSeU5HoZxqY5dcR7o696C3IX1PENQwejk9tJa VYzH1wzs1ALlnoUrGMldITlNim0Ml+jCZFc0rUE0vhWCNBwl X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB For nested guests where HFGITR_EL2.nGCSSTR_EL1 is clear or when there are L2 GCS data check exceptions we need to forward the exception to the guest. Add handling to do so. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- arch/arm64/kvm/handle_exit.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index db37678dcb05..a8198e96fcb4 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -304,12 +304,24 @@ static int handle_svc(struct kvm_vcpu *vcpu) return 1; } =20 +/* + * We might get GCS exceptions that need to be forwarded to the + * hypervisor when a nested guest has HFGITR_EL2.nGCSSTR_EL1 clear, or + * for a GCS data check exception for a L2 guest. + */ static int kvm_handle_gcs(struct kvm_vcpu *vcpu) { - /* We don't expect GCS, so treat it with contempt */ - if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) - WARN_ON_ONCE(1); + if (!kvm_has_gcs(vcpu->kvm)) { + kvm_inject_undefined(vcpu); + return 1; + } =20 + if (vcpu_has_nv(vcpu)) { + kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); + return 1; + } + + WARN_ON_ONCE(1); kvm_inject_undefined(vcpu); return 1; } --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EBB1263F4A; Tue, 1 Sep 2026 21:51:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299468; cv=none; b=Tp+4oJN3mMPDJMzOqXLLoDjtkRwxuIQVxl2Xs350MQu2o7GRPaLJKN1SDMEBLmKIFSRAjw7GRf+pPCEhkEovYJht4cWTEqCmlRas+E3aWWtJJ4W8pSGO4ponqyHUztHskEmYu1lQPFzaVNzVJdHUhkjI7P4XJbcU7If1HBsDuQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299468; c=relaxed/simple; bh=myX2r5YA1lyE6PF9X7vRwEe8NUR6TEzLmdONy7VX99g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per I_CFFNS and the pseudocode for the SPSR_ELx and ELR_ELx registers a GCS exception with ExType 1 is generated for attempts to write to those registers when both GCSCR_ELx.EXLOCKEN and PSTATE.EXLOCK are set. Ensure that this is enforced for guests if access to these registers from the guest is handled by the hypervisor. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- arch/arm64/include/asm/kvm_emulate.h | 8 +++++++ arch/arm64/kvm/sys_regs.c | 42 ++++++++++++++++++++++++++++++++= ---- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 0cd91b3d6c82..e47ab38327de 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -81,6 +81,14 @@ int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); int kvm_inject_nested_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); int kvm_inject_nested_serror(struct kvm_vcpu *vcpu, u64 esr); =20 +static inline void kvm_inject_exlock(struct kvm_vcpu *vcpu) +{ + u64 esr =3D FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_GCS) | ESR_ELx_IL | + FIELD_PREP(ESR_ELx_ExType_MASK, ESR_ELx_ExType_EXLOCK); + + kvm_inject_sync(vcpu, esr); +} + static inline void kvm_inject_nested_sve_trap(struct kvm_vcpu *vcpu) { u64 esr =3D FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SVE) | diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c5ce18b3f7d8..1f80c26a9839 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2866,14 +2866,42 @@ static bool access_sp_el1(struct kvm_vcpu *vcpu, return true; } =20 +static inline bool sysregs_exlocked(struct kvm_vcpu *vcpu) +{ + u64 gcscr; + + if (!kvm_has_gcs(vcpu->kvm)) + return false; + + if (!(vcpu->arch.ctxt.regs.pstate & PSR_EXLOCK_BIT)) + return false; + + /* + * Note that the EXLOCKEN for the running EL is checked + * regardless of the register written to. + */ + if (is_hyp_ctxt(vcpu)) + gcscr =3D vcpu_read_sys_reg(vcpu, GCSCR_EL2); + else + gcscr =3D vcpu_read_sys_reg(vcpu, GCSCR_EL1); + + return gcscr & GCSCR_ELx_EXLOCKEN; +} + static bool access_elr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - if (p->is_write) + if (p->is_write) { + if (sysregs_exlocked(vcpu)) { + kvm_inject_exlock(vcpu); + return false; + } + vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); - else + } else { p->regval =3D vcpu_read_sys_reg(vcpu, ELR_EL1); + } =20 return true; } @@ -2882,10 +2910,16 @@ static bool access_spsr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - if (p->is_write) + if (p->is_write) { + if (sysregs_exlocked(vcpu)) { + kvm_inject_exlock(vcpu); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-9-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1947; i=broonie@kernel.org; h=from:subject:message-id; bh=sVwijteYWmwsPHrOhzgNw/h8bxNw24CK78k3J1PaD0o=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0ijTOOgU+g5ib2qdw5i9m5Up1vp0bgOidFbt N7sgbGHYNeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIowAKCRAk1otyXVSH 0D71B/9cf0Tr9O/jvhvol2aAHSpSGqkbgy5qn1+oWqbQ4Gr2Q8DUJj38IvXWXLZVU8+mD9f0BzI RtT9nnduQBP9zjkO0Xxjf2lFL5sbJ63eu12X6ZfULwyCASUzTxOB4VRzEGLcvtshRdpMuT6+biJ 3m+VMjNbqpucJqLCszqSimSggsuxOQfPGRjG9j1VGfpSH4onTKf/XLJBhSIhv7+UeD7YAm1WwaT LMWdOt2tkZHP1u003Em5G86ogV5SkGYzZgZwwboiYBQYJGxdKle9Jw2XVPL+9Tp1+Y8hJkR7nZi 6UsaFzTADQQoNB+2II6Dyf4v8uTDYWTiy9eotFc+bsA97CDa X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Now that required functionality for GCS is in place expose ID_AA64PFR1_EL1.GCS, allowing guests to be given the feature. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- arch/arm64/kvm/nested.c | 3 +-- arch/arm64/kvm/sys_regs.c | 5 +++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 17123f0b6dab..a9dea85b6192 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1702,11 +1702,10 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 v= al) break; =20 case SYS_ID_AA64PFR1_EL1: - /* Only support BTI, SSBS, CSV2_frac */ + /* Only support GCS, BTI, SSBS, CSV2_frac */ val &=3D ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | - ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_SME | diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1f80c26a9839..fb2c9fd42e24 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2193,10 +2193,12 @@ static u64 sanitise_id_aa64pfr1_el1(const struct kv= m_vcpu *vcpu, u64 val) SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) =3D=3D ID_AA64PFR0_EL1_RA= S_IMP)) val &=3D ~ID_AA64PFR1_EL1_RAS_frac; =20 + if (!system_supports_gcs()) + val &=3D ~ID_AA64PFR1_EL1_GCS; + val &=3D ~ID_AA64PFR1_EL1_SME; val &=3D ~ID_AA64PFR1_EL1_RNDR_trap; val &=3D ~ID_AA64PFR1_EL1_NMI; - val &=3D ~ID_AA64PFR1_EL1_GCS; val &=3D ~ID_AA64PFR1_EL1_THE; val &=3D ~ID_AA64PFR1_EL1_MTEX; val &=3D ~ID_AA64PFR1_EL1_PFAR; @@ -3444,7 +3446,6 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | - ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_RNDR_trap | --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4927D39A4B3; Tue, 1 Sep 2026 21:51:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; 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Tue, 1 Sep 2026 21:51:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299472; bh=bWXcOIpJt0ovJU16FmG1ZP6mcgZr3j3D33y4oNpUlCk=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=dqQPdV4QMg72eA3iW8tJJRqLOIA3F5BlZLW8dD7q2dPiYVDJSr359F5NR7j9vFmVK Mon/0Z7P6jlrpCzz57D+uRnz17CO7t9tUixggeqoFi9iTrpZVsdOCllWeWffL5P2Ag zT9PxufQBtqGq8pFC2mmiqZZk2XQ+Lo1DniFYpMwCdgxHrbVrYdhWFD9XCF5/KA3sb t/+EUNtjlm4NxkQ+TlLOSVgUbAmYeeuGgqKEm38P8dBr9mnR4h4QlPS2wuWaA/O6vr sgs0fT4pD/srWe/TfPBaFkI6Jy5RfyZHHsYg9XfkiUqFy4SG9RmPqmf4W8etOqcQg0 xiZ6R3NdXTo0w== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:08 +0100 Subject: [PATCH v20 10/14] KVM: selftests: arm64: Add GCS registers to get-reg-list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-10-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown , Thiago Jung Bauermann X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2412; i=broonie@kernel.org; h=from:subject:message-id; bh=xg1pj0+0KbUi3OkikMffllT1hzgPv//XZnVR7ZYSlfM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0ikrF8qYlqNzoV4imfln/ELsFLZ1ykMLSIE4 /+fOyDllMyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIpAAKCRAk1otyXVSH 0JrCB/9O6BHtHIZ3KZPo6pGnkjDz4YRHxA3MD7UGXtBSYcGJjGcJUACQ47c+uH3kQ3awMogdvcx 5+UI+3m3pCYcWqfTgRVLDrEIPK+jYxUujMZ2uKoylHw5P3eHxB1F0CsdXRet7bPkTQynABylSnU gvvl/zH7Nh9Q+kGPXEwPfx7dKflhY6IyyKB1uQqKKoOD4PtVcDK3GE2XoktOtpQ3keY9+v+ch23 9m0qx3MaIPD64YXK1g70TJ1FoqaTrToFlt2r8ETrGp3pahKQmbtlQ/6nhtxzD9b/BkxUVUNEPPW 3R1vJR68Kj1fbfR+TJb2Wck5I8NlysmJChEfo6RdGZa0TCkU X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS adds new registers GCSCR_ELx, GCSCRE0_EL1 and GCSPR_ELx. Add these to those validated by get-reg-list. Reviewed-by: Thiago Jung Bauermann Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/get-reg-list.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testi= ng/selftests/kvm/arm64/get-reg-list.c index 533994687b5d..5c1469153b6c 100644 --- a/tools/testing/selftests/kvm/arm64/get-reg-list.c +++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c @@ -42,6 +42,12 @@ struct feature_id_reg { static struct feature_id_reg feat_id_regs[] =3D { REG_FEAT(TCR2_EL1, ID_AA64MMFR3_EL1, TCRX, IMP), REG_FEAT(TCR2_EL2, ID_AA64MMFR3_EL1, TCRX, IMP), + REG_FEAT(GCSPR_EL0, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL2, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCRE0_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL2, ID_AA64PFR1_EL1, GCS, IMP), REG_FEAT(PIRE0_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIRE0_EL2, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIR_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), @@ -503,6 +509,9 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 0), /* GCSCR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 1), /* GCSPR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 2), /* GCSCRE0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 0), /* AFSR0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 1), /* AFSR1_EL1 */ ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ @@ -519,6 +528,7 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ + ARM64_SYS_REG(3, 3, 2, 5, 1), /* GCSPR_EL0 */ ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ @@ -740,6 +750,8 @@ static __u64 el2_regs[] =3D { SYS_REG(VTTBR_EL2), SYS_REG(VTCR_EL2), SYS_REG(VNCR_EL2), + SYS_REG(GCSPR_EL2), + SYS_REG(GCSCR_EL2), SYS_REG(HDFGRTR2_EL2), SYS_REG(HDFGWTR2_EL2), SYS_REG(HFGRTR2_EL2), --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 785B837C0F6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-11-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=987; i=broonie@kernel.org; h=from:subject:message-id; bh=d3SxEv6RjSY+xiyxMK7Zi+tIruIS+RbgPdYjX8k0TSU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0ile6y9IO6whC6xpi+oS4hBxrk51YhD+JwGo bxQJVnl5W+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIpQAKCRAk1otyXVSH 0KhKB/97CmnH6U9bJtP2Mm28nFOfYooeNFvRGvFyuo5tp3UZest+BV+9oPUvc0BIX6un3pRpFd3 VfPIcW0YCn6rulXH3lKsQctM4zDKNEodrdn2KM015lmcrdS5U1u+gcqN3xP6LuwxxZAdUGaalyC lIW9GB5nOV2DiujzdzxkmhjThpX+8rrwbJtZmpEjlZH8O+ltbMmOyOn7NcGuedzaA49vYvviBkW PDhHqTGLgGZbzpKtTgOxFCKX+TAPkq2ptxIbD7QEZDfKF9NFi4ea8QJtYeNG3bU+wYTBi2rsl/f hsjb/FP8n87EAAW+92sGNqZpeeUCQvB0g/FzhIKxNyo9Z+T2 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Now that GCS is configurable via the ID registers update set_id_regs to cover ID_AA64PFR1_EL1.GCS. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 7429a1055df5..34e59fbbbe89 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -154,6 +154,7 @@ static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = =3D { =20 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] =3D { REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, GCS, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_= NI), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0), --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C22E2D0C89; Tue, 1 Sep 2026 21:51:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299481; cv=none; b=oh17lqKzErHkecL2yK8bWag1YNkB++wOuH/QJcDgE8tArnUkzvg8hc07BAaHnkDh7eCTXmimon9Cse7jfxG9cS7rUPkizoQkv6QbwKeazyG7V3MnVd7lKi7Y/HPcUK0Uc33xD/0lsnJaNGgO9Iw7z9pI73se3fQXuBszexNOqdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299481; c=relaxed/simple; bh=kq5inm4XLV9y3q0emrqMvgSlwP7yu7PrdQSzkYGOWPo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MXuCa3ZIaGmwyejC/LlRqFCubZgSbcfrIkfkbV/geEcw5WnO+PoF9H2Fv3X8v1KoO/oE5i9FjDl/0wta/IPxFymEjUpInxHS6gTEYMOyyLyD1pafW0uNzqlGd30OMpFW5RdnCJbqGQNUoqZpzBW68osViMSqmMoD7jhoHxBK0wc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FZaa0EOE; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FZaa0EOE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 800EA1F000E9; Tue, 1 Sep 2026 21:51:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299479; bh=nW2uwG3VWmqTYBYq5oWNcIeaMFqReX/mfTA7yT0Lz8Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=FZaa0EOECdWg2EgzznRZk6c5LR2LAC5TUfhY0ew/EHHwcGGfLh2DjlILvi/uE5unV VTNCRFXyIOGMPSepAF3zZe3egbb+j4dqiWFSAxHs+/BaJTjYbS6GqdAYJKylb6iZL6 4QEtx6wIb0XC3+pshtqlwjGj0EWT3FisTFkab+xa5KyIec1jcYOV2J3dbXgzufoMBt 3ulC5lw1giIAc8bzZaHyEHBEu49cg0j5XprAxICF6OtjzwaGPrhTE/blM/9B+XbYck SrgcnEvewn5gohjP6sJoWDM9s8LRwpH5JMX3TuOpZg6MXxuEWoZzAcdO5pXnNQBn1h yyypQuF2d6Yfg== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:10 +0100 Subject: [PATCH v20 12/14] KVM: selftests: arm64: Only restore SPSR_EL1 and ELR_EL1 if they change Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-12-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1508; i=broonie@kernel.org; h=from:subject:message-id; bh=kq5inm4XLV9y3q0emrqMvgSlwP7yu7PrdQSzkYGOWPo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0iliOMUqxh8DIPCCcFfMaZ3eY2IVxW8m+MHV xhDFuanEVmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIpQAKCRAk1otyXVSH 0EVBB/0RCAXJEfmE292StzFEMt6Xvh301atWZ16nvdp7WSfV9/IGI9oAnQ+BdlPcSXspY37gzpe 2QAe9yOe+sdXjCLybMonWti/OK5GdTR45EHQJNJcBFgjL/mOFtKwYSnkpQAUQSozRBWEAZ02zYA iK44Ng1rBjrfJpDQKsSevJnC0+/nJkLzFST6dVVpjd/0Vf5/RptCCYm1XEm9aBHZ9tuZwO8fSO2 i1g/Lk6yytq+hHmaldxudHH6zYzOGgEfIUBcdGrFlR9Vxt028FpJTpRwnmI/ltwoRz+Anb48EVv qKexXAtgYwwx07GOL2I8dqWDbyLlJAktHiKXbdSZiCX8Ob0m X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When EXLOCK is enabled for ELx writes to SPSR_ELx and ELR_ELx generate GCS exceptions. Currently the selftest helpers unconditionally reload the saved values for these registers regardless of if the handler didn't change them. This gets in the way of EXLOCK testing, making it hard to generate contexts which will generate an invalid ERET since we never get as far as doing an exception return while EXLOCK is enabled. In order to facilitate testing of nested virtualisation emulation of EXLOCK change our reloads into read/modify/write cycles, suppressing the writes when they would not change the value in the register. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- tools/testing/selftests/kvm/lib/arm64/handlers.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/kvm/lib/arm64/handlers.S b/tools/testi= ng/selftests/kvm/lib/arm64/handlers.S index 0e443eadfac6..367c22d61cba 100644 --- a/tools/testing/selftests/kvm/lib/arm64/handlers.S +++ b/tools/testing/selftests/kvm/lib/arm64/handlers.S @@ -33,8 +33,18 @@ =20 .macro restore_registers ldp x1, x2, [sp, #16 * 16] /* PC, PSTATE */ + + /* Suppress redundant writes to support GCS exception lock testing */ + mrs x3, elr_el1 + cmp x1, x3 + beq .Lskip_elr_\@ msr elr_el1, x1 +.Lskip_elr_\@: + mrs x3, spsr_el1 + cmp x2, x3 + beq .Lskip_spsr_\@ msr spsr_el1, x2 +.Lskip_spsr_\@: =20 /* sp is not restored */ ldp x30, xzr, [sp, #16 * 15] /* x30, SP */ --=20 2.47.3 From nobody Sat Sep 26 11:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FAED3932EE; Tue, 1 Sep 2026 21:51:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299486; cv=none; b=Bz7caDTCvmlhOHE6XpnWbjyCZd0us2813AA1FEHL0nAXfadZX73QBS8+g7mA4GCFo1gDNBM3nYJFbYXBv5eI37Aq/nEwtIA4awi7bk5kvhnDyHOvm8mxjO/edA5+ROQOqd9PmyOwQt0EcDQRvuTYidqqITBRKW+qk3foq99+i5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788299486; c=relaxed/simple; bh=sIWieTk4WURR6tewmd4CqdDOGodIh/nx0/zJZ1rNZT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nTVCgjhJw7/tXsPdwVMPvIuQVmg1Ybvv/pAhmLddlOBr8d3IBBJjBF8P/8yI4VNr5UWrMc+l9OJCxkz2gTwXFdhXvRCJ54vvcJDgvea9xn7TfT7jd7Fi4T1KTvZ0TpIwYhsDzSLH59kBG4CzDdK/bxhtvR9u0WYGevWTGE3QWdA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iDi3EeGK; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iDi3EeGK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 056771F00A3A; Tue, 1 Sep 2026 21:51:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788299483; bh=0g4KetOtT1QniGH3lYu0d4Ii94UczTzbZTbGp4YhhKU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=iDi3EeGKJaYtBIojbLpS5N0OLWSo1izf2RwLsJ0gxZcaQw+EwQ9ETmrtOuk49m4nD jFkH6pt44yyzLI6TxAB2xsZLPsU6Z7UJUkm4A2OOIVdJwBOPoOK/L5KalV1nLnjX4+ tmlgcODVW3/FLUiOeiYpJ3Cr658TVv1cwFmSlpTDd0P2jpksRFd1Lr5/godT04fE6s CpzquNZDnVNKjgSyNDsmsK2RvPVeI+qH+zPKzreMc/u6uivHwv20lqRX5oYwbFDuap 8YDVGEsEF1wHuEb9cA92DVKUgGaV+Iy7cw/T8MlsBxORtlp/ScGY8JJTO7gEFKLXy4 U5Fa4wFd79Tbw== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:11 +0100 Subject: [PATCH v20 13/14] tools: Synchronise the kernel esr.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-13-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=7181; i=broonie@kernel.org; h=from:subject:message-id; bh=sIWieTk4WURR6tewmd4CqdDOGodIh/nx0/zJZ1rNZT8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0imBQxEEr3vcZmyvBDItQlk6ar13Ok6c3WqA OBtjlpceX+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIpgAKCRAk1otyXVSH 0BcEB/9zxzdPIYQMiyDpY6kaeGESJ+LHf1tieFJiWuSJhsYZxQOt1icvo6dGsZzIKLl8vqVWtra IDfKBR16wYgZRNI73rHOYgcZzbEKuTWg8Wgn2Wlgzd+M+WzK6r5PIouRIEQXwvvA2U6X2OsspG7 JB7DV0D4LvwS2tw/egDfF9zbGYpqGuTEkx1dCIchPwZ/fkGcRC6VP0JdeEnoqhyhRCN7ieBJ0Qf bNbrCGVJOP/RivaIF2B44PAheOWK+4KrjaPxZSR2Wrm1i4IhTy2dOS9rnCXfhXEP5R5H/pHWZXD WiC5ozd0S9nX0BOSRbDKpRi3cKvRPDv0Wl5UtiMpceHETrkw X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB To pick up definitions for GCS. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- tools/arch/arm64/include/asm/esr.h | 113 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 102 insertions(+), 11 deletions(-) diff --git a/tools/arch/arm64/include/asm/esr.h b/tools/arch/arm64/include/= asm/esr.h index f3c6403e5ef2..24c6ebe3fd41 100644 --- a/tools/arch/arm64/include/asm/esr.h +++ b/tools/arch/arm64/include/asm/esr.h @@ -19,7 +19,8 @@ #define ESR_ELx_EC_FP_ASIMD UL(0x07) #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ -/* Unallocated EC: 0x0A - 0x0B */ +#define ESR_ELx_EC_OTHER UL(0x0A) +/* Unallocated EC: 0x0B */ #define ESR_ELx_EC_CP14_64 UL(0x0C) #define ESR_ELx_EC_BTI UL(0x0D) #define ESR_ELx_EC_ILL UL(0x0E) @@ -50,7 +51,8 @@ #define ESR_ELx_EC_FP_EXC32 UL(0x28) /* Unallocated EC: 0x29 - 0x2B */ #define ESR_ELx_EC_FP_EXC64 UL(0x2C) -/* Unallocated EC: 0x2D - 0x2E */ +#define ESR_ELx_EC_GCS UL(0x2D) +/* Unallocated EC: 0x2E */ #define ESR_ELx_EC_SERROR UL(0x2F) #define ESR_ELx_EC_BREAKPT_LOW UL(0x30) #define ESR_ELx_EC_BREAKPT_CUR UL(0x31) @@ -97,6 +99,8 @@ #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) =20 /* Shared ISS field definitions for Data/Instruction aborts */ +#define ESR_ELx_VNCR_SHIFT (13) +#define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT) #define ESR_ELx_SET_SHIFT (11) #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) #define ESR_ELx_FnV_SHIFT (10) @@ -119,6 +123,16 @@ #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) #define ESR_ELx_FSC_SECC (0x18) #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) +#define ESR_ELx_FSC_EXCL_ATOMIC (0x35) +#define ESR_ELx_FSC_ADDRSZ (0x00) + +/* + * Annoyingly, the negative levels for Address size faults aren't laid out + * contiguously (or in the desired order) + */ +#define ESR_ELx_FSC_ADDRSZ_nL(n) ((n) =3D=3D -1 ? 0x25 : 0x2C) +#define ESR_ELx_FSC_ADDRSZ_L(n) ((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \ + (ESR_ELx_FSC_ADDRSZ + (n))) =20 /* Status codes for individual page table levels */ #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) @@ -141,12 +155,12 @@ #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) #define ESR_ELx_AR_SHIFT (14) #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) -#define ESR_ELx_VNCR_SHIFT (13) -#define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT) #define ESR_ELx_CM_SHIFT (8) #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) =20 /* ISS2 field definitions for Data Aborts */ +#define ESR_ELx_HDBSSF_SHIFT (11) +#define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT) #define ESR_ELx_TnD_SHIFT (10) #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) #define ESR_ELx_TagAccess_SHIFT (9) @@ -161,8 +175,6 @@ #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) =20 /* ISS field definitions for exceptions taken in to Hyp */ -#define ESR_ELx_FSC_ADDRSZ (0x00) -#define ESR_ELx_FSC_ADDRSZ_L(n) (ESR_ELx_FSC_ADDRSZ + (n)) #define ESR_ELx_CV (UL(1) << 24) #define ESR_ELx_COND_SHIFT (20) #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) @@ -174,6 +186,13 @@ #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) =20 +/* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */ +#define ESR_ELx_ISS_OTHER_ST64BV (0) +#define ESR_ELx_ISS_OTHER_ST64BV0 (1) +#define ESR_ELx_ISS_OTHER_LDST64B (2) +#define ESR_ELx_ISS_OTHER_TSBCSYNC (3) +#define ESR_ELx_ISS_OTHER_PSBCSYNC (4) + #define DISR_EL1_IDS (UL(1) << 24) /* * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may me= an @@ -371,12 +390,14 @@ /* * ISS values for SME traps */ +#define ESR_ELx_SME_ISS_SMTC_MASK GENMASK(2, 0) +#define ESR_ELx_SME_ISS_SMTC(esr) ((esr) & ESR_ELx_SME_ISS_SMTC_MASK) =20 -#define ESR_ELx_SME_ISS_SME_DISABLED 0 -#define ESR_ELx_SME_ISS_ILL 1 -#define ESR_ELx_SME_ISS_SM_DISABLED 2 -#define ESR_ELx_SME_ISS_ZA_DISABLED 3 -#define ESR_ELx_SME_ISS_ZT_DISABLED 4 +#define ESR_ELx_SME_ISS_SMTC_SME_DISABLED 0 +#define ESR_ELx_SME_ISS_SMTC_ILL 1 +#define ESR_ELx_SME_ISS_SMTC_SM_DISABLED 2 +#define ESR_ELx_SME_ISS_SMTC_ZA_DISABLED 3 +#define ESR_ELx_SME_ISS_SMTC_ZT_DISABLED 4 =20 /* ISS field definitions for MOPS exceptions */ #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) @@ -387,6 +408,31 @@ #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) =20 +/* ISS field definitions for GCS */ +#define ESR_ELx_ExType_SHIFT (20) +#define ESR_ELx_ExType_MASK GENMASK(23, 20) +#define ESR_ELx_Raddr_SHIFT (10) +#define ESR_ELx_Raddr_MASK GENMASK(14, 10) +#define ESR_ELx_Rn_SHIFT (5) +#define ESR_ELx_Rn_MASK GENMASK(9, 5) +#define ESR_ELx_Rvalue_SHIFT 5 +#define ESR_ELx_Rvalue_MASK GENMASK(9, 5) +#define ESR_ELx_IT_SHIFT (0) +#define ESR_ELx_IT_MASK GENMASK(4, 0) + +#define ESR_ELx_ExType_DATA_CHECK 0 +#define ESR_ELx_ExType_EXLOCK 1 +#define ESR_ELx_ExType_STR 2 + +#define ESR_ELx_IT_RET 0 +#define ESR_ELx_IT_GCSPOPM 1 +#define ESR_ELx_IT_RET_KEYA 2 +#define ESR_ELx_IT_RET_KEYB 3 +#define ESR_ELx_IT_GCSSS1 4 +#define ESR_ELx_IT_GCSSS2 5 +#define ESR_ELx_IT_GCSPOPCX 6 +#define ESR_ELx_IT_GCSPOPX 7 + #ifndef __ASSEMBLER__ #include =20 @@ -408,6 +454,11 @@ static inline bool esr_is_cfi_brk(unsigned long esr) (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) =3D=3D CFI_BRK_IMM_BASE; } =20 +static inline bool esr_is_ubsan_brk(unsigned long esr) +{ + return (esr_brk_comment(esr) & ~UBSAN_BRK_MASK) =3D=3D UBSAN_BRK_IMM; +} + static inline bool esr_fsc_is_translation_fault(unsigned long esr) { esr =3D esr & ESR_ELx_FSC; @@ -439,6 +490,46 @@ static inline bool esr_fsc_is_access_flag_fault(unsign= ed long esr) (esr =3D=3D ESR_ELx_FSC_ACCESS_L(0)); } =20 +static inline bool esr_fsc_is_excl_atomic_fault(unsigned long esr) +{ + esr =3D esr & ESR_ELx_FSC; + + return esr =3D=3D ESR_ELx_FSC_EXCL_ATOMIC; +} + +static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr) +{ + esr &=3D ESR_ELx_FSC; + + return (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(3)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(2)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(1)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(0)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(-1)); +} + +static inline bool esr_fsc_is_sea_ttw(unsigned long esr) +{ + esr =3D esr & ESR_ELx_FSC; + + return (esr =3D=3D ESR_ELx_FSC_SEA_TTW(3)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(2)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(1)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(0)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(-1)); 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b=ChYhXE29DCjxkQFIn+hWhkMmNlw73JMvwwlN2O/5uPuL4k/JMZx0hWCMxNTd0WxiT ap8WiT75KQ3Ak9Wo3FaXYWqA74bXyADAcrOgbFiGhmiBmtocvwUFCHU2BFDeetGGt/ qY4LUNih8ZZwFs2T0fAu9vCeRdrSPs5DfmOwdswplFYHQcW3UyhhKMxnqPmuaYLAtQ NKeeL1ut/jNB+M9FJY8FZTYn4D1dXsqRQoeU/uF74jHxRc9DceslM6MwPkOL4jvxVZ cqpcWzqOtv1Lqe/NI8pvNTFGtv87Ee480luXmb//J55/cq7L4/MinN8hnYqFeNS7Jc L1HL99QbfwWUQ== From: Mark Brown Date: Tue, 01 Sep 2026 22:47:12 +0100 Subject: [PATCH v20 14/14] KVM: selftests: arm64: Add GCS EXLOCK exception emulation test Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260901-arm64-gcs-v20-14-f31750bdfadb@kernel.org> References: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> In-Reply-To: <20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Oliver Upton , Fuad Tabba Cc: Peter Maydell , Leonardo Bras , Wei-Lin Chang , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=11852; i=broonie@kernel.org; h=from:subject:message-id; bh=TIDZs+B7zu6gVSc89XYBcC4NUO41wOhM/wTzdrOu6fU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBql0inpmhNxIZJMCs+N19D3cF1Rtkk77lzjQH9a X2Qg+QGEvWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapdIpwAKCRAk1otyXVSH 0B7MB/4jwLl0G5DBb6EqKPBOysyt8+1EIIjVDA9M6zywUrgrfWbRD4IJt0uYNNDnuWguFyCm7jy 3sxUFhcAdToRs4jrrwUnbKz6as4mqrA8HhWxzXl63DoQWklQVva844M3gjd+nqzoK8HlWRKslxD f2Ap7I+3fNbbS+HMUz4wYFqRkMvHtPM7Lgh0vBmx1dn8v+fuz+6ykpjPgjwCdUOheEHeOC4AYYd SnLwi0/Bslw4+WPlFxZl5exu25CcOh0X/TKuNzHcrX0EREN3tfdlnVFe6up2GLadG8/N8sd+yqS dBBmTnUEqfFS0JojBsA0/h66FUHMMk0aETYGYhKD9P2I0Gwq X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When running in vEL2 ERET is emulated, this means that we must emulate the behaviour of GCSCR_EL2.EXLOCKEN. Add a test that validates the behaviour. As per DDI0487 R_WTXBY PSTATE.EXLOCK is set to the value of GCSCR_ELx.EXLOCKEN when taking an exception to the same exception level. As per DDI0487 R_TYTWB if on exception return to the same EL GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK is not 1 then the exception return is illegal. We nest handling of two UDFs to allow us to both observe and modify PSTATE.EXLOCK, checking that expected exceptions are generated for ERET. We also repeat the UDF tests having enabled fine grained traps for ERET to try to ensure that the slow paths are taken. We also attempt to write to both SPSR_ELx and ELR_ELx, again using a UDF handler to control PSTATE.EXLOCK. We do all this both with and without having enabled EXLOCKEN, though only for code running at EL2 due to framework limitations. For completeness we also inject a data abort from EL0 to EL2 with GCSCR_EL2.EXLOCKEN set, ensuring that PSTATE.EXLOCK is not set. Signed-off-by: Mark Brown Reviewed-by: Leonardo Bras --- tools/testing/selftests/kvm/Makefile.kvm | 1 + tools/testing/selftests/kvm/arm64/gcs_exceptions.c | 346 +++++++++++++++++= ++++ 2 files changed, 347 insertions(+) diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 96bab7002d39..0286453ab223 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -179,6 +179,7 @@ TEST_GEN_PROGS_arm64 +=3D arm64/hello_el2 TEST_GEN_PROGS_arm64 +=3D arm64/host_sve TEST_GEN_PROGS_arm64 +=3D arm64/hypercalls TEST_GEN_PROGS_arm64 +=3D arm64/external_aborts +TEST_GEN_PROGS_arm64 +=3D arm64/gcs_exceptions TEST_GEN_PROGS_arm64 +=3D arm64/mmio_sign_ext TEST_GEN_PROGS_arm64 +=3D arm64/page_fault_test TEST_GEN_PROGS_arm64 +=3D arm64/psci_test diff --git a/tools/testing/selftests/kvm/arm64/gcs_exceptions.c b/tools/tes= ting/selftests/kvm/arm64/gcs_exceptions.c new file mode 100644 index 000000000000..de5bc6590727 --- /dev/null +++ b/tools/testing/selftests/kvm/arm64/gcs_exceptions.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Test KVM's handling of Guarded Control Stack exception state. + */ + +#include "kvm_util.h" +#include "processor.h" +#include "test_util.h" +#include "ucall.h" + +#include +#include + +#define PSTATE_IL_BIT BIT(20) + +static void require_guest_gcs(struct kvm_vcpu *vcpu) +{ + u64 pfr1 =3D vcpu_get_reg(vcpu, + KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); + + TEST_REQUIRE(SYS_FIELD_GET(ID_AA64PFR1_EL1, GCS, pfr1) >=3D + ID_AA64PFR1_EL1_GCS_IMP); +} + +static bool expect_exlock; +static unsigned int undef_count; +static unsigned int illegal_count; +static unsigned int gcs_count; +static u64 handler_pstate; +static u64 illegal_pstate; + +static u64 expected_illegal_pc; +static enum udf_mode { + UDF_COLLECT, /* Initial UDF we collect PSTATE from */ + UDF_VALIDATE, /* Secondary UDF that collects and validates */ + UDF_REPAIR, /* UDF to clear EXLOCK */ + UDF_ELR_EL1, /* Write to ELR_EL1 with EXLOCK */ + UDF_ELR_EL2, /* Write to ELR_EL2 with EXLOCK */ + UDF_SPSR_EL1, /* Write to SPSR_EL1 with EXLOCK */ + UDF_SPSR_EL2, /* Write to SPSR_EL2 with EXLOCK */ +} udf_mode; + +static void guest_undef_handler(struct ex_regs *regs) +{ + u64 esr =3D read_sysreg(esr_el2); + u64 val; + + undef_count++; + + /* Just skip the instruction either way. */ + GUEST_ASSERT_EQ(esr, ESR_ELx_IL); + regs->pc +=3D 4; + + switch (udf_mode) { + case UDF_COLLECT: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + /* + * If we want the nested exception handler to change + * PSTATE it can't have EXLOCK set. + */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + /* + * Take another exception without returning so we can + * collect the EXLOCK state we're seeing here and make + * our return illegal. + */ + expected_illegal_pc =3D regs->pc; + udf_mode =3D UDF_VALIDATE; + asm volatile("udf #0" ::: "memory"); + + /* Reenable so PSTATE.EXLOCK is checked */ + write_sysreg_s(expect_exlock ? GCSCR_ELx_EXLOCKEN : 0, + SYS_GCSCR_EL2); + isb(); + break; + + case UDF_VALIDATE: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + 0); + + /* Validate the EXLOCK of the original exception. */ + handler_pstate =3D regs->pstate; + GUEST_ASSERT_EQ(!!(regs->pstate & PSR_EXLOCK_BIT), + expect_exlock); + + /* Clearing PSTATE.EXLOCK triggers an illegal ERET. */ + regs->pstate &=3D ~PSR_EXLOCK_BIT; + break; + + case UDF_REPAIR: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + 0); + + /* Disable EXLOCK for the requesting context */ + regs->pstate &=3D ~PSR_EXLOCK_BIT; + break; + + case UDF_ELR_EL1: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, elr_el1 \n\ + msr elr_el1, %0" + : "=3Dr"(val) :: "memory"); + break; + + case UDF_ELR_EL2: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, elr_el2 \n\ + msr elr_el2, %0" + : "=3Dr"(val) :: "memory"); + break; + + case UDF_SPSR_EL1: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, spsr_el1 \n\ + msr spsr_el1, %0" + : "=3Dr"(val) :: "memory"); + break; + + case UDF_SPSR_EL2: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, spsr_el2 \n\ + msr spsr_el2, %0" + : "=3Dr"(val) :: "memory"); + break; + + default: + GUEST_FAIL("Invalid udf_mode"); + } +} + +static void guest_illegal_handler(struct ex_regs *regs) +{ + u64 esr =3D read_sysreg(esr_el2); + + illegal_count++; + illegal_pstate =3D regs->pstate; + + GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_ILL); + GUEST_ASSERT(esr & ESR_ELx_IL); + GUEST_ASSERT(regs->pstate & PSTATE_IL_BIT); + GUEST_ASSERT(!(regs->pstate & PSR_EXLOCK_BIT)); + GUEST_ASSERT_EQ(regs->pc, expected_illegal_pc); + + /* Disable exception locking so we can repair the return state. */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + /* We need our own EXLOCK clearing so we can repair the original */ + udf_mode =3D UDF_REPAIR; + asm volatile("udf #0" ::: "memory"); + + /* Disable EXLOCK for the generating context, making things legal */ + regs->pstate &=3D ~(PSTATE_IL_BIT | PSR_EXLOCK_BIT); +} + +static void guest_gcs_handler(struct ex_regs *regs) +{ + u64 esr =3D read_sysreg(esr_el2); + + gcs_count++; + + GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_GCS); + GUEST_ASSERT_EQ(FIELD_GET(ESR_ELx_ExType_MASK, esr), + ESR_ELx_ExType_EXLOCK); + + /* Disabling EXLOCKEN makes sysreg writes legal. */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); +} + +static noinline void test_udf_exception(bool enable_exlock) +{ + unsigned int initial_undef =3D undef_count; + unsigned int initial_illegal =3D illegal_count; + unsigned int initial_gcs =3D gcs_count; + + expect_exlock =3D enable_exlock; + write_sysreg_s(enable_exlock ? GCSCR_ELx_EXLOCKEN : 0, + SYS_GCSCR_EL2); + isb(); + + udf_mode =3D UDF_COLLECT; + asm volatile("udf #0" ::: "memory"); + + /* Leave GCS disabled even if a broken ERET skipped the ILL handler. */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + GUEST_ASSERT_EQ(undef_count, initial_undef + 2 + enable_exlock); + GUEST_ASSERT_EQ(illegal_count, initial_illegal + enable_exlock); + GUEST_ASSERT_EQ(!!(handler_pstate & PSR_EXLOCK_BIT), enable_exlock); + if (enable_exlock) + GUEST_ASSERT(illegal_pstate & PSTATE_IL_BIT); + GUEST_ASSERT_EQ(initial_gcs, gcs_count); +} + +static noinline void test_sysreg(enum udf_mode reg, bool enable_exlock) +{ + unsigned int initial_undef =3D undef_count; + unsigned int initial_gcs =3D gcs_count; + + expect_exlock =3D enable_exlock; + + write_sysreg_s(enable_exlock ? GCSCR_ELx_EXLOCKEN : 0, + SYS_GCSCR_EL2); + isb(); + + udf_mode =3D reg; + asm volatile("udf #0" ::: "memory"); + + /* Ensure EXLOCK is disabled */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + GUEST_ASSERT_EQ(gcs_count, initial_gcs + expect_exlock); + GUEST_ASSERT_EQ(undef_count, initial_undef + 1); +} + +static void guest_code(void) +{ + GUEST_ASSERT_EQ(get_current_el(), 2); + + /* + * Try straightforwardly generating an exception without and + * with EXLOCK. + */ + test_udf_exception(false); + test_sysreg(UDF_ELR_EL1, false); + test_sysreg(UDF_ELR_EL2, false); + test_sysreg(UDF_SPSR_EL1, false); + test_sysreg(UDF_SPSR_EL2, false); + + test_udf_exception(true); + test_sysreg(UDF_ELR_EL1, true); + test_sysreg(UDF_ELR_EL2, true); + test_sysreg(UDF_SPSR_EL1, true); + test_sysreg(UDF_SPSR_EL2, true); + + /* Force ERET directly through the slow emulation path as well. */ + sysreg_clear_set_s(SYS_HFGITR_EL2, 0, HFGITR_EL2_ERET); + isb(); + + test_udf_exception(false); + + test_udf_exception(true); + + sysreg_clear_set_s(SYS_HFGITR_EL2, HFGITR_EL2_ERET, 0); + isb(); + GUEST_DONE(); +} + +static void test_exception_from_same_el(void) +{ + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + struct ucall uc; + + vm =3D vm_create(1); + kvm_get_default_vcpu_target(vm, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_HAS_EL2); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code); + require_guest_gcs(vcpu); + + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(vcpu); + vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, + ESR_ELx_EC_UNKNOWN, guest_undef_handler); + vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, + ESR_ELx_EC_ILL, guest_illegal_handler); + vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, + ESR_ELx_EC_GCS, guest_gcs_handler); + kvm_arch_vm_finalize_vcpus(vm); + + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_DONE: + break; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + default: + TEST_FAIL("Unhandled ucall: %ld", uc.cmd); + } + + kvm_vm_free(vm); +} + +static void test_exception_from_lower_el(void) +{ + struct kvm_vcpu_events events =3D {}; + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + u64 pstate; + + vm =3D vm_create(1); + kvm_get_default_vcpu_target(vm, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_HAS_EL2); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, NULL); + require_guest_gcs(vcpu); + kvm_arch_vm_finalize_vcpus(vm); + + /* + * Inject an EL0 data abort to vEL2 with EXLOCK enabled for + * vEL2. + */ + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2), + vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2)) | + HCR_EL2_TGE); + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_GCSCR_EL2), + GCSCR_ELx_EXLOCKEN); + vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pstate), + PSR_MODE_EL0t | PSR_EXLOCK_BIT); + + events.exception.ext_dabt_pending =3D true; + vcpu_events_set(vcpu, &events); + + pstate =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); + TEST_ASSERT_EQ(pstate & PSR_MODE_MASK, PSR_MODE_EL2h); + TEST_ASSERT(!(pstate & PSR_EXLOCK_BIT), + "EXLOCK set on exception from a lower EL"); + + kvm_vm_free(vm); +} + +int main(void) +{ + TEST_REQUIRE(kvm_check_cap(KVM_CAP_ARM_EL2)); + test_exception_from_same_el(); + test_exception_from_lower_el(); + + return 0; +} --=20 2.47.3