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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4843ce8b015sm6235156f8f.13.2026.08.31.07.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:46 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 01/17] iommu/dma: Prepare MSI physical address lists Date: Mon, 31 Aug 2026 16:59:27 +0200 Message-ID: <20260831145943.313726-2-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: UvaWYjjkjSwQuFc9qtnCnctWbO7cZ_eE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX35ZgG0F8b6JO ue6Mhw3agIJu4o6HkFTukFlUasrwmHU3rIUUSUBdUBNxuAXE5w/NROYS/YKD3SSeby5RzernRAT NhNCHic9acbGzXw2YRFoGQs029ULCeqqZOTuVgDSuQDHJPYl/EFJ72o4Ek/mPc9a5ch2UgM3O5q XqPqbfhR5erw9drk6JyrhDscYUOZhhmLcqQZL1JGwPn9o2BIQ30Ngx4tQnZKz5QUElngOyFGEDZ D9pA0BRtGfZ9HAcjLDdU+7pgVhRi426j17MAbjpT0fuxtBGwREtHZjngI4DB0z0/Ntpy2Gm+DvX Eti+vY8JkZ4GK4Hsfu1yiszPplOPkJE7yLCYZlhG7TfA8+1GN5SBOb/aXzsP25ENKwYJBtCnzuU a+4fylEHz1yM7f0ypdtFEXyrafbY6WQ/KcSdYXDwzceURyJDgha1TIkyMJMaHgYYuLhASPOPMNE Fp5DZS+E4TDzdj0ZrqA== X-Proofpoint-GUID: UvaWYjjkjSwQuFc9qtnCnctWbO7cZ_eE X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX/hAz5dyqi1zS 5M9IL37GHb7NUN81ggglF8FNKAzWUp1xXd044oJzwmI+QLYJCgVzQ+qD/kLgMmsGzFpq+Avx9Kt AKJdT54mYmUo2aVK5K/C3VoTsH+X8xY= X-Authority-Analysis: v=2.4 cv=GbQnWwXL c=1 sm=1 tr=0 ts=6a9596e4 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=kJPfLSheDWDr1nFXzE0A:9 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 adultscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Software MSI mappings may cover an ordered list of physical addresses which must be mapped into one contiguous IOVA range. Extend the internal DMA-IOMMU mapping helpers to accept an address array, address count, and required mapping granule. Teach iommu_dma_get_msi_page() to map the list into one contiguous IOVA allocation. Keep the existing per-page cache entries and mark the first entry with the size of the allocation so an identical list can reuse the mapping without changing the existing cache representation. This prepares for the forthcoming iommu_dma_prepare_msi_list() API. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/dma-iommu.c | 116 +++++++++++++++++++++++++++++--------- 1 file changed, 88 insertions(+), 28 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9a07eb39336e..38a0c4e244d6 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -42,6 +42,7 @@ struct iommu_dma_msi_page { struct list_head list; dma_addr_t iova; phys_addr_t phys; + size_t range_size; /* IOVA range size, or 0 if not the first map */ }; =20 enum iommu_dma_queue_type { @@ -481,7 +482,7 @@ static int cookie_init_hw_msi_region(struct iommu_dma_c= ookie *cookie, num_pages =3D iova_align(iovad, end - start) >> iova_shift(iovad); =20 for (i =3D 0; i < num_pages; i++) { - msi_page =3D kmalloc_obj(*msi_page); + msi_page =3D kzalloc_obj(*msi_page); if (!msi_page) return -ENOMEM; =20 @@ -2196,15 +2197,42 @@ static struct list_head *cookie_msi_pages(const str= uct iommu_domain *domain) } } =20 +static bool iommu_dma_msi_range_matches(struct list_head *msi_page_list, + const struct iommu_dma_msi_page *base_page, + const phys_addr_t *phys_addrs, + unsigned int nr_addrs, size_t granule) +{ + const struct iommu_dma_msi_page *msi_page; + unsigned int nr_found =3D 0; + dma_addr_t offset; + + list_for_each_entry(msi_page, msi_page_list, list) { + if (msi_page->iova < base_page->iova) + continue; + offset =3D msi_page->iova - base_page->iova; + if (offset >=3D base_page->range_size) + continue; + if (!IS_ALIGNED((size_t)offset, granule) || + msi_page->phys !=3D phys_addrs[(size_t)offset / granule]) + return false; + nr_found++; + } + + return nr_found =3D=3D nr_addrs; +} + static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *de= v, - phys_addr_t msi_addr, struct iommu_domain *domain) + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granule, + struct iommu_domain *domain) { struct list_head *msi_page_list =3D cookie_msi_pages(domain); - struct iommu_dma_msi_page *msi_page; - dma_addr_t iova; + struct iommu_dma_msi_page *msi_page, *first_page =3D NULL; int prot =3D IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - size_t size =3D cookie_msi_granule(domain); static DEFINE_MUTEX(msi_prepare_lock); + LIST_HEAD(new_msi_pages); + dma_addr_t base_iova; + unsigned int i; + size_t size; =20 /* * Normally a device's default domain is only ever attached to that @@ -2218,32 +2246,60 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi= _page(struct device *dev, */ guard(mutex)(&msi_prepare_lock); =20 - msi_addr &=3D ~(phys_addr_t)(size - 1); - list_for_each_entry(msi_page, msi_page_list, list) - if (msi_page->phys =3D=3D msi_addr) + if (!nr_addrs || nr_addrs > SIZE_MAX / granule) + return NULL; + size =3D nr_addrs * granule; + + list_for_each_entry(msi_page, msi_page_list, list) { + if (msi_page->phys !=3D phys_addrs[0]) + continue; + if (nr_addrs =3D=3D 1) + return msi_page; + if (msi_page->range_size =3D=3D size && + iommu_dma_msi_range_matches(msi_page_list, msi_page, phys_addrs, + nr_addrs, granule)) return msi_page; + } =20 - msi_page =3D kzalloc_obj(*msi_page); - if (!msi_page) - return NULL; + for (i =3D 0; i < nr_addrs; i++) { + msi_page =3D kzalloc_obj(*msi_page); + if (!msi_page) + goto out_free_pages; + list_add_tail(&msi_page->list, &new_msi_pages); + } =20 - iova =3D iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); - if (!iova) - goto out_free_page; + base_iova =3D iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); + if (!base_iova) + goto out_free_pages; =20 - if (iommu_map(domain, iova, msi_addr, size, prot, GFP_KERNEL)) - goto out_free_iova; + i =3D 0; + list_for_each_entry(msi_page, &new_msi_pages, list) { + msi_page->phys =3D phys_addrs[i]; + msi_page->iova =3D base_iova + i * granule; + if (!i) + first_page =3D msi_page; + if (iommu_map(domain, msi_page->iova, msi_page->phys, granule, prot, GFP= _KERNEL)) + goto out_unmap; + i++; + } =20 - INIT_LIST_HEAD(&msi_page->list); - msi_page->phys =3D msi_addr; - msi_page->iova =3D iova; - list_add(&msi_page->list, msi_page_list); - return msi_page; + first_page->range_size =3D size; + list_splice(&new_msi_pages, msi_page_list); + return first_page; =20 -out_free_iova: - iommu_dma_free_iova(domain, iova, size, NULL); -out_free_page: - kfree(msi_page); +out_unmap: + if (i) { + size_t unmap =3D iommu_unmap(domain, base_iova, i * granule); + + WARN_ON_ONCE(unmap !=3D i * granule); + } + iommu_dma_free_iova(domain, base_iova, size, NULL); +out_free_pages: + while (!list_empty(&new_msi_pages)) { + msi_page =3D list_first_entry(&new_msi_pages, typeof(*msi_page), list); + list_del(&msi_page->list); + kfree(msi_page); + } return NULL; } =20 @@ -2252,19 +2308,23 @@ int iommu_dma_sw_msi(struct iommu_domain *domain, s= truct msi_desc *desc, { struct device *dev =3D msi_desc_to_dev(desc); const struct iommu_dma_msi_page *msi_page; + phys_addr_t phys_addr; + size_t granule; =20 if (!has_msi_cookie(domain)) { msi_desc_set_iommu_msi_iova(desc, 0, 0); return 0; } =20 + granule =3D cookie_msi_granule(domain); + phys_addr =3D ALIGN_DOWN(msi_addr, granule); + iommu_group_mutex_assert(dev); - msi_page =3D iommu_dma_get_msi_page(dev, msi_addr, domain); + msi_page =3D iommu_dma_get_msi_page(dev, &phys_addr, 1, granule, domain); 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482fbb20713sm22270269f8f.21.2026.08.31.07.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:47 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 02/17] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Date: Mon, 31 Aug 2026 16:59:28 +0200 Message-ID: <20260831145943.313726-3-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXxVp2TFLDTDc7 UC7xKN/T7PyQG5lpt6jlCCOdZzTSrBoRiXD95/Z58Kw5ND5wvkii0crB/i+RHDMXRwLgk7T1tU7 KKZO3LmIQcuIA6DZ+/ThOZ46B1ZkTeY= X-Authority-Analysis: v=2.4 cv=CpaPtH4D c=1 sm=1 tr=0 ts=6a9596e6 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=8L5tTrZ4L9qXjquGIIcA:9 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX1vQqszePTWlW cqHy4TXBVQJA0HCFBnIS9zF0pHo8nq5HNHiLVbs9hsG8EV3Zyfu4i4byVdzji6+CgVj6XDVrZ93 G8e0l/fVCElvEpOlUBk9xHqwYVpgOgb1UOIucnC2m3z655o5H+b4akM1gWSxpFu/XTQ5GnlGuL1 pYrS7KKUb8uE9JcajyKCQl5bmH8TScXw9Jfyg03KhR0NCsU2PwjDuQSODtVQ82x7U6tB5+3wn9Y nRTCayqXzO2UnYZFOzUuz5w2U6OSgctC/AwYg8k9GF2pwOjGEimPW0wx7Gne2+JR7FRAkfXu64D vam77s1MzvNgqnfSbQyS8u3nA/qjmDW1YqqXGyfpW6DaVU6PoN4ImjBj3kFqi7b2G9q5B+kshIe asU+/pU/sCD0sj+stax63jqgI3BFIyNCYhvsm93/aaFvuqNKtJw9nhogDaPMKFIsFU8kwaWioHM BVHdGqqSxweQgGGXDhA== X-Proofpoint-ORIG-GUID: TRJlnozOCyK5S-70Bkts9Q1UJ5QPnFNT X-Proofpoint-GUID: TRJlnozOCyK5S-70Bkts9Q1UJ5QPnFNT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" struct iommufd_sw_msi_maps uses a fixed 64-bit bitmap, limiting each group and hardware page table to 64 software MSI mappings. RISC-V interrupt remapping needs a mapping for every possible CPU, so this limit is insufficient. Make the bitmap grow on demand and treat IDs beyond its current size as absent. Cap it at 16K entries to bound allocation size while leaving ample room for expected software MSI users. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/device.c | 3 +- drivers/iommu/iommufd/driver.c | 37 ++++++++++++++-------- drivers/iommu/iommufd/hw_pagetable.c | 1 + drivers/iommu/iommufd/iommufd_private.h | 41 +++++++++++++++++++++++-- 4 files changed, 66 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index d488c23fd353..868f1e591208 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -34,6 +34,7 @@ static void iommufd_group_release(struct kref *kref) NULL, GFP_KERNEL); iommu_group_put(igroup->group); mutex_destroy(&igroup->lock); + kfree(igroup->required_sw_msi.bitmap); kfree(igroup); } =20 @@ -384,7 +385,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, int rc; =20 if (cur->sw_msi_start !=3D igroup->sw_msi_start || - !test_bit(cur->id, igroup->required_sw_msi.bitmap)) + !iommufd_sw_msi_maps_test_bit(&igroup->required_sw_msi, cur->id)) continue; =20 rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, cur); diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 3b8067976eac..d0b05b1fda42 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -196,13 +196,15 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys= _addr_t msi_addr, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { if (cur->sw_msi_start !=3D sw_msi_start) continue; + if (cur->pgoff =3D=3D UINT_MAX) + return ERR_PTR(-EOVERFLOW); max_pgoff =3D max(max_pgoff, cur->pgoff + 1); if (cur->msi_addr =3D=3D msi_addr) return cur; } =20 - if (ictx->sw_msi_id >=3D - BITS_PER_BYTE * sizeof_field(struct iommufd_sw_msi_maps, bitmap)) + if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || + max_pgoff > (ULONG_MAX - sw_msi_start) / PAGE_SIZE) return ERR_PTR(-EOVERFLOW); =20 cur =3D kzalloc_obj(*cur); @@ -222,21 +224,25 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, struct iommufd_sw_msi_map *msi_map) { unsigned long iova; + int rc; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 + if (iommufd_sw_msi_maps_test_bit(&hwpt_paging->present_sw_msi, msi_map->i= d)) + return 0; + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - if (!test_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap)) { - int rc; - - rc =3D iommu_map(hwpt_paging->common.domain, iova, - msi_map->msi_addr, PAGE_SIZE, - IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, - GFP_KERNEL_ACCOUNT); - if (rc) - return rc; - __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); - } + rc =3D iommufd_sw_msi_maps_ensure(&hwpt_paging->present_sw_msi, msi_map->= id); + if (rc) + return rc; + + rc =3D iommu_map(hwpt_paging->common.domain, iova, + msi_map->msi_addr, PAGE_SIZE, + IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, + GFP_KERNEL_ACCOUNT); + if (rc) + return rc; + __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); return 0; } EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); @@ -290,6 +296,11 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 + rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, + msi_map->id); + if (rc) + return rc; + rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); if (rc) return rc; diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index 623cc608ca0c..54873de43eb0 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -32,6 +32,7 @@ void iommufd_hwpt_paging_destroy(struct iommufd_object *o= bj) } =20 __iommufd_hwpt_destroy(&hwpt_paging->common); + kfree(hwpt_paging->present_sw_msi.bitmap); refcount_dec(&hwpt_paging->ioas->obj.users); } =20 diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index 43fbc5bed8de..9ca5f9f92cdf 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -29,11 +30,47 @@ struct iommufd_sw_msi_map { unsigned int id; }; =20 -/* Bitmap of struct iommufd_sw_msi_map::id */ +/* Bitmap of struct iommufd_sw_msi_map::id; starts empty, grows on demand.= */ struct iommufd_sw_msi_maps { - DECLARE_BITMAP(bitmap, 64); + unsigned long *bitmap; + unsigned int nbits; }; =20 +/* Large enough for foreseeable SW MSI users while bounding bitmap growth.= */ +#define IOMMUFD_SW_MSI_MAX_ID (16U * 1024 - 1) + +/* Grow bitmap to accommodate id. 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482fbb33070sm23895053f8f.36.2026.08.31.07.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:49 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 03/17] iommufd: Split software MSI map lookup and allocation Date: Mon, 31 Aug 2026 16:59:29 +0200 Message-ID: <20260831145943.313726-4-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX/wFhNR1saqQ6 c5+0YuvGWVnN9ksfXR3YPTAem2ikDDw3SrsSu29So4AlJbQyWiGDq+Bs9SBFLCTf7eQD1k+h1Fr Oi98uGLzXSiC4r+eG0DH1ZlmWID6rCo= X-Proofpoint-GUID: psYfwtiJPvIz2JBiIGvQdRP4mSkR9ale X-Authority-Analysis: v=2.4 cv=CYE4Irrl c=1 sm=1 tr=0 ts=6a9596e7 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=_mR3RRazA89hjPCjrIEA:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: psYfwtiJPvIz2JBiIGvQdRP4mSkR9ale X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX48b0Bcr953wL ZZbTemABpeAovIw52WxDM+kStFEXKKHC3CnqiG7ZPpyxlo+Q1RsaFo69aoKOdYHsnDBV2Y2Mk6p 1N/sAXVq68yly2diWjZzhZTSa6Nm3ZCmMWeJXlMezwwIOBhfosZWsIZOlYsF+zg+t4PNAM9foqN KjgYHBZIRzuKD8NnQ7O/EjFexLOcB7uJJhRnfgJwBUg+BhrIaK4RsxoZMMm4/yASJWaRNhozy+r 9ouLs88izTW/4UmGYVuiTIjxh3pz6YazA3aSWmJsw9N1fBPImsBteyQL2V8+MyZYoK9fsQ+nTNH YzydWfsvgI67cJDHIp0hh9EvMdE+QhjNCvT9Xbxj2abRIY5RoNlBYlysA6nx+62TRh2phHV+e1z Zytjyh4cuZb7JmLNW2EiXE3IRRQZJXbztWs1Q7gW+8XIPGo2lOn8dAC2QOWT41uYfpOHed6SQWE qL8rbhAGiF1JI079Amw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Separate lookup of an existing software MSI mapping from allocation of a new mapping. This prepares the code for allocating multiple mappings for an MSI physical address list. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index d0b05b1fda42..3856989f5c4b 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -189,6 +189,23 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_= addr_t msi_addr, phys_addr_t sw_msi_start) { struct iommufd_sw_msi_map *cur; + + lockdep_assert_held(&ictx->sw_msi_lock); + + list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { + if (cur->sw_msi_start !=3D sw_msi_start) + continue; + if (cur->msi_addr =3D=3D msi_addr) + return cur; + } + return NULL; +} + +static struct iommufd_sw_msi_map * +iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, + phys_addr_t sw_msi_start) +{ + struct iommufd_sw_msi_map *cur; unsigned int max_pgoff =3D 0; =20 lockdep_assert_held(&ictx->sw_msi_lock); @@ -199,8 +216,6 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_a= ddr_t msi_addr, if (cur->pgoff =3D=3D UINT_MAX) return ERR_PTR(-EOVERFLOW); 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b963c3c0asm526216835e9.10.2026.08.31.07.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:51 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 04/17] iommufd: Bound software MSI mappings to the reserved range Date: Mon, 31 Aug 2026 16:59:30 +0200 Message-ID: <20260831145943.313726-5-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=E9f9Y6dl c=1 sm=1 tr=0 ts=6a9596ee cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=f1RXMQGm8Qq6PoD2gk0A:9 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX3GQI8giojD1T 8EZmBd2U97XkgEj8HaAWkLkUBJ1ctEQq41FFhHbO6Z926L/JEKL/tSnuT+VQlurLly9QGlYWGVZ 0mD6x3x6qjtOGkn0PO8olclCuqJqF5k= X-Proofpoint-ORIG-GUID: jVgNotJ380QGYOKIgX2edY4wf0J-wve0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX/4KH62xiQHuj +or84oNvFiV+3B3dc3leqGHtJ8yRYtR00pyZNDiDq4+OSpGSWrsoXoS2NzboLXZGA7QU/6NHRaW yFhaIj3H8yve9rk+S5ht6X6BuwDTR7WUzue205Vwt/kQ895pBjnaINtm+mX4lAzqWzGH6WfTQVR sfXwhUiwKJbPKD+1vxfV3M+GUBosEtWxOtZcV6v2a8dQQMdzWnmIsC2FVo91yW9FIuD06S+5qSi B/H4hhutLE4sIbiIxlq84hbLce72Gor2sk4xy/57/W6ASsM2gFwsw6Tk/Eg9etJH2TKoheJOhLS bMYHcnfikhT4i9eDTKKOdI17cuAjaO+B18JOk3aj/Eze5cMiXB6XcrWfnA4+LYUMgbZB6Y2xerK ghllQ0pESC2uZTq75PsUljUxUGpZaEf5mrh9tLojrxnKdbSJhVxIwvUZgjOxBeRIlFfh3JPTFFO 1DNq5vNo1LOuNmj5uRg== X-Proofpoint-GUID: jVgNotJ380QGYOKIgX2edY4wf0J-wve0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Track the start and length of the software MSI reserved region as one range and pass it to the mapping lookup and allocation helpers. Reject cached mappings outside the region and new mappings when no complete page remains. This enforces the reserved region bounds and prepares the helpers to allocate contiguous MSI address lists. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/device.c | 17 +++++++++++------ drivers/iommu/iommufd/driver.c | 21 ++++++++++++--------- drivers/iommu/iommufd/io_pagetable.c | 9 +++++---- drivers/iommu/iommufd/iommufd_private.h | 9 +++++++-- 4 files changed, 35 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index 868f1e591208..7b83810a1c90 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -97,7 +97,7 @@ static struct iommufd_group *iommufd_get_group(struct iom= mufd_ctx *ictx, kref_init(&new_igroup->ref); mutex_init(&new_igroup->lock); xa_init(&new_igroup->pasid_attach); - new_igroup->sw_msi_start =3D PHYS_ADDR_MAX; + new_igroup->sw_msi_range.start =3D PHYS_ADDR_MAX; /* group reference moves into new_igroup */ new_igroup->group =3D group; =20 @@ -374,7 +374,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, struct iommufd_ctx *ictx =3D igroup->ictx; struct iommufd_sw_msi_map *cur; =20 - if (igroup->sw_msi_start =3D=3D PHYS_ADDR_MAX) + if (igroup->sw_msi_range.start =3D=3D PHYS_ADDR_MAX) return 0; =20 /* @@ -384,7 +384,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { int rc; =20 - if (cur->sw_msi_start !=3D igroup->sw_msi_start || + if (cur->sw_msi_start !=3D igroup->sw_msi_range.start || !iommufd_sw_msi_maps_test_bit(&igroup->required_sw_msi, cur->id)) continue; =20 @@ -414,18 +414,23 @@ static int iommufd_device_attach_reserved_iova(struct iommufd_device *idev, struct iommufd_hwpt_paging *hwpt_paging) { + struct iommufd_sw_msi_range sw_msi_range =3D { + .start =3D PHYS_ADDR_MAX, + }; struct iommufd_group *igroup =3D idev->igroup; + bool first_attach; int rc; =20 lockdep_assert_held(&igroup->lock); =20 + first_attach =3D iommufd_group_first_attach(igroup, IOMMU_NO_PASID); rc =3D iopt_table_enforce_dev_resv_regions(&hwpt_paging->ioas->iopt, - idev->dev, - &igroup->sw_msi_start); + idev->dev, &sw_msi_range); if (rc) return rc; =20 - if (iommufd_group_first_attach(igroup, IOMMU_NO_PASID)) { + if (first_attach) { + igroup->sw_msi_range =3D sw_msi_range; rc =3D iommufd_group_setup_msi(igroup, hwpt_paging); if (rc) { iopt_remove_reserved_iova(&hwpt_paging->ioas->iopt, diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 3856989f5c4b..8bb47a81fed1 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -186,14 +186,15 @@ EXPORT_SYMBOL_NS_GPL(iommufd_viommu_report_event, "IO= MMUFD"); */ static struct iommufd_sw_msi_map * iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - phys_addr_t sw_msi_start) + const struct iommufd_sw_msi_range *sw_msi_range) { struct iommufd_sw_msi_map *cur; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { - if (cur->sw_msi_start !=3D sw_msi_start) + if (cur->sw_msi_start !=3D sw_msi_range->start || + cur->pgoff >=3D sw_msi_range->length / PAGE_SIZE) continue; if (cur->msi_addr =3D=3D msi_addr) return cur; @@ -203,7 +204,7 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_a= ddr_t msi_addr, =20 static struct iommufd_sw_msi_map * iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - phys_addr_t sw_msi_start) + const struct iommufd_sw_msi_range *sw_msi_range) { struct iommufd_sw_msi_map *cur; unsigned int max_pgoff =3D 0; @@ -211,7 +212,7 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys= _addr_t msi_addr, lockdep_assert_held(&ictx->sw_msi_lock); =20 list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { - if (cur->sw_msi_start !=3D sw_msi_start) + if (cur->sw_msi_start !=3D sw_msi_range->start) continue; if (cur->pgoff =3D=3D UINT_MAX) return ERR_PTR(-EOVERFLOW); @@ -219,14 +220,16 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, ph= ys_addr_t msi_addr, } =20 if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || - max_pgoff > (ULONG_MAX - sw_msi_start) / PAGE_SIZE) + max_pgoff > (ULONG_MAX - sw_msi_range->start) / PAGE_SIZE) return ERR_PTR(-EOVERFLOW); + if (max_pgoff >=3D sw_msi_range->length / PAGE_SIZE) + return ERR_PTR(-ENOSPC); =20 cur =3D kzalloc_obj(*cur); if (!cur) return ERR_PTR(-ENOMEM); =20 - cur->sw_msi_start =3D sw_msi_start; + cur->sw_msi_start =3D sw_msi_range->start; cur->msi_addr =3D msi_addr; cur->pgoff =3D max_pgoff; cur->id =3D ictx->sw_msi_id++; @@ -295,7 +298,7 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct = msi_desc *desc, =20 handle =3D to_iommufd_handle(raw_handle); /* No IOMMU_RESV_SW_MSI means no change to the msi_msg */ - if (handle->idev->igroup->sw_msi_start =3D=3D PHYS_ADDR_MAX) + if (handle->idev->igroup->sw_msi_range.start =3D=3D PHYS_ADDR_MAX) return 0; =20 ictx =3D handle->idev->ictx; @@ -307,11 +310,11 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, */ msi_map =3D iommufd_sw_msi_get_map(handle->idev->ictx, msi_addr & PAGE_MASK, - handle->idev->igroup->sw_msi_start); + &handle->idev->igroup->sw_msi_range); if (!msi_map) msi_map =3D iommufd_sw_msi_alloc_map(handle->idev->ictx, msi_addr & PAGE_MASK, - handle->idev->igroup->sw_msi_start); + &handle->idev->igroup->sw_msi_range); if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 diff --git a/drivers/iommu/iommufd/io_pagetable.c b/drivers/iommu/iommufd/i= o_pagetable.c index 24d4917105d9..8bf2554af334 100644 --- a/drivers/iommu/iommufd/io_pagetable.c +++ b/drivers/iommu/iommufd/io_pagetable.c @@ -1501,7 +1501,7 @@ void iopt_remove_access(struct io_pagetable *iopt, /* Narrow the valid_iova_itree to include reserved ranges from a device. */ int iopt_table_enforce_dev_resv_regions(struct io_pagetable *iopt, struct device *dev, - phys_addr_t *sw_msi_start) + struct iommufd_sw_msi_range *sw_msi_range) { struct iommu_resv_region *resv; LIST_HEAD(resv_regions); @@ -1520,10 +1520,11 @@ int iopt_table_enforce_dev_resv_regions(struct io_p= agetable *iopt, if (resv->type =3D=3D IOMMU_RESV_DIRECT_RELAXABLE) continue; =20 - if (sw_msi_start && resv->type =3D=3D IOMMU_RESV_MSI) + if (sw_msi_range && resv->type =3D=3D IOMMU_RESV_MSI) num_hw_msi++; - if (sw_msi_start && resv->type =3D=3D IOMMU_RESV_SW_MSI) { - *sw_msi_start =3D resv->start; + if (sw_msi_range && resv->type =3D=3D IOMMU_RESV_SW_MSI) { + sw_msi_range->start =3D resv->start; + sw_msi_range->length =3D resv->length; num_sw_msi++; } =20 diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index 9ca5f9f92cdf..4e2d32809695 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -22,6 +22,11 @@ struct iommu_option; struct iommufd_device; struct dma_buf_attachment; =20 +struct iommufd_sw_msi_range { + phys_addr_t start; + size_t length; +}; + struct iommufd_sw_msi_map { struct list_head sw_msi_item; phys_addr_t sw_msi_start; @@ -171,7 +176,7 @@ void iopt_table_remove_domain(struct io_pagetable *iopt, struct iommu_domain *domain); int iopt_table_enforce_dev_resv_regions(struct io_pagetable *iopt, struct device *dev, - phys_addr_t *sw_msi_start); + struct iommufd_sw_msi_range *sw_msi_range); int iopt_set_allow_iova(struct io_pagetable *iopt, struct rb_root_cached *allowed_iova); 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b945816f2sm346414945e9.8.2026.08.31.07.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:52 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 05/17] iommufd: Prepare software MSI maps for address lists Date: Mon, 31 Aug 2026 16:59:31 +0200 Message-ID: <20260831145943.313726-6-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXyibVCpCUCnTr lZ75rz8Lqh2Vg+NPCxm/yktT5OI5iw5up0cXkucDRDo9pkv7J4XtVER17rGVlrrSRFrZHK/2X4U HtOAbVJSvMR4siLQddZWhzxqN7SX48o= X-Authority-Analysis: v=2.4 cv=CpaPtH4D c=1 sm=1 tr=0 ts=6a9596ea cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=noCGlsY9V4GqTmqY_BAA:9 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX/kvcFYGkWUG3 nZNXb4GMT8qj9Uu7GI1lzuy13WthdqlRIryB6+e+FjtiOSkQvilZ2+xbrHv1ynTZc1kNl2K4jSS 3o+2gi5BERdOAQS1d3JBtRLzEMPK9BQBguCvlSZ8rhbvK1pD6XFM67P7QfYtlH/5SgL7k2MvZS3 tprN80ISZZU1Pg+0Fk7ae2UP7NnNRvSl1cjx4Y6QQ2YOx52ZPH9ZnUBRuC1mEbbrOqHVA7TIsQP 6sV6vyR3ASMbQtb6M/kPDOPCrlOI2glAP2lrn7HwaawZr/CUeSRuGNTBpEl7+n5DkdJcQIujuc9 j60MuliaZ+eU5T84tWheNieAW9Dawhz/NeQYbCu6koDVGoxx1eVDLuHsKezwW/j6mgor9XlUQY7 7uEN8CNROjO6qkrMVxk8JQcwiOstrE6Q9pAPJxc5WOFerzaRGOjhjUMhQE10r8EgljrMX2wPSR/ Fq81IXPmIRIc1Uo6Bkg== X-Proofpoint-ORIG-GUID: yD7JEfqZ9dGT6UKxO2K7o1XgI56GWGTx X-Proofpoint-GUID: yD7JEfqZ9dGT6UKxO2K7o1XgI56GWGTx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Teach iommufd_sw_msi_get_map() to match an ordered physical address list against an existing contiguous IOVA range. Mark the first map with the range size so an identical list can reuse the allocation. Teach iommufd_sw_msi_alloc_map() to reserve identifiers and offsets for the complete list and build its maps on a temporary list. Keep the existing scalar installation behavior and only publish newly allocated maps after installation succeeds. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 161 ++++++++++++++++++------ drivers/iommu/iommufd/iommufd_private.h | 1 + 2 files changed, 123 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 8bb47a81fed1..6a0527f4b058 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -179,35 +179,91 @@ EXPORT_SYMBOL_NS_GPL(iommufd_viommu_report_event, "IO= MMUFD"); =20 #ifdef CONFIG_IRQ_MSI_IOMMU /* - * Get a iommufd_sw_msi_map for the msi physical address requested by the = irq + * Get an iommufd_sw_msi_map for the msi physical addresses requested by t= he irq * layer. The mapping to IOVA is global to the iommufd file descriptor, ev= ery * domain that is attached to a device using the same MSI parameters will = use - * the same IOVA. + * the same contiguous IOVA range. */ static struct iommufd_sw_msi_map * -iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - const struct iommufd_sw_msi_range *sw_msi_range) +iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, const phys_addr_t *phys_a= ddrs, + unsigned int nr_addrs, const struct iommufd_sw_msi_range *sw_msi_= range) { - struct iommufd_sw_msi_map *cur; + struct iommufd_sw_msi_map *cur, *msi_map; + unsigned int nr_found; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 - list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { - if (cur->sw_msi_start !=3D sw_msi_range->start || - cur->pgoff >=3D sw_msi_range->length / PAGE_SIZE) + list_for_each_entry(msi_map, &ictx->sw_msi_list, sw_msi_item) { + if (msi_map->sw_msi_start !=3D sw_msi_range->start || + msi_map->msi_addr !=3D phys_addrs[0]) + continue; + if (msi_map->range_size !=3D nr_addrs * PAGE_SIZE) continue; - if (cur->msi_addr =3D=3D msi_addr) - return cur; + if (msi_map->pgoff > sw_msi_range->length / PAGE_SIZE || + nr_addrs > sw_msi_range->length / PAGE_SIZE - msi_map->pgoff) + continue; + + nr_found =3D 0; + list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { + unsigned int index; + + if (cur->sw_msi_start !=3D sw_msi_range->start || + cur->pgoff < msi_map->pgoff) + continue; + index =3D cur->pgoff - msi_map->pgoff; + if (index >=3D nr_addrs) + continue; + if (cur->msi_addr !=3D phys_addrs[index]) + break; + nr_found++; + } + if (nr_found =3D=3D nr_addrs) + return msi_map; } return NULL; } =20 +static int iommufd_sw_msi_check_alloc(struct iommufd_ctx *ictx, + const struct iommufd_sw_msi_range *sw_msi_range, + unsigned int first_pgoff, unsigned int nr_addrs, + size_t *range_size) +{ + unsigned long max_iova_pgoff; + unsigned int last_pgoff; + unsigned int last_id; + size_t range_pages; + + if (!nr_addrs) + return -EINVAL; + if (sw_msi_range->start > ULONG_MAX) + return -EOVERFLOW; + + range_pages =3D sw_msi_range->length / PAGE_SIZE; + max_iova_pgoff =3D (ULONG_MAX - sw_msi_range->start) / PAGE_SIZE; + + if (check_add_overflow(ictx->sw_msi_id, nr_addrs - 1, &last_id) || + last_id > IOMMUFD_SW_MSI_MAX_ID || + check_add_overflow(first_pgoff, nr_addrs - 1, &last_pgoff) || + last_pgoff > max_iova_pgoff || + check_mul_overflow((size_t)nr_addrs, PAGE_SIZE, range_size)) + return -EOVERFLOW; + + if (last_pgoff >=3D range_pages) + return -ENOSPC; + + return 0; +} + static struct iommufd_sw_msi_map * -iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - const struct iommufd_sw_msi_range *sw_msi_range) +iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, const phys_addr_t *phys= _addrs, + unsigned int nr_addrs, const struct iommufd_sw_msi_range *sw_msi_range, + struct list_head *new_msi_maps) { - struct iommufd_sw_msi_map *cur; - unsigned int max_pgoff =3D 0; + struct iommufd_sw_msi_map *cur, *first_map =3D NULL; + unsigned int next_pgoff =3D 0; + unsigned int i; + size_t size; + int rc; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 @@ -216,25 +272,38 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, ph= ys_addr_t msi_addr, continue; if (cur->pgoff =3D=3D UINT_MAX) return ERR_PTR(-EOVERFLOW); - max_pgoff =3D max(max_pgoff, cur->pgoff + 1); + next_pgoff =3D max(next_pgoff, cur->pgoff + 1); } =20 - if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || - max_pgoff > (ULONG_MAX - sw_msi_range->start) / PAGE_SIZE) - return ERR_PTR(-EOVERFLOW); - if (max_pgoff >=3D sw_msi_range->length / PAGE_SIZE) - return ERR_PTR(-ENOSPC); - - cur =3D kzalloc_obj(*cur); - if (!cur) - return ERR_PTR(-ENOMEM); - - cur->sw_msi_start =3D sw_msi_range->start; - cur->msi_addr =3D msi_addr; - cur->pgoff =3D max_pgoff; - cur->id =3D ictx->sw_msi_id++; - list_add_tail(&cur->sw_msi_item, &ictx->sw_msi_list); - return cur; + rc =3D iommufd_sw_msi_check_alloc(ictx, sw_msi_range, next_pgoff, nr_addr= s, &size); + if (rc) + return ERR_PTR(rc); + + for (i =3D 0; i < nr_addrs; i++) { + cur =3D kzalloc_obj(*cur); + if (!cur) + goto err_free; + + cur->sw_msi_start =3D sw_msi_range->start; + cur->msi_addr =3D phys_addrs[i]; + cur->pgoff =3D next_pgoff + i; + cur->id =3D ictx->sw_msi_id + i; + if (!i) { + cur->range_size =3D size; + first_map =3D cur; + } + list_add_tail(&cur->sw_msi_item, new_msi_maps); + } + + return first_map; + +err_free: + while (!list_empty(new_msi_maps)) { + cur =3D list_first_entry(new_msi_maps, typeof(*cur), sw_msi_item); + list_del(&cur->sw_msi_item); + kfree(cur); + } + return ERR_PTR(-ENOMEM); } =20 int iommufd_sw_msi_install(struct iommufd_ctx *ictx, @@ -280,7 +349,9 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct = msi_desc *desc, struct iommufd_attach_handle *handle; struct iommufd_sw_msi_map *msi_map; struct iommufd_ctx *ictx; + LIST_HEAD(new_msi_maps); unsigned long iova; + phys_addr_t phys_addr; int rc; =20 /* @@ -308,29 +379,41 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, * assume the caller has checked that it is contained with a MMIO region * that is secure to map at PAGE_SIZE. */ - msi_map =3D iommufd_sw_msi_get_map(handle->idev->ictx, - msi_addr & PAGE_MASK, - &handle->idev->igroup->sw_msi_range); + phys_addr =3D msi_addr & PAGE_MASK; + msi_map =3D iommufd_sw_msi_get_map(ictx, &phys_addr, 1, &handle->idev->ig= roup->sw_msi_range); if (!msi_map) - msi_map =3D iommufd_sw_msi_alloc_map(handle->idev->ictx, - msi_addr & PAGE_MASK, - &handle->idev->igroup->sw_msi_range); + msi_map =3D iommufd_sw_msi_alloc_map(ictx, &phys_addr, 1, + &handle->idev->igroup->sw_msi_range, + &new_msi_maps); if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, msi_map->id); if (rc) - return rc; + goto err_free; =20 rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); if (rc) - return rc; + goto err_free; __set_bit(msi_map->id, handle->idev->igroup->required_sw_msi.bitmap); =20 + if (!list_empty(&new_msi_maps)) { + list_splice_tail_init(&new_msi_maps, &ictx->sw_msi_list); + ictx->sw_msi_id++; + } + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; msi_desc_set_iommu_msi_iova(desc, iova, PAGE_SHIFT); return 0; + +err_free: + while (!list_empty(&new_msi_maps)) { + msi_map =3D list_first_entry(&new_msi_maps, typeof(*msi_map), sw_msi_ite= m); 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4843dcc00a6sm5323372f8f.33.2026.08.31.07.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:54 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 06/17] iommufd: Install software MSI map ranges atomically Date: Mon, 31 Aug 2026 16:59:32 +0200 Message-ID: <20260831145943.313726-7-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 00UTNl2pPGlYqlfua6NFIMia0xZF6AhJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX7VlUwo0rwwx/ 24QR2w0tfIj7ar7MzQQxeo6qJZRukbs16D2UWRKKRnlqYo+BGhq783/kL82utYCU8LURMfRh+3l g8FhrBn29B3ILGTnpTZOEpnwXjNPCAvZcsIx5dE/6VyMdCYYmsKLNrlZFlG6hvuYYctBvKhd7h9 0lzO47mHFgJw0lwy4lC5HR6u2CRFDHXFvIt0vWYBv4Z6hfc46r9alUmUY/5DN9lzrXy6TQWjg0m 7ZCntknUL/KtTFxIBDotYsxC1lIzipj++CPhc1xjiIA53azyVO+j3mxH5lc7vcUQlVzUFsD083L 8PRkNUNG2Yaqritaxvrb6mlhlTujb5L1I6nHl1t4sYf1oOtVLxwH4vTl19W6H7J9FrWyBoU1ZVu asGxYYefIuaPmqLI1Nmp7uvmZRLb5HvqJWHrQL0sHG4Xb846gH8GCR+Lbb2M62TrAqOZWxxaaHJ P9cmC+JpjcONrKvO05A== X-Proofpoint-GUID: 00UTNl2pPGlYqlfua6NFIMia0xZF6AhJ X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX3Az4ONhQ+76y ZCkCp4+QhI0CgCs9gtozz4pDr7nJMzX6Hka/hAiLpyWd1eMTV94dfOJvcJdgaHuxZk/VK9Vu2Eg oaNuQRN0/MzFm/7vncWbsUR0IMVldwc= X-Authority-Analysis: v=2.4 cv=GbQnWwXL c=1 sm=1 tr=0 ts=6a9596ec cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=0NqqyPg6VgUUedX_kk0A:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 adultscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Add a range installation helper which installs every map in a contiguous software MSI range and rolls back only mappings added by the failed operation. Use the helper when replaying range mappings into a new paging domain. This prepares iommufd to publish and install physical address lists without exposing partially installed ranges. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 76 ++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 6a0527f4b058..a43a25078f87 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -178,6 +178,17 @@ int iommufd_viommu_report_event(struct iommufd_viommu = *viommu, EXPORT_SYMBOL_NS_GPL(iommufd_viommu_report_event, "IOMMUFD"); =20 #ifdef CONFIG_IRQ_MSI_IOMMU +static bool iommufd_sw_msi_range_index(const struct iommufd_sw_msi_map *ma= p, + const struct iommufd_sw_msi_map *base_map, + unsigned int nr_addrs, unsigned int *index) +{ + if (map->sw_msi_start !=3D base_map->sw_msi_start || map->pgoff < base_ma= p->pgoff) + return false; + + *index =3D map->pgoff - base_map->pgoff; + return *index < nr_addrs; +} + /* * Get an iommufd_sw_msi_map for the msi physical addresses requested by t= he irq * layer. The mapping to IOVA is global to the iommufd file descriptor, ev= ery @@ -207,11 +218,7 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, const= phys_addr_t *phys_addrs, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { unsigned int index; =20 - if (cur->sw_msi_start !=3D sw_msi_range->start || - cur->pgoff < msi_map->pgoff) - continue; - index =3D cur->pgoff - msi_map->pgoff; - if (index >=3D nr_addrs) + if (!iommufd_sw_msi_range_index(cur, msi_map, nr_addrs, &index)) continue; if (cur->msi_addr !=3D phys_addrs[index]) break; @@ -306,9 +313,9 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, cons= t phys_addr_t *phys_addrs return ERR_PTR(-ENOMEM); } =20 -int iommufd_sw_msi_install(struct iommufd_ctx *ictx, - struct iommufd_hwpt_paging *hwpt_paging, - struct iommufd_sw_msi_map *msi_map) +static int iommufd_sw_msi_install_one(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct iommufd_sw_msi_map *msi_map) { unsigned long iova; int rc; @@ -332,6 +339,59 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); return 0; } + +int iommufd_sw_msi_install(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct iommufd_sw_msi_map *base_map) +{ + struct iommufd_sw_msi_map *msi_map; + struct list_head *msi_maps =3D &ictx->sw_msi_list; + unsigned long *newly_mapped; + unsigned int nr_addrs =3D base_map->range_size ? base_map->range_size / P= AGE_SIZE : 1; + unsigned int nr_found =3D 0; + unsigned int index; + int rc =3D 0; + + newly_mapped =3D bitmap_zalloc(nr_addrs, GFP_KERNEL_ACCOUNT); + if (!newly_mapped) + return -ENOMEM; + + list_for_each_entry(msi_map, msi_maps, sw_msi_item) { + if (!iommufd_sw_msi_range_index(msi_map, base_map, nr_addrs, &index)) + continue; + if (iommufd_sw_msi_maps_test_bit(&hwpt_paging->present_sw_msi, msi_map->= id)) { + nr_found++; + continue; + } + rc =3D iommufd_sw_msi_install_one(ictx, hwpt_paging, msi_map); + if (rc) + goto err_unmap; + __set_bit(index, newly_mapped); + nr_found++; + } + if (nr_found !=3D nr_addrs) { + rc =3D -EINVAL; + goto err_unmap; + } + + bitmap_free(newly_mapped); + return 0; + +err_unmap: + list_for_each_entry(msi_map, msi_maps, sw_msi_item) { + unsigned long iova; + + if (!iommufd_sw_msi_range_index(msi_map, base_map, nr_addrs, &index) || + !test_bit(index, newly_mapped)) + continue; + + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; + WARN_ON_ONCE(iommu_unmap(hwpt_paging->common.domain, iova, PAGE_SIZE) != =3D PAGE_SIZE); + __clear_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); + } + bitmap_free(newly_mapped); + return rc; +} EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 /* --=20 2.43.0 From nobody Sat Sep 26 14:39:01 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81D304A6CEE for ; Mon, 31 Aug 2026 14:59:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdb13f094sm40886845e9.3.2026.08.31.07.59.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:56 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 07/17] iommufd: Prepare software MSI installation for address lists Date: Mon, 31 Aug 2026 16:59:33 +0200 Message-ID: <20260831145943.313726-8-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX05J7Qqt/2qVk QDec6B6jUESI3KDRREqVuDL+Zakd4SwCd2aVQwh9WIC5gGgjXNeDcyTo8IvIjVEdnLYy3rIfzHm PbLnUjQhFFJQ4fDilBvOuurrS/kuC54= X-Authority-Analysis: v=2.4 cv=CpaPtH4D c=1 sm=1 tr=0 ts=6a9596ee cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=fyE6B5mSzfnmm1qxREQA:9 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX9wvE/PjwB2vI rDT4XUpsn/D1jO1chJz0zCVoqwwcau4NJNFmEHNA4OwhYsCdjrFCBTMogTVQkJ3wXOHI4Dntpvx Fm7ftM3eBmM2ILOjKY1fsbpxyLvvWOtVwKb825yJXjtWmg9KY8aY7UyH4AqMYDbn9QK1LmXgB/2 3YaShHgCchftXr+RUnBZGO2YACxWUMqrqDVArhlj8hj5wRTJc38hphwb3GB84Sa4Z2bRHPiuSVw hVCw1U4FoOR5PlmFuoxwOh4qJLkQSRwL4ASFEtDt1+l11jBRnsRdneOMQTqSF57KmcRHnxe6WPv J1+3m8MfWv7794l7jbFpA1sAf0SIGFHreWmvcb+iwrBDv/m4ovaUmQvfPBSHADQdy5yy2soeKT7 qXXnfwlo1rJJoi6o3+GRMikE9BXLbrDmBXMUrFRQVOCtRO3Cd1nt65XGLO+tL96p9SD3EjTi49a NwfCCLHwRZuZWhJQdlA== X-Proofpoint-ORIG-GUID: K721EMGJ18Mke-t1mLZMMFQtrGfu4Pad X-Proofpoint-GUID: K721EMGJ18Mke-t1mLZMMFQtrGfu4Pad X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Teach the software MSI path to install every mapping in an address list before publishing newly allocated maps. Mark the complete list as required by the group and roll back mappings installed by a failed operation. Keep iommufd_sw_msi() as a one-address wrapper so existing callers retain their current behavior. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 101 +++++++++++++++++++++++---------- 1 file changed, 72 insertions(+), 29 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index a43a25078f87..45278c11c688 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -340,14 +340,14 @@ static int iommufd_sw_msi_install_one(struct iommufd_= ctx *ictx, return 0; } =20 -int iommufd_sw_msi_install(struct iommufd_ctx *ictx, - struct iommufd_hwpt_paging *hwpt_paging, - struct iommufd_sw_msi_map *base_map) +static int __iommufd_sw_msi_install_range(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct list_head *msi_maps, + const struct iommufd_sw_msi_map *base_map, + unsigned int nr_addrs) { struct iommufd_sw_msi_map *msi_map; - struct list_head *msi_maps =3D &ictx->sw_msi_list; unsigned long *newly_mapped; - unsigned int nr_addrs =3D base_map->range_size ? base_map->range_size / P= AGE_SIZE : 1; unsigned int nr_found =3D 0; unsigned int index; int rc =3D 0; @@ -392,16 +392,36 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, bitmap_free(newly_mapped); return rc; } + +int iommufd_sw_msi_install(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct iommufd_sw_msi_map *base_map) +{ + unsigned int nr_addrs =3D base_map->range_size ? base_map->range_size / P= AGE_SIZE : 1; + + return __iommufd_sw_msi_install_range(ictx, hwpt_paging, &ictx->sw_msi_li= st, base_map, + nr_addrs); +} EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 -/* - * Called by the irq code if the platform translates the MSI address throu= gh the - * IOMMU. msi_addr is the physical address of the MSI page. iommufd will - * allocate a fd global iova for the physical page that is the same on all - * domains and devices. - */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +static void iommufd_sw_msi_set_required(struct iommufd_group *igroup, + struct list_head *msi_maps, + const struct iommufd_sw_msi_map *base_map, + unsigned int nr_addrs) +{ + struct iommufd_sw_msi_map *msi_map; + unsigned int index; + + list_for_each_entry(msi_map, msi_maps, sw_msi_item) { + if (!iommufd_sw_msi_range_index(msi_map, base_map, nr_addrs, &index)) + continue; + __set_bit(msi_map->id, igroup->required_sw_msi.bitmap); + } +} + +static int iommufd_sw_msi_list(struct iommu_domain *domain, struct msi_des= c *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) { struct device *dev =3D msi_desc_to_dev(desc); struct iommufd_hwpt_paging *hwpt_paging; @@ -410,10 +430,19 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, struct iommufd_sw_msi_map *msi_map; struct iommufd_ctx *ictx; LIST_HEAD(new_msi_maps); + struct list_head *msi_maps; unsigned long iova; - phys_addr_t phys_addr; + unsigned int i; int rc; =20 + if (granule !=3D PAGE_SIZE) + return -EOPNOTSUPP; + if (!nr_addrs || nr_addrs > SIZE_MAX / PAGE_SIZE) + return -EINVAL; + for (i =3D 0; i < nr_addrs; i++) + if (!IS_ALIGNED(phys_addrs[i], PAGE_SIZE)) + return -EINVAL; + /* * It is safe to call iommu_attach_handle_get() here because the iommu * core code invokes this under the group mutex which also prevents any @@ -434,33 +463,33 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, =20 ictx =3D handle->idev->ictx; guard(mutex)(&ictx->sw_msi_lock); - /* - * The input msi_addr is the exact byte offset of the MSI doorbell, we - * assume the caller has checked that it is contained with a MMIO region - * that is secure to map at PAGE_SIZE. - */ - phys_addr =3D msi_addr & PAGE_MASK; - msi_map =3D iommufd_sw_msi_get_map(ictx, &phys_addr, 1, &handle->idev->ig= roup->sw_msi_range); - if (!msi_map) - msi_map =3D iommufd_sw_msi_alloc_map(ictx, &phys_addr, 1, + msi_map =3D iommufd_sw_msi_get_map(ictx, phys_addrs, nr_addrs, + &handle->idev->igroup->sw_msi_range); + if (msi_map) { + msi_maps =3D &ictx->sw_msi_list; + } else { + msi_map =3D iommufd_sw_msi_alloc_map(ictx, phys_addrs, nr_addrs, &handle->idev->igroup->sw_msi_range, &new_msi_maps); - if (IS_ERR(msi_map)) - return PTR_ERR(msi_map); + if (IS_ERR(msi_map)) + return PTR_ERR(msi_map); + msi_maps =3D &new_msi_maps; + } =20 rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, - msi_map->id); + msi_map->id + nr_addrs - 1); if (rc) goto err_free; =20 - rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); + rc =3D __iommufd_sw_msi_install_range(ictx, hwpt_paging, msi_maps, msi_ma= p, nr_addrs); if (rc) goto err_free; - __set_bit(msi_map->id, handle->idev->igroup->required_sw_msi.bitmap); + + iommufd_sw_msi_set_required(handle->idev->igroup, msi_maps, msi_map, nr_a= ddrs); =20 if (!list_empty(&new_msi_maps)) { list_splice_tail_init(&new_msi_maps, &ictx->sw_msi_list); - ictx->sw_msi_id++; + ictx->sw_msi_id +=3D nr_addrs; } =20 iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; @@ -475,6 +504,20 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, } return rc; } + +/* + * Called by the irq code if the platform translates the MSI address throu= gh the + * IOMMU. msi_addr is the physical address of the MSI page. iommufd will + * allocate a fd global iova for the physical page that is the same on all + * domains and devices. + */ +int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + phys_addr_t msi_addr) +{ + phys_addr_t phys_addr =3D msi_addr & PAGE_MASK; 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ccea6b814sm180435205e9.0.2026.08.31.07.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:57 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 08/17] iommu/dma: Introduce iommu_dma_prepare_msi_list() Date: Mon, 31 Aug 2026 16:59:34 +0200 Message-ID: <20260831145943.313726-9-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX7db9vtgXQ3A5 1Db7L5A2pCkCS+lZeXBII+nMARfE3DAY+STMZMxx2FisnHDvSyW9ZHp2PJFGlLrS1pPtrovo3ti IZIWkAl7squbnT4JvXJ5ZF2Me3aHNqQ= X-Proofpoint-GUID: hocgLZFEHrS1JcQpoNMbPOtFeIZm3WH6 X-Authority-Analysis: v=2.4 cv=CYE4Irrl c=1 sm=1 tr=0 ts=6a9596f0 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=2ceW4JgIosI8Fxwmn1gA:9 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-ORIG-GUID: hocgLZFEHrS1JcQpoNMbPOtFeIZm3WH6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXyWSwKh0Kuiaz Nk/jXAszIfMTVYd+t8L+4H12ItlwZWwKjkJVp4s3Gf+HkZlxjdcis4npWh9loLnWxExHzOFxSMC b4st9OBTmd1S9hRmOP83PyR4I1GUz8Bz02hMyanZuFjH9oDz6vjmN2BjKglfDK5g0PcETqtqLjo G5icD7D78nGzPJKtSJzoy9ONNvamSs9OX+21OSS6z0hMam8a+xyDLlfxACb07jgX8ZkBeedUxR9 wqMgjP+PMZ0DCYwZt+4XwdTQZyKN5Y5Iwj6h8X+nNeYohvQ098SqJysZNeECZ3gAWNAs+9zmgub w1NA2l3oMOuZgOHyxvVLiXGhM7JuPZRBp1/jQZxPePI84/kr9Y9yEMThpgpgXfHYj+JxZUJNxUP +4H4xosUCS9yZEkIuup+LywjKg5GNnzJJi/fSNMjK9mYlKEzhPveDoFsbEwiO3PbF+wZuU6vr3I cmO2gSwPiBS9PtHcaSQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Add iommu_dma_prepare_msi_list() to map an ordered physical address list through the current domain backend. Validate that the requested granule is a power of two no smaller than PAGE_SIZE and that every address is aligned to it. Refactor iommu_dma_prepare_msi() to obtain the backend granule and align its single address before using the same list dispatcher. Convert the DMA-IOMMU and iommufd backend entry points to consume address lists directly. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/dma-iommu.c | 13 ++-- drivers/iommu/dma-iommu.h | 13 +++- drivers/iommu/iommu-priv.h | 7 ++- drivers/iommu/iommu.c | 109 +++++++++++++++++++++++++++------ drivers/iommu/iommufd/driver.c | 24 +++----- include/linux/iommu.h | 8 +++ 6 files changed, 126 insertions(+), 48 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 38a0c4e244d6..c9fdc792416c 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2173,7 +2173,7 @@ static bool has_msi_cookie(const struct iommu_domain = *domain) domain->cookie_type =3D=3D IOMMU_COOKIE_DMA_MSI); } =20 -static size_t cookie_msi_granule(const struct iommu_domain *domain) +size_t iommu_dma_msi_granule(const struct iommu_domain *domain) { switch (domain->cookie_type) { case IOMMU_COOKIE_DMA_IOVA: @@ -2304,23 +2304,20 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi= _page(struct device *dev, } =20 int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granul= e) { struct device *dev =3D msi_desc_to_dev(desc); const struct iommu_dma_msi_page *msi_page; - phys_addr_t phys_addr; - size_t granule; =20 if (!has_msi_cookie(domain)) { msi_desc_set_iommu_msi_iova(desc, 0, 0); return 0; } - - granule =3D cookie_msi_granule(domain); - phys_addr =3D ALIGN_DOWN(msi_addr, granule); + if (granule !=3D iommu_dma_msi_granule(domain)) + return -EOPNOTSUPP; =20 iommu_group_mutex_assert(dev); - msi_page =3D iommu_dma_get_msi_page(dev, &phys_addr, 1, granule, domain); + msi_page =3D iommu_dma_get_msi_page(dev, phys_addrs, nr_addrs, granule, d= omain); if (!msi_page) return -ENOMEM; =20 diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 040d00252563..bf9cd4102d35 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -19,8 +19,9 @@ int iommu_dma_init_fq(struct iommu_domain *domain); =20 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list= ); =20 +size_t iommu_dma_msi_granule(const struct iommu_domain *domain); int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granul= e); =20 extern bool iommu_dma_forcedac; =20 @@ -53,8 +54,14 @@ static inline void iommu_dma_get_resv_regions(struct dev= ice *dev, struct list_he { } =20 -static inline int iommu_dma_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) +static inline size_t iommu_dma_msi_granule(const struct iommu_domain *doma= in) +{ + return 0; +} + +static inline int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi= _desc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) { return -ENODEV; } diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index aaffad5854fc..1122c99566d5 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -54,10 +54,11 @@ int iommu_replace_group_handle(struct iommu_group *grou= p, =20 #if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) && IS_ENABLED(CONFIG_IRQ_MSI_IO= MMU) int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granule); #else /* !CONFIG_IOMMUFD_DRIVER_CORE || !CONFIG_IRQ_MSI_IOMMU */ -static inline int iommufd_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) +static inline int iommufd_sw_msi(struct iommu_domain *domain, struct msi_d= esc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) { return -EOPNOTSUPP; } diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index a3dea7353500..692e793c624e 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -4223,42 +4223,115 @@ void pci_dev_reset_iommu_done(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_done); =20 #if IS_ENABLED(CONFIG_IRQ_MSI_IOMMU) +static int __iommu_dma_prepare_msi_list(struct iommu_group *group, struct = msi_desc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) +{ + if (!group->domain || group->domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) + return 0; + + switch (group->domain->cookie_type) { + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_DMA_IOVA: + return iommu_dma_sw_msi(group->domain, desc, phys_addrs, nr_addrs, granu= le); + case IOMMU_COOKIE_IOMMUFD: + return iommufd_sw_msi(group->domain, desc, phys_addrs, nr_addrs, granule= ); + default: + return -EOPNOTSUPP; + } +} + +static int iommu_dma_validate_msi_list(const phys_addr_t *phys_addrs, unsi= gned int nr_addrs, + size_t granule) +{ + unsigned int i; + + if (!nr_addrs || granule < PAGE_SIZE || !is_power_of_2(granule) || + nr_addrs > SIZE_MAX / granule) + return -EINVAL; + + for (i =3D 0; i < nr_addrs; i++) + if (!IS_ALIGNED(phys_addrs[i], granule)) + return -EINVAL; + + return 0; +} + +/** + * iommu_dma_prepare_msi_list() - Map MSI pages in the IOMMU domain + * @desc: MSI descriptor to update with the base IOVA + * @phys_addrs: Ordered MSI target physical addresses + * @nr_addrs: Number of addresses in @phys_addrs + * @granule: Mapping granule for every address + * + * @nr_addrs must be nonzero and @granule must be a power of two no smalle= r than + * PAGE_SIZE. Every address must be aligned to @granule. The addresses are= mapped + * in order to one contiguous IOVA range and may repeat. The list is consu= med + * synchronously and is not retained. + * + * When a software MSI mapping is required, the backend records the base I= OVA + * and granule shift in @desc. Otherwise, @desc is left unchanged. + * + * Return: 0 on success, -EINVAL if the parameters are invalid, -EOPNOTSUP= P if + * the domain backend cannot provide the mapping, or another negative error + * code from the backend. + */ +int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *p= hys_addrs, + unsigned int nr_addrs, size_t granule) +{ + struct device *dev =3D msi_desc_to_dev(desc); + struct iommu_group *group =3D dev->iommu_group; + int ret; + + ret =3D iommu_dma_validate_msi_list(phys_addrs, nr_addrs, granule); + if (ret || !group) + return ret; + + mutex_lock(&group->mutex); + ret =3D __iommu_dma_prepare_msi_list(group, desc, phys_addrs, nr_addrs, g= ranule); + mutex_unlock(&group->mutex); + return ret; +} + /** * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain * @desc: MSI descriptor, will store the MSI page * @msi_addr: MSI target address to be mapped * - * The implementation of sw_msi() should take msi_addr and map it to - * an IOVA in the domain and call msi_desc_set_iommu_msi_iova() with the - * mapping information. - * * Return: 0 on success or negative error code if the mapping failed. */ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) { struct device *dev =3D msi_desc_to_dev(desc); struct iommu_group *group =3D dev->iommu_group; + phys_addr_t phys_addr; + size_t granule; int ret =3D 0; =20 if (!group) return 0; =20 mutex_lock(&group->mutex); - /* An IDENTITY domain must pass through */ - if (group->domain && group->domain->type !=3D IOMMU_DOMAIN_IDENTITY) { - switch (group->domain->cookie_type) { - case IOMMU_COOKIE_DMA_MSI: - case IOMMU_COOKIE_DMA_IOVA: - ret =3D iommu_dma_sw_msi(group->domain, desc, msi_addr); - break; - case IOMMU_COOKIE_IOMMUFD: - ret =3D iommufd_sw_msi(group->domain, desc, msi_addr); - break; - default: - ret =3D -EOPNOTSUPP; - break; - } + if (!group->domain || group->domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) + goto out_unlock; + + switch (group->domain->cookie_type) { + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_DMA_IOVA: + granule =3D iommu_dma_msi_granule(group->domain); + break; + case IOMMU_COOKIE_IOMMUFD: + granule =3D PAGE_SIZE; + break; + default: + ret =3D -EOPNOTSUPP; + goto out_unlock; } + + phys_addr =3D ALIGN_DOWN(msi_addr, granule); + ret =3D __iommu_dma_prepare_msi_list(group, desc, &phys_addr, 1, granule); + +out_unlock: mutex_unlock(&group->mutex); return ret; } diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 45278c11c688..72e9ce63a5ee 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -419,9 +419,14 @@ static void iommufd_sw_msi_set_required(struct iommufd= _group *igroup, } } =20 -static int iommufd_sw_msi_list(struct iommu_domain *domain, struct msi_des= c *desc, - const phys_addr_t *phys_addrs, unsigned int nr_addrs, - size_t granule) +/* + * Called by the irq code if the platform translates the MSI addresses thr= ough the + * IOMMU. phys_addrs are the physical addresses of the MSI pages. iommufd = will + * allocate contiguous fd global iovas for the physical pages that are the= same on + * all domains and devices. + */ +int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granule) { struct device *dev =3D msi_desc_to_dev(desc); struct iommufd_hwpt_paging *hwpt_paging; @@ -505,19 +510,6 @@ static int iommufd_sw_msi_list(struct iommu_domain *do= main, struct msi_desc *des return rc; } =20 -/* - * Called by the irq code if the platform translates the MSI address throu= gh the - * IOMMU. msi_addr is the physical address of the MSI page. iommufd will - * allocate a fd global iova for the physical page that is the same on all - * domains and devices. - */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) -{ - phys_addr_t phys_addr =3D msi_addr & PAGE_MASK; - - return iommufd_sw_msi_list(domain, desc, &phys_addr, 1, PAGE_SIZE); -} EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi, "IOMMUFD"); #endif =20 diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ac43b8b93f14..bf08be172e40 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1561,8 +1561,16 @@ static inline void pci_dev_reset_iommu_done(struct p= ci_dev *pdev) =20 #ifdef CONFIG_IRQ_MSI_IOMMU #ifdef CONFIG_IOMMU_API +int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *p= hys_addrs, + unsigned int nr_addrs, size_t granule); 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4843dcc00a6sm5323903f8f.33.2026.08.31.07.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:59 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 09/17] iommu/riscv: Report cache coherency capability Date: Mon, 31 Aug 2026 16:59:35 +0200 Message-ID: <20260831145943.313726-10-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=W6UIkxWk c=1 sm=1 tr=0 ts=6a9596f1 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Ikd4Dj_1AAAA:8 a=ITBYzW_wA1tX7bdzKc4A:9 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: DTaDWr7hCDa0sawzT4nOpsl98LDLusO8 X-Proofpoint-GUID: DTaDWr7hCDa0sawzT4nOpsl98LDLusO8 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXxldQodQRXSvG Ke3brgBPPzf24z9FjrCEiuQyN8Hg55GSxNWTreenCoyCQ59WI4sv0QzuWjHBynDMnSve88h8YrX FWFXmG2JJLKyTv7yD4y1nn3lubEDRrg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXyWd3qMxUyP/I SRZbk8FUenE+UNZL9WHQWj1lNYo7TfIgJmYE3ZAg8jGhFGmncsQZZTxGjl8VAIkPOBUwQYrFwVw Tr6f+6Xl8IFU3/B0KOnvZGed2j+NvFyYF9pHwNiGjIqph1TzYEPjHPAy5ey/AJedljNNoBU3lxP /kvHSjpjsvtG0Pr6RsgZ3UeHaOz0njga9H2tidNbPugZbpuZRuXWiqc7L8dHj+u7XEyt69TEQLH mCHMbixfIr33Q3TDV3VgWgCi8xrMZuY/QudbZDRaoybRkrYLY5Hh27aq6XL2Eno4hkZCgN9jE+7 8Z494lNbDVMWkiJ9Az8gA1MIteLxy/OstAB3Zq3vMzucI9SYqzu0lDB9rgRsTCg9vt56IFunc9C y7ewA74emRVspHO+MI00X2cg3IS6q4khGgYvmwpDkZA5xCkruuCzrlYKLEYphRlKzc5jJfEW5hb e95GCETtr5gMpZgxIjQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" VFIO and iommufd require IOMMU_CAP_CACHE_COHERENCY because they use IOMMU_CACHE mappings and have no userspace cache-maintenance path. RISC-V page tables preserve physical memory attributes for IOMMU_CACHE mappings. Svpbmt marks mappings without IOMMU_CACHE as non-cacheable, but preserving physical attributes cannot make a noncoherent device path coherent. Report the capability only for devices marked DMA coherent. This limits userspace assignment to paths that can honor cacheable mappings. Signed-off-by: Andrew Jones Reviewed-by: Jason Gunthorpe Tested-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cec3ddd7ab10..e5818ce44515 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -1422,6 +1423,16 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) return generic_device_group(dev); } =20 +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + return dev_is_dma_coherent(dev); + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandl= e_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1483,6 +1494,7 @@ static void riscv_iommu_release_device(struct device = *dev) =20 static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, + .capable =3D riscv_iommu_capable, .identity_domain =3D &riscv_iommu_identity_domain, .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, --=20 2.43.0 From nobody Sat Sep 26 14:39:01 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 349EE4F6466 for ; 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cd2e9d9fcsm219790525e9.1.2026.08.31.08.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:00 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 10/17] iommu/riscv: Reserve an MSI IOVA window for iommufd Date: Mon, 31 Aug 2026 16:59:36 +0200 Message-ID: <20260831145943.313726-11-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX7UNEbouhCO/m TTumFx8x1rc3yDjXlNM7jmsJgmnaNxfxlg36gmd7zTP8Ulm821LIZglVJ9uH+fUBvw/M6REYyoe 5k+jVP4pWVFwhpXJ5z1sGlvybUfg790= X-Authority-Analysis: v=2.4 cv=CpaPtH4D c=1 sm=1 tr=0 ts=6a9596f2 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=BnA8ekc9z0NdPsKvynsA:9 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX0Yrn/G46CgcS LX+zPZ8S9mH/MYDLsuWzk/xNXd2MjPZ3ntRuGBAajeb99OWU6CD7fpSNo8h6jeXxWCjLVj1Qie1 VvrFH89apEU1DE270h3o3apD0Rkw2+jxjhvmIEyGUfze+gEEz3iq2I6HH1HPfkyPjFHu0VJEz5G qCmmvfo4MhqUwi3vxQmGE9H0NZYXo/s1vk0yJYbDdhJPjAbYqd6vYiHT7eJ9KyzIDh4Ah9Rkpnk VZnQaJOhDyKyZb5q+YxhelysGSaPYgeLK9YfUoqdDLM7ta1/SYH356x+AldM4pdw4e0fxYcBihi iFFWxT45hBKL0dLD+P2diK6p32B2+02rCvcLvOlJC+g58MjzFfCd3ypxl9rGEY4egKE7zJFnJC9 /5o/6rW6YER8CNEB5A+PNbdsd7oNc5QJ04IWG82GMOSKPe1pSt6coaXHaaL2+IxrXa+4jFVAYNd FvqwDbuRpc4386w3h0A== X-Proofpoint-ORIG-GUID: MLxNPRbv45FtXPtz_BoV76jaQdsOAZ8_ X-Proofpoint-GUID: MLxNPRbv45FtXPtz_BoV76jaQdsOAZ8_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" iommufd requires an IOMMU_RESV_SW_MSI region to allocate stable IOVAs for MSI targets. Advertise such a region when the device uses an IMSIC MSI hierarchy so interrupt remapping can map IMSIC pages instead of falling back to physical addresses. Reserve one page per possible CPU, sufficient for each supervisor IMSIC page. Place the window at 128 MiB, matching the established ARM SMMU MSI IOVA convention rather than introducing an architecture-specific choice. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 20 ++++++++++++++++++++ drivers/iommu/riscv/iommu.h | 4 ++++ drivers/irqchip/irq-riscv-imsic-state.c | 22 ++++++++++++++++++++++ include/linux/irqchip/riscv-imsic.h | 6 ++++++ 4 files changed, 52 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index e5818ce44515..7c4a250d61ca 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -20,10 +20,12 @@ #include #include #include +#include #include #include #include =20 +#include "../dma-iommu.h" #include "../iommu-pages.h" #include "iommu-bits.h" #include "iommu.h" @@ -1492,6 +1494,23 @@ static void riscv_iommu_release_device(struct device= *dev) kfree_rcu_mightsleep(info); } =20 +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_h= ead *head) +{ + struct iommu_resv_region *region; + + if (imsic_dev_has_imsic_msi_parent(dev)) { + /* Each hart has one S-mode IMSIC page, a.k.a MSI target page */ + region =3D iommu_alloc_resv_region(RISCV_IOMMU_MSI_IOVA_BASE, + (size_t)num_possible_cpus() * PAGE_SIZE, + IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO, + IOMMU_RESV_SW_MSI, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, head); + } + + iommu_dma_get_resv_regions(dev, head); +} + static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, .capable =3D riscv_iommu_capable, @@ -1502,6 +1521,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, .release_device =3D riscv_iommu_release_device, + .get_resv_regions =3D riscv_iommu_get_resv_regions, }; =20 static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..078ed0ea65bc 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,9 +14,13 @@ #include #include #include +#include =20 #include "iommu-bits.h" =20 +/* IOVA base for the SW MSI reservation; same convention as ARM SMMU. */ +#define RISCV_IOMMU_MSI_IOVA_BASE SZ_128M + struct riscv_iommu_device; =20 struct riscv_iommu_queue { diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index b8d1bbbf42f7..df38a7670a89 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -64,6 +64,28 @@ const struct imsic_global_config *imsic_get_global_confi= g(void) } EXPORT_SYMBOL_GPL(imsic_get_global_config); =20 +/** + * imsic_dev_has_imsic_msi_parent - Check for an IMSIC MSI parent + * @dev: Device to check + * + * Return: true if @dev's MSI domain or any parent domain is the IMSIC base + * domain. + */ +bool imsic_dev_has_imsic_msi_parent(struct device *dev) +{ + struct irq_domain *domain; + + if (!imsic || !imsic->base_domain) + return false; + + for (domain =3D dev_get_msi_domain(dev); domain; domain =3D domain->paren= t) + if (domain =3D=3D imsic->base_domain) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(imsic_dev_has_imsic_msi_parent); + static bool __imsic_eix_read_clear(unsigned long id, bool pend) { unsigned long isel, imask; diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h index 61af3a5bea09..662cb0442424 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -81,6 +81,7 @@ struct imsic_global_config { #ifdef CONFIG_RISCV_IMSIC =20 const struct imsic_global_config *imsic_get_global_config(void); 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b90f78244sm333359565e9.10.2026.08.31.08.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:02 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 11/17] irqchip/riscv-imsic: Add S-mode MSI address list Date: Mon, 31 Aug 2026 16:59:37 +0200 Message-ID: <20260831145943.313726-12-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX2UdO6wEBScJ8 qtU2sEuyfjlH6Qz8c2SMrLveOUgw/ZBLRsXapAiQU4Fe9eI4SS0vOBykE5B0iDFiBTDRXduEX2O QEr2LhSn6quaYKE6flTZOsbR8UU8qd0= X-Proofpoint-GUID: APpIULgBkH-3jvxlH0xwDyFqisrMam5F X-Authority-Analysis: v=2.4 cv=CYE4Irrl c=1 sm=1 tr=0 ts=6a9596f4 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=yikt5F2n8VKCXyCzpw0A:9 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: APpIULgBkH-3jvxlH0xwDyFqisrMam5F X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXxDEFtTwcePaP DcohQiCI6i4mVa+NWx4W4BGKXG9GybLC2ygVLUTAYfIVDuq3C9tPTVKO/kg5iYwkDi40SrBckEp 2H4Qr6AjIyrMx8pTNxuLPcVeczRT2wfNqjyvfrkwz5u+LOk83+sCZ0IlbtRukO5wSSbRMKqo2oU fQVwYcwVsRIZIxD1n9HOKuly7vPg9zWJNZgpMwrsmJYfKSCKSKEmKxn8KTG/B0TfEZoglyubHq2 IXWyXF/dDEU8NcAaNX3Jilm9xnetJBzmikTrBO+1wCP+wrQqpnG8n74AE5uF8h9MJ2Qo8XPZf2b eAwaR80gZWX3cw+CExtT2tnKgAAuTfxydsHXTInikXfkKUWU2yVOQBoIVfsFi1/tz1f8g0mcvLm 5rqp/X0VEReMQXgDfhHbIUYOXaAKzcfPu6jvkoGNLVQjZs2JRScOUTUjrbDziVuX74tYQZgmK5i NhBHZC3l/aBRbRxe8SQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" Upcoming RISC-V IOMMU interrupt remapping needs to map every possible host IMSIC target into one contiguous MSI IOVA range. MSI message composition then uses the target CPU's position within that range. Build an S-mode IMSIC physical address array indexed by logical CPU. Require every possible CPU to have an initialized IMSIC page before publishing the array. This preserves physical address zero as a valid target and guarantees the array has num_possible_cpus() entries. The array size and each target's index can therefore be derived directly, without storing duplicate count or per-CPU index metadata. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/irqchip/irq-riscv-imsic-state.c | 32 +++++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 1 + 2 files changed, 33 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index df38a7670a89..c7ebddd308ec 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -709,6 +709,31 @@ static int __init imsic_get_mmio_resource(struct fwnod= e_handle *fwnode, return of_address_to_resource(to_of_node(fwnode), index, res); } =20 +static int __init imsic_init_smode_msi_pa(void) +{ + struct imsic_global_config *global =3D &imsic->global; + phys_addr_t *smode_msi_pa; + unsigned int cpu; + + smode_msi_pa =3D kcalloc(num_possible_cpus(), sizeof(*smode_msi_pa), GFP_= KERNEL); + if (!smode_msi_pa) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + struct imsic_local_config *local =3D per_cpu_ptr(global->local, cpu); + + if (!local->msi_va) { + kfree(smode_msi_pa); + return -ENODEV; + } + + smode_msi_pa[cpu] =3D local->msi_pa; + } + + imsic->smode_msi_pa =3D smode_msi_pa; + return 0; +} + static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, struct imsic_global_config *global, u32 *nr_parent_irqs, @@ -959,6 +984,12 @@ int __init imsic_setup_state(struct fwnode_handle *fwn= ode, void *opaque) goto out_local_cleanup; } =20 + rc =3D imsic_init_smode_msi_pa(); + if (rc) { + pr_err("%pfwP: failed to initialize S-mode MSI addresses\n", fwnode); + goto out_local_cleanup; + } + /* Initialize matrix allocator */ rc =3D imsic_matrix_init(); if (rc) { @@ -984,6 +1015,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwn= ode, void *opaque) out_free_local: free_percpu(imsic->global.local); out_free_priv: + kfree(imsic->smode_msi_pa); kfree(imsic); imsic =3D NULL; return rc; diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index c42ee180b305..11352f14e32d 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -49,6 +49,7 @@ struct imsic_priv { =20 /* Global configuration common for all HARTs */ struct imsic_global_config global; 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b94dcaf61sm272743545e9.4.2026.08.31.08.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:04 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 12/17] irqchip/riscv-imsic: Support IOMMU MSI address lists Date: Mon, 31 Aug 2026 16:59:38 +0200 Message-ID: <20260831145943.313726-13-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: r8Hp6k9tDeJN0b1nalRrfBIVFyy49NLY X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX8D2wzfVD73HJ JyfFcPJ4Z+tx4/EIpDg6ymRLxe2ntGjkccMWtlbqps5PSKM2v7vZgFBvPAR+XOhQi/S9mdpoQvX fzKZAPisCxtpvZMs0Mwrg6kNN1a9Nc8= X-Proofpoint-ORIG-GUID: r8Hp6k9tDeJN0b1nalRrfBIVFyy49NLY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX4ABlyOrQuvLU yZUBevi1qs1nSNHLcU3RYT4zuM1EhVgadz3SUndN5o0uW3B1Ivm0JzGPnrOVO8bATFXHQ3uC4i3 iKMUYWawwejEf2WCKUWE7gd5iQIFFROjhE9G8dq8IWZfzMTotBmTIDxFu7gdquZOCPedf5Fh9cq XDPU+ar7NUj/em/DS206GeI/eC96+Iic28mzmRopinuMfkBLpH7M7PaigV2BrgZ/uBYxWoBqXRb 2KtBHkD+Ia8h2ZAHTHPeJiLEoQWMLkn21Syj3CK9h77PsAWKy95GIWurd1kdioUVYKyBgWpN/he Ohw3iWubwmInMh/Z5iMpTKVL8kf4oH8WV66L17TwgeTKm1TMCrd1978JVHJNHtJCmNMjlzUNhvh Ed823Gcu0O0cqIDYP/SRQh93uLXMn1IepAtFGkMA2IQxKkmMbyVFMYfL1y7eA1hMcmJrVBAK0eG 4iGbiloGmsWqSZjJtwQ== X-Authority-Analysis: v=2.4 cv=YsY/gYYX c=1 sm=1 tr=0 ts=6a9596f6 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=jAyyop91dzRkNHH0oPsA:9 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" RISC-V IOMMU host interrupt remapping maps every possible host IMSIC target into one contiguous IOVA range. MSI message composition therefore needs each target's position within that range. When the S-mode IMSIC address list is available, prepare the complete list while allocating an IRQ. This allows the IOMMU backend to map the pages and cache the contiguous base IOVA in the MSI descriptor. Skip the optional preparation when no list is available, allowing devices which do not need IOMMU MSI translation to keep using physical MSI messages. When the descriptor has an IOMMU MSI mapping, use the selected logical CPU directly as the page index within the IOVA range. Use the same path for initial composition and affinity updates. Messages remain physical when no IOMMU MSI mapping is required. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-riscv-imsic-platform.c | 25 +++++++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 42f2278a702d..c7cda52b21eb 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -656,6 +656,7 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_MSI_IRQ + select IRQ_MSI_IOMMU select IRQ_MSI_LIB =20 config RISCV_RPMI_SYSMSI diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 643c8e459611..6e26a31f7503 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -69,8 +70,10 @@ static void imsic_irq_ack(struct irq_data *d) irq_move_irq(d); } =20 -static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct = msi_msg *msg) +static void imsic_irq_compose_vector_msg(struct irq_data *d, struct imsic_= vector *vec, + struct msi_msg *msg) { + struct msi_desc *desc =3D irq_data_get_msi_desc(d); phys_addr_t msi_addr; =20 if (WARN_ON(!vec)) @@ -79,6 +82,11 @@ static void imsic_irq_compose_vector_msg(struct imsic_ve= ctor *vec, struct msi_ms if (WARN_ON(!imsic_cpu_page_phys(vec->cpu, 0, &msi_addr))) return; =20 + if (desc->iommu_msi_shift) { + msi_addr =3D (desc->iommu_msi_iova << desc->iommu_msi_shift) + + vec->cpu * IMSIC_MMIO_PAGE_SZ; + } + msg->address_hi =3D upper_32_bits(msi_addr); msg->address_lo =3D lower_32_bits(msi_addr); msg->data =3D vec->local_id; @@ -86,7 +94,7 @@ static void imsic_irq_compose_vector_msg(struct imsic_vec= tor *vec, struct msi_ms =20 static void imsic_irq_compose_msg(struct irq_data *d, struct msi_msg *msg) { - imsic_irq_compose_vector_msg(irq_data_get_irq_chip_data(d), msg); + imsic_irq_compose_vector_msg(d, irq_data_get_irq_chip_data(d), msg); } =20 #ifdef CONFIG_SMP @@ -94,7 +102,7 @@ static void imsic_msi_update_msg(struct irq_data *d, str= uct imsic_vector *vec) { struct msi_msg msg =3D { }; =20 - imsic_irq_compose_vector_msg(vec, &msg); + imsic_irq_compose_vector_msg(d, vec, &msg); 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ccd1e19desm252798825e9.1.2026.08.31.08.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:08 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v5 14/17] vfio: enable IOMMU_TYPE1 for RISC-V Date: Mon, 31 Aug 2026 16:59:40 +0200 Message-ID: <20260831145943.313726-15-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX+OJ5RUDbwFVy VSeirUHrmL+NUTwqok5/+e4FcBqS2uezgL6tlIGO0wGi6fkyB3kLd9GEQTy5ah04uNqvU1ZY/ZK 2+Bd4vCeLsFqRhFy2p/+4qSHyZ+DpHo= X-Proofpoint-GUID: DDZku3CxVgt0RI-ADMDtlDEdQcehNFDs X-Authority-Analysis: v=2.4 cv=CYE4Irrl c=1 sm=1 tr=0 ts=6a9596fa cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=e-vb6wPzIjHU0Swrx_MA:9 a=NFOGd7dJGGMPyQGDc5-O:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-ORIG-GUID: DDZku3CxVgt0RI-ADMDtlDEdQcehNFDs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX+33Q4Jui/MUW WHMGGVn2W0c2BvAK24yIQgPf5rXQciYrNO62uEw1oVLsrPQ+IUothVXUWz5dP/uCUnNM9wbgSvy cM2zFmtxAmIs5s8NFocq/pLTpUuFhlH6H0o9g6igTGHfoLu3ADXQpUGa2P/pYQG40nXvRtcAAtv C9b0vSWvXjOH9ZZPbTCfF8PBmdxEtMjkgwnEZRw2te+HKPte2ubQ3FfJz0XlXOrpUK+WCv2Hz9+ Qxq5Qw20XKqzeH8TL2SPffiqeh17HNQeZMzggkouXXHwjKcfjxzMGwrNvTbfBXr92uzDrFM5dMm R4jzXWyUj9e87XXcRxcLv4XLN9YKcOCU14TLyHEBU6zFdR9+a2mDPxl3hHj5qCWg6tHx0nLCjrm Pa8valj9iZ6WIPPe9VdQsnB9BEuvpnFF/kaFb4v0IJVtMz0EzuTU9BPrvZon5iNvm9i8HTquF8q tz7NVV81TQgIne9j/RQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable VFIO support on RISC-V architecture, now that the RISC-V IOMMU driver reports the IOMMU_CAP_CACHE_COHERENCY capability VFIO_TYPE1 and iommufd both require before allowing a device to be bound. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu Tested-by: Fangyu Yu --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index ceae52fd7586..ad62205b4e45 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -39,7 +39,7 @@ config VFIO_GROUP =20 config VFIO_CONTAINER bool "Support for the VFIO container /dev/vfio/vfio" - select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV) depends on VFIO_GROUP default y help --=20 2.43.0 From nobody Sat Sep 26 14:39:01 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 714DE4FC8D5 for ; Mon, 31 Aug 2026 15:00:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48440e4319bsm1480512f8f.4.2026.08.31.08.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:09 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v5 15/17] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Date: Mon, 31 Aug 2026 16:59:41 +0200 Message-ID: <20260831145943.313726-16-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: Q3lyaWyY5W9JJv898UVYxMSTEoMJwmZi X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX84i1Lo6ynNWg veI+RMlqvOym0RRHGyBICHkzuFqJoylKP4lTug80oaR5HbvnYZkGl2u6uMrxuWbdp5D9q3O3maD 4X962IyXDmuBUrSto8w+S37ZVtS3pdo= X-Proofpoint-ORIG-GUID: Q3lyaWyY5W9JJv898UVYxMSTEoMJwmZi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX24IKbH3dfC0u qO2M1HBb3PGGIm7V4hTO8/AQ8Uk/kK5JQe+NZIV6vZgq9RMy3oV8/n3jBEwet2C1koZI8Ov6+n4 ZsXQJgBIk8J6elcU1qJ2pXRvKamfzf03CEvzh5oQnssvx3ep/u9GuAPMbRksyNJLnTMxE5sC5eC ryMJpeXguM8Ule3OCMMBcOHRHzGhlmws78JkZkUtpOrOZhZmDYllCmbjtqlBMtBvmY9wqFUX0Il ycAE8JlwisT8WvkdC24ODt+KEyCv6c3sKRZsVN1AQB91H3eHrsDqEKpPGJhlIdq4+C82FauJqyt uRfgSY6vwmtofV9te3wwYqZY65S1kvOBEh1z2tySw4NLbmrXohri0DJfNipYPJjaL2JBiMQFzN/ F85lxlCW9TOgsw8aI+PoxNbkfuCWESsWOdg6Y+vfb8sY0kBqtYFHF25JRbbzwExEm++tBp6qpPi 2B1hKmOf8asacByuXTA== X-Authority-Analysis: v=2.4 cv=YsY/gYYX c=1 sm=1 tr=0 ts=6a9596fd cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=Hp3hLBw8nfLOXl02dSwA:9 a=IoWCM6iH3mJn3m4BftBB:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable KVM/VFIO support on RISC-V architecture, now that VFIO device assignment is available on RISC-V through VFIO_IOMMU_TYPE1, so a RISC-V KVM guest can be notified about VFIO-assigned devices. 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Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ed605b5e3162..bae9a0f32f89 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -249,6 +249,10 @@ CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy CONFIG_MMP_PDMA=3Dm +CONFIG_IOMMUFD=3Dm +CONFIG_VFIO_DEVICE_CDEV=3Dy +CONFIG_VFIO=3Dm +CONFIG_VFIO_PCI=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.43.0 From nobody Sat Sep 26 14:39:01 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42FF14FDE59 for ; Mon, 31 Aug 2026 15:00:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cd775dae8sm136267455e9.9.2026.08.31.08.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:13 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 17/17] selftests/vfio: Allow building on RISC-V Date: Mon, 31 Aug 2026 16:59:43 +0200 Message-ID: <20260831145943.313726-18-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: _VNzxVJK0WwYwmSB7zDycCQPuz0sVxWQ X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX2Fs9+pLhMMC7 OqdwG6JGTdEUpl1QzneeOHdQC1HwyzzoktvG97CJe00kX8kp5+axbcy5XWmIxHsbfbrG5qLqW5e BCxiUTF4gX8j6VuoW5kmdcm4bHeEd44= X-Proofpoint-ORIG-GUID: _VNzxVJK0WwYwmSB7zDycCQPuz0sVxWQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX/sqYMhUzA5NM xeAi9+iDcWu61QeQoTXNBjTItDvlxDqOxVTFRLWP0OcDCqo6sv/ymo4XErjw2tgUSaqfJsHO3oH RJ+L7h2PuJvcXWIGugJfE1Vu0Ib9C2waCfNLSOK0RggsnD5hXGDSh/uj3j9GI6fF8Mb49eMIM3P 16pmxLDrZo1oo053kFQ3GM0jwZIaXJh7PV2hPVQ4HD9syFowffvr/Kyct/3Al1JAsD4bEzwzN2Z sK39wB5xEJqyARp6DgJZwNSh631k024SJSIhG++syzZw9eSKlsEU9xrprLBuONPAp2zRGBCsXob cG8pzo2qiHvzrV/n7Dgp+E+olQmBzFMbhNx3UyhcZexpaSbEV+l/Sf8Wy9QYjLp6BHr4MZdq3xG w97DvbP12Yg+OAtXjTasdXKaK0YENqzs9kh2nCaaw2Fj2f8wsD93AQbcKOTCzjCamTRTv5VeV3V 489Bmak5xR37r0cWK9A== X-Authority-Analysis: v=2.4 cv=YsY/gYYX c=1 sm=1 tr=0 ts=6a9596ff cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=hTGq5wxE4AYYcur-NToA:9 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 Content-Type: text/plain; charset="utf-8" The generic VFIO selftests, including iommufd coverage, require no RISC-V-specific source changes. Top-level kselftest builds normalize riscv64 to riscv, while direct builds may use riscv64. Include both names in the architecture filter. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- tools/testing/selftests/vfio/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/vfio/Makefile b/tools/testing/selftest= s/vfio/Makefile index 2c32c48db509..2c7d8ea81b61 100644 --- a/tools/testing/selftests/vfio/Makefile +++ b/tools/testing/selftests/vfio/Makefile @@ -1,6 +1,6 @@ ARCH ?=3D $(shell uname -m) =20 -ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64)) +ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64 riscv riscv64)) # Do nothing on unsupported architectures include ../lib.mk else --=20 2.43.0