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Mon, 31 Aug 2026 14:55:37 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:37 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 01/20] KVM: arm64: Refactor idreg caching into dedicated structure Date: Mon, 31 Aug 2026 16:55:16 +0200 Message-ID: <20260831145536.913567-2-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=EIc2FVZC c=1 sm=1 tr=0 ts=6a9595f1 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=LNVzOGTwHolIvdFCj68A:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX76Rl1Fez0CBI CDVSHnkKXXTV20Rx9x/gSP2iyLYL8mR0bCML80XrmsSleLjEio0yNZCUkecppfTQg6VNjNsmEil qNX2QNhCGxokI3DFB2bROchl01MpwQoPry8ysyfU1G0DUSwswpXh09FP27lymJhmblzWfQXpZ24 YqMODEUwzROHrFETDBIe8ya1WrtYpJCLMAEvYMbva9A+3iOhpgDSXdiD/koT5iuxBpCmp8ZPqmA FcrY13WFRoan9cTKj0RugUji3N8XZtlVL4aWF+kmPmikhBgiTff/XEsYECV0KArG/QEpxAPAa3y THG4li5sLG5ZQzWGddyjDpZLMbh0n9qG0z4wzcZHgu6gj5IPNOHHcOcMBOCVD1/o61Zye+6BPnQ V32qF904xee5Tb0ZHbhXTZjfbm6+wEu9xs7f4uboH2Vg6LuD0fU3OemnUKjb7utBub6KS9kjU5t NGQhoUyRFOHy4HDQgpg== X-Proofpoint-GUID: LaLHm07Mg0oo9fmbHz6s4rnhmqkuMq1v X-Proofpoint-ORIG-GUID: 7doDAoFkK5nGYWMUFtE8aDQa7R2gRfXp X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfXyIev3iT2igoJ IZ+qUhWL8l5bQvrsIFim2nkGhEJSfcN5W/mevPKitr88Mye/wWEwAkeB3dYlUor2B15PlrQHEHA P8GXZvCQ6ILpLI76mu/J++JFgT0hQXs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Move VM-wide ID register emulation fields from struct kvm_arch into a new struct kvm_vm_id_regs to prepare future sharing of these fields and functions using them. Update all users to use the new structure. No functional changes. Co-developed-by: Nina Schoetterl-Glausch Signed-off-by: Nina Schoetterl-Glausch Signed-off-by: Steffen Eiden --- arch/arm64/include/asm/kvm_host.h | 50 ++++++++++++++++-------------- arch/arm64/kvm/config.c | 2 +- arch/arm64/kvm/hyp/nvhe/pkvm.c | 7 +++-- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 4 +-- arch/arm64/kvm/sys_regs.c | 2 +- 5 files changed, 35 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index a8ddce3921b8..f9e90ef9ee4b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -349,6 +349,25 @@ enum fgt_group_id { __NR_FGT_GROUP_IDS__ }; =20 +struct kvm_vm_id_regs { + /* + * Emulated CPU ID registers per VM + * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it + * is (3, 0, 0, crm, op2), where 1<=3Dcrm<8, 0<=3Dop2<8. + * + * These emulated idregs are VM-wide, but accessed from the context of a = vCPU. + * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. + */ +#define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) +#define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) + u64 ftr_reg[KVM_ARM_ID_REG_NUM]; + + u64 midr_el1; + u64 revidr_el1; + u64 aidr_el1; + u64 ctr_el0; +}; + struct kvm_arch { struct kvm_s2_mmu mmu; =20 @@ -408,22 +427,7 @@ struct kvm_arch { struct kvm_smccc_features smccc_feat; struct maple_tree smccc_filter; =20 - /* - * Emulated CPU ID registers per VM - * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it - * is (3, 0, 0, crm, op2), where 1<=3Dcrm<8, 0<=3Dop2<8. - * - * These emulated idregs are VM-wide, but accessed from the context of a = vCPU. - * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. - */ -#define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) -#define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) - u64 id_regs[KVM_ARM_ID_REG_NUM]; - - u64 midr_el1; - u64 revidr_el1; - u64 aidr_el1; - u64 ctr_el0; + struct kvm_vm_id_regs id_regs; =20 /* Masks for VNCR-backed and general EL2 sysregs */ struct kvm_sysreg_masks *sysreg_masks; @@ -1563,19 +1567,19 @@ static inline void kvm_hyp_reserve(void) { } void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); =20 -static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) +static inline u64 *__vm_id_reg(struct kvm_vm_id_regs *id_regs, u32 reg) { switch (reg) { case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): - return &ka->id_regs[IDREG_IDX(reg)]; + return &id_regs->ftr_reg[IDREG_IDX(reg)]; case SYS_CTR_EL0: - return &ka->ctr_el0; + return &id_regs->ctr_el0; case SYS_MIDR_EL1: - return &ka->midr_el1; + return &id_regs->midr_el1; case SYS_REVIDR_EL1: - return &ka->revidr_el1; + return &id_regs->revidr_el1; case SYS_AIDR_EL1: - return &ka->aidr_el1; + return &id_regs->aidr_el1; default: WARN_ON_ONCE(1); return NULL; @@ -1583,7 +1587,7 @@ static inline u64 *__vm_id_reg(struct kvm_arch *ka, u= 32 reg) } =20 #define kvm_read_vm_id_reg(kvm, reg) \ - ({ u64 __val =3D *__vm_id_reg(&(kvm)->arch, reg); __val; }) + ({ u64 __val =3D *__vm_id_reg(&(kvm)->arch.id_regs, reg); __val; }) =20 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); =20 diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index 1053676551af..de56656237f4 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -1410,7 +1410,7 @@ void __init check_feature_map(void) =20 static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_fea= t_map *map) { - u64 regval =3D kvm->arch.id_regs[map->regidx]; + u64 regval =3D kvm->arch.id_regs.ftr_reg[map->regidx]; u64 regfld =3D (regval >> map->shift) & GENMASK(map->width - 1, 0); =20 if (map->sign) { diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 459bd9eb7e4b..bb11561de05e 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -343,7 +343,7 @@ static void pkvm_init_features_from_host(struct pkvm_hy= p_vm *hyp_vm, const struc DECLARE_BITMAP(allowed_features, KVM_VCPU_MAX_FEATURES); =20 /* CTR_EL0 is always under host control, even for protected VMs. */ - hyp_vm->kvm.arch.ctr_el0 =3D host_kvm->arch.ctr_el0; + hyp_vm->kvm.arch.id_regs.ctr_el0 =3D host_kvm->arch.id_regs.ctr_el0; =20 /* Preserve the vgic model so that GICv3 emulation works */ hyp_vm->kvm.arch.vgic.vgic_model =3D host_kvm->arch.vgic.vgic_model; @@ -358,7 +358,7 @@ static void pkvm_init_features_from_host(struct pkvm_hy= p_vm *hyp_vm, const struc KVM_VCPU_MAX_FEATURES); =20 if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &host_arch_flags)) - hyp_vm->kvm.arch.midr_el1 =3D host_kvm->arch.midr_el1; + hyp_vm->kvm.arch.id_regs.midr_el1 =3D host_kvm->arch.id_regs.midr_el1; =20 return; } @@ -492,7 +492,8 @@ static int vm_copy_id_regs(struct pkvm_hyp_vcpu *hyp_vc= pu) if (test_and_set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) return 0; =20 - memcpy(kvm->arch.id_regs, host_kvm->arch.id_regs, sizeof(kvm->arch.id_reg= s)); + memcpy(kvm->arch.id_regs.ftr_reg, host_kvm->arch.id_regs.ftr_reg, + sizeof(kvm->arch.id_regs.ftr_reg)); =20 return 0; } diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/s= ys_regs.c index 8758c6801776..3e70b71d8f4f 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -293,7 +293,7 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, return 0; =20 if (reg >=3D sys_reg(3, 0, 0, 1, 0) && reg <=3D sys_reg(3, 0, 0, 7, 7)) - return kvm->arch.id_regs[IDREG_IDX(reg)]; + return kvm->arch.id_regs.ftr_reg[IDREG_IDX(reg)]; =20 return 0; } @@ -544,7 +544,7 @@ void kvm_init_pvm_id_regs(struct kvm_vcpu *vcpu) * for protected VMs. */ for (r =3D sys_reg(3, 0, 0, 4, 0); r <=3D sys_reg(3, 0, 0, 7, 7); r +=3D = sys_reg(0, 0, 0, 0, 1)) - ka->id_regs[IDREG_IDX(r)] =3D pvm_calc_id_reg(vcpu, r); + ka->id_regs.ftr_reg[IDREG_IDX(r)] =3D pvm_calc_id_reg(vcpu, r); =20 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 44aae52c473d..06dc8ec7a883 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2543,7 +2543,7 @@ static int set_id_reg(struct kvm_vcpu *vcpu, const st= ruct sys_reg_desc *rd, =20 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) { - u64 *p =3D __vm_id_reg(&kvm->arch, reg); + u64 *p =3D __vm_id_reg(&kvm->arch.id_regs, reg); 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Mon, 31 Aug 2026 14:55:37 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:37 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 02/20] KVM: arm64: Extract number of sys_reg_desc into a constant Date: Mon, 31 Aug 2026 16:55:17 +0200 Message-ID: <20260831145536.913567-3-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfXwwsp7QcqGon2 /naIXQfKKua5WSm0UYnBmbYcGAAuBpiKPe+QRx1LH9Jcg1N9u8qsvCGMR54NNL3KpF342u2zdSL TwbRVL28+x1LHBgnPhwXYHEYU2HmwoTEJKlFcebGAYrazJVVZq+/s3mx8LhpnQtVrP9EQBN1hTN CDvk3+I+c0BOfarZkK+as8xMp8khnzd45LY46DaVB83beX+7lTGDWzdWzvz7RuQGvywPqDH6Jmi 1gBoEc4ChP3VBSntlZnor/OUtkiCG9KscZ7SmucZ0KIwswwFCWGVFNqSDJrMtZSKq0pQIGYZ80B cteKX8bgzxZ3I3IyUujaSCLnXvq13lzkhym5hOu4Q5P1ZLLX7bldbMItxmMTi/hmOI6F88IRYqI gbgoxNiaSTJm7EdXiYo485rHJ1QoTCJjQwq1tVArIfzD9lI0jlApsGkrnmwLMSmA7RN6pLaSqqB Rwt5cIwf/oYMJu08ocQ== X-Proofpoint-ORIG-GUID: zGEpnRcRaj9hXPagxpChJ2f52TpXAKp3 X-Authority-Analysis: v=2.4 cv=CNgamxrD c=1 sm=1 tr=0 ts=6a9595f3 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=z2kGeGWSKoQvA0gLZOcA:9 X-Proofpoint-GUID: cHDuoPV_7b1T8YBK4QJkYjJg0tuyxjyH X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX7yvVyKvIySnJ PxXbUipa4CqqC3wqGM/ndkTBFXUZr1yb8LKVQoqF16DpE2FzkwwU+xTX4F0ljI883XQzSsLWrni x4axGiEm8Ya5iM7ySkrRgP9Gfdu8tb0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Define the constant `num_sys_reg_descs` which stores the number of elements in the sys_reg_descs array. Replace all occurrences of ARRAY_SIZE(sys_reg_descs) with the new constant. This refactoring eases the integration of handling system registers for arm on s390. Signed-off-by: Steffen Eiden --- arch/arm64/kvm/sys_regs.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 06dc8ec7a883..7d0047b542f4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3976,6 +3976,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { EL2_REG(SP_EL2, NULL, reset_unknown, 0), }; =20 +static const size_t num_sys_reg_descs =3D ARRAY_SIZE(sys_reg_descs); + static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *= p, const struct sys_reg_desc *r) { @@ -5187,7 +5189,7 @@ static bool emulate_sys_reg(struct kvm_vcpu *vcpu, { const struct sys_reg_desc *r; =20 - r =3D find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); + r =3D find_reg(params, sys_reg_descs, num_sys_reg_descs); if (likely(r)) { perform_access(vcpu, params, r); return true; @@ -5205,7 +5207,7 @@ static const struct sys_reg_desc *idregs_debug_find(s= truct kvm *kvm, loff_t pos) { unsigned long i, idreg_idx =3D 0; =20 - for (i =3D 0; i < ARRAY_SIZE(sys_reg_descs); i++) { + for (i =3D 0; i < num_sys_reg_descs; i++) { const struct sys_reg_desc *r =3D &sys_reg_descs[i]; =20 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) @@ -5268,7 +5270,7 @@ static const struct sys_reg_desc *sr_resx_find(struct= kvm *kvm, loff_t pos) { unsigned long i, sr_idx =3D 0; =20 - for (i =3D 0; i < ARRAY_SIZE(sys_reg_descs); i++) { + for (i =3D 0; i < num_sys_reg_descs; i++) { const struct sys_reg_desc *r =3D &sys_reg_descs[i]; =20 if (r->reg < __SANITISED_REG_START__) @@ -5370,7 +5372,7 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) struct kvm *kvm =3D vcpu->kvm; unsigned long i; =20 - for (i =3D 0; i < ARRAY_SIZE(sys_reg_descs); i++) { + for (i =3D 0; i < num_sys_reg_descs; i++) { const struct sys_reg_desc *r =3D &sys_reg_descs[i]; =20 if (!r->reset) @@ -5594,8 +5596,8 @@ int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) return demux_c15_get(vcpu, reg->id, uaddr); =20 - return kvm_sys_reg_get_user(vcpu, reg, - sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); + return kvm_sys_reg_get_user(vcpu, reg, sys_reg_descs, + num_sys_reg_descs); } =20 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *= reg, @@ -5634,8 +5636,8 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) return demux_c15_set(vcpu, reg->id, uaddr); =20 - return kvm_sys_reg_set_user(vcpu, reg, - sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); + return kvm_sys_reg_set_user(vcpu, reg, sys_reg_descs, + num_sys_reg_descs); } =20 static unsigned int num_demux_regs(void) @@ -5723,7 +5725,7 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 _= _user *uind) int err; =20 i2 =3D sys_reg_descs; - end2 =3D sys_reg_descs + ARRAY_SIZE(sys_reg_descs); + end2 =3D sys_reg_descs + num_sys_reg_descs; =20 while (i2 !=3D end2) { err =3D walk_one_sys_reg(vcpu, i2++, &uind, &total); @@ -5772,7 +5774,7 @@ int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *k= vm, struct reg_mask_range * if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) return -EFAULT; =20 - for (int i =3D 0; i < ARRAY_SIZE(sys_reg_descs); i++) { + for (int i =3D 0; i < num_sys_reg_descs; i++) { const struct sys_reg_desc *reg =3D &sys_reg_descs[i]; u32 encoding =3D reg_to_encoding(reg); u64 val; @@ -5939,7 +5941,7 @@ int __init kvm_sys_reg_table_init(void) int ret =3D 0; =20 /* Make sure tables are unique and in order. */ - valid &=3D check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), t= rue); + valid &=3D check_sysreg_table(sys_reg_descs, num_sys_reg_descs, true); valid &=3D check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), false); valid &=3D check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), fal= se); valid &=3D check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), false); @@ -5958,7 +5960,7 @@ int __init kvm_sys_reg_table_init(void) =20 check_feature_map(); =20 - for (i =3D 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) + for (i =3D 0; !ret && i < num_sys_reg_descs; i++) ret =3D populate_sysreg_config(sys_reg_descs + i, i); =20 for (i =3D 0; !ret && i < ARRAY_SIZE(sys_insn_descs); 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charset="utf-8" Define the missing mask for the OLSK field of OSLSR_EL1 which is required to safely write a value to that field. Signed-off-by: Steffen Eiden --- arch/arm64/include/asm/sysreg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 1c5c4df260be..5a439853b721 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -200,6 +200,7 @@ #define OSLSR_EL1_OSLM_NI 0 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3) #define OSLSR_EL1_OSLK BIT(1) +#define OSLSR_EL1_OSLK_MASK BIT(1) =20 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E40753A380E; Mon, 31 Aug 2026 14:56:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; 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charset="utf-8" Mark more headers as shared or move definitions to an already shared location if the context is similar. Most of them are required to implement system register handling for the host. Signed-off-by: Steffen Eiden --- arch/arm64/include/asm/cache.h | 3 +++ arch/arm64/include/asm/cputype.h | 3 +++ arch/arm64/include/asm/kvm_emulate.h | 5 ++++- arch/arm64/include/asm/kvm_host.h | 18 +++++++++++++----- arch/arm64/include/asm/spectre.h | 7 +++++++ arch/arm64/kvm/sys_regs.h | 1 + 6 files changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 10a7ffadee3d..f9dbc8143dc9 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -8,6 +8,7 @@ #define L1_CACHE_SHIFT (6) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) =20 +#ifdef ARM64_S390_COMMON #define CLIDR_LOUU_SHIFT 27 #define CLIDR_LOC_SHIFT 24 #define CLIDR_LOUIS_SHIFT 21 @@ -25,6 +26,8 @@ /* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n =3D 1 to 7 */ #define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHI= FT) =20 +#endif /* ARM64_S390_COMMON */ + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 1fa29616e586..a5fd2b749b3b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -5,6 +5,7 @@ #ifndef __ASM_CPUTYPE_H #define __ASM_CPUTYPE_H =20 +#ifdef ARM64_S390_COMMON #define INVALID_HWID ULONG_MAX =20 #define MPIDR_UP_BITMASK (0x1 << 30) @@ -259,6 +260,8 @@ #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0)) #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0) =20 +#endif /* ARM64_S390_COMMON */ + #ifndef __ASSEMBLER__ =20 #include diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 09f04a5686a1..6cd9b244d82e 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -23,6 +23,7 @@ #include #include =20 +#ifdef ARM64_S390_COMMON #define CURRENT_EL_SP_EL0_VECTOR 0x0 #define CURRENT_EL_SP_ELx_VECTOR 0x200 #define LOWER_EL_AArch64_VECTOR 0x400 @@ -35,6 +36,8 @@ enum exception_type { except_type_serror =3D 0x180, }; =20 +#endif /* ARM64_S390_COMMON */ + #define kvm_exception_type_names \ { except_type_sync, "SYNC" }, \ { except_type_irq, "IRQ" }, \ @@ -525,13 +528,13 @@ static __always_inline bool kvm_vcpu_abt_issea(const = struct kvm_vcpu *vcpu) } } =20 +#ifdef ARM64_S390_COMMON static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) { u64 esr =3D kvm_vcpu_get_esr(vcpu); return ESR_ELx_SYS64_ISS_RT(esr); } =20 -#ifdef ARM64_S390_COMMON static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) { if (kvm_vcpu_abt_iss1tw(vcpu)) { diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index f9e90ef9ee4b..2ca5fbc39f15 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -349,6 +349,7 @@ enum fgt_group_id { __NR_FGT_GROUP_IDS__ }; =20 +#ifdef ARM64_S390_COMMON struct kvm_vm_id_regs { /* * Emulated CPU ID registers per VM @@ -368,6 +369,8 @@ struct kvm_vm_id_regs { u64 ctr_el0; }; =20 +#endif /* ARM64_S390_COMMON */ + struct kvm_arch { struct kvm_s2_mmu mmu; =20 @@ -1240,9 +1243,6 @@ u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *,= enum vcpu_sysreg, u64); __v; \ }) =20 -u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); -void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); - struct kvm_vm_stat { struct kvm_vm_stat_generic generic; }; @@ -1322,11 +1322,9 @@ int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); -int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); =20 void kvm_sys_regs_create_debugfs(struct kvm *kvm); -void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); =20 int __init kvm_sys_reg_table_init(void); struct sys_reg_desc; @@ -1337,6 +1335,11 @@ int __init populate_nv_trap_config(void); void kvm_calculate_traps(struct kvm_vcpu *vcpu); =20 #ifdef ARM64_S390_COMMON +u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); +void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); +int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); +void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); + unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); @@ -1538,8 +1541,10 @@ struct kvm *kvm_arch_alloc_vm(void); (system_supports_32bit_el0() && \ !static_branch_unlikely(&arm64_mismatched_32bit_el0)) =20 +#ifdef ARM64_S390_COMMON #define kvm_vm_has_ran_once(kvm) \ (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) +#endif /* ARM64_S390_COMMON */ =20 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int featu= re) { @@ -1567,6 +1572,7 @@ static inline void kvm_hyp_reserve(void) { } void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); =20 +#ifdef ARM64_S390_COMMON static inline u64 *__vm_id_reg(struct kvm_vm_id_regs *id_regs, u32 reg) { switch (reg) { @@ -1640,6 +1646,8 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 = val); (kvm_cmp_feat(kvm, id, fld, >=3D, min) && \ kvm_cmp_feat(kvm, id, fld, <=3D, max)) =20 +#endif /* ARM64_S390_COMMON */ + /* Check for a given level of PAuth support */ #define kvm_has_pauth(k, l) \ ({ \ diff --git a/arch/arm64/include/asm/spectre.h b/arch/arm64/include/asm/spec= tre.h index 296ae3420bfd..e1c13797ea7c 100644 --- a/arch/arm64/include/asm/spectre.h +++ b/arch/arm64/include/asm/spectre.h @@ -19,6 +19,7 @@ #include #include =20 +#ifdef ARM64_S390_COMMON /* Watch out, ordering is important here. */ enum mitigation_state { SPECTRE_UNAFFECTED, @@ -26,6 +27,8 @@ enum mitigation_state { SPECTRE_VULNERABLE, }; =20 +#endif /* ARM64_S390_COMMON */ + struct pt_regs; struct task_struct; =20 @@ -81,7 +84,9 @@ static __always_inline void arm64_apply_bp_hardening(void) d->fn(); } =20 +#ifdef ARM64_S390_COMMON enum mitigation_state arm64_get_spectre_v2_state(void); +#endif /* ARM64_S390_COMMON */ bool has_spectre_v2(const struct arm64_cpu_capabilities *cap, int scope); void spectre_v2_enable_mitigation(const struct arm64_cpu_capabilities *__u= nused); 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Mon, 31 Aug 2026 14:55:39 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:39 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 05/20] KVM: s390: arm64: Prepare for sharing more arm64 code Date: Mon, 31 Aug 2026 16:55:20 +0200 Message-ID: <20260831145536.913567-6-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: p-c3AW8SKTUCsy2-biXaILle2jf1XXcI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX+IHiw1y7pzKN xPaKxv4jEGl2mzppZC3e5ty9Q3+z9VKTvAz27Gw/BSCqXl1TNUl9sdTHoG+Buyi/ZP6OW3GZ0gx CjgIYRvyuhKH+0aRvtiRJh2Rss9FK5MQ97gLkdtjR92vTxbOmKkT+ZhwYdHCeS6rkdpGJ8KLyo6 Sij29U7jCqgSTp4riR5k4MjgdZPw5GcIn2LLQaurBZiXMX77yB2EvoMW06BTZRC7OTYeSnB1kEe D8FlG1Po5w6IK/WOj6H1NG0etrQXgxCFMvg1eSpxTFfK8Vnwuo+Nu/TJF2uvWAD2DxN3rbVx3QK 5lvNc8cRt+eJT67Ab+yDj31f6qJgByp2GH+P8MgB108bynLSAiiWZbCLcKKtnp/r1PRyQtM+G3G mWxyByXCaY2qAQuAo4sTQqUKpibsgP216sO+oCBupGv1Az2vvtgW+2HLWvSsUF26GTkmwXUXQiA Z3GmfrPim8ElGjixi0A== X-Authority-Analysis: v=2.4 cv=Osl/DS/t c=1 sm=1 tr=0 ts=6a9595f5 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=2KF_O6z7hVLubVMqFCsA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX9IBZBmYIC5H/ B8s+HPx+6aizBhHf+Lh9OPOY0Ejcsma6HvznaQIPl307xECc+Qn+OvdsODXlLYnE5ilIq/CZI/l ykpeZ3XDrBxifTE5SnQSMEi+0VtJJIM= X-Proofpoint-ORIG-GUID: RheUh-09W2a3-PN2uxRgCigWMwhsZAqQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Add required SVE definitions to the arm64 on s390 host code. The definitions are required to be able to build shared SVE related code. Signed-off-by: Steffen Eiden --- arch/s390/kvm/arm64/guest.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/s390/kvm/arm64/guest.c b/arch/s390/kvm/arm64/guest.c index 4ea6fe2c270d..8b5ee9e79a4f 100644 --- a/arch/s390/kvm/arm64/guest.c +++ b/arch/s390/kvm/arm64/guest.c @@ -5,6 +5,12 @@ #include #include =20 +#define SVE_VQ_MIN __SVE_VQ_MIN +#define SVE_NUM_ZREGS KVM_ARM64_SVE_NUM_ZREGS +#define SVE_NUM_PREGS KVM_ARM64_SVE_NUM_PREGS + +#define vcpu_sve_slices(_vcpu) 1 + #define __INCL_GEN_ARM_FILE #include "generated/guest.inc" #undef __INCL_GEN_ARM_FILE --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5128D4582CC; Mon, 31 Aug 2026 14:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; 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Mon, 31 Aug 2026 14:55:39 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:39 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 06/20] KVM: arm64: Prepare sys_regs.c for sharing with s390 Date: Mon, 31 Aug 2026 16:55:21 +0200 Message-ID: <20260831145536.913567-7-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=PPc/P/qC c=1 sm=1 tr=0 ts=6a9595f5 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=ij1lYihUeJT8dvZHXdMA:9 X-Proofpoint-GUID: l8CeX09BAcs-5KdSLesq6XqQMWOQcj1r X-Proofpoint-ORIG-GUID: 572vbWJLKU_EE3ExR3nIQY2XukXZic_6 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX51eO/bYuMVOJ QhApnQqsz9Uya79UwctrOWx4Ob1nDdJI0PK6KmyX3A6u/ycdM5BhwQPd3XZtiNK7J3w5CgqJ726 GyrIu7nPkfZac6VfDyipXLnhzxgjN6c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX2VMQon3K1S9s 9cHp1gqRzXtiTaeEVdrNgLElUmnPoGddrjZj6HfaoCqZiNaD57r/wyfmKCkmKZYMpYX7jlLG1Av /SWj17tGtBPs4QLlqLb7xsJE6EdG6cHATWkYUA6cHIIqYUALqhyXaMiA2y9R42Aoblo/YjnYTbi AAJw4hlmB9ssHWSvg7SAyzRqXd0FbvJT1+1j1e9WWVcNyRaz8kj9TwuaCW6bFUxelQBmZJIpf8+ hDzbwoGUhDTkkbHami2mZ9JiYa1E5zW/MMTdk3V0GiqPufPwufkd80NdZIhnlWpy/38eDgyBuag JPPfFX5HyYoaBasD7YqLaHgK6FEZZgjAe8g17VluWvA3aIxVN8HnK4lVOS2voTKcB1HTo3GpvE+ 2b30pJedslmbmH6FALpiI/gQzxb4JW/ciWPBMPDCrjKSJIm1QOoPQsJ2yOALA2E8e5sgpm40Roh FBHlDYXcyD6UhE32mBw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Prepare sharing of sys_regs.c with s390 by moving functions to another location inside sys_regs.c. This reduces the number of shared regions. Signed-off-by: Steffen Eiden --- arch/arm64/kvm/sys_regs.c | 100 +++++++++++++++++++------------------- arch/s390/kvm/arm64/arm.c | 2 + 2 files changed, 52 insertions(+), 50 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7d0047b542f4..53d096803d9d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2043,13 +2043,6 @@ static inline bool is_vcpu_ftr_id_reg(u32 id) return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); } =20 -static inline bool is_aa32_id_reg(u32 id) -{ - return (sys_reg_Op0(id) =3D=3D 3 && sys_reg_Op1(id) =3D=3D 0 && - sys_reg_CRn(id) =3D=3D 0 && sys_reg_CRm(id) >=3D 1 && - sys_reg_CRm(id) <=3D 3); -} - static unsigned int id_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -2065,20 +2058,6 @@ static unsigned int id_visibility(const struct kvm_v= cpu *vcpu, return 0; } =20 -static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, - const struct sys_reg_desc *r) -{ - /* - * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any - * EL. Promote to RAZ/WI in order to guarantee consistency between - * systems. - */ - if (!kvm_supports_32bit_el0()) - return REG_RAZ | REG_USER_WI; - - return id_visibility(vcpu, r); -} - static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -2099,6 +2078,27 @@ static bool access_id_reg(struct kvm_vcpu *vcpu, return true; } =20 +static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + /* + * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any + * EL. Promote to RAZ/WI in order to guarantee consistency between + * systems. + */ + if (!kvm_supports_32bit_el0()) + return REG_RAZ | REG_USER_WI; + + return id_visibility(vcpu, r); +} + +static inline bool is_aa32_id_reg(u32 id) +{ + return (sys_reg_Op0(id) =3D=3D 3 && sys_reg_Op1(id) =3D=3D 0 && + sys_reg_CRn(id) =3D=3D 0 && sys_reg_CRm(id) >=3D 1 && + sys_reg_CRm(id) <=3D 3); +} + /* Visibility overrides for SVE-specific control registers */ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) @@ -2553,29 +2553,6 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64= val) *p =3D val; } =20 -static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r= d, - u64 *val) -{ - *val =3D 0; - return 0; -} - -static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, - u64 val) -{ - return 0; -} - -static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, - const struct sys_reg_desc *r) -{ - if (p->is_write) - return write_to_read_only(vcpu, p, r); - - p->regval =3D kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); - return true; -} - static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -2684,6 +2661,29 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, return true; } =20 +static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r= d, + u64 *val) +{ + *val =3D 0; + return 0; +} + +static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + return 0; +} + +static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + return write_to_read_only(vcpu, p, r); + + p->regval =3D kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); + return true; +} + static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -4855,12 +4855,6 @@ static bool check_sysreg_table(const struct sys_reg_= desc *table, unsigned int n, return true; } =20 -int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) -{ - kvm_inject_undefined(vcpu); - return 1; -} - static void perform_access(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *r) @@ -4944,6 +4938,12 @@ static void unhandled_cp_access(struct kvm_vcpu *vcp= u, kvm_inject_undefined(vcpu); } =20 +int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) +{ + kvm_inject_undefined(vcpu); + return 1; +} + /** * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access * @vcpu: The VCPU pointer diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index 3caa72f780a5..2740ee3b703e 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include =20 @@ -25,6 +26,7 @@ #include "trace.h" =20 static unsigned long system_supported_vcpu_features(void); +#define read_sanitised_ftr_reg(_id) 0 =20 #define __INCL_GEN_ARM_FILE #include "generated/arm.inc" --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FD6150AC16; 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Mon, 31 Aug 2026 14:55:40 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:40 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 07/20] KVM: arm64: Share more arm64 code with s390 Date: Mon, 31 Aug 2026 16:55:22 +0200 Message-ID: <20260831145536.913567-8-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=bc1bluPB c=1 sm=1 tr=0 ts=6a9595f7 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=DGrxBuOW4VxBNXMv79cA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfXyuNh26ymLXGF FS5nyANwtHCmN4LtLjhu71kKIraOaYt03kyda9wQXhxupuWwSGDxFHvYZPcNf96OrmknlFEt6ix 0aI84KtRCr/1TE1LTrTGTSV3QWSsUe8= X-Proofpoint-ORIG-GUID: kpBibWaTCGTcfrntdZ795KBzW2Gsz0eo X-Proofpoint-GUID: sBuuWfzlxarD2b9vH300xAnW5O2Nov50 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfXzrLnksKpTNFy zKkfrhZH3h4nDicSYsCl8cGekXfKaqAA+3jc4cui6hk5z0k0NQG2v5nHpwv33I+dphoUxcbWQc1 fJZWDsnicAc7aN2wYZ7UKYF9xpDBDHbHEH6gd0PSBdONVDoCbs1vyRvubt4UU7O5wSdXCopKV4A 8tO8eK41SJ/w1j8aOY3Bo0rYaZolhHQJLmYRij3Vv0VCD/HBAbiasp9tGxL4PhxeAP/OpkcbVzk XHab2lICzwXIP6ss5cLpZuTZMF4v3tMSpX7ncdiTh+ydkUBo/VdQbx79wQt+Fsw8XPIIt16fmcK KDrBXjp06xP8Mn/kjxf7VWGbZHJuVdjrl4gCCUaMua8qwTCCuW32b4Vyz2ubLr6qjr/G0u82xT+ 4ks0p0zyDlJM0PbH4tB1cqgLHw99VGG46HEKKEPU7DjnPNP0ySne0YFCX8LzYPzpuA4NoJQSBRn x/Iwp8pjoijIBJhfDOA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Mark functions that s390 can use to implement arm on s390 as shared functions. Signed-off-by: Steffen Eiden --- arch/arm64/kvm/arm.c | 3 +++ arch/arm64/kvm/guest.c | 11 +++++++---- arch/arm64/kvm/sys_regs.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 6b92a3c1d490..62e8b32ee74e 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -340,6 +340,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm) kvm_arm_teardown_hypercalls(kvm); } =20 +#ifdef ARM64_S390_COMMON static bool kvm_has_full_ptr_auth(void) { bool apa, gpa, api, gpi, apa3, gpa3; @@ -374,6 +375,8 @@ static bool kvm_has_full_ptr_auth(void) (apa + api + apa3) =3D=3D 1); } =20 +#endif /* ARM64_S390_COMMON */ + int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) { int r; diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 6ca5a9f357cd..e978b2fbeb76 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -307,12 +307,12 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const = struct kvm_one_reg *reg) return err; } =20 -#endif /* ARM64_S390_COMMON */ - #define vq_word(vq) (((vq) - SVE_VQ_MIN) / 64) #define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64) #define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq))) =20 +#endif /* ARM64_S390_COMMON */ + static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { unsigned int max_vq, vq; @@ -383,6 +383,7 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) return 0; } =20 +#ifdef ARM64_S390_COMMON #define SVE_REG_SLICE_SHIFT 0 #define SVE_REG_SLICE_BITS 5 #define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS) @@ -399,6 +400,8 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) #define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0)) #define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0)) =20 +#endif /* ARM64_S390_COMMON */ + /* * Number of register slices required to cover each whole SVE register. * NOTE: Only the first slice every exists, for now. @@ -595,8 +598,6 @@ static unsigned long num_core_regs(const struct kvm_vcp= u *vcpu) return copy_core_reg_indices(vcpu, NULL); } =20 -#endif /* ARM64_S390_COMMON */ - static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu) { const unsigned int slices =3D vcpu_sve_slices(vcpu); @@ -658,6 +659,8 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, return num_regs; } =20 +#endif /* ARM64_S390_COMMON */ + /** * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG * @vcpu: the vCPU pointer diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 53d096803d9d..b167f9d06fd4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -45,6 +45,7 @@ * 64bit interface. */ =20 +#ifdef ARM64_S390_COMMON static u64 sys_reg_to_index(const struct sys_reg_desc *reg); static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val); @@ -82,6 +83,8 @@ static bool write_to_read_only(struct kvm_vcpu *vcpu, "sys_reg write to read-only register"); } =20 +#endif /* ARM64_S390_COMMON */ + enum sr_loc_attr { SR_LOC_MEMORY =3D 0, /* Register definitely in memory */ SR_LOC_LOADED =3D BIT(0), /* Register on CPU, unless it cannot */ @@ -428,6 +431,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val,= enum vcpu_sysreg reg) __vcpu_assign_sys_reg(vcpu, reg, val); } =20 +#ifdef ARM64_S390_COMMON /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 =20 @@ -533,6 +537,8 @@ static bool access_rw(struct kvm_vcpu *vcpu, return true; } =20 +#endif /* ARM64_S390_COMMON */ + /* * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualize= d). */ @@ -800,6 +806,7 @@ static bool access_gicv5_ppi_enabler(struct kvm_vcpu *v= cpu, return true; } =20 +#ifdef ARM64_S390_COMMON static bool trap_raz_wi(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -853,6 +860,8 @@ static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, return true; } =20 +#endif /* ARM64_S390_COMMON */ + static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc = *rd, u64 val) { @@ -1011,6 +1020,7 @@ static u64 reset_actlr(struct kvm_vcpu *vcpu, const s= truct sys_reg_desc *r) return actlr; } =20 +#ifdef ARM64_S390_COMMON static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { u64 mpidr =3D kvm_calculate_mpidr(vcpu); @@ -1019,6 +1029,8 @@ static u64 reset_mpidr(struct kvm_vcpu *vcpu, const s= truct sys_reg_desc *r) return mpidr; } =20 +#endif /* ARM64_S390_COMMON */ + static unsigned int hidden_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -1922,6 +1934,7 @@ static u8 pmuver_to_perfmon(u8 pmuver) } } =20 +#ifdef ARM64_S390_COMMON static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val); static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val); @@ -2078,6 +2091,8 @@ static bool access_id_reg(struct kvm_vcpu *vcpu, return true; } =20 +#endif /* ARM64_S390_COMMON */ + static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -2127,6 +2142,7 @@ static unsigned int fp8_visibility(const struct kvm_v= cpu *vcpu, return REG_HIDDEN; } =20 +#ifdef ARM64_S390_COMMON static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) { if (!vcpu_has_sve(vcpu)) @@ -2288,6 +2304,8 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, val); } =20 +#endif /* ARM64_S390_COMMON */ + static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -2332,6 +2350,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, val); } =20 +#ifdef ARM64_S390_COMMON static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 user_val) { @@ -2661,6 +2680,8 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, stru= ct sys_reg_params *p, return true; } =20 +#endif /* ARM64_S390_COMMON */ + static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r= d, u64 *val) { @@ -2764,6 +2785,7 @@ static bool bad_redir_trap(struct kvm_vcpu *vcpu, SYS_REG_USER_FILTER(name, access_arch_timer, reset_val, 0, \ arch_timer_get_user, arch_timer_set_user, vis) =20 +#ifdef ARM64_S390_COMMON /* * Since reset() callback and field val are not used for idregs, they will= be * used for specific purposes for idregs. @@ -2840,6 +2862,8 @@ static bool bad_redir_trap(struct kvm_vcpu *vcpu, .val =3D 0, \ } =20 +#endif /* ARM64_S390_COMMON */ + static bool access_sp_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3212,6 +3236,7 @@ static void init_imp_id_regs(void) boot_cpu_aidr_val =3D read_sysreg(aidr_el1); } =20 +#ifdef ARM64_S390_COMMON static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_de= sc *r) { switch (reg_to_encoding(r)) { @@ -3269,6 +3294,8 @@ static int set_imp_id_reg(struct kvm_vcpu *vcpu, cons= t struct sys_reg_desc *r, .val =3D mask, \ } =20 +#endif /* ARM64_S390_COMMON */ + static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { __vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters); @@ -4833,6 +4860,7 @@ static const struct sys_reg_desc cp15_64_regs[] =3D { { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, }; =20 +#ifdef ARM64_S390_COMMON static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned = int n, bool reset_check) { @@ -4882,6 +4910,8 @@ static void perform_access(struct kvm_vcpu *vcpu, kvm_incr_pc(vcpu); } =20 +#endif /* ARM64_S390_COMMON */ + /* * emulate_cp -- tries to match a sys_reg access in a handling table, and * call the corresponding trap handler. @@ -5340,6 +5370,7 @@ void kvm_sys_regs_create_debugfs(struct kvm *kvm) &sr_resx_fops); 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charset="utf-8" In addition to sharing headers in arch/arm64/include/{asm, uapi/asm} also allow to share headers in arch/arm64/kvm which provide local KVM definitions. Signed-off-by: Steffen Eiden --- arch/s390/tools/Makefile.arm64h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/s390/tools/Makefile.arm64h b/arch/s390/tools/Makefile.arm= 64h index 069473ea335d..49f344636e83 100644 --- a/arch/s390/tools/Makefile.arm64h +++ b/arch/s390/tools/Makefile.arm64h @@ -7,10 +7,11 @@ arm64api :=3D $(objtree)/arch/$(ARCH)/include/generated/a= rm64 arm64uapi :=3D $(objtree)/arch/$(ARCH)/include/generated/uapi/arm64 =20 # List of ARM64 headers to share with s390 KVM -# Format: [uapi:]header.h or header-gen.h +# Format: [uapi:|kvm:]header.h or header-gen.h # # * header.h - from arch/arm64/include/asm/ to arm64/ # * uapi:header.h - from arch/arm64/include/uapi/asm/ to uapi/arm64/ +# * kvm:header.h - from arch/arm64/kvm/ to arm64/ # * header-gen.h - generated as header-gen.h from ARM64 header header.h # If a header contains partial markers (#ifdef ARM64_S390_COMMON) only thi= s part will be copied. # If the file does not contain any markers the whole file will be copied. @@ -37,7 +38,9 @@ arm64-type =3D $(firstword $(subst :, ,$(1))) arm64-base =3D $(or $(word 2,$(subst :, ,$(1))),$(1)) arm64-src-base =3D $(patsubst %-gen.h,%.h,$(call arm64-base,$(1))) =20 -arm64-src =3D $(srctree)/arch/arm64/include/$(if $(filter uapi,$(call arm6= 4-type,$(1))),uapi/)asm/$(call arm64-src-base,$(1)) +arm64-src =3D $(if $(filter kvm,$(call arm64-type,$(1))),\ + $(srctree)/arch/arm64/kvm/$(call arm64-src-base,$(1)),\ + $(srctree)/arch/arm64/include/$(if $(filter uapi,$(call arm64-type,$(1))= ),uapi/)asm/$(call arm64-src-base,$(1))) arm64-dst =3D $(if $(filter uapi,$(call arm64-type,$(1))),$(arm64uapi),$(a= rm64api))/$(call arm64-base,$(1)) =20 $(foreach hdr,$(ARM64_SHARED_HEADERS),\ --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A65350AC1A; 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charset="utf-8" Introduce Extract Arm System Register and Store Arm System Register to enable s390 hosts to read and write system registers for arm64 guests. The new instructions use the new RIE_H instruction format. Add assembler macros to create instructions in RIE_H format manually. Add Support for disassembling the new instructions. Co-developed-by: Andreas Grapentin Signed-off-by: Andreas Grapentin Signed-off-by: Steffen Eiden --- arch/s390/include/asm/sae-asm.h | 48 +++++++++++++++++++++++++++ arch/s390/include/asm/sae.h | 58 +++++++++++++++++++++++++++++++++ arch/s390/kernel/dis.c | 1 + arch/s390/tools/opcodes.txt | 2 ++ 4 files changed, 109 insertions(+) create mode 100644 arch/s390/include/asm/sae-asm.h diff --git a/arch/s390/include/asm/sae-asm.h b/arch/s390/include/asm/sae-as= m.h new file mode 100644 index 000000000000..d81ed89eb4ed --- /dev/null +++ b/arch/s390/include/asm/sae-asm.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_S390_SAE_ASM_H +#define __ASM_S390_SAE_ASM_H + +#ifdef __ASSEMBLER__ + +.macro GPR_NUM opd gr + \opd =3D 255 + .irp rs,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + .ifc \gr,%r\rs + \opd =3D \rs + .endif + .endr + .if \opd =3D=3D 255 + \opd =3D \gr + .endif +.endm + +/* + * RIE_H - RIE-h instruction format + * + * RIE-h format: R1, R3, I2, M4 + * +--------+----+----+----+-----------------+----+--------+ + * | OpCode | R1 |////| R3 | I2 | M4 | Opcode | + * +--------+----+----+----+-----------------+----+--------+ + * 0 8 12 16 20 36 40 47 + */ +.macro RIE_H opc, gr1, gr3, imm2, m4 + GPR_NUM r1, \gr1 + GPR_NUM r3, \gr3 + .byte (\opc & 0xff00) >> 8 + .byte r1 << 4 + .byte (r3 << 4) | ((\imm2 & 0xf000) >> 12) + .byte ((\imm2 & 0x0ff0) >> 4) + .byte ((\imm2 & 0x000f) << 4) | (\m4 & 0xf) + .byte \opc & 0xff +.endm + +.macro SASR r1, r3, i2, m4 + RIE_H 0xed99, \r1, \r3, \i2, \m4, +.endm + +.macro EASR r1, r3, i2, m4 + RIE_H 0xed9b, \r1, \r3, \i2, \m4, +.endm + +#endif /* __ASSEMBLER__ */ +#endif /* __ASM_S390_SAE_ASM_H */ diff --git a/arch/s390/include/asm/sae.h b/arch/s390/include/asm/sae.h index 389c5ac2a36c..6580536544ee 100644 --- a/arch/s390/include/asm/sae.h +++ b/arch/s390/include/asm/sae.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #ifndef __ASSEMBLER__ =20 @@ -13,6 +14,12 @@ asmlinkage void __sae64a(phys_addr_t sae_block_phys); #include #include =20 +asm(".include \"asm/sae-asm.h\"\n"); + +#define _SAE_ASR_REG_SHIFT 5 +#define SASR_FLAG_INITIALIZED 0x8 +#define EASR_FLAG_SA 0x8 + /** * __sae64a() - Start Arm Execution */ @@ -21,6 +28,57 @@ static inline void sae64a(struct kvm_sae_block *sae_bloc= k) __sae64a(virt_to_phys(sae_block)); } =20 +/** + * sasr() - Set Arm System Register + * @arm_reg: ARM system register identifier; compile-time constant + * @val: Value to set + * @save_area: Pointer to SAE save area + * @flags: Operation flags; compile-time constant + * + * Sets an ARM system register value. + */ +static __always_inline void sasr(unsigned int arm_reg, u64 val, + struct kvm_sae_save_area *save_area, + u64 flags) +{ + struct kvm_sae_save_area *sdo =3D (void *)save_area->sdo; + u16 reg =3D arm_reg >> _SAE_ASR_REG_SHIFT; + + asm volatile ( + " SASR %[r1],%[r3],%[i2],%[m4]\n" + : "+m" (*save_area), "+m" (*sdo) + : [r1] "d" (val), + [r3] "a" (save_area), [i2] "K" (reg), [m4] "I" (flags) + ); +} + +/** + * easr() - Extract Arm System Register + * @arm_reg: ARM system register identifier; compile-time constant + * @save_area: Pointer to SAE save area + * @flags: Operation flags; compile-time constant + * + * Reads an ARM system register value. + * + * Return: Register value + */ +static __always_inline u64 easr(unsigned int arm_reg, + const struct kvm_sae_save_area *save_area, + u64 flags) +{ + struct kvm_sae_save_area *sdo =3D (void *)save_area->sdo; + u16 reg =3D arm_reg >> _SAE_ASR_REG_SHIFT; + u64 val; + + asm volatile( + " EASR %[r1],%[r3],%[i2],%[m4]\n" + : [r1] "=3Dd"(val) + : "m"(*save_area), + "m"(*sdo), [r3] "a"(save_area), [i2] "K"(reg), [m4] "I"(flags) + ); + return val; +} + /** * stiasrm() - STore and Invalidate Arm System Register Multiple * @save_area: Pointer to SAE save area diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c index 1cec93895b3a..6ff8fd09d5bc 100644 --- a/arch/s390/kernel/dis.c +++ b/arch/s390/kernel/dis.c @@ -208,6 +208,7 @@ static const unsigned char formats[][6] =3D { [INSTR_RIE_RUI0] =3D { R_8, I16_16, U4_12, 0, 0, 0 }, [INSTR_RIE_RUPI] =3D { R_8, I8_32, U4_12, J16_16, 0, 0 }, [INSTR_RIE_RUPU] =3D { R_8, U8_32, U4_12, J16_16, 0, 0 }, + [INSTR_RIE_R0RIU] =3D { R_8, R_16, U16_20, U4_36, 0, 0 }, [INSTR_RIL_RI] =3D { R_8, I32_16, 0, 0, 0, 0 }, [INSTR_RIL_RP] =3D { R_8, J32_16, 0, 0, 0, 0 }, [INSTR_RIL_RU] =3D { R_8, U32_16, 0, 0, 0, 0 }, diff --git a/arch/s390/tools/opcodes.txt b/arch/s390/tools/opcodes.txt index 0e4773c94af0..18af14071290 100644 --- a/arch/s390/tools/opcodes.txt +++ b/arch/s390/tools/opcodes.txt @@ -1255,6 +1255,8 @@ ed64 ley RXY_FRRD ed65 ldy RXY_FRRD ed66 stey RXY_FRRD ed67 stdy RXY_FRRD +ed99 sasr RIE_R0RIU +ed9b easr RIE_R0RIU eda8 czdt RSL_LRDFU eda9 czxt RSL_LRDFU edaa cdzt RSL_LRDFU --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D5D73A5E87; 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Mon, 31 Aug 2026 14:55:41 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:41 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 10/20] s390: Add functions to query arm guest time Date: Mon, 31 Aug 2026 16:55:25 +0200 Message-ID: <20260831145536.913567-11-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: uMF_uENXEeg89Z0zfvnqJLaVc5nTEbik X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX9MKJCnXGmZWB H1EExZIUXy8xvoO2kxFlBKul8Chgc2sCBVdI0kBqXfaZCz7dHTA2SEaUNNuVwy/MM7JkVRK4PkA NpwCAEe1S/AXCCREjlKmusW30Wnyidd3r3/ZfE+WtKNhVHs9qrWEvcQ4KAhml+aoX7awAYsDdQB zeRd16Qr4CHvRDQhPD50SgzIDSRWVqJetuP3qKosBii2vGsfCXdkSg6hFhD02TkGvqMDHHEFXFY GJaFuJoelNGqJYplkbL91M7lTy7GnhHgyKtFbEviKZwX1srYnyTg2woXAZtXZqJGmkbTg4V4i9N yL0W3sNuEVWZidst5fpCeMcTzda6E12yDs6KhK2/Y2lx9bgwySrGbclBK0Rwc0vsZttNrdQRwps DF5genxnl3Rl5IEMJG6TT9uE9Q2r+AS1mgQEWgoxL0C8WaXm/G4FsM7Oj5D1w3AqxqKRHy8nvfO dgT2gohkKQzVNdtWztA== X-Authority-Analysis: v=2.4 cv=Osl/DS/t c=1 sm=1 tr=0 ts=6a9595f7 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=zcYnEf6ijrO-n6df9P0A:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX7Qsjf5A+Aywh EOCfhDi2pTxmRelUxZKe3a4J8Ifxik7NTtjIePVnz3W21W5hwNhPuNh5a9e69l3bUwpclDCN4BY aePHw+J19lCBd/anmmKetlLh+gkWj/4= X-Proofpoint-ORIG-GUID: DpC-zNWhyRfXAWpYM09Nx0mIOct46RbM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Add functions to convert between ARM guest time (LSB0) and s390 host time (MSB0) using new ptff function codes. Co-developed-by: Nico Boehr Signed-off-by: Nico Boehr Signed-off-by: Steffen Eiden --- arch/s390/include/asm/timex.h | 49 +++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h index 23421b6eb225..e3a2b13022c7 100644 --- a/arch/s390/include/asm/timex.h +++ b/arch/s390/include/asm/timex.h @@ -81,6 +81,8 @@ extern unsigned char ptff_function_mask[16]; #define PTFF_QSI 0x02 /* query steering information */ #define PTFF_QPT 0x03 /* query physical clock */ #define PTFF_QUI 0x04 /* query UTC information */ +#define PTFF_QAGTO 0x10 /* query arm guest time offset */ +#define PTFF_QAGPT 0x11 /* query arm guest physical time offset */ #define PTFF_ATO 0x40 /* adjust tod offset */ #define PTFF_STO 0x41 /* set tod offset */ #define PTFF_SFS 0x42 /* set fine steering rate */ @@ -118,6 +120,17 @@ struct ptff_qui { unsigned int pad_0x5c[41]; } __packed; =20 +/* + * Query Arm Guest Time + * used for: + * - Query Arm Guest Time Offset + * - Query Arm Guest Physical Time + */ +struct ptff_qagt { + u64 in; + u64 out; +}; + /* * ptff - Perform timing facility function * @ptff_block: Pointer to ptff parameter block @@ -266,4 +279,40 @@ static inline int tod_after_eq(unsigned long a, unsign= ed long b) return a >=3D b; } =20 +/* + * ptff_qagto() - Query Arm Guest Time Offset + * + * @physical_time: Arm guest physical time in MSb 0 + * + * Converts Arm guest physical time in MSb 0 bit ordering + * into the Arm guest offset in LSb 0 bit ordering. + * + * Return: Arm guest time offset in LSb 0 + */ +static inline u64 ptff_qagto(u64 physical_time) +{ + struct ptff_qagt qagto =3D { .in =3D physical_time }; + + ptff(&qagto, sizeof(qagto), PTFF_QAGTO); + return qagto.out; +} + +/* + * ptff_qagpt() - Query Arm Guest Physical Time + * + * @guest_time_offset: Arm guest time offset in MSb 0 + * + * Converts Arm guest offset in MSb 0 bit ordering + * into the Arm guest physical time in LSb 0 bit ordering. + * + * Return: Arm guest physical time in LSb 0 + */ +static inline u64 ptff_qagpt(u64 guest_time_offset) +{ + struct ptff_qagt qagpt =3D { .in =3D guest_time_offset }; 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Mon, 31 Aug 2026 14:55:49 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay03.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67VEthH745482444 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Aug 2026 14:55:43 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F090E2004B; Mon, 31 Aug 2026 14:55:42 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7A1BE20043; Mon, 31 Aug 2026 14:55:42 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:42 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 11/20] KVM: s390: arm64: Query Available Arm features Date: Mon, 31 Aug 2026 16:55:26 +0200 Message-ID: <20260831145536.913567-12-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=PPc/P/qC c=1 sm=1 tr=0 ts=6a9595f7 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=CKwS3Y6PJaTERBR545sA:9 X-Proofpoint-GUID: QvUhSyyf-Pnt7Tauu4D_iiR7pFaImIpl X-Proofpoint-ORIG-GUID: eCww6_D9fKaWwm_sknPbdAdH4UT_XIXu X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfXwkSXmNmKXR/A JID1B5RW5qPcWU9wbntDS8GlnRNp5/QmrhWWteLNjymKn8gvsAcRDW86rTM6o3MmmhgdAbQrc5L xP0TNjYJk0nK3x7csROXXeNSWa9gWQc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX6+flEdlCUjbE sdqtxOn3nFslj1VBVK7QAtcNGIe7J+5hvVS9GtcH0ay08ndSXxLw2WyFt8Bhc8O/hf70sUiYXa9 xP4JQmv0JDuGWUVoM7OwAFbC+9FPi5wmQhMiiTv/+TKnWu26brMxcd/6JrsUiJEG6YmblZayW9h pxvh0UuctY8TAWXdhLKPpsTdb38FmDIS6sKUIzfUvAeAK/9DgWSVdCdpPq4A9owvzAgdzvhBq3g O6NUQ34UQXNbUR4sEt++ncs3J/AnB411KTIP1osUI5tLH669SGSoNFpVkvnApG2UOAnLUD8G0/M pTpVZqkBhxVJOuqkFo2U/SqMB0QcUJXLW2sS/cmScqLmZVGcSX0h70rCPj9xL+4iKIms8zoNxmY TzmhnuqK11geLXbjzQ7QNE9pC5srgv3jNNUj7viO8EQQ5Q3neC9ZmBF3q8f7FooDK6oeneC0GdS TXlXY7wBXX8pU6gXWdA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" QAAF enables s390 hosts to gain information about the support and handling of various arm features supported by the machine. Function code 1 provides general information about available formats, machine defined content of system/id register, and other various information for running arm guests. Function code 2 provides a initialised save area. Co-developed-by: Andreas Grapentin Signed-off-by: Andreas Grapentin Signed-off-by: Steffen Eiden --- arch/s390/include/asm/aef.h | 28 +++++ arch/s390/include/asm/kvm_host_arm64_types.h | 111 +++++++++++++++++++ arch/s390/include/asm/sae.h | 25 +++++ arch/s390/kernel/Makefile | 2 +- arch/s390/kernel/aef.c | 101 +++++++++++++++++ arch/s390/kvm/arm64/Makefile | 1 + arch/s390/kvm/arm64/arm.c | 3 +- arch/s390/kvm/arm64/qaaf.c | 69 ++++++++++++ arch/s390/kvm/arm64/qaaf.h | 10 ++ arch/s390/tools/opcodes.txt | 1 + 10 files changed, 349 insertions(+), 2 deletions(-) create mode 100644 arch/s390/include/asm/aef.h create mode 100644 arch/s390/kernel/aef.c create mode 100644 arch/s390/kvm/arm64/qaaf.c create mode 100644 arch/s390/kvm/arm64/qaaf.h diff --git a/arch/s390/include/asm/aef.h b/arch/s390/include/asm/aef.h new file mode 100644 index 000000000000..2f29e3875d4e --- /dev/null +++ b/arch/s390/include/asm/aef.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_S390_AEF_H +#define _ASM_S390_AEF_H + +#include + +/** + * kvm_init_save_area() - Initialize Guest Save Area + * @save_area: Pointer to kvm_sae_save_area structure to initialize + * + * Context: Must be called before using the save area with lasrm/stiasrm i= nstructions. + */ +void kvm_vcpu_init_save_area(struct kvm_sae_save_area *sa); +struct qaaf_qmc_block *aef_qmc(void); + +struct aef_info { + unsigned long arm_guest_supp; + unsigned long sae_avail; + unsigned long ptff_avail; + unsigned long supp_state_desc_formats; + unsigned long supp_save_area_formats; + unsigned long max_num_vcpu; +}; + +const struct aef_info *aef_info(void); + +#endif /* _ASM_S390_AEF_H */ diff --git a/arch/s390/include/asm/kvm_host_arm64_types.h b/arch/s390/inclu= de/asm/kvm_host_arm64_types.h index 2c922ef478d1..93fd649a26f4 100644 --- a/arch/s390/include/asm/kvm_host_arm64_types.h +++ b/arch/s390/include/asm/kvm_host_arm64_types.h @@ -115,4 +115,115 @@ struct kvm_sae_save_area { } __packed __aligned(PAGE_SIZE); static_assert(sizeof(struct kvm_sae_save_area) =3D=3D PAGE_SIZE); =20 +#define QAAF_FC_QMC 1 +#define QAAF_FC_GISRSA 2 + +union qaaf_gr0_gisrsa { + struct { + u8 _0000[6]; + u8 saf; + u8 : 2; + u8 fc : 6; + }; + u64 val; +}; + +static_assert(sizeof(union qaaf_gr0_gisrsa) =3D=3D sizeof(u64)); + +/* QAAF Query Model Capabilities */ +struct qaaf_qmc_block { + u64 _0000; /* 0x0000 */ + u8 ssdf; /* 0x0008 */ + u8 _0009; /* 0x0009 */ + u8 ssaf; /* 0x000a */ + u8 _000b[3]; /* 0x000b */ + u16 maxncpu; /* 0x000e */ + u64 regs[0x1fe]; /* 0x0010 */ +} __aligned(PAGE_SIZE); +static_assert(sizeof(struct qaaf_qmc_block) =3D=3D PAGE_SIZE); + +union qaaf_block { + struct qaaf_qmc_block qmc; + struct kvm_sae_save_area save_area; +} __aligned(PAGE_SIZE); +static_assert(sizeof(union qaaf_block) =3D=3D PAGE_SIZE); + +/* + * Keep in sync with mapping from SYS_* to QAAF_* in feature.c! + */ +enum { + QAAF_REG_MIDR_EL1 =3D 0x02, + /* 0x03 -0x06 reserved */ + QAAF_REG_MPIDR_EL1 =3D 0x07, + QAAF_REG_REVIDR_EL1 =3D 0x08, + /* 0x09 reserved */ + QAAF_REG_ID_PFR0_EL1 =3D 0x0a, + QAAF_REG_ID_PFR1_EL1 =3D 0x0b, + QAAF_REG_ID_DFR0_EL1 =3D 0x0c, + QAAF_REG_ID_AFR0_EL1 =3D 0x0d, + QAAF_REG_ID_MMFR0_EL1 =3D 0x0e, + QAAF_REG_ID_MMFR1_EL1 =3D 0x0f, + QAAF_REG_ID_MMFR2_EL1 =3D 0x10, + QAAF_REG_ID_MMFR3_EL1 =3D 0x11, + QAAF_REG_ID_ISAR0_EL1 =3D 0x12, + QAAF_REG_ID_ISAR1_EL1 =3D 0x13, + QAAF_REG_ID_ISAR2_EL1 =3D 0x14, + QAAF_REG_ID_ISAR3_EL1 =3D 0x15, + QAAF_REG_ID_ISAR4_EL1 =3D 0x16, + QAAF_REG_ID_ISAR5_EL1 =3D 0x17, + QAAF_REG_ID_MMFR4_EL1 =3D 0x18, + QAAF_REG_ID_ISAR6_EL1 =3D 0x19, + QAAF_REG_MVFR0_EL1 =3D 0x1a, + QAAF_REG_MVFR1_EL1 =3D 0x1b, + QAAF_REG_MVFR2_EL1 =3D 0x1c, + /* 0x1d reserved */ + QAAF_REG_ID_PFR2_EL1 =3D 0x1e, + QAAF_REG_ID_DFR1_EL1 =3D 0x1f, + QAAF_REG_ID_MMFR5_EL1 =3D 0x20, + /* 0x21 reserved */ + QAAF_REG_ID_AA64PFR0_EL1 =3D 0x22, + QAAF_REG_ID_AA64PFR1_EL1 =3D 0x23, + QAAF_REG_ID_AA64PFR2_EL1 =3D 0x24, + /* 0x25 reserved */ + QAAF_REG_ID_AA64ZFR0_EL1 =3D 0x26, + QAAF_REG_ID_AA64SMFR0_EL1 =3D 0x27, + /* 0x28 reserved */ + QAAF_REG_ID_AA64FPFR0_EL1 =3D 0x29, + QAAF_REG_ID_AA64DFR0_EL1 =3D 0x2a, + QAAF_REG_ID_AA64DFR1_EL1 =3D 0x2b, + QAAF_REG_ID_AA64DFR2_EL1 =3D 0x2c, + /* 0x2d reserved */ + QAAF_REG_ID_AA64AFR0_EL1 =3D 0x2e, + QAAF_REG_ID_AA64AFR1_EL1 =3D 0x2f, + /* 0x30,0x31 reserved */ + QAAF_REG_ID_AA64ISAR0_EL1 =3D 0x32, + QAAF_REG_ID_AA64ISAR1_EL1 =3D 0x33, + QAAF_REG_ID_AA64ISAR2_EL1 =3D 0x34, + QAAF_REG_ID_AA64ISAR3_EL1 =3D 0x35, + /* 0x36-0x39 reserved */ + QAAF_REG_ID_AA64MMFR0_EL1 =3D 0x3a, + QAAF_REG_ID_AA64MMFR1_EL1 =3D 0x3b, + QAAF_REG_ID_AA64MMFR2_EL1 =3D 0x3c, + QAAF_REG_ID_AA64MMFR3_EL1 =3D 0x3d, + QAAF_REG_ID_AA64MMFR4_EL1 =3D 0x3e, + /* 0x3f-0x41 reserved */ + QAAF_REG_CNTFRQ_EL0 =3D 0x42, + QAAF_REG_CTR_EL0 =3D 0x43, + QAAF_REG_AIDR_EL1 =3D 0x44, + /* 0x43-0x49 reserved */ + QAAF_IRPTC =3D 0x4a, + /* 0x4b reserved */ + QAAF_REG_ICH_VTR_EL2 =3D 0x4c, + QAAF_GIC_ATTR =3D 0x4d, + /* 0x4E-0x51 reserved */ + QAAF_REG_PMMIR_EL1 =3D 0x52, + QAAF_REG_PMCR_EL0 =3D 0x53, + QAAF_REG_PMCEID0_EL0 =3D 0x54, + QAAF_REG_PMCEID1_EL0 =3D 0x55, + /* 0x56-0x1ff reserved */ + _QAAF_MAX +}; + +static_assert(sizeof(struct qaaf_qmc_block) / 8 + 1 >=3D _QAAF_MAX); + #endif /* ASM_KVM_HOST_ARM64_TYPES_H */ diff --git a/arch/s390/include/asm/sae.h b/arch/s390/include/asm/sae.h index 6580536544ee..f88d15b8f1e9 100644 --- a/arch/s390/include/asm/sae.h +++ b/arch/s390/include/asm/sae.h @@ -111,5 +111,30 @@ static __always_inline void lasrm(struct kvm_sae_save_= area *save_area) ); } =20 +/** + * qaaf() - Query Available Arm Features + * @gr0: QAAF function code, placed in greg 0 + * @qaaf_block: Pointer to the page for the output + * + * Perform QAAF. The result ins written to qaaf_block. + */ +static __always_inline int qaaf(u64 gr0, union qaaf_block *qaaf_block) +{ + int exception =3D 1; + + asm volatile( + " lgr 0,%[r0]\n" + " .insn rre,0xb9ad0000,%[r1],0\n" + "0: lhi %[exc],0\n" + "1:\n" + EX_TABLE(0b, 1b) + : "=3Dm"(*qaaf_block), [exc] "+d"(exception) + : [r1] "a"(qaaf_block), [r0] "d"(gr0) + : "r0" + ); + + return exception; +} + #endif /* !__ASSEMBLER__ */ #endif /* __ASM_S390_SAE_H */ diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile index f84b8fb41331..0f3b9fcd1885 100644 --- a/arch/s390/kernel/Makefile +++ b/arch/s390/kernel/Makefile @@ -46,7 +46,7 @@ obj-y +=3D runtime_instr.o cache.o fpu.o dumpstack.o guar= ded_storage.o sthyi.o obj-y +=3D entry.o reipl.o kdebugfs.o alternative.o skey.o obj-y +=3D nospec-branch.o ipl_vmparm.o machine_kexec_reloc.o unwind_bc.o obj-y +=3D smp.o text_amode31.o stacktrace.o abs_lowcore.o facility.o uv.o= wti.o -obj-y +=3D diag/ +obj-y +=3D diag/ aef.o =20 always-$(KBUILD_BUILTIN) +=3D vmlinux.lds =20 diff --git a/arch/s390/kernel/aef.c b/arch/s390/kernel/aef.c new file mode 100644 index 000000000000..825e2643a892 --- /dev/null +++ b/arch/s390/kernel/aef.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "linux/export.h" +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static struct qaaf_qmc_block qmc =3D {}; +static struct kvm_sae_save_area save_area =3D {}; +static struct aef_info info =3D {}; + +/** + * kvm_init_save_area() - Initialize Guest Save Area + * @save_area: Pointer to kvm_sae_save_area structure to initialize + * + * Context: Must be called before using the save area with lasrm/stiasrm i= nstructions. + */ +void kvm_vcpu_init_save_area(struct kvm_sae_save_area *sa) +{ + memcpy(sa, &save_area, sizeof(save_area)); +} +EXPORT_SYMBOL(kvm_vcpu_init_save_area); + +struct qaaf_qmc_block *aef_qmc(void) +{ + return &qmc; +} +EXPORT_SYMBOL(aef_qmc); + +const struct aef_info *aef_info(void) +{ + return &info; +} +EXPORT_SYMBOL(aef_info); + +static int __init aef_init_save_area(void) +{ + int ret; + + union qaaf_gr0_gisrsa gr0 =3D { + .fc =3D QAAF_FC_GISRSA, + .saf =3D SAE_SAVE_AREA_FORMAT_0, + }; + + ret =3D qaaf(gr0.val, (union qaaf_block *)&save_area); + if (ret) + return ret; + + return 0; +} + +static int __init aef_query_info(void) +{ + int ret; + + if (IS_ENABLED(CONFIG_KVM_S390_ARM64)) { + info.sae_avail =3D sclp.has_aef; + info.ptff_avail =3D ptff_query(PTFF_QAGTO) && + ptff_query(PTFF_QAGPT); + info.arm_guest_supp =3D info.sae_avail && info.ptff_avail; + } + if (!info.sae_avail) + return 0; + + ret =3D qaaf(QAAF_FC_QMC, (union qaaf_block *)&qmc); + if (ret) + return ret; + + info.supp_state_desc_formats =3D qmc.ssdf; + info.supp_save_area_formats =3D qmc.ssaf; + info.max_num_vcpu =3D qmc.maxncpu; + + return 0; +} + +static int __init aef_sysfs_init(void) +{ + int rc =3D -ENOMEM; + + if (!IS_ENABLED(CONFIG_KVM_S390_ARM64)) + return 0; + + rc =3D aef_query_info(); + if (rc) + return rc; + + rc =3D aef_init_save_area(); + if (rc) + return rc; + + return 0; +} + +arch_initcall(aef_sysfs_init); diff --git a/arch/s390/kvm/arm64/Makefile b/arch/s390/kvm/arm64/Makefile index ae614a62f7b5..577b0653a68e 100644 --- a/arch/s390/kvm/arm64/Makefile +++ b/arch/s390/kvm/arm64/Makefile @@ -14,6 +14,7 @@ kvm-arm64-obj :=3D \ inject_fault.o \ mmio.o \ mmu.o \ + qaaf.o \ reset.o \ =20 kvm-arm64-obj +=3D $(patsubst %.o,%-arm64.o,$(kvm-y)) diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index 2740ee3b703e..664fea5cf6b5 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -12,6 +12,7 @@ #include =20 #include +#include =20 #include #include @@ -744,7 +745,7 @@ long kvm_arch_vcpu_unlocked_ioctl(struct file *filp, un= signed int ioctl, =20 static int __init kvm_s390_arm64_init(void) { - if (!sclp.has_aef) + if (!aef_info()->arm_guest_supp) return -ENXIO; =20 return kvm_init_with_dev(sizeof(struct kvm_vcpu), 0, THIS_MODULE, diff --git a/arch/s390/kvm/arm64/qaaf.c b/arch/s390/kvm/arm64/qaaf.c new file mode 100644 index 000000000000..c3124d38afc2 --- /dev/null +++ b/arch/s390/kvm/arm64/qaaf.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include "qaaf.h" + +#define _qaaf_reg_case(id) case SYS_##id: return aef_qmc()->regs[QAAF_REG_= ##id] + +u64 kvm_qaaf_read_ftr_reg(u32 id) +{ + switch (id) { + _qaaf_reg_case(MIDR_EL1); + _qaaf_reg_case(MPIDR_EL1); + _qaaf_reg_case(REVIDR_EL1); + _qaaf_reg_case(ID_PFR0_EL1); + _qaaf_reg_case(ID_PFR1_EL1); + _qaaf_reg_case(ID_DFR0_EL1); + _qaaf_reg_case(ID_AFR0_EL1); + _qaaf_reg_case(ID_MMFR0_EL1); + _qaaf_reg_case(ID_MMFR1_EL1); + _qaaf_reg_case(ID_MMFR2_EL1); + _qaaf_reg_case(ID_MMFR3_EL1); + _qaaf_reg_case(ID_ISAR0_EL1); + _qaaf_reg_case(ID_ISAR1_EL1); + _qaaf_reg_case(ID_ISAR2_EL1); + _qaaf_reg_case(ID_ISAR3_EL1); + _qaaf_reg_case(ID_ISAR4_EL1); + _qaaf_reg_case(ID_ISAR5_EL1); + _qaaf_reg_case(ID_MMFR4_EL1); + _qaaf_reg_case(ID_ISAR6_EL1); + _qaaf_reg_case(MVFR0_EL1); + _qaaf_reg_case(MVFR1_EL1); + _qaaf_reg_case(MVFR2_EL1); + _qaaf_reg_case(ID_PFR2_EL1); + _qaaf_reg_case(ID_DFR1_EL1); + _qaaf_reg_case(ID_MMFR5_EL1); + _qaaf_reg_case(ID_AA64PFR0_EL1); + _qaaf_reg_case(ID_AA64PFR1_EL1); + _qaaf_reg_case(ID_AA64PFR2_EL1); + _qaaf_reg_case(ID_AA64ZFR0_EL1); + _qaaf_reg_case(ID_AA64SMFR0_EL1); + _qaaf_reg_case(ID_AA64FPFR0_EL1); + _qaaf_reg_case(ID_AA64DFR0_EL1); + _qaaf_reg_case(ID_AA64DFR1_EL1); + _qaaf_reg_case(ID_AA64DFR2_EL1); + _qaaf_reg_case(ID_AA64AFR0_EL1); + _qaaf_reg_case(ID_AA64AFR1_EL1); + _qaaf_reg_case(ID_AA64ISAR0_EL1); + _qaaf_reg_case(ID_AA64ISAR1_EL1); + _qaaf_reg_case(ID_AA64ISAR2_EL1); + _qaaf_reg_case(ID_AA64ISAR3_EL1); + _qaaf_reg_case(ID_AA64MMFR0_EL1); + _qaaf_reg_case(ID_AA64MMFR1_EL1); + _qaaf_reg_case(ID_AA64MMFR2_EL1); + _qaaf_reg_case(ID_AA64MMFR3_EL1); + _qaaf_reg_case(ID_AA64MMFR4_EL1); + _qaaf_reg_case(CNTFRQ_EL0); + _qaaf_reg_case(CTR_EL0); + _qaaf_reg_case(AIDR_EL1); + _qaaf_reg_case(ICH_VTR_EL2); + _qaaf_reg_case(PMMIR_EL1); + _qaaf_reg_case(PMCR_EL0); + _qaaf_reg_case(PMCEID0_EL0); + _qaaf_reg_case(PMCEID1_EL0); + default: + WARN(true, "Unknown feature register 0x%x\n", id); + return 0xbad1234bad; + } +} diff --git a/arch/s390/kvm/arm64/qaaf.h b/arch/s390/kvm/arm64/qaaf.h new file mode 100644 index 000000000000..8fed7f795ce0 --- /dev/null +++ b/arch/s390/kvm/arm64/qaaf.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef ARCH_S390_KVM_ARM64_QAAF_H +#define ARCH_S390_KVM_ARM64_QAAF_H + +#include + +u64 kvm_qaaf_read_ftr_reg(u32 id); + +#endif diff --git a/arch/s390/tools/opcodes.txt b/arch/s390/tools/opcodes.txt index 18af14071290..fd5483107961 100644 --- a/arch/s390/tools/opcodes.txt +++ b/arch/s390/tools/opcodes.txt @@ -600,6 +600,7 @@ b9a7 stiasrm RRE_R0 b9aa lptea RRF_RURR2 b9ab essa RRF_U0RR b9ac irbm RRE_RR +b9ad qaaf RRE_R0 b9ae rrbm RRE_RR b9af pfmf RRE_RR b9b0 cu14 RRF_U0RR --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40A8A3D9DC5; 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Mon, 31 Aug 2026 14:55:43 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:42 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 12/20] KVM: s390: arm64: Implement feature sanitisation Date: Mon, 31 Aug 2026 16:55:27 +0200 Message-ID: <20260831145536.913567-13-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX2fxiJD+YMfAd cIi4Y4MZvmwVB1fSgpaxKbT3elHw4fnLMBSSNiqKat3K9eAYrvVT9UGyPyoe2Ibb7tA8dQzkqlo yAhpmYOo3clQ3SgYcFAsXGelSzzGW8d8NyvFKjI9/yWZqytutxKfLpbKGUw4RGqEuArMcBwkGwn Fydzhk/8Hh4R3lvdvP5YvK9SUFmk7eBzoaPDTG4K8JKrk9x5UCLHNQn6/ZDZRIX048yFpClNMyb C1ZWhvw5yX6cVdYY80ESn4FGpDHUzVUrYehRCtNYnM3CSyrV2b3bwtg6s8kTs47awlaFvQucD33 a/APP1W42MnrtY3AF/eEg4nAVDNpoO9VhnB2Q/A2boeaubD3EFUf6X/62SvaqjACALK3pYzvk8O s+sFMiTSf7pFIpRhH7rlkdtHOfRoBVu4Vpq4job8ffqrSHhY6ciJd2MkCYWiJEt98OkW0FtesSk 0IcKIwuzF0VfCkSaDnQ== X-Proofpoint-ORIG-GUID: W7qZTtvfIUsNiJj6DzQ9e6r_1z2MYBQW X-Authority-Analysis: v=2.4 cv=CNgamxrD c=1 sm=1 tr=0 ts=6a9595f7 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=GB6mbaFeBmmjm_s_m-AA:9 X-Proofpoint-GUID: N-08JLcRBowA8b1Lj3VmYCboL8uf6WPv X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX3JASSlDvIMUz W2avplZII+FQLqGNZR2TBAVRINB7Mcxmo3Osa2Hq5xKMKxpdmtDj+Pyf5aa+PVB4TxA59pb/Vw3 uThxBjOZOaVRMmdAiPYZrlzzCuuBr7c= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Implement feature detection and sanitization for arm64 KVM guests on s390. Query hardware capabilities using QAAF instruction and sanitize arm64 ID registers. Provide accessor functions for queried capabilities and integrate feature detection into module initialization sequence. Signed-off-by: Steffen Eiden --- arch/s390/include/asm/kvm_host_arm64.h | 13 ++ arch/s390/kvm/arm64/Makefile | 1 + arch/s390/kvm/arm64/arm.c | 5 +- arch/s390/kvm/arm64/feature.c | 165 +++++++++++++++++++++++++ arch/s390/kvm/arm64/feature.h | 87 +++++++++++++ arch/s390/kvm/arm64/qaaf.c | 7 +- arch/s390/kvm/arm64/qaaf.h | 1 + 7 files changed, 277 insertions(+), 2 deletions(-) create mode 100644 arch/s390/kvm/arm64/feature.c create mode 100644 arch/s390/kvm/arm64/feature.h diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm= /kvm_host_arm64.h index b8a689c649bd..22e4bf788fa2 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -14,6 +14,19 @@ =20 #include =20 +enum { + ARM64_HAS_WFXT, + ARM64_HAS_RASV1P1_EXTN, + ARM64_HAS_STAGE2_FWB, + ARM64_HAS_RAS_EXTN, + ARM64_HAS_EVT, + ARM64_HAS_HCR_NV1, + ARM64_MISMATCHED_CACHE_TYPE, + ARM64_HAS_ECV_CNTPOFF, +}; + +bool cpus_have_final_cap(unsigned int num); + #define KVM_HAVE_MMU_RWLOCK #define KVM_MAX_VCPUS 1 #define KVM_S390_ARM64_IMPL_FEATURES \ diff --git a/arch/s390/kvm/arm64/Makefile b/arch/s390/kvm/arm64/Makefile index 577b0653a68e..8c7110956573 100644 --- a/arch/s390/kvm/arm64/Makefile +++ b/arch/s390/kvm/arm64/Makefile @@ -9,6 +9,7 @@ ccflags-y +=3D -I $(src) -I $(objtree)/$(obj) -I$(srctree)/= arch/s390/kvm/gmap -DKV =20 kvm-arm64-obj :=3D \ arm.o \ + feature.o \ guest.o \ handle_exit.o \ inject_fault.o \ diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index 664fea5cf6b5..c573a3da5766 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -22,12 +22,13 @@ =20 #include "arm.h" #include "handle_exit.h" +#include "qaaf.h" +#include "feature.h" =20 #define CREATE_TRACE_POINTS #include "trace.h" =20 static unsigned long system_supported_vcpu_features(void); -#define read_sanitised_ftr_reg(_id) 0 =20 #define __INCL_GEN_ARM_FILE #include "generated/arm.inc" @@ -748,6 +749,8 @@ static int __init kvm_s390_arm64_init(void) if (!aef_info()->arm_guest_supp) return -ENXIO; =20 + kvm_init_qaaf(); + return kvm_init_with_dev(sizeof(struct kvm_vcpu), 0, THIS_MODULE, KVM_DEV_NAME, MISC_DYNAMIC_MINOR); } diff --git a/arch/s390/kvm/arm64/feature.c b/arch/s390/kvm/arm64/feature.c new file mode 100644 index 000000000000..39c8ae7e951c --- /dev/null +++ b/arch/s390/kvm/arm64/feature.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include + +#include + +#include "feature.h" + +#define MASK_RESERVED(_qaafp, _id) \ + ({ \ + u64 *_reg =3D &((_qaafp)->regs[QAAF_REG_##_id]); \ + *_reg =3D (*_reg & ~_id##_RES0) | _id##_RES1; \ + }) + +#define QAAF_FIELD_MODIFY(_idp, _id_field, _val) \ + FIELD_MODIFY(_id_field##_MASK, _idp, _id_field##_##_val) + +#define MODIFY(_qaafp, _id, _field, _val) \ + QAAF_FIELD_MODIFY(&((_qaafp)->regs[QAAF_REG_##_id]), _id##_##_field, _val) + +int __init kvm_arm_host_sanitize_features(struct qaaf_qmc_block *qaaf_qmc) +{ + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR0_EL1); + + MODIFY(qaaf_qmc, ID_AA64ISAR1_EL1, LS64, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR1_EL1); + + MODIFY(qaaf_qmc, ID_AA64ISAR2_EL1, SYSINSTR_128, NI); + MODIFY(qaaf_qmc, ID_AA64ISAR2_EL1, SYSREG_128, NI); + MODIFY(qaaf_qmc, ID_AA64ISAR2_EL1, PAC_frac, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR2_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR3_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR2_EL1); + + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, Spec_FPACC, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, ADERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, SDERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, ANERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, SNERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, MEC, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR3_EL1); + + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, SRMASK, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, E3DSE, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, RMEGDI, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, FGWTE3, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, ASID2, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR4_EL1); + + MODIFY(qaaf_qmc, ID_AA64PFR0_EL1, SEL2, NI); + MODIFY(qaaf_qmc, ID_AA64PFR0_EL1, SVE, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64PFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64PFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64PFR2_EL1); + + MODIFY(qaaf_qmc, ID_AA64DFR0_EL1, PMUVer, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64DFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64DFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64DFR2_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64AFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64AFR1_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64ZFR0_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64SMFR0_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64FPFR0_EL1); + + MASK_RESERVED(qaaf_qmc, ID_PFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_PFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_PFR2_EL1); + + MASK_RESERVED(qaaf_qmc, ID_DFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_DFR1_EL1); + + MASK_RESERVED(qaaf_qmc, ID_MMFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR2_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR3_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR4_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR5_EL1); + + MASK_RESERVED(qaaf_qmc, ID_ISAR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR2_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR3_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR4_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR5_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR6_EL1); + + MASK_RESERVED(qaaf_qmc, MVFR0_EL1); + MASK_RESERVED(qaaf_qmc, MVFR1_EL1); + MASK_RESERVED(qaaf_qmc, MVFR2_EL1); + + MASK_RESERVED(qaaf_qmc, CTR_EL0); + + MASK_RESERVED(qaaf_qmc, ICH_VTR_EL2); + + return 0; +} + +/** + * cpus_have_final_cap - Check if an ARM64 CPU capability is supported + * @num: Capability number to check + * + * Maps ARM64 CPU capabilities to their corresponding ID register fields + * and checks if the feature is supported by the s390 hardware via QAAF. + * + * Return: true if capability is supported, false otherwise + */ +bool cpus_have_final_cap(unsigned int num) +{ + u64 reg_val; + + switch (num) { + case ARM64_HAS_STAGE2_FWB: + reg_val =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + return SYS_FIELD_GET(ID_AA64MMFR2_EL1, FWB, reg_val) >=3D + ID_AA64MMFR2_EL1_FWB_IMP; + + case ARM64_HAS_WFXT: + reg_val =3D read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); + return SYS_FIELD_GET(ID_AA64ISAR2_EL1, WFxT, reg_val) >=3D + ID_AA64ISAR2_EL1_WFxT_IMP; + + case ARM64_HAS_RASV1P1_EXTN: + reg_val =3D read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); + return SYS_FIELD_GET(ID_AA64PFR1_EL1, RAS_frac, reg_val) =3D=3D + ID_AA64PFR1_EL1_RAS_frac_RASv1p1; + + case ARM64_HAS_HCR_NV1: + reg_val =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + return SYS_FIELD_GET(ID_AA64MMFR2_EL1, NV, reg_val) >=3D + ID_AA64MMFR2_EL1_NV_IMP; + + case ARM64_HAS_RAS_EXTN: + reg_val =3D read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + return SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, reg_val) >=3D + ID_AA64PFR0_EL1_RAS_IMP; + + case ARM64_HAS_EVT: + reg_val =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + return SYS_FIELD_GET(ID_AA64MMFR2_EL1, EVT, reg_val) >=3D + ID_AA64MMFR2_EL1_EVT_IMP; + + case ARM64_HAS_ECV_CNTPOFF: + reg_val =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + return SYS_FIELD_GET(ID_AA64MMFR1_EL1, PAN, reg_val) >=3D + ID_AA64MMFR1_EL1_PAN_IMP; + + case ARM64_MISMATCHED_CACHE_TYPE: + return false; + default: + return false; + } +} diff --git a/arch/s390/kvm/arm64/feature.h b/arch/s390/kvm/arm64/feature.h new file mode 100644 index 000000000000..9c902df1f26c --- /dev/null +++ b/arch/s390/kvm/arm64/feature.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef ARCH_S390_KVM_FEATURE_H +#define ARCH_S390_KVM_FEATURE_H + +#include +#include + +#include + +#include "qaaf.h" + +int __init kvm_arm_host_sanitize_features(struct qaaf_qmc_block *qaaf_qmc); + +/** + * read_sanitised_ftr_reg() - Get the value of a sys register + * + * @id - ARM sysreg id + * + * Get the value of a sys register describing the host configuration. + * The returned value indicates support by the machine (HW/FW) + * after some sanitisation. + * See `enum qaaf_regs` for supported registers. + * + * Example: + * read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1) + * + * Return: Sanitised HW value of the specified register + */ +static inline u64 read_sanitised_ftr_reg(u32 id) +{ + return kvm_qaaf_read_ftr_reg(id); +} + +/** + * kvm_sae_supported_sd_formats() - Retrieve supported SAE SD formats + * + * Return: Bitmap of supported SAE state description formats. + */ +static inline u32 kvm_sae_supported_sd_formats(void) +{ + extern struct qaaf_qmc_block __qaaf_qmp; + + return __qaaf_qmp.ssdf; +} + +/** + * kvm_sae_supported_sa_formats() - Retrieve supported SAE SA formats + * + * Return: Bitmap of supported SAE save area formats. + */ +static inline u32 kvm_sae_supported_sa_formats(void) +{ + extern struct qaaf_qmc_block __qaaf_qmp; + + return __qaaf_qmp.ssaf; +} + +/** + * kvm_sae_max_vcpus() - Retrieve maximum supported vcpus + * + * Return: Max number of vCPUs supported by the SAE instruction/the machine + * as indicated by QAAF, not necessarily that supported by the host softwa= re. + */ +static inline u16 kvm_sae_max_vcpus(void) +{ + extern struct qaaf_qmc_block __qaaf_qmp; + + /* QAAF QMP reports the max id not the max num */ + return __qaaf_qmp.maxncpu + 1; +} + +/** + * kvm_sae_irptc() - Retrieve supported SAE IRPTCs + * + * Return: Bitmap of supported SAE IRPTCs. + */ +static inline u64 kvm_sae_irptc(void) +{ + extern struct qaaf_qmc_block __qaaf_qmp; + + return __qaaf_qmp.regs[QAAF_IRPTC]; +} + +#define kvm_vcpu_has_pmu(_v) false + +#endif /* ARCH_S390_KVM_FEATURE_H */ diff --git a/arch/s390/kvm/arm64/qaaf.c b/arch/s390/kvm/arm64/qaaf.c index c3124d38afc2..228e9cdcd684 100644 --- a/arch/s390/kvm/arm64/qaaf.c +++ b/arch/s390/kvm/arm64/qaaf.c @@ -3,9 +3,14 @@ #include #include #include "qaaf.h" +#include "feature.h" =20 -#define _qaaf_reg_case(id) case SYS_##id: return aef_qmc()->regs[QAAF_REG_= ##id] +void __init kvm_init_qaaf(void) +{ + kvm_arm_host_sanitize_features(aef_qmc()); +} =20 +#define _qaaf_reg_case(id) case SYS_##id: return aef_qmc()->regs[QAAF_REG_= ##id] u64 kvm_qaaf_read_ftr_reg(u32 id) { switch (id) { diff --git a/arch/s390/kvm/arm64/qaaf.h b/arch/s390/kvm/arm64/qaaf.h index 8fed7f795ce0..87042f81e882 100644 --- a/arch/s390/kvm/arm64/qaaf.h +++ b/arch/s390/kvm/arm64/qaaf.h @@ -5,6 +5,7 @@ =20 #include =20 +__init void kvm_init_qaaf(void); u64 kvm_qaaf_read_ftr_reg(u32 id); =20 #endif --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E46AD50C2AB; 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Mon, 31 Aug 2026 14:55:43 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:43 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 13/20] KVM: s390: arm64: Implement arm sysreg managing infrastructure Date: Mon, 31 Aug 2026 16:55:28 +0200 Message-ID: <20260831145536.913567-14-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX374NYoJRWtFg 9OhOH0e90yEIRipcGVxVES4LEGIj837wOz5tONQ0jqmHm45YWvNp4EIdGuzHXAevKxKyjwQD2TX zEdLIPcHnLlhjxdrv9u7lw408lGpMoS2byHuM/PFLeaIlg+GzQx/l9D4pGv8hUTGMLHzb++qwDG D0GmpqDnCQXzJGUqhIm/QnV9BDU5d8A1mn/t/GQ2G43XsmekgEs3f8ugHH65MODSETy/YNK4wvE pQ4Ol3HcB0JZNEbnzvaRSAAcCM5gC7hwRVWaMYYqDyEMvb6y84tdndnW3itlReJX1ps5Vshr76J U4M2KAFsJiqyWSa4io/PuJxgsD32OYEg2FDrKkb5+2DyQDYjwF5Whune0PPXV168V9+dRK/HGTu rEEQfET5hMuaYlt9d3Ijm+GNLcvN1veMAAnxH7JFn4yaDXMDFduKtmbm2INgECeDe+vbScewjoR Ol0ha9liWuh6H96Irpg== X-Proofpoint-ORIG-GUID: VJ3tCxbC5ReJsT1TS3f9AOrpgocX8Dac X-Authority-Analysis: v=2.4 cv=CNgamxrD c=1 sm=1 tr=0 ts=6a9595fb cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=oZHtAar1Vk6HErUEWy4A:9 X-Proofpoint-GUID: 8eV9Kk5R85-Va2KLyLtZ83p3ieZt7K-Q X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX4kXuQrc6wMM5 yqL1mPdiNFiQ2PnkheIXkskDhqLqUogENEtEIlMZPGebyeqAU+hd2cM5oOakag82v+EreLr+NBU f6dvr9WH+Rywtprrdpp8ackNvq2930A= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Implement the infrastructures for the s390 host to read and write the arm64 guest system register. The host can access and modify (non-id) system registers through the new instructions EASR/SASR or their multiple variant. Guest accesses to ID registers are trapped and handled by KVM. KVM gets the data form the result of QAAF and sanitizes it using the shared infrastructure with arm64. Signed-off-by: Steffen Eiden --- arch/s390/include/arm64/kvm_hyp.h | 18 + arch/s390/include/arm64/kvm_nested.h | 5 + arch/s390/include/arm64/sys_regs.h | 9 + arch/s390/include/asm/kvm_host_arm64.h | 204 ++++++- arch/s390/kvm/arm64/Makefile | 2 + arch/s390/kvm/arm64/Makefile.gen | 1 + arch/s390/kvm/arm64/spectre.c | 14 + arch/s390/kvm/arm64/sys_regs.c | 750 +++++++++++++++++++++++++ arch/s390/kvm/arm64/trace.h | 51 ++ arch/s390/tools/Makefile.arm64h | 4 + 10 files changed, 1057 insertions(+), 1 deletion(-) create mode 100644 arch/s390/include/arm64/kvm_hyp.h create mode 100644 arch/s390/include/arm64/sys_regs.h create mode 100644 arch/s390/kvm/arm64/spectre.c create mode 100644 arch/s390/kvm/arm64/sys_regs.c diff --git a/arch/s390/include/arm64/kvm_hyp.h b/arch/s390/include/arm64/kv= m_hyp.h new file mode 100644 index 000000000000..e425b7c3c80d --- /dev/null +++ b/arch/s390/include/arm64/kvm_hyp.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __S390_ARM64_KVM_HYP_H__ +#define __S390_ARM64_KVM_HYP_H__ + +#include + +static __always_inline bool has_vhe(void) +{ + return true; +} + +static __always_inline bool is_protected_kvm_enabled(void) +{ + return false; +} + +#endif /* __S390_ARM64_KVM_HYP_H__ */ diff --git a/arch/s390/include/arm64/kvm_nested.h b/arch/s390/include/arm64= /kvm_nested.h index e950b1a10c41..9c02ac5c62cc 100644 --- a/arch/s390/include/arm64/kvm_nested.h +++ b/arch/s390/include/arm64/kvm_nested.h @@ -8,4 +8,9 @@ static inline bool vcpu_has_nv(const struct kvm_vcpu *vcpu) return false; } =20 +static inline u64 limit_nv_id_reg(struct kvm *kvm, u32 id, u64 val) +{ + return val; +} + #endif /* ASM_KVM_NESTED_H */ diff --git a/arch/s390/include/arm64/sys_regs.h b/arch/s390/include/arm64/s= ys_regs.h new file mode 100644 index 000000000000..dafb090ee1af --- /dev/null +++ b/arch/s390/include/arm64/sys_regs.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __S390_ARM64_SYS_REGS_H__ +#define __S390_ARM64_SYS_REGS_H__ + +#include +#include + +#endif /* __S390_ARM64_SYS_REGS_H__ */ diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm= /kvm_host_arm64.h index 22e4bf788fa2..65e5e0c48b07 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -3,11 +3,13 @@ #define ASM_KVM_HOST_ARM64_H =20 #include +#include =20 #include #include =20 #define vcpu_gp_regs(v) ((v)->arch.sae_block.gpr) +enum vcpu_sysreg; =20 #include #include @@ -40,7 +42,12 @@ bool cpus_have_final_cap(unsigned int num); #define KVM_IRQCHIP_NUM_PINS 1 #define irqchip_in_kernel(_k) false =20 -#define __ctxt_sys_reg(ctx, reg) NULL +#define __ctxt_sys_reg(ctx, reg) \ + ({ \ + BUILD_BUG_ON(!__builtin_constant_p(reg)); \ + ___ctxt_sys_reg(ctx, reg); \ + }) + struct kvm_cpu_context { /* * These are just for 32 bit, which we don't have, making them RES0. @@ -52,6 +59,10 @@ struct kvm_cpu_context { u64 spsr_fiq; =20 __vector128 __aligned(16) vregs[32]; + + /* shadowed sysregs to comply with arm64 infrastructure */ + u64 elr_el1; + u64 spsr_el1; }; =20 struct kvm_vcpu_arch { @@ -59,10 +70,19 @@ struct kvm_vcpu_arch { struct kvm_sae_save_area save_area; struct kvm_cpu_context ctxt; =20 + /* Guest system registers not part of save area or ID registers */ + u64 sys_reg_clidr_el1; + u64 sys_reg_csselr_el1; + /* Per-vcpu CCSIDR override or NULL */ + u32 *ccsidr; + u32 host_acrs[NUM_ACRS]; =20 /* Hypervisor Configuration Register */ u64 hcr_elz; + u64 hcrx_elz; + + u64 mpidr; =20 /* Configuration flags, set once and for all before the vcpu can run */ u8 cflags; @@ -133,6 +153,9 @@ struct kvm_arch { DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); =20 unsigned long mem_limit; + + /* Per-VM ID register storage */ + struct kvm_vm_id_regs id_regs; }; =20 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int featu= re) @@ -221,4 +244,183 @@ static inline void kvm_arch_async_page_present_queued= (struct kvm_vcpu *vcpu) =20 #define kvm_supports_32bit_el0() false =20 +#define __vcpu_sys_reg(__vcpu, __reg) \ + vcpu_read_sys_reg(__vcpu, __reg) + +#define __vcpu_assign_sys_reg(__vcpu, __reg, __val) \ + vcpu_write_sys_reg(__vcpu, __val, __reg) + +#define __vcpu_rmw_sys_reg(C, V, OP, R) \ +({ \ + u64 __val =3D vcpu_read_sys_reg(C, R); \ + __val OP V; \ + vcpu_write_sys_reg(C, __val, R); \ +}) + +/** + * _vcpu_read_sys_reg() - read a guest sysreg with easr + * - R - sysreg id; must be readable by easr; must be compile time constant + * + * if SYSREGS_ON_CPU: proceed with flags =3D 0 + * otherwise: proceed with either + * read: flags =3D EASR_FLAG_SA + * write: flags =3D SASR_FLAG_INITIALIZED + * + */ +#define _vcpu_read_sys_reg(C, R) \ + ({ BUILD_BUG_ON(!__builtin_constant_p((R))); \ + BUG_ON(vcpu_is_loaded(C) && smp_processor_id() !=3D (C)->cpu); \ + (vcpu_is_loaded(C)) \ + ? __vcpu_read_sr((C), (R), 0) \ + : __vcpu_read_sr((C), (R), EASR_FLAG_SA); }) + +/** + * _vcpu_write_sys_reg() - write a guest sysreg with sasr + * - R - sysreg id; must be readable by sasr; must be compile time constant + + * if SYSREGS_ON_CPU: proceed with flags =3D 0 + * otherwise: proceed with either + * read: flags =3D EASR_FLAG_SA + * write: flags =3D SASR_FLAG_INITIALIZED + */ +#define _vcpu_write_sys_reg(C, V, R) \ + ({ BUILD_BUG_ON(!__builtin_constant_p((R))); \ + BUG_ON(vcpu_is_loaded(C) && smp_processor_id() !=3D (C)->cpu); \ + (vcpu_is_loaded(C)) \ + ? __vcpu_write_sr((C), (V), (R), 0) \ + : __vcpu_write_sr((C), (V), (R), SASR_FLAG_INITIALIZED); }) + +/* Forward to easr / sasr + * assert that F and R are constant + */ +#define __vcpu_read_sr(C, R, F) \ + ({ BUILD_BUG_ON(!__builtin_constant_p((R))); \ + BUILD_BUG_ON(!__builtin_constant_p((F))); \ + easr((R), &(C)->arch.save_area, (F)); }) + +#define __vcpu_write_sr(C, V, R, F) \ + ({ BUILD_BUG_ON(!__builtin_constant_p((R))); \ + BUILD_BUG_ON(!__builtin_constant_p((F))); \ + sasr((R), (V), &(C)->arch.save_area, (F)); }) + +#define SR_GROUP(NAME, ...) \ + __##NAME##_BEGIN__, \ + __VA_ARGS__ \ + __##NAME##_END__ + +/** enum vcpu_sysreg - available guest sysregs + * + * Contains all arm64 guest-syregs supported by s390. + */ +enum vcpu_sysreg { + __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ + + /* EL 0,1 Register from state description in order of appearance */ + SR_GROUP(STATE_DESC, + CNTP_CTL_EL0, + CNTV_CTL_EL0, + CONTEXTIDR_EL1, + SP_EL1, + ), + + /* EL 0,1 Register requiring special handling. */ + SR_GROUP(SPECIAL, + CSSELR_EL1, + CLIDR_EL1, + MPIDR_EL1, + ELR_EL1, + SPSR_EL1, + ), + + /* EL 0,1 register from save area in order of appearance */ + SR_GROUP(SAVE_AREA, + ACTLR_EL1, + AFSR0_EL1, + AFSR1_EL1, + CNTFRQ_EL0, + CNTP_CVAL_EL0, + CNTV_CVAL_EL0, + DISR_EL1, + MIDR_EL1, + OSLSR_EL1, + PAR_EL1, + OSLAR_EL1, + SCTLR_EL1, + CPACR_EL1, + VBAR_EL1, + ESR_EL1, + TCR_EL1, + MAIR_EL1, + TTBR0_EL1, + TTBR1_EL1, + FAR_EL1, + TPIDR_EL0, + TPIDR_EL1, + TPIDRRO_EL0, + CNTKCTL_EL1, + ZCR_EL1, + SCXTNUM_EL0, + SCXTNUM_EL1, + APIBKEYLO_EL1, + APIBKEYHI_EL1, + APIAKEYLO_EL1, + APIAKEYHI_EL1, + APGAKEYLO_EL1, + APGAKEYHI_EL1, + APDBKEYLO_EL1, + APDBKEYHI_EL1, + APDAKEYLO_EL1, + APDAKEYHI_EL1, + MDSCR_EL1, + ), + + NR_SYS_REGS /* Nothing after this line! */ +}; + +static __always_inline u64 *___ctxt_sys_reg(struct kvm_cpu_context *ctxt, + const enum vcpu_sysreg reg) +{ + switch (reg) { + case ELR_EL1: + return &ctxt->elr_el1; + case SPSR_EL1: + return &ctxt->spsr_el1; + default: + BUG(); + break; + } +} + +void vcpu_write_host_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); +u64 vcpu_read_host_sys_reg(const struct kvm_vcpu *vcpu, int reg); + +#define kvm_debug_handle_oslar(_v, _val) /* debug not implemented yet*/ + +static inline u8 kvm_arm_pmu_get_pmuver_limit(void) +{ + return 0; +} + +int __init kvm_sys_reg_table_init(void); + +static inline bool system_supports_poe(void) +{ + return false; +} + +static inline bool vgic_host_has_gicv3(void) +{ + return false; +} + +static inline bool vgic_host_has_gicv5(void) +{ + return false; +} + +static inline bool has_broken_cntvoff(void) +{ + return false; +} + #endif /* ASM_KVM_HOST_ARM64_H */ diff --git a/arch/s390/kvm/arm64/Makefile b/arch/s390/kvm/arm64/Makefile index 8c7110956573..e19040cdc27d 100644 --- a/arch/s390/kvm/arm64/Makefile +++ b/arch/s390/kvm/arm64/Makefile @@ -17,6 +17,8 @@ kvm-arm64-obj :=3D \ mmu.o \ qaaf.o \ reset.o \ + spectre.o \ + sys_regs.o \ =20 kvm-arm64-obj +=3D $(patsubst %.o,%-arm64.o,$(kvm-y)) kvm-arm64-obj +=3D $(patsubst %.o,%-arm64.o,$(gmap-y)) diff --git a/arch/s390/kvm/arm64/Makefile.gen b/arch/s390/kvm/arm64/Makefil= e.gen index 6ac7602b57cb..99298dc49dcc 100644 --- a/arch/s390/kvm/arm64/Makefile.gen +++ b/arch/s390/kvm/arm64/Makefile.gen @@ -8,6 +8,7 @@ ARM64_CFILES :=3D \ arm.c \ guest.c \ handle_exit.c \ + sys_regs.c \ mmio.c \ =20 quiet_cmd_extract_inc =3D GEN $@ diff --git a/arch/s390/kvm/arm64/spectre.c b/arch/s390/kvm/arm64/spectre.c new file mode 100644 index 000000000000..dfe5b4be54d6 --- /dev/null +++ b/arch/s390/kvm/arm64/spectre.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +enum mitigation_state arm64_get_spectre_v2_state(void) +{ + return SPECTRE_UNAFFECTED; +} + +enum mitigation_state arm64_get_meltdown_state(void) +{ + return SPECTRE_UNAFFECTED; +} + diff --git a/arch/s390/kvm/arm64/sys_regs.c b/arch/s390/kvm/arm64/sys_regs.c new file mode 100644 index 000000000000..44ed8a203e93 --- /dev/null +++ b/arch/s390/kvm/arm64/sys_regs.c @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "feature.h" + +#include "trace.h" + +static int arm64_check_features(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd, u64 val); +static const struct sys_reg_desc sys_reg_descs[]; +static const size_t num_sys_reg_descs; +static u64 __ro_after_init boot_cpu_midr_val; +static u64 __ro_after_init boot_cpu_revidr_val; +static u64 __ro_after_init boot_cpu_aidr_val; + +#define __INCL_GEN_ARM_FILE +#include "generated/sys_regs.inc" +#undef __INCL_GEN_ARM_FILE + +#define SR_INVALID 0x8badf00d8badf00d + +enum sr_loc_attr { + SR_LOC_SAVE_AREA, /* Register on SA, loaded (on cpu) */ + SR_LOC_SPECIAL, /* Register in state description or Special care registe= r*/ + SR_LOC_INVALID, /* Register is unknown */ +}; + +struct sr_loc { + enum sr_loc_attr loc; +}; + +#define SREG_RANGE(NAME) __##NAME##_BEGIN__ + 1 ... __##NAME##_END__ - 1 +static __always_inline void locate_register(const struct kvm_vcpu *vcpu, + enum vcpu_sysreg reg, + struct sr_loc *loc) +{ + switch (reg) { + case SREG_RANGE(STATE_DESC): + case SREG_RANGE(SPECIAL): + loc->loc =3D SR_LOC_SPECIAL; + break; + case SREG_RANGE(SAVE_AREA): + loc->loc =3D SR_LOC_SAVE_AREA; + break; + default: + WARN(true, "%s wants to read invalid register %x", __func__, reg); + loc->loc =3D SR_LOC_INVALID; + } +} + +static __always_inline u64 read_special_sr(const struct kvm_vcpu *vcpu, + enum vcpu_sysreg reg) +{ + switch (reg) { + case CLIDR_EL1: return vcpu->arch.sys_reg_clidr_el1; + case CSSELR_EL1: return vcpu->arch.sys_reg_csselr_el1; + case MPIDR_EL1: return vcpu->arch.mpidr; + case ELR_EL1: return vcpu->arch.ctxt.elr_el1; + case SPSR_EL1: return vcpu->arch.ctxt.spsr_el1; + case CNTP_CTL_EL0: return vcpu->arch.sae_block.cntp_ctl; + case CNTV_CTL_EL0: return vcpu->arch.sae_block.cntv_ctl; + case CONTEXTIDR_EL1: return vcpu->arch.sae_block.contextidr_el1; + case SP_EL1: return vcpu->arch.sae_block.sp_el1; + default: + WARN(true, "%s wants to read non-special register %x", __func__, reg); + return SR_INVALID; + } +} + +static __always_inline u64 read_sr_from_vcpu(const struct kvm_vcpu *vcpu, + enum vcpu_sysreg reg) +{ + switch (reg) { + case ACTLR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_ACTLR_EL1); + case AFSR0_EL1: return _vcpu_read_sys_reg(vcpu, SYS_AFSR0_EL1); + case AFSR1_EL1: return _vcpu_read_sys_reg(vcpu, SYS_AFSR1_EL1); + case CNTFRQ_EL0: return _vcpu_read_sys_reg(vcpu, SYS_CNTFRQ_EL0); + case CNTP_CVAL_EL0: return _vcpu_read_sys_reg(vcpu, SYS_CNTP_CVAL_EL0); + case CNTV_CVAL_EL0: return _vcpu_read_sys_reg(vcpu, SYS_CNTV_CVAL_EL0); + case DISR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_DISR_EL1); + case MIDR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_MIDR_EL1); + case OSLSR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_OSLSR_EL1); + case PAR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_PAR_EL1); + case SCTLR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_SCTLR_EL1); + case CPACR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_CPACR_EL1); + case VBAR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_VBAR_EL1); + case ESR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_ESR_EL1); + case TCR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_TCR_EL1); + case MAIR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_MAIR_EL1); + case TTBR0_EL1: return _vcpu_read_sys_reg(vcpu, SYS_TTBR0_EL1); + case TTBR1_EL1: return _vcpu_read_sys_reg(vcpu, SYS_TTBR1_EL1); + case FAR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_FAR_EL1); + case TPIDR_EL0: return _vcpu_read_sys_reg(vcpu, SYS_TPIDR_EL0); + case TPIDR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_TPIDR_EL1); + case TPIDRRO_EL0: return _vcpu_read_sys_reg(vcpu, SYS_TPIDRRO_EL0); + case CNTKCTL_EL1: return _vcpu_read_sys_reg(vcpu, SYS_CNTKCTL_EL1); + case ZCR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_ZCR_EL1); + case SCXTNUM_EL0: return _vcpu_read_sys_reg(vcpu, SYS_SCXTNUM_EL0); + case SCXTNUM_EL1: return _vcpu_read_sys_reg(vcpu, SYS_SCXTNUM_EL1); + case APIBKEYLO_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APIBKEYLO_EL1); + case APIBKEYHI_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APIBKEYHI_EL1); + case APIAKEYLO_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APIAKEYLO_EL1); + case APIAKEYHI_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APIAKEYHI_EL1); + case APGAKEYLO_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APGAKEYLO_EL1); + case APGAKEYHI_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APGAKEYHI_EL1); + case APDBKEYLO_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APDBKEYLO_EL1); + case APDBKEYHI_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APDBKEYHI_EL1); + case APDAKEYLO_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APDAKEYLO_EL1); + case APDAKEYHI_EL1: return _vcpu_read_sys_reg(vcpu, SYS_APDAKEYHI_EL1); + case MDSCR_EL1: return _vcpu_read_sys_reg(vcpu, SYS_MDSCR_EL1); + default: + WARN(true, "%s: failed to resolve %x", __func__, reg); + return SR_INVALID; + } +} + +u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg) +{ + struct sr_loc loc =3D {}; + + locate_register(vcpu, reg, &loc); + + if (unlikely(loc.loc =3D=3D SR_LOC_INVALID)) { + WARN(true, "%s: failed to locate %u", __func__, reg); + return SR_INVALID; + } + + if (loc.loc =3D=3D SR_LOC_SPECIAL) + return read_special_sr(vcpu, reg); + + return read_sr_from_vcpu(vcpu, reg); +} + +static __always_inline void write_special_sr(struct kvm_vcpu *vcpu, u64 va= l, + enum vcpu_sysreg reg) +{ + switch (reg) { + case CLIDR_EL1: vcpu->arch.sys_reg_clidr_el1 =3D val; break; + case CSSELR_EL1: vcpu->arch.sys_reg_csselr_el1 =3D val; break; + case MPIDR_EL1: vcpu->arch.mpidr =3D val; break; + case CNTP_CTL_EL0: vcpu->arch.sae_block.cntp_ctl =3D val; break; + case CNTV_CTL_EL0: vcpu->arch.sae_block.cntv_ctl =3D val; break; + case CONTEXTIDR_EL1: vcpu->arch.sae_block.contextidr_el1 =3D val; break; + case SP_EL1: vcpu->arch.sae_block.sp_el1 =3D val; break; + case ELR_EL1: vcpu->arch.ctxt.elr_el1 =3D val ; break; + case SPSR_EL1: vcpu->arch.ctxt.spsr_el1 =3D val; break; + default: + WARN(true, "%s wants to write non-special register %x", __func__, reg); + } +} + +static __always_inline void write_sr_to_vcpu(struct kvm_vcpu *vcpu, u64 va= l, + enum vcpu_sysreg reg) +{ + switch (reg) { + case ACTLR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_ACTLR_EL1); break; + case AFSR0_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_AFSR0_EL1); break; + case AFSR1_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_AFSR1_EL1); break; + case CNTFRQ_EL0: _vcpu_write_sys_reg(vcpu, val, SYS_CNTFRQ_EL0); break; + case CNTP_CVAL_EL0: _vcpu_write_sys_reg(vcpu, val, SYS_CNTP_CVAL_EL0); br= eak; + case CNTV_CVAL_EL0: _vcpu_write_sys_reg(vcpu, val, SYS_CNTV_CVAL_EL0); br= eak; + case DISR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_DISR_EL1); break; + case MIDR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_MIDR_EL1); break; + case PAR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_PAR_EL1); break; + case OSLAR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_OSLAR_EL1); break; + case SCTLR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_SCTLR_EL1); break; + case CPACR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_CPACR_EL1); break; + case VBAR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_VBAR_EL1); break; + case ESR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_ESR_EL1); break; + case TCR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_TCR_EL1); break; + case MAIR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_MAIR_EL1); break; + case TTBR0_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_TTBR0_EL1); break; + case TTBR1_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_TTBR1_EL1); break; + case FAR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_FAR_EL1); break; + case TPIDR_EL0: _vcpu_write_sys_reg(vcpu, val, SYS_TPIDR_EL0); break; + case TPIDR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_TPIDR_EL1); break; + case TPIDRRO_EL0: _vcpu_write_sys_reg(vcpu, val, SYS_TPIDRRO_EL0); break; + case CNTKCTL_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_CNTKCTL_EL1); break; + case ZCR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_ZCR_EL1); break; + case SCXTNUM_EL0: _vcpu_write_sys_reg(vcpu, val, SYS_SCXTNUM_EL0); break; + case SCXTNUM_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_SCXTNUM_EL1); break; + case APIBKEYLO_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APIBKEYLO_EL1); br= eak; + case APIBKEYHI_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APIBKEYHI_EL1); br= eak; + case APIAKEYLO_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APIAKEYLO_EL1); br= eak; + case APIAKEYHI_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APIAKEYHI_EL1); br= eak; + case APGAKEYLO_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APGAKEYLO_EL1); br= eak; + case APGAKEYHI_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APGAKEYHI_EL1); br= eak; + case APDBKEYLO_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APDBKEYLO_EL1); br= eak; + case APDBKEYHI_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APDBKEYHI_EL1); br= eak; + case APDAKEYLO_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APDAKEYLO_EL1); br= eak; + case APDAKEYHI_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_APDAKEYHI_EL1); br= eak; + case MDSCR_EL1: _vcpu_write_sys_reg(vcpu, val, SYS_MDSCR_EL1); break; + default: + WARN(true, "%s: failed to resolve %x", __func__, reg); + } +} + +void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg r= eg) +{ + struct sr_loc loc =3D {}; + + locate_register(vcpu, reg, &loc); + + if (unlikely(loc.loc =3D=3D SR_LOC_INVALID)) { + WARN(true, "%s: failed to locate %u", __func__, reg); + return; + } + + if (loc.loc =3D=3D SR_LOC_SPECIAL) { + write_special_sr(vcpu, val, reg); + return; + } + + write_sr_to_vcpu(vcpu, val, reg); +} + +u64 vcpu_read_host_sys_reg(const struct kvm_vcpu *vcpu, int reg) +{ + switch (reg) { + case SYS_ICH_LR0_EL2: return vcpu->arch.sae_block.ic_regs.ich_lrn_el2[0]; + case SYS_ICH_LR1_EL2: return vcpu->arch.sae_block.ic_regs.ich_lrn_el2[1]; + case SYS_ICH_LR2_EL2: return vcpu->arch.sae_block.ic_regs.ich_lrn_el2[2]; + case SYS_ICH_LR3_EL2: return vcpu->arch.sae_block.ic_regs.ich_lrn_el2[3]; + case SYS_ICH_HCR_EL2: return vcpu->arch.sae_block.ic_regs.ich_hcr_el2; + case SYS_ICH_AP0R0_EL2: return vcpu->arch.sae_block.ic_regs.ich_ap0r0_el2; + case SYS_ICH_AP1R0_EL2: return vcpu->arch.sae_block.ic_regs.ich_ap1r0_el2; + case SYS_ICH_VMCR_EL2: return vcpu->arch.sae_block.ic_regs.ich_vmcr_el2; + case SYS_VSESR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_VSESR_EL2); + case SYS_HCR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_HCR_EL2); + case SYS_CPTR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_CPTR_EL2); + case SYS_MDCR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_MDCR_EL2); + case SYS_HCRX_EL2: return _vcpu_read_sys_reg(vcpu, SYS_HCRX_EL2); + case SYS_HFGRTR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_HFGRTR_EL2); + case SYS_HFGWTR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_HFGWTR_EL2); + case SYS_HDFGWTR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_HDFGWTR_EL2); + case SYS_HDFGRTR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_HDFGRTR_EL2); + case SYS_HFGITR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_HFGITR_EL2); + case SYS_CNTHCTL_EL2: return _vcpu_read_sys_reg(vcpu, SYS_CNTHCTL_EL2); + case SYS_ICC_SRE_EL2: return _vcpu_read_sys_reg(vcpu, SYS_ICC_SRE_EL2); + case SYS_VMPIDR_EL2: return _vcpu_read_sys_reg(vcpu, SYS_VMPIDR_EL2); + default: + WARN(true, "%s wants to read non-host register %x", __func__, reg); + return SR_INVALID; + } +} + +void vcpu_write_host_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) +{ + switch (reg) { + case SYS_ICH_LR0_EL2: vcpu->arch.sae_block.ic_regs.ich_lrn_el2[0] =3D val= ; break; + case SYS_ICH_LR1_EL2: vcpu->arch.sae_block.ic_regs.ich_lrn_el2[1] =3D val= ; break; + case SYS_ICH_LR2_EL2: vcpu->arch.sae_block.ic_regs.ich_lrn_el2[2] =3D val= ; break; + case SYS_ICH_LR3_EL2: vcpu->arch.sae_block.ic_regs.ich_lrn_el2[3] =3D val= ; break; + case SYS_ICH_HCR_EL2: vcpu->arch.sae_block.ic_regs.ich_hcr_el2 =3D val; = break; + case SYS_ICH_AP0R0_EL2: vcpu->arch.sae_block.ic_regs.ich_ap0r0_el2 =3D va= l; break; + case SYS_ICH_AP1R0_EL2: vcpu->arch.sae_block.ic_regs.ich_ap1r0_el2 =3D va= l; break; + case SYS_ICH_VMCR_EL2: vcpu->arch.sae_block.ic_regs.ich_vmcr_el2 =3D val;= break; + case SYS_VSESR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_VSESR_EL2); break; + case SYS_HCR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_HCR_EL2); break; + case SYS_CPTR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_CPTR_EL2); break; + case SYS_MDCR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_MDCR_EL2); break; + case SYS_HCRX_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_HCRX_EL2); break; + case SYS_HFGRTR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_HFGRTR_EL2); bre= ak; + case SYS_HFGWTR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_HFGWTR_EL2); bre= ak; + case SYS_HDFGWTR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_HDFGWTR_EL2); br= eak; + case SYS_HDFGRTR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_HDFGRTR_EL2); br= eak; + case SYS_HFGITR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_HFGITR_EL2); bre= ak; + case SYS_CNTHCTL_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_CNTHCTL_EL2); br= eak; + case SYS_ICC_SRE_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_ICC_SRE_EL2); br= eak; + case SYS_VMPIDR_EL2: _vcpu_write_sys_reg(vcpu, val, SYS_VMPIDR_EL2); bre= ak; + default: + WARN(true, "%s wants to write non-host register %x", __func__, reg); + } +} + +static int arm64_check_features(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd, u64 val) +{ + u32 id =3D reg_to_encoding(rd); + u64 host_val; + u64 old_val; + + /* + * This is a very minimal implementation to sanitise only the craziest + * shenanigans we could get from userspace. The final goal is to share + * the sanitisation with arm as well but this needs access to arm + * (core) kernel code for which there is no suitable solution yet. TODO + */ + + /* + * If the register is RAZ we know the only safe value is 0. + */ + if (sysreg_visible_as_raz(vcpu, rd)) + return val ? -E2BIG : 0; + + host_val =3D read_sanitised_ftr_reg(id); + + switch (id) { + case SYS_ID_AA64MMFR0_EL1: + /* Forbid PRANGE values larger than the host supports*/ + if (SYS_FIELD_GET(ID_AA64MMFR0_EL1, PARANGE, val) > + SYS_FIELD_GET(ID_AA64MMFR0_EL1, PARANGE, host_val)) + return -E2BIG; + break; + case SYS_CTR_EL0: + /* forbid upgrading from VIPT to PIPT */ + old_val =3D read_id_reg(vcpu, rd); + if (SYS_FIELD_GET(CTR_EL0, L1Ip, old_val) =3D=3D CTR_EL0_L1Ip_VIPT && + SYS_FIELD_GET(CTR_EL0, L1Ip, val) =3D=3D CTR_EL0_L1Ip_PIPT) + return -E2BIG; + break; + } + return 0; +} + +static void init_imp_id_regs(void) +{ + boot_cpu_midr_val =3D read_sanitised_ftr_reg(SYS_MIDR_EL1); + boot_cpu_revidr_val =3D read_sanitised_ftr_reg(SYS_REVIDR_EL1); + boot_cpu_aidr_val =3D read_sanitised_ftr_reg(SYS_AIDR_EL1); +} + +static bool access_imp_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params= *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + return write_to_read_only(vcpu, p, r); + + /* + * Return the VM-scoped implementation ID register values if userspace + * has made them writable. + */ + if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &vcpu->kvm->arch.flags)) + return access_id_reg(vcpu, p, r); + + switch (reg_to_encoding(r)) { + case SYS_REVIDR_EL1: + p->regval =3D boot_cpu_revidr_val; //no old api to conform to? + break; + case SYS_AIDR_EL1: + p->regval =3D boot_cpu_aidr_val; + break; + default: + WARN_ON_ONCE(1); + } + + return true; +} + +static int get_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,= u64 *val) +{ + *val =3D vcpu->arch.mpidr; + return 0; +} + +static int set_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,= u64 val) +{ + vcpu->arch.mpidr =3D val; + return 0; +} + +static u64 reset_midr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + _vcpu_write_sys_reg(vcpu, boot_cpu_midr_val, SYS_MIDR_EL1); + return boot_cpu_midr_val; +} + +static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc = *rd, + u64 val) +{ + u64 oslk; + + /* + * The only modifiable bit is the OSLK bit. Refuse the write if + * userspace attempts to change any other bit in the register. + */ + if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) + return -EINVAL; + + /* + * Redirect the write to the proper control register. + * OSLSR is read-only + */ + oslk =3D SYS_FIELD_GET(OSLSR_EL1, OSLK, val); + __vcpu_assign_sys_reg(vcpu, OSLAR_EL1, SYS_FIELD_PREP(OSLAR_EL1, OSLK, os= lk)); + return 0; +} + +static u64 reset_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_des= c *r) +{ + u64 oslsr =3D r->val; + + set_oslsr_el1(vcpu, r, oslsr); + return oslsr; +} + +static int arch_timer_set_user(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd, + u64 val) +{ + switch (reg_to_encoding(rd)) { + case SYS_CNTVCT_EL0: + vcpu->arch.sae_block.gpto =3D ptff_qagto(val); + return 0; + case SYS_CNTPCT_EL0: + return 0; + } + + __vcpu_assign_sys_reg(vcpu, rd->reg, val); + return 0; +} + +static int arch_timer_get_user(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd, + u64 *val) +{ + switch (reg_to_encoding(rd)) { + case SYS_CNTVCT_EL0: + *val =3D ptff_qagpt(vcpu->arch.sae_block.gpto); + break; + case SYS_CNTPCT_EL0: + *val =3D ptff_qagpt(vcpu->arch.sae_block.gpto); + break; + default: + *val =3D __vcpu_sys_reg(vcpu, rd->reg); + } + + return 0; +} + +#define TIMER_REG(name) { \ + SYS_DESC(SYS_##name), \ + .reset =3D reset_val, \ + .reg =3D name, \ + .get_user =3D arch_timer_get_user, \ + .set_user =3D arch_timer_set_user, \ +} + +/* + * Architected system registers. + * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 + */ +static const struct sys_reg_desc sys_reg_descs[] =3D { + /* Op0 =3D 2 */ + { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, + { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_oslsr_el1, OSLSR_EL1, + OSLSR_EL1_OSLM_IMPLEMENTED, NULL, set_oslsr_el1 }, + + /* Op0 =3D 3 */ + /* Op1 =3D 0 */ + /* CRn =3D 0 */ + /* CRm =3D 0 */ + + { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr, 0, GENMASK_ULL(31, 0), + get_id_reg, set_imp_id_reg }, + { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1, 0, get_mpidr, + set_mpidr }, + IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)), + + /* + * ID regs: all ID_SANITISED() entries here must have corresponding + * entries in arm64_ftr_regs[]. + */ + + /* AArch64 mappings of the AArch32 ID registers */ + /* CRm=3D1 */ + ID_HIDDEN(ID_PFR0_EL1), + ID_HIDDEN(ID_PFR1_EL1), + ID_HIDDEN(ID_DFR0_EL1), + ID_HIDDEN(ID_AFR0_EL1), + ID_HIDDEN(ID_MMFR0_EL1), + ID_HIDDEN(ID_MMFR1_EL1), + ID_HIDDEN(ID_MMFR2_EL1), + ID_HIDDEN(ID_MMFR3_EL1), + + /* CRm=3D2 */ + ID_HIDDEN(ID_ISAR0_EL1), + ID_HIDDEN(ID_ISAR1_EL1), + ID_HIDDEN(ID_ISAR2_EL1), + ID_HIDDEN(ID_ISAR3_EL1), + ID_HIDDEN(ID_ISAR4_EL1), + ID_HIDDEN(ID_ISAR5_EL1), + ID_HIDDEN(ID_MMFR4_EL1), + ID_HIDDEN(ID_ISAR6_EL1), + + /* CRm=3D3 */ + ID_HIDDEN(MVFR0_EL1), + ID_HIDDEN(MVFR1_EL1), + ID_HIDDEN(MVFR2_EL1), + ID_UNALLOCATED(3, 3), + ID_HIDDEN(ID_PFR2_EL1), + ID_HIDDEN(ID_DFR1_EL1), + ID_HIDDEN(ID_MMFR5_EL1), + ID_UNALLOCATED(3, 7), + + /* AArch64 ID registers */ + /* CRm=3D4 */ + ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, + ~(ID_AA64PFR0_EL1_AMU | ID_AA64PFR0_EL1_MPAM | + ID_AA64PFR0_EL1_SVE | ID_AA64PFR0_EL1_RAS | + ID_AA64PFR0_EL1_GIC | ID_AA64PFR0_EL1_AdvSIMD | + ID_AA64PFR0_EL1_FP)), + ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, + ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_DF2 | + ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | + ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | + ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_RNDR_trap | + ID_AA64PFR1_EL1_SME | ID_AA64PFR1_EL1_RES0 | + ID_AA64PFR1_EL1_MPAM_frac | ID_AA64PFR1_EL1_RAS_frac | + ID_AA64PFR1_EL1_MTE)), + ID_FILTERED(ID_AA64PFR2_EL1, id_aa64pfr2_el1, + (ID_AA64PFR2_EL1_FPMR | + ID_AA64PFR2_EL1_MTEFAR | + ID_AA64PFR2_EL1_MTESTOREONLY | + ID_AA64PFR2_EL1_GCIE)), + ID_UNALLOCATED(4, 3), + ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), + ID_HIDDEN(ID_AA64SMFR0_EL1), + ID_UNALLOCATED(4, 6), + ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), + + /* CRm=3D5 */ + /* + * Prior to FEAT_Debugv8.9, the architecture defines context-aware + * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). + * KVM does not trap + emulate the breakpoint registers, and as such + * cannot support a layout that misaligns with the underlying hardware. + * While it may be possible to describe a subset that aligns with + * hardware, just prevent changes to BRPs and CTX_CMPs altogether for + * simplicity. + * + * See DDI0487K.a, section D2.8.3 Breakpoint types and linking + * of breakpoints for more details. + */ + ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, + ID_AA64DFR0_EL1_DoubleLock_MASK | + ID_AA64DFR0_EL1_WRPs_MASK | + ID_AA64DFR0_EL1_PMUVer_MASK | + ID_AA64DFR0_EL1_DebugVer_MASK), + ID_SANITISED(ID_AA64DFR1_EL1), + ID_UNALLOCATED(5, 2), + ID_UNALLOCATED(5, 3), + ID_HIDDEN(ID_AA64AFR0_EL1), + ID_HIDDEN(ID_AA64AFR1_EL1), + ID_UNALLOCATED(5, 6), + ID_UNALLOCATED(5, 7), + + /* CRm=3D6 */ + ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), + ID_WRITABLE(ID_AA64ISAR1_EL1, + ~(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | + ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA)), + ID_WRITABLE(ID_AA64ISAR2_EL1, + ~(ID_AA64ISAR2_EL1_RES0 | ID_AA64ISAR2_EL1_APA3 | + ID_AA64ISAR2_EL1_GPA3)), + ID_WRITABLE(ID_AA64ISAR3_EL1, + (ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX)), + ID_UNALLOCATED(6, 4), + ID_UNALLOCATED(6, 5), + ID_UNALLOCATED(6, 6), + ID_UNALLOCATED(6, 7), + + /* CRm=3D7 */ + ID_FILTERED(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1, + ~(ID_AA64MMFR0_EL1_RES0 | ID_AA64MMFR0_EL1_ASIDBITS)), + ID_WRITABLE(ID_AA64MMFR1_EL1, + ~(ID_AA64MMFR1_EL1_RES0 | ID_AA64MMFR1_EL1_HCX | + ID_AA64MMFR1_EL1_TWED | ID_AA64MMFR1_EL1_XNX | + ID_AA64MMFR1_EL1_VH | ID_AA64MMFR1_EL1_VMIDBits)), + ID_FILTERED(ID_AA64MMFR2_EL1, id_aa64mmfr2_el1, + ~(ID_AA64MMFR2_EL1_RES0 | ID_AA64MMFR2_EL1_EVT | + ID_AA64MMFR2_EL1_FWB | ID_AA64MMFR2_EL1_IDS | + ID_AA64MMFR2_EL1_NV | ID_AA64MMFR2_EL1_CCIDX)), + ID_WRITABLE(ID_AA64MMFR3_EL1, + (ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1PIE | + ID_AA64MMFR3_EL1_S1POE)), + ID_WRITABLE(ID_AA64MMFR4_EL1, ID_AA64MMFR4_EL1_NV_frac), + ID_UNALLOCATED(7, 5), + ID_UNALLOCATED(7, 6), + ID_UNALLOCATED(7, 7), + + /* CRn =3D 1 */ + { SYS_DESC(SYS_SCTLR_EL1), NULL, reset_val, SCTLR_EL1, 0x00C50078 }, + { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, + + /* CRn =3D 2 */ + { SYS_DESC(SYS_TTBR0_EL1), access_rw, reset_val, TTBR0_EL1, 0 }, + { SYS_DESC(SYS_TTBR1_EL1), access_rw, reset_val, TTBR1_EL1, 0 }, + { SYS_DESC(SYS_TCR_EL1), access_rw, reset_val, TCR_EL1, 0 }, + + { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, + /* CRn =3D 10 */ + { SYS_DESC(SYS_MAIR_EL1), NULL, reset_unknown, MAIR_EL1 }, + { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, + { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, + { SYS_DESC(SYS_LORN_EL1), trap_loregion }, + { SYS_DESC(SYS_LORC_EL1), trap_loregion }, + { SYS_DESC(SYS_LORID_EL1), trap_loregion }, + + /* CRn =3D 12 */ + { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, + + /* CRn =3D 13 */ + { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, + + /* Op1 =3D 1 */ + /* CRn =3D 0 */ + /* CRm =3D 0 */ + { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, + { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, + ~CLIDR_EL1_RES0, .set_user =3D set_clidr }, + IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), + { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, + ID_FILTERED(CTR_EL0, ctr_el0, + CTR_EL0_DIC_MASK | CTR_EL0_IDC_MASK | + CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | + CTR_EL0_IminLine_MASK), + + { SYS_DESC(SYS_CNTFRQ_EL0), NULL, reset_val, CNTFRQ_EL0, 0x3B9ACA00 }, + { SYS_DESC(SYS_CNTPCT_EL0), .get_user =3D arch_timer_get_user, + .set_user =3D arch_timer_set_user }, + { SYS_DESC(SYS_CNTVCT_EL0), .get_user =3D arch_timer_get_user, + .set_user =3D arch_timer_set_user }, + TIMER_REG(CNTP_CTL_EL0), + TIMER_REG(CNTP_CVAL_EL0), + TIMER_REG(CNTV_CTL_EL0), + TIMER_REG(CNTV_CVAL_EL0), +}; + +static const size_t num_sys_reg_descs =3D ARRAY_SIZE(sys_reg_descs); + +/** + * kvm_reset_sys_regs - sets system registers to reset value + * @vcpu: The VCPU pointer + * + * This function finds the right table above and sets the registers on the + * virtual CPU struct to their architecturally defined reset values. + */ +void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm =3D vcpu->kvm; + unsigned long i; + + for (i =3D 0; i < num_sys_reg_descs; i++) { + const struct sys_reg_desc *r =3D &sys_reg_descs[i]; + + if (!r->reset) + continue; + + if (is_vm_ftr_id_reg(reg_to_encoding(r))) { + reset_vm_ftr_id_reg(vcpu, r); + /* + * ID registers are stored per VCPU as well and need a + * meaningful reset value. Reset the VCPU regas well. + */ + if (!kvm_vcpu_initialized(vcpu)) + r->reset(vcpu, r); + } else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) { + reset_vcpu_ftr_id_reg(vcpu, r); + } else { + r->reset(vcpu, r); + } + } + + set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); + + if (kvm_vcpu_has_pmu(vcpu)) + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); +} + +/* + * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instructi= on + * trap on a guest execution + * @vcpu: The VCPU pointer + */ +int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) +{ + const struct sys_reg_desc *desc =3D NULL; + struct sys_reg_params params; + unsigned long esr =3D kvm_vcpu_get_esr(vcpu); + int Rt =3D kvm_vcpu_sys_get_rt(vcpu); + + trace_kvm_handle_sys_reg(esr); + + params =3D esr_sys64_to_params(esr); + params.regval =3D vcpu_get_reg(vcpu, Rt); + + /* System registers have Op0=3D=3D{2,3}, as per DDI487 J.a C5.1.2 */ + if (params.Op0 =3D=3D 2 || params.Op0 =3D=3D 3) + desc =3D find_reg(¶ms, sys_reg_descs, num_sys_reg_descs); + else + WARN(true, "system instruction handling not supported"); + + if (!desc) { + if (!(params.Op0 =3D=3D 3 && (params.CRn & 0b1011) =3D=3D 0b1011)) + print_sys_reg_msg(¶ms, + "Unsupported guest access at: %lx\n", + *vcpu_pc(vcpu)); + kvm_inject_undefined(vcpu); + return 1; + } else { + perform_access(vcpu, ¶ms, desc); + } + + /* Read from system register? */ + if (!params.is_write && + (params.Op0 =3D=3D 2 || params.Op0 =3D=3D 3)) + vcpu_set_reg(vcpu, Rt, params.regval); + + return 1; +} + +int __init kvm_sys_reg_table_init(void) +{ + init_imp_id_regs(); + + bool valid =3D + check_sysreg_table(sys_reg_descs, num_sys_reg_descs, false); + + if (!valid) + return -EINVAL; + + return 0; +} + +/* + * Perform last adjustments to the ID registers that are implied by the + * configuration outside of the ID regs themselves, as well as any + * initialisation that directly depend on these ID registers (such as + * RES0/RES1 behaviours). This is not the place to configure traps though. + * + * Because this can be called once per CPU, changes must be idempotent. + */ +int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) +{ + return 0; +} + diff --git a/arch/s390/kvm/arm64/trace.h b/arch/s390/kvm/arm64/trace.h index 2a205ba0165c..77d146e3d6a5 100644 --- a/arch/s390/kvm/arm64/trace.h +++ b/arch/s390/kvm/arm64/trace.h @@ -4,6 +4,8 @@ =20 #include =20 +#include + #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm_arm64 =20 @@ -31,6 +33,55 @@ TRACE_EVENT(kvm_mmio_nisv, __entry->far, __entry->vcpu_pc) ); =20 +TRACE_EVENT(kvm_handle_sys_reg, + TP_PROTO(unsigned long hsr), + TP_ARGS(hsr), + + TP_STRUCT__entry( + __field(unsigned long, hsr) + ), + + TP_fast_assign( + __entry->hsr =3D hsr; + ), + + TP_printk("HSR 0x%08lx", __entry->hsr) +); + +TRACE_EVENT(kvm_sys_access, + TP_PROTO(unsigned long vcpu_pc, struct sys_reg_params *params, const stru= ct sys_reg_desc *reg), + TP_ARGS(vcpu_pc, params, reg), + + TP_STRUCT__entry( + __field(unsigned long, vcpu_pc) + __field(bool, is_write) + __field(const char *, name) + __field(u8, Op0) + __field(u8, Op1) + __field(u8, CRn) + __field(u8, CRm) + __field(u8, Op2) + ), + + TP_fast_assign( + __entry->vcpu_pc =3D vcpu_pc; + __entry->is_write =3D params->is_write; + __entry->name =3D reg->name; + __entry->Op0 =3D reg->Op0; + __entry->Op0 =3D reg->Op0; + __entry->Op1 =3D reg->Op1; + __entry->CRn =3D reg->CRn; + __entry->CRm =3D reg->CRm; + __entry->Op2 =3D reg->Op2; + ), + + TP_printk("PC: %lx %s (%d,%d,%d,%d,%d) %s", + __entry->vcpu_pc, __entry->name ?: "UNKN", + __entry->Op0, __entry->Op1, __entry->CRn, + __entry->CRm, __entry->Op2, + str_write_read(__entry->is_write)) +); + #endif /* KVM_ARM64_TRACE_KVM_H */ =20 #undef TRACE_INCLUDE_PATH diff --git a/arch/s390/tools/Makefile.arm64h b/arch/s390/tools/Makefile.arm= 64h index 49f344636e83..28103cdc243c 100644 --- a/arch/s390/tools/Makefile.arm64h +++ b/arch/s390/tools/Makefile.arm64h @@ -17,12 +17,16 @@ arm64uapi :=3D $(objtree)/arch/$(ARCH)/include/generate= d/uapi/arm64 # If the file does not contain any markers the whole file will be copied. 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charset="utf-8" Integrate the previously established system register managing infrastructure into the host. Initialize sysregs during vcpu init. Finalize sysregs on PID change, Initialize sysreg table on kvm init, report availability to userspace and let userspace read&modify guest system register. Signed-off-by: Steffen Eiden --- arch/s390/include/asm/kvm_host_arm64.h | 3 ++ arch/s390/kvm/arm64/arm.c | 27 +++++++++++++++++ arch/s390/kvm/arm64/guest.c | 12 +++++--- arch/s390/kvm/arm64/handle_exit.c | 1 + arch/s390/kvm/arm64/reset.c | 42 ++++++++++++++++++++++++++ 5 files changed, 81 insertions(+), 4 deletions(-) diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm= /kvm_host_arm64.h index 65e5e0c48b07..0bf396ef54c2 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -156,6 +156,9 @@ struct kvm_arch { =20 /* Per-VM ID register storage */ struct kvm_vm_id_regs id_regs; + + /* The EPD as it should be on all VCPUs. */ + u64 epd; }; =20 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int featu= re) diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index c573a3da5766..3a0bba6e0a06 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -16,6 +16,7 @@ =20 #include #include +#include =20 #include #include @@ -136,6 +137,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long typ= e) goto out_err; kvm->arch.mem_limit =3D kvm->arch.guest_phys_size; =20 + kvm->arch.epd =3D ptff_qagto(0); + VM_EVENT(kvm, 3, "vm created with type %lu", type); return 0; =20 @@ -191,6 +194,7 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) sae_block->mso =3D 0L; sae_block->msl =3D vcpu->kvm->arch.mem_limit; sae_block->save_area =3D virt_to_phys(save_area); + sae_block->gpto =3D vcpu->kvm->arch.epd; =20 VM_EVENT(vcpu->kvm, 3, "create cpu %d at 0x%p, sae block at 0x%p, satellite at 0x%p", @@ -259,6 +263,7 @@ bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) { struct kvm *kvm =3D vcpu->kvm; + int ret; =20 if (!kvm_vcpu_initialized(vcpu)) return -ENOEXEC; @@ -272,6 +277,10 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) scoped_guard(mutex, &kvm->arch.config_lock) set_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &kvm->arch.flags); =20 + ret =3D kvm_finalize_sys_regs(vcpu); + if (ret) + return ret; + return 0; } =20 @@ -390,10 +399,20 @@ static void arm_vcpu_run(struct kvm_vcpu *vcpu) guest_state_enter_irqoff(); local_irq_enable(); =20 + vcpu_write_host_sys_reg(vcpu, vcpu->arch.hcr_elz, SYS_HCR_EL2); + vcpu_write_host_sys_reg(vcpu, vcpu->arch.hcrx_elz, SYS_HCRX_EL2); + vcpu_write_host_sys_reg(vcpu, vcpu->arch.mpidr, SYS_VMPIDR_EL2); + + _vcpu_write_sys_reg(vcpu, vcpu->arch.ctxt.elr_el1, SYS_ELR_EL1); + _vcpu_write_sys_reg(vcpu, vcpu->arch.ctxt.spsr_el1, SYS_SPSR_EL1); + sae_block->icptr =3D 0; =20 sae64a(sae_block); =20 + vcpu->arch.ctxt.elr_el1 =3D _vcpu_read_sys_reg(vcpu, SYS_ELR_EL1); + vcpu->arch.ctxt.spsr_el1 =3D _vcpu_read_sys_reg(vcpu, SYS_SPSR_EL1); + local_irq_disable(); guest_state_exit_irqoff(); guest_timing_exit_irqoff(); @@ -746,11 +765,19 @@ long kvm_arch_vcpu_unlocked_ioctl(struct file *filp, = unsigned int ioctl, =20 static int __init kvm_s390_arm64_init(void) { + int ret; + if (!aef_info()->arm_guest_supp) return -ENXIO; =20 kvm_init_qaaf(); =20 + ret =3D kvm_sys_reg_table_init(); + if (ret) { + kvm_info("Error initializing system register tables"); + return ret; + } + return kvm_init_with_dev(sizeof(struct kvm_vcpu), 0, THIS_MODULE, KVM_DEV_NAME, MISC_DYNAMIC_MINOR); } diff --git a/arch/s390/kvm/arm64/guest.c b/arch/s390/kvm/arm64/guest.c index 8b5ee9e79a4f..047460975936 100644 --- a/arch/s390/kvm/arm64/guest.c +++ b/arch/s390/kvm/arm64/guest.c @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #define SVE_VQ_MIN __SVE_VQ_MIN #define SVE_NUM_ZREGS KVM_ARM64_SVE_NUM_ZREGS @@ -60,12 +61,15 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64= __user *uindices) return ret; uindices +=3D ret; =20 - return 0; + return kvm_arm_copy_sys_reg_indices(vcpu, uindices); } =20 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) { - return num_core_regs(vcpu); + unsigned long num =3D num_core_regs(vcpu); + + num +=3D kvm_arm_num_sys_reg_descs(vcpu); + return num; } =20 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) @@ -78,7 +82,7 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct k= vm_one_reg *reg) case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg); default: - return -EINVAL; + return kvm_arm_sys_reg_get_reg(vcpu, reg); } } =20 @@ -92,7 +96,7 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct k= vm_one_reg *reg) case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg); default: - return -EINVAL; + return kvm_arm_sys_reg_set_reg(vcpu, reg); } } =20 diff --git a/arch/s390/kvm/arm64/handle_exit.c b/arch/s390/kvm/arm64/handle= _exit.c index 8b03e8ee5acf..b6cb4612675a 100644 --- a/arch/s390/kvm/arm64/handle_exit.c +++ b/arch/s390/kvm/arm64/handle_exit.c @@ -55,6 +55,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu) static exit_handle_fn arm_exit_handlers[] =3D { [0 ... ESR_ELx_EC_MAX] =3D kvm_handle_unknown_ec, [ESR_ELx_EC_HVC64] =3D handle_hvc, + [ESR_ELx_EC_SYS64] =3D kvm_handle_sys_reg, [ESR_ELx_EC_IABT_LOW] =3D kvm_handle_guest_abort, [ESR_ELx_EC_DABT_LOW] =3D kvm_handle_guest_abort, }; diff --git a/arch/s390/kvm/arm64/reset.c b/arch/s390/kvm/arm64/reset.c index 0e162be1bcd5..74622ba6f081 100644 --- a/arch/s390/kvm/arm64/reset.c +++ b/arch/s390/kvm/arm64/reset.c @@ -5,6 +5,10 @@ =20 #include #include +#include +#include + +#include =20 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) { @@ -21,6 +25,39 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) HCR_EL2_TIDCP | HCR_EL2_TLOR; } =20 +static inline void vcpu_reset_hcrx(struct kvm_vcpu *vcpu) +{ + vcpu->arch.hcrx_elz =3D 0; + if (kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) + vcpu->arch.hcrx_elz |=3D HCRX_EL2_MSCEn; +} + +static inline void vcpu_reset_cptr(struct kvm_vcpu *vcpu) +{ + u64 cptr; + + /* we unconditionally have E2H, so disable traps to EL2 for FP and SVE, i= f enabled */ + cptr =3D CPACR_EL1_FPEN; + if (vcpu_has_sve(vcpu)) + cptr |=3D CPACR_EL1_ZEN; + vcpu_write_host_sys_reg(vcpu, cptr, SYS_CPTR_EL2); +} + +static inline void vcpu_reset_cnthctl(struct kvm_vcpu *vcpu) +{ + u64 cnthctl; + + /* we unconditionally have E2H, so disable traps to EL2 for physical time= r registers */ + cnthctl =3D (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10; + vcpu_write_host_sys_reg(vcpu, cnthctl, SYS_CNTHCTL_EL2); +} + +static inline void vcpu_reset_icc(struct kvm_vcpu *vcpu) +{ + /* ensure ICC_SRE_EL2.Enable =3D 1 so ICC_SRE_EL1 is handled in hardware = */ + vcpu_write_host_sys_reg(vcpu, 0xf, SYS_ICC_SRE_EL2); +} + void kvm_reset_vcpu(struct kvm_vcpu *vcpu) { struct vcpu_reset_state reset_state; @@ -43,9 +80,14 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) vcpu_put(vcpu); =20 kvm_reset_vcpu_core(vcpu); + kvm_reset_sys_regs(vcpu); =20 /* Reset special registers */ vcpu_reset_hcr(vcpu); + vcpu_reset_hcrx(vcpu); + vcpu_reset_cptr(vcpu); + vcpu_reset_cnthctl(vcpu); + vcpu_reset_icc(vcpu); =20 if (reset_state.reset) { *vcpu_pc(vcpu) =3D reset_state.pc; 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charset="utf-8" Use the (cached) result of QAAF fc2 (Generate Initial System-Registers-Save Area) to initialize the Save Area. Signed-off-by: Steffen Eiden --- arch/s390/kvm/arm64/arm.c | 1 - arch/s390/kvm/arm64/reset.c | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index 3a0bba6e0a06..ab6e7d135435 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -360,7 +360,6 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcp= u *vcpu, int ret; =20 sae_block->save_area =3D virt_to_phys(save_area); - save_area->sdo =3D virt_to_phys(sae_block); =20 ret =3D kvm_vcpu_set_target(vcpu, init); if (ret) diff --git a/arch/s390/kvm/arm64/reset.c b/arch/s390/kvm/arm64/reset.c index 74622ba6f081..bc7bcee75779 100644 --- a/arch/s390/kvm/arm64/reset.c +++ b/arch/s390/kvm/arm64/reset.c @@ -10,6 +10,8 @@ =20 #include =20 +#include "qaaf.h" + bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) { return true; @@ -79,6 +81,9 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) if (loaded) vcpu_put(vcpu); =20 + kvm_vcpu_init_save_area(&vcpu->arch.save_area); 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charset="utf-8" Add exception injection support for s390 KVM arm64 architecture. This implements the core exception entry mechanism and fault injection functions needed for proper guest exception handling. Co-developed-by: Andreas Grapentin Signed-off-by: Andreas Grapentin Signed-off-by: Steffen Eiden --- arch/s390/include/asm/kvm_host_arm64.h | 2 + arch/s390/kvm/arm64/Makefile | 1 + arch/s390/kvm/arm64/arm.c | 15 +--- arch/s390/kvm/arm64/exception.c | 105 +++++++++++++++++++++++++ arch/s390/kvm/arm64/inject_fault.c | 73 ++++++++++++++++- 5 files changed, 183 insertions(+), 13 deletions(-) create mode 100644 arch/s390/kvm/arm64/exception.c diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm= /kvm_host_arm64.h index 0bf396ef54c2..16a378b68c8a 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -426,4 +426,6 @@ static inline bool has_broken_cntvoff(void) return false; } =20 +void kvm_adjust_pc(struct kvm_vcpu *vcpu); + #endif /* ASM_KVM_HOST_ARM64_H */ diff --git a/arch/s390/kvm/arm64/Makefile b/arch/s390/kvm/arm64/Makefile index e19040cdc27d..cb3bf6da6d63 100644 --- a/arch/s390/kvm/arm64/Makefile +++ b/arch/s390/kvm/arm64/Makefile @@ -9,6 +9,7 @@ ccflags-y +=3D -I $(src) -I $(objtree)/$(obj) -I$(srctree)/= arch/s390/kvm/gmap -DKV =20 kvm-arm64-obj :=3D \ arm.o \ + exception.o \ feature.o \ guest.o \ handle_exit.o \ diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index ab6e7d135435..89984c6a5b64 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -379,19 +379,11 @@ int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm= _irq_level *irq_level, return -EINVAL; } =20 -static void adjust_pc(struct kvm_vcpu *vcpu) -{ - if (vcpu_get_flag(vcpu, INCREMENT_PC)) { - kvm_skip_instr(vcpu); - vcpu_clear_flag(vcpu, INCREMENT_PC); - } -} - static void arm_vcpu_run(struct kvm_vcpu *vcpu) { struct kvm_sae_block *sae_block =3D &vcpu->arch.sae_block; =20 - adjust_pc(vcpu); + kvm_adjust_pc(vcpu); =20 local_irq_disable(); guest_timing_enter_irqoff(); @@ -496,8 +488,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) =20 kvm_sigset_deactivate(vcpu); out: - if (unlikely(vcpu_get_flag(vcpu, INCREMENT_PC))) - adjust_pc(vcpu); + if (unlikely(vcpu_get_flag(vcpu, PENDING_EXCEPTION) || + vcpu_get_flag(vcpu, INCREMENT_PC))) + kvm_adjust_pc(vcpu); =20 save_vx_regs(vcpu->arch.ctxt.vregs); kernel_fpu_end(&fpu_save, KERNEL_FPC | KERNEL_VXR); diff --git a/arch/s390/kvm/arm64/exception.c b/arch/s390/kvm/arm64/exceptio= n.c new file mode 100644 index 000000000000..b2d016740488 --- /dev/null +++ b/arch/s390/kvm/arm64/exception.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include + +/* + * This performs the exception entry at a given EL (@target_mode), stashin= g PC + * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTAT= E. + * The EL passed to this function *must* be a non-secure, privileged mode = with + * bit 0 being set (PSTATE.SP =3D=3D 1). + * + * When an exception is taken, most PSTATE fields are left unchanged in the + * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily= all + * of the inherited bits have the same position in the AArch64/AArch32 SPS= R_ELx + * layouts, so we don't need to shuffle these for exceptions from AArch32 = EL0. + * + * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429. + * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426. + * + * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, = from + * MSB to LSB. + */ +static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_= mode, + enum exception_type type) +{ + unsigned long sctlr, vbar, old_pstate, new, mode; + u64 exc_offset; + + old_pstate =3D *vcpu_cpsr(vcpu); + mode =3D old_pstate & (PSR_MODE_MASK | PSR_MODE32_BIT); + + if (mode =3D=3D target_mode) + exc_offset =3D CURRENT_EL_SP_ELx_VECTOR; + else if ((mode | PSR_MODE_THREAD_BIT) =3D=3D target_mode) + exc_offset =3D CURRENT_EL_SP_EL0_VECTOR; + else if (!(mode & PSR_MODE32_BIT)) + exc_offset =3D LOWER_EL_AArch64_VECTOR; + else + exc_offset =3D LOWER_EL_AArch32_VECTOR; + + switch (target_mode) { + case PSR_MODE_EL1h: + vbar =3D vcpu_read_sys_reg(vcpu, VBAR_EL1); + sctlr =3D vcpu_read_sys_reg(vcpu, SCTLR_EL1); + vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1); + vcpu_write_sys_reg(vcpu, old_pstate, SPSR_EL1); + break; + default: + panic("Unknown PSR Mode: 0x%lx.", target_mode); + } + + *vcpu_pc(vcpu) =3D vbar + exc_offset + type; + + new =3D 0; + + new |=3D (old_pstate & PSR_N_BIT); + new |=3D (old_pstate & PSR_Z_BIT); + new |=3D (old_pstate & PSR_C_BIT); + new |=3D (old_pstate & PSR_V_BIT); + new |=3D (old_pstate & PSR_DIT_BIT); + new |=3D (old_pstate & PSR_PAN_BIT); + + if (!(sctlr & SCTLR_EL1_SPAN)) + new |=3D PSR_PAN_BIT; + + if (sctlr & SCTLR_ELx_DSSBS) + new |=3D PSR_SSBS_BIT; + + new |=3D PSR_D_BIT; + new |=3D PSR_A_BIT; + new |=3D PSR_I_BIT; + new |=3D PSR_F_BIT; + + new |=3D target_mode; + + *vcpu_cpsr(vcpu) =3D new; +} + +static void kvm_inject_exception(struct kvm_vcpu *vcpu) +{ + switch (vcpu_get_flag(vcpu, EXCEPT_MASK)) { + case unpack_vcpu_flag(EXCEPT_AA64_EL1_SYNC): + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync); + break; + } +} + +/* + * Adjust the guest PC (and potentially exception state) depending on + * flags provided by the emulation code. + */ +void kvm_adjust_pc(struct kvm_vcpu *vcpu) +{ + if (vcpu_get_flag(vcpu, PENDING_EXCEPTION)) { + kvm_inject_exception(vcpu); + vcpu_clear_flag(vcpu, PENDING_EXCEPTION); + vcpu_clear_flag(vcpu, EXCEPT_MASK); + } else if (vcpu_get_flag(vcpu, INCREMENT_PC)) { + kvm_skip_instr(vcpu); + vcpu_clear_flag(vcpu, INCREMENT_PC); + } +} diff --git a/arch/s390/kvm/arm64/inject_fault.c b/arch/s390/kvm/arm64/injec= t_fault.c index 425dbeaa421c..7ecf91f86d90 100644 --- a/arch/s390/kvm/arm64/inject_fault.c +++ b/arch/s390/kvm/arm64/inject_fault.c @@ -2,6 +2,39 @@ =20 #include =20 +static void pend_sync_exception(struct kvm_vcpu *vcpu) +{ + kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC); +} + +static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned lon= g addr) +{ + unsigned long cpsr =3D *vcpu_cpsr(vcpu); + bool is_aarch32 =3D vcpu_mode_is_32bit(vcpu); + u64 esr =3D 0; + + if (kvm_vcpu_abt_iss1tw(vcpu)) + esr |=3D ESR_ELx_FSC_SEA_TTW(kvm_vcpu_abt_gltl(vcpu)); + else + esr |=3D ESR_ELx_FSC_EXTABT; + + pend_sync_exception(vcpu); + + if (kvm_vcpu_trap_il_is32bit(vcpu)) + esr |=3D ESR_ELx_IL; + + if (is_aarch32 || (cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL0t) + esr |=3D (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT); + else + esr |=3D (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT); + + if (!is_iabt) + esr |=3D ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT; + + vcpu_write_sys_reg(vcpu, addr, FAR_EL1); + vcpu_write_sys_reg(vcpu, esr, ESR_EL1); +} + /** * kvm_inject_undefined - inject an undefined instruction into the guest * @vcpu: The vCPU in which to inject the exception @@ -11,11 +44,47 @@ */ void kvm_inject_undefined(struct kvm_vcpu *vcpu) { - /* Stub until s390 supports arm64 sysregs TODO sysregs*/ + u64 esr =3D (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT); + + /* + * Build an unknown exception, depending on the instruction + * set. + */ + if (kvm_vcpu_trap_il_is32bit(vcpu)) + esr |=3D ESR_ELx_IL; + + kvm_inject_sync(vcpu, esr); +} + +static void __kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr) +{ + inject_abt64(vcpu, iabt, addr); } =20 int kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr) { - /* Stub until s390 supports arm64 sysregs TODO sysregs*/ + lockdep_assert_held(&vcpu->mutex); + + __kvm_inject_sea(vcpu, iabt, addr); return 1; } + +void kvm_inject_size_fault(struct kvm_vcpu *vcpu) +{ + unsigned long addr, esr; + + addr =3D kvm_vcpu_get_fault_ipa(vcpu); + addr |=3D FAR_TO_FIPA_OFFSET(kvm_vcpu_get_hfar(vcpu)); + + __kvm_inject_sea(vcpu, kvm_vcpu_trap_is_iabt(vcpu), addr); + + esr =3D vcpu_read_sys_reg(vcpu, ESR_EL1); + esr &=3D ~GENMASK_ULL(5, 0); + vcpu_write_sys_reg(vcpu, esr, ESR_EL1); +} + +void kvm_inject_sync(struct kvm_vcpu *vcpu, u64 esr) +{ + pend_sync_exception(vcpu); + vcpu_write_sys_reg(vcpu, esr, ESR_EL1); +} --=20 2.53.0 From nobody Sat Sep 26 14:38:31 2026 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B4FE50AC18; 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charset="utf-8" Complete the page fault handling implementation by replacing temporary error returns with proper ARM64 exception injection. Signed-off-by: Steffen Eiden --- arch/s390/include/asm/kvm_host_arm64.h | 1 + arch/s390/kvm/arm64/arm.c | 6 +++ arch/s390/kvm/arm64/mmu.c | 68 ++++++++++++++++++-------- 3 files changed, 54 insertions(+), 21 deletions(-) diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm= /kvm_host_arm64.h index 16a378b68c8a..c0e8fbddc9dc 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -427,5 +427,6 @@ static inline bool has_broken_cntvoff(void) } =20 void kvm_adjust_pc(struct kvm_vcpu *vcpu); +size_t kvm_parange_to_address_sanitized(u32 id_parange); =20 #endif /* ASM_KVM_HOST_ARM64_H */ diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index 89984c6a5b64..d2ff69422217 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -62,9 +62,15 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long e= xt) =20 static u64 kvm_max_guest_address(void) { + u64 mmfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + u64 id_pa_addr; u64 max_addr; =20 + id_pa_addr =3D kvm_parange_to_address_sanitized( + SYS_FIELD_GET(ID_AA64MMFR0_EL1, PARANGE, mmfr0)); + max_addr =3D min_t(u64, TASK_SIZE_MAX, sclp.hamax); + max_addr =3D min_t(u64, max_addr, id_pa_addr); max_addr =3D max_t(u64, max_addr, SZ_1G - 1); return ALIGN_DOWN(max_addr + 1, SZ_1G) - 1; } diff --git a/arch/s390/kvm/arm64/mmu.c b/arch/s390/kvm/arm64/mmu.c index bf3442d3609b..b5f1dc3ca0d2 100644 --- a/arch/s390/kvm/arm64/mmu.c +++ b/arch/s390/kvm/arm64/mmu.c @@ -30,12 +30,14 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, gpa_t = fault_ipa, ret =3D kvm_s390_faultin_gfn(vcpu, NULL, &f); if (ret <=3D 0) return ret; - if (ret =3D=3D PGM_ADDRESSING) + if (ret =3D=3D PGM_ADDRESSING) { /* - * Without the relevant sysregs we cannot do anything for now. - * Go back to userspace with an error. TODO sysreg handling + * There is no page with the requested address. Inject size fault + * which is the closest arm match to PGM-addressing */ - return -ENOEXEC; + kvm_inject_size_fault(vcpu); + return 1; + } KVM_BUG_ON(ret, vcpu->kvm); return -EINVAL; } @@ -68,6 +70,33 @@ static int kvm_handle_pic(struct kvm_vcpu *vcpu, bool *t= ranslation) return 0; } =20 +size_t kvm_parange_to_address_sanitized(u32 id_parange) +{ + static u32 ranges_map[6] =3D { + [ID_AA64MMFR0_EL1_PARANGE_32] =3D 32, + [ID_AA64MMFR0_EL1_PARANGE_36] =3D 36, + [ID_AA64MMFR0_EL1_PARANGE_40] =3D 40, + [ID_AA64MMFR0_EL1_PARANGE_42] =3D 42, + [ID_AA64MMFR0_EL1_PARANGE_44] =3D 44, + [ID_AA64MMFR0_EL1_PARANGE_48] =3D 48, + }; + u32 parange; + + /* + * Future values must be higher than we know already. + * See ARM DDI 0487C.a. Return a safe limit. + */ + parange =3D ranges_map[min(id_parange, ID_AA64MMFR0_EL1_PARANGE_48)]; + return BIT_ULL(parange); +} + +static size_t kvm_get_pa_address(struct kvm *kvm) +{ + u32 id_parange =3D get_idreg_field_enum(kvm, ID_AA64MMFR0_EL1, PARANGE); + + return kvm_parange_to_address_sanitized(id_parange); +} + int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) { struct kvm_memory_slot *memslot; @@ -97,16 +126,17 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) } =20 if (translation) { - /* - * For both cases: - * Without the relevant sysregs we cannot do anything for now. - * Go back to userspace with an error. TODO sysreg handling - */ - if (fault_ipa >=3D BIT_ULL(get_kvm_ipa_limit())) - return -ENOEXEC; + /* Beyond sanitised PA range (which is the IPA limit) */ + if (fault_ipa >=3D kvm_get_pa_address(vcpu->kvm)) { + kvm_inject_size_fault(vcpu); + return 1; + } =20 - if (fault_ipa >=3D vcpu->kvm->arch.guest_phys_size) - return -ENOEXEC; + /* Falls between the IPA range and the PA range? */ + if (fault_ipa >=3D vcpu->kvm->arch.guest_phys_size) { + fault_ipa |=3D kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0); + return kvm_inject_sea(vcpu, is_iabt, fault_ipa); + } } =20 idx =3D srcu_read_lock(&vcpu->kvm->srcu); @@ -122,18 +152,14 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) * The guest has put either its instructions or its page-tables * somewhere it shouldn't have. Userspace won't be able to do * anything about this (there's no syndrome for a start). - * - * Without the relevant sysregs we cannot do anything for now. - * Go back to userspace with an error. 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Mon, 31 Aug 2026 14:55:55 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67VEtk6I51184082 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Aug 2026 14:55:47 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 986DB2004D; Mon, 31 Aug 2026 14:55:46 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 202A12004B; Mon, 31 Aug 2026 14:55:46 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:46 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 18/20] KVM: s390: arm64: Implement SVE for arm guests Date: Mon, 31 Aug 2026 16:55:33 +0200 Message-ID: <20260831145536.913567-19-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: nrw0vK86z51JOtYhQOLga4hUDbYzckZR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX8RnGh/LuG2Zk hVTDEI4Rwbl5lWfp5mIJOQVzN9egmeak43zwPDKi0UHeE6NnkrAIpAurYX+0wbxFAF0grD7J+wy oZf6Ksm0ebK8i4neKB0NtklXfuqxiuqtFL0XhuMbl6eE5X1ZQQmFSg2iUNboNwF4wcekBLjriTy D7n2G+ReX/Gzx5xpwzO10p0tX5GecYgNahoD/JBl79yeKeqxn90Pdf4lVto2UpA+0025972jTmt eZe8kg1NF3il1J97Pxb7Hvle2nghms5zlgnFAYhkHgWbr7EBOCbu/Xi6mq5t00GvjdkSuT6Wx7s yRdB5BUMyJyfgrJZbSPZv+P/DWXeH9yyFtqD0nBdK5l38AD/UT711+FDivRPox07pHeP5BxRV92 XuyNF4pNHgfndsDiChXy3SGi+ERKDwz/GJvaTPPk9X8kxm5WI0nbdDZfwC6kbzjNIQXcmVwp7oP WcHpES5GBvJY+j2eQ7A== X-Proofpoint-ORIG-GUID: zHrYd4-axRbu28OfRnqLc_QTBJsJX__4 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfX8Mi3CwD23jBw UOwU3vrw/4Sb0k3jZjlPgRG25TCemz8k70XsvYImf6VMWbxqwgxg4C3MMp4z6jPG44iOulAh90q SaTndNyMmPM+O7LB8looHhMgsXn46/8= X-Authority-Analysis: v=2.4 cv=B92JFutM c=1 sm=1 tr=0 ts=6a9595fd cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=cbRFlhSh8nMfZDnRg2QA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Add support for Scalable Vector Extension (SVE) in ARM64 guests running on s390 hardware, providing 128-bit vector operations backed by s390's Vector Extension (VX). The implementation is limited to 128-bit vectors (VQ=3D1) matching s390 VX register width. Z registers reuse existing FP/SIMD register space (vregs), while P registers and FFR are stored in the SAE block. This enables ARM64 guests to use basic SVE instructions while maintaining compatibility with s390 hardware capabilities. Co-developed-by: Friedrich Welter Signed-off-by: Friedrich Welter Signed-off-by: Steffen Eiden --- arch/s390/include/asm/kvm_host_arm64.h | 6 +- arch/s390/kvm/arm64/arm.c | 7 + arch/s390/kvm/arm64/feature.c | 9 +- arch/s390/kvm/arm64/feature.h | 10 ++ arch/s390/kvm/arm64/guest.c | 204 +++++++++++++++++++++++++ arch/s390/kvm/arm64/reset.c | 22 ++- 6 files changed, 253 insertions(+), 5 deletions(-) diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm= /kvm_host_arm64.h index c0e8fbddc9dc..73eb09e98848 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -31,8 +31,9 @@ bool cpus_have_final_cap(unsigned int num); =20 #define KVM_HAVE_MMU_RWLOCK #define KVM_MAX_VCPUS 1 -#define KVM_S390_ARM64_IMPL_FEATURES \ - (BIT(KVM_ARM_VCPU_PTRAUTH_ADDRESS) | BIT(KVM_ARM_VCPU_PTRAUTH_GENERIC)) +#define KVM_S390_ARM64_IMPL_FEATURES ( \ + BIT(KVM_ARM_VCPU_SVE) \ +) =20 #define KVM_HALT_POLL_NS_DEFAULT 50000 =20 @@ -132,7 +133,6 @@ struct kvm_vcpu_stat { }; =20 #define kvm_has_mte(_kvm) false -#define vcpu_has_sve(_vcpu) false #define vcpu_has_ptrauth(_vcpu) false =20 struct kvm_arch_memory_slot { diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index d2ff69422217..a46c9c62a5f9 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -22,6 +22,7 @@ #include =20 #include "arm.h" +#include "feature.h" #include "handle_exit.h" #include "qaaf.h" #include "feature.h" @@ -53,6 +54,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ex= t) case KVM_CAP_IOEVENTFD: ret =3D 1; break; + case KVM_CAP_ARM_SVE: + ret =3D system_supports_sve(); + break; default: ret =3D 0; } @@ -258,6 +262,9 @@ static unsigned long system_supported_vcpu_features(voi= d) { unsigned long features =3D KVM_S390_ARM64_IMPL_FEATURES; =20 + if (!system_supports_sve()) + clear_bit(KVM_ARM_VCPU_SVE, &features); + return features; } =20 diff --git a/arch/s390/kvm/arm64/feature.c b/arch/s390/kvm/arm64/feature.c index 39c8ae7e951c..3847cdd2f92b 100644 --- a/arch/s390/kvm/arm64/feature.c +++ b/arch/s390/kvm/arm64/feature.c @@ -56,7 +56,6 @@ int __init kvm_arm_host_sanitize_features(struct qaaf_qmc= _block *qaaf_qmc) MASK_RESERVED(qaaf_qmc, ID_AA64MMFR4_EL1); =20 MODIFY(qaaf_qmc, ID_AA64PFR0_EL1, SEL2, NI); - MODIFY(qaaf_qmc, ID_AA64PFR0_EL1, SVE, NI); MASK_RESERVED(qaaf_qmc, ID_AA64PFR0_EL1); MASK_RESERVED(qaaf_qmc, ID_AA64PFR1_EL1); MASK_RESERVED(qaaf_qmc, ID_AA64PFR2_EL1); @@ -163,3 +162,11 @@ bool cpus_have_final_cap(unsigned int num) return false; } } + +bool system_supports_sve(void) +{ + return cpu_has_vx() && + SYS_FIELD_GET(ID_AA64PFR0_EL1, SVE, + read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) =3D=3D + ID_AA64PFR0_EL1_SVE_IMP; +} diff --git a/arch/s390/kvm/arm64/feature.h b/arch/s390/kvm/arm64/feature.h index 9c902df1f26c..892cf8bcf3a1 100644 --- a/arch/s390/kvm/arm64/feature.h +++ b/arch/s390/kvm/arm64/feature.h @@ -5,9 +5,13 @@ =20 #include #include +#include =20 #include =20 +#include +#include + #include "qaaf.h" =20 int __init kvm_arm_host_sanitize_features(struct qaaf_qmc_block *qaaf_qmc); @@ -84,4 +88,10 @@ static inline u64 kvm_sae_irptc(void) =20 #define kvm_vcpu_has_pmu(_v) false =20 +#define vcpu_has_sve(_vcpu) \ + (system_supports_sve() && \ + test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &((_vcpu)->kvm)->arch.flags)) + +bool system_supports_sve(void); + #endif /* ARCH_S390_KVM_FEATURE_H */ diff --git a/arch/s390/kvm/arm64/guest.c b/arch/s390/kvm/arm64/guest.c index 047460975936..63fc4a64ab48 100644 --- a/arch/s390/kvm/arm64/guest.c +++ b/arch/s390/kvm/arm64/guest.c @@ -5,6 +5,9 @@ #include #include #include +#include + +#include "feature.h" =20 #define SVE_VQ_MIN __SVE_VQ_MIN #define SVE_NUM_ZREGS KVM_ARM64_SVE_NUM_ZREGS @@ -52,6 +55,197 @@ const struct kvm_stats_header kvm_vcpu_stats_header =3D= { sizeof(kvm_vcpu_stats_desc), }; =20 +static int sve_zreg_index(__u64 id, unsigned int *regnum) +{ + /* Currently only one slice is supported on arm, and our zreg is only 128= bit */ + const u64 zreg_id_max =3D KVM_REG_ARM64_SVE_ZREG(KVM_ARM64_SVE_NUM_ZREGS = - 1, + KVM_ARM64_SVE_MAX_SLICES - 1); + const u64 zreg_id_min =3D KVM_REG_ARM64_SVE_ZREG(0, 0); + + if (id < zreg_id_min || id > zreg_id_max) + return -EINVAL; + if ((id & SVE_REG_SLICE_MASK) > 0) + return -ENOENT; + + *regnum =3D (id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; + + return 0; +} + +static int sve_preg_index(u64 id, unsigned int *regnum) +{ + const u64 preg_id_max =3D KVM_REG_ARM64_SVE_FFR(KVM_ARM64_SVE_MAX_SLICES = - 1); + const u64 preg_id_min =3D KVM_REG_ARM64_SVE_PREG(0, 0); + + if (id < preg_id_min || id > preg_id_max) + return -EINVAL; + if ((id & SVE_REG_SLICE_MASK) > 0) + return -ENOENT; + + *regnum =3D (id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; + + return 0; +} + +static int sve_ffr_index(u64 id, unsigned int *regnum) +{ + if (id !=3D KVM_REG_ARM64_SVE_FFR(0)) + return -EINVAL; + if ((id & SVE_REG_SLICE_MASK) > 0) + return -ENOENT; + + *regnum =3D (id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; + + return 0; +} + +static inline int get_sve_ffr_reg(struct kvm_vcpu *vcpu, unsigned int regn= um, + u16 __user *uptr) +{ + /* ffr is pregmax + 1 */ + if (regnum !=3D KVM_ARM64_SVE_NUM_PREGS) + return -EINVAL; + + if (put_user(vcpu->arch.sae_block.sve_ffr, uptr)) + return -EFAULT; + return 0; +} + +static inline int get_sve_preg(struct kvm_vcpu *vcpu, unsigned int regnum, + u16 __user *uptr) +{ + if (regnum < 0 || regnum >=3D KVM_ARM64_SVE_NUM_PREGS) + return -EINVAL; + + if (put_user(vcpu->arch.sae_block.sve_pregs[regnum], uptr)) + return -EFAULT; + return 0; +} + +static inline int get_sve_zreg(struct kvm_vcpu *vcpu, unsigned int regnum, + __vector128 __user *uptr) +{ + if (regnum < 0 || regnum >=3D KVM_ARM64_SVE_NUM_ZREGS) + return -EINVAL; + + /* vreg and svreg overlap and zreg is also just 128 bit so we reuse the v= reg space */ + if (copy_to_user(uptr, &vcpu->arch.ctxt.vregs[regnum], + sizeof(vcpu->arch.ctxt.vregs[regnum]))) + return -EFAULT; + return 0; +} + +static inline int set_sve_ffr_reg(struct kvm_vcpu *vcpu, unsigned int regn= um, + const u16 __user *uptr) +{ + /* ffr is pregmax + 1*/ + if (regnum !=3D KVM_ARM64_SVE_NUM_PREGS) + return -EINVAL; + + if (get_user(vcpu->arch.sae_block.sve_ffr, uptr)) + return -EFAULT; + return 0; +} + +static inline int set_sve_preg(struct kvm_vcpu *vcpu, unsigned int regnum, + const u16 __user *uptr) +{ + if (regnum < 0 || regnum >=3D KVM_ARM64_SVE_NUM_PREGS) + return -EINVAL; + + if (get_user(vcpu->arch.sae_block.sve_pregs[regnum], uptr)) + return -EFAULT; + return 0; +} + +static inline int set_sve_zreg(struct kvm_vcpu *vcpu, unsigned int regnum, + const __vector128 __user *uptr) +{ + if (regnum < 0 || regnum >=3D KVM_ARM64_SVE_NUM_ZREGS) + return -EINVAL; + + /*vreg and svreg overlap and zreg is also just 128 bit so we reuse the vr= eg space*/ + if (copy_from_user(&vcpu->arch.ctxt.vregs[regnum], uptr, + sizeof(vcpu->arch.ctxt.vregs[regnum]))) + return -EFAULT; + return 0; +} + +static int set_sve_vls(struct kvm_vcpu *vcpu, const void __user *uptr) +{ + u64 vqs[KVM_ARM64_SVE_VLS_WORDS] =3D { 0 }; + unsigned int vq; + + if (!vcpu_has_sve(vcpu)) + return -ENOENT; + + if (kvm_arm_vcpu_sve_finalized(vcpu)) + return -EPERM; + + if (copy_from_user(vqs, uptr, sizeof(vqs))) + return -EFAULT; + + /* only 128 bit and 1 VQ are supported , nothing saved just check validit= y */ + for (vq =3D KVM_ARM64_SVE_VQ_MIN + 1; vq <=3D KVM_ARM64_SVE_VQ_MAX; ++vq) + if (vq_present(vqs, vq)) + return -EINVAL; + + /* run with a vl of 0 not valid */ + if (!vq_present(vqs, KVM_ARM64_SVE_VQ_MIN)) + return -EINVAL; + + return 0; +} + +static int get_sve_vls(struct kvm_vcpu *vcpu, void __user *uptr) +{ + u64 vqs[KVM_ARM64_SVE_VLS_WORDS] =3D { 0 }; + + /* currently only 128 bit are supported so we only set bit 0 hardcoded */ + vqs[0] |=3D vq_mask(KVM_ARM64_SVE_VQ_MIN); + + if (copy_to_user(uptr, vqs, sizeof(vqs))) + return -EFAULT; + + return 0; +} + +static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + void __user *uptr =3D (void __user *)reg->addr; + unsigned int regnum; + int ret =3D -EFAULT; + + if (reg->id =3D=3D KVM_REG_ARM64_SVE_VLS) + ret =3D get_sve_vls(vcpu, uptr); + else if (sve_ffr_index(reg->id, ®num) >=3D 0) + ret =3D get_sve_ffr_reg(vcpu, regnum, uptr); + else if (sve_preg_index(reg->id, ®num) >=3D 0) + ret =3D get_sve_preg(vcpu, regnum, uptr); + else if (sve_zreg_index(reg->id, ®num) >=3D 0) + ret =3D get_sve_zreg(vcpu, regnum, uptr); + + return ret; +} + +static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + const void __user *uptr =3D (const void __user *)reg->addr; + int ret =3D -EFAULT; + unsigned int regnum; + + if (reg->id =3D=3D KVM_REG_ARM64_SVE_VLS) + ret =3D set_sve_vls(vcpu, uptr); + else if (sve_ffr_index(reg->id, ®num) >=3D 0) + ret =3D set_sve_ffr_reg(vcpu, regnum, uptr); + else if (sve_preg_index(reg->id, ®num) >=3D 0) + ret =3D set_sve_preg(vcpu, regnum, uptr); + else if (sve_zreg_index(reg->id, ®num) >=3D 0) + ret =3D set_sve_zreg(vcpu, regnum, uptr); + + return ret; +} + int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) { int ret; @@ -61,6 +255,11 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64= __user *uindices) return ret; uindices +=3D ret; =20 + ret =3D copy_sve_reg_indices(vcpu, uindices); + if (ret < 0) + return ret; + uindices +=3D ret; + return kvm_arm_copy_sys_reg_indices(vcpu, uindices); } =20 @@ -68,6 +267,7 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) { unsigned long num =3D num_core_regs(vcpu); =20 + num +=3D num_sve_regs(vcpu); num +=3D kvm_arm_num_sys_reg_descs(vcpu); return num; } @@ -81,6 +281,8 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct = kvm_one_reg *reg) switch (reg->id & KVM_REG_ARM_COPROC_MASK) { case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg); + case KVM_REG_ARM64_SVE: + return get_sve_reg(vcpu, reg); default: return kvm_arm_sys_reg_get_reg(vcpu, reg); } @@ -95,6 +297,8 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct = kvm_one_reg *reg) switch (reg->id & KVM_REG_ARM_COPROC_MASK) { case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg); + case KVM_REG_ARM64_SVE: + return set_sve_reg(vcpu, reg); default: return kvm_arm_sys_reg_set_reg(vcpu, reg); } diff --git a/arch/s390/kvm/arm64/reset.c b/arch/s390/kvm/arm64/reset.c index bc7bcee75779..754c4d4a70b6 100644 --- a/arch/s390/kvm/arm64/reset.c +++ b/arch/s390/kvm/arm64/reset.c @@ -3,6 +3,8 @@ #include #include =20 +#include "asm/cpufeature.h" + #include #include #include @@ -11,9 +13,13 @@ #include =20 #include "qaaf.h" +#include "feature.h" =20 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) { + if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu)) + return false; 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charset="utf-8" Promote the pointer authentication capability if supported by hardware. Signed-off-by: Steffen Eiden --- arch/s390/include/asm/kvm_host_arm64.h | 8 ++------ arch/s390/kvm/arm64/arm.c | 9 +++++++++ arch/s390/kvm/arm64/feature.c | 18 ++++++++++++++++++ arch/s390/kvm/arm64/feature.h | 5 +++++ 4 files changed, 34 insertions(+), 6 deletions(-) diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm= /kvm_host_arm64.h index 73eb09e98848..32facf045704 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -32,6 +32,8 @@ bool cpus_have_final_cap(unsigned int num); #define KVM_HAVE_MMU_RWLOCK #define KVM_MAX_VCPUS 1 #define KVM_S390_ARM64_IMPL_FEATURES ( \ + BIT(KVM_ARM_VCPU_PTRAUTH_ADDRESS) | \ + BIT(KVM_ARM_VCPU_PTRAUTH_GENERIC) | \ BIT(KVM_ARM_VCPU_SVE) \ ) =20 @@ -133,7 +135,6 @@ struct kvm_vcpu_stat { }; =20 #define kvm_has_mte(_kvm) false -#define vcpu_has_ptrauth(_vcpu) false =20 struct kvm_arch_memory_slot { }; @@ -170,11 +171,6 @@ struct kvm_vm_stat { struct kvm_vm_stat_generic generic; }; =20 -static inline bool system_has_full_ptr_auth(void) -{ - return true; -} - #define kvm_vm_is_protected(_kvm) false #define vcpu_is_protected(_vcpu) false =20 diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index a46c9c62a5f9..ebd8045c0900 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -57,6 +57,10 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long e= xt) case KVM_CAP_ARM_SVE: ret =3D system_supports_sve(); break; + case KVM_CAP_ARM_PTRAUTH_ADDRESS: + case KVM_CAP_ARM_PTRAUTH_GENERIC: + ret =3D kvm_has_full_ptr_auth(); + break; default: ret =3D 0; } @@ -265,6 +269,11 @@ static unsigned long system_supported_vcpu_features(vo= id) if (!system_supports_sve()) clear_bit(KVM_ARM_VCPU_SVE, &features); =20 + if (!kvm_has_full_ptr_auth()) { + clear_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, &features); + clear_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, &features); + } + return features; } =20 diff --git a/arch/s390/kvm/arm64/feature.c b/arch/s390/kvm/arm64/feature.c index 3847cdd2f92b..a2848e4b3e62 100644 --- a/arch/s390/kvm/arm64/feature.c +++ b/arch/s390/kvm/arm64/feature.c @@ -170,3 +170,21 @@ bool system_supports_sve(void) read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) =3D=3D ID_AA64PFR0_EL1_SVE_IMP; } + +bool system_has_full_ptr_auth(void) +{ + u64 isar1 =3D read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1); + u64 isar2 =3D read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); + bool address_auth; + bool generic_auth; + + address_auth =3D SYS_FIELD_GET(ID_AA64ISAR1_EL1, APA, isar1) >=3D ID_AA64= ISAR1_EL1_APA_PAuth || + SYS_FIELD_GET(ID_AA64ISAR1_EL1, API, isar1) >=3D ID_AA64ISAR1_EL1= _API_PAuth || + SYS_FIELD_GET(ID_AA64ISAR2_EL1, APA3, isar2) >=3D ID_AA64ISAR2_EL= 1_APA3_PAuth; + + generic_auth =3D SYS_FIELD_GET(ID_AA64ISAR1_EL1, GPA, isar1) >=3D ID_AA64= ISAR1_EL1_GPA_IMP || + SYS_FIELD_GET(ID_AA64ISAR1_EL1, GPI, isar1) >=3D ID_AA64ISAR1_EL1= _GPI_IMP || + SYS_FIELD_GET(ID_AA64ISAR2_EL1, GPA3, isar2) >=3D ID_AA64ISAR2_EL= 1_GPA3_IMP; + + return address_auth && generic_auth; +} diff --git a/arch/s390/kvm/arm64/feature.h b/arch/s390/kvm/arm64/feature.h index 892cf8bcf3a1..c11ac0daa428 100644 --- a/arch/s390/kvm/arm64/feature.h +++ b/arch/s390/kvm/arm64/feature.h @@ -94,4 +94,9 @@ static inline u64 kvm_sae_irptc(void) =20 bool system_supports_sve(void); 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Mon, 31 Aug 2026 14:55:54 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4gcarjxgck-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Aug 2026 14:55:54 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67VEtlu545416924 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Aug 2026 14:55:47 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 924D320040; Mon, 31 Aug 2026 14:55:47 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 223DD20043; Mon, 31 Aug 2026 14:55:47 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 14:55:47 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v2 20/20] s390: Report AEF features to sysfs Date: Mon, 31 Aug 2026 16:55:35 +0200 Message-ID: <20260831145536.913567-21-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831145536.913567-1-seiden@linux.ibm.com> References: <20260831145536.913567-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: cgKoid8oBZbsBqN5flcpESsmNzrk2mQ_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfXwxTMr/h3bS1j VmZTGZ4PRF5/SDMgv1xykVVMizcyGEUBSuBO75VyzvP8KXmPqhNIJzQ4ZoAxCzSnjbUz8eLFVrp NnsMJtAax7UvFrenjpX3tI6Asld0TE/KYuuHX+AhNtVhM59eXcECce51ByElD2XNc0i5UfkMzUV 0gBPVKZk4Sg9foiqXOHhz8d+mdX1tViPZGR/coaZXk9X3FR5I/IhFIzn3xBOz2SSaPQT79FuJ2z KvBCYJUkpnu3CWvRo824AEhRYNapMSls21dzhBriCD6wUYDL7tdzNpHdpadTgrgHHAONWOQvZP2 aM8L9mh2H0k2VYMLuBsPyn70zSMk70GbmGW0Eyo7GOqCdydyd7rFbEtWoEt6A8LsBQRQJFfRiJJ 6qjgLFAqgUEbcPqMB1PlaP/0jA0G+LNJd2TH1Lgb0Cco5bi+xThhhU/7rT4d5uPp6z1b6uyT5Xa kxqraRVpLEmObkc8hnA== X-Authority-Analysis: v=2.4 cv=Osl/DS/t c=1 sm=1 tr=0 ts=6a9595fb cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=Q6p9WaQqMra0dl70cWIA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyNSBTYWx0ZWRfXwp6HT7Fc9dbO iOieHxbselxGXAc7QPqfaU9ina+gGu3leKxZj2M5DtOVMR3KOmxSjCRVp23ehjpzKbOSRqAZyLb XUFYGOmeplAcQb4Ej80OSz7XkW7D0L0= X-Proofpoint-ORIG-GUID: EH6jG6WzePSfrBc3sqxsZLrZsQ3wltoZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310125 Content-Type: text/plain; charset="utf-8" Display various information about the Arm execution Facility (AEF) to userspace. The files are located in /sys/firmware/aef/. Show if the feature is available and usable for the host, which formats are available, and how many arm vCPUS per guest are supported by the machine. Additionally, provide the raw binary output of QAAF fc1 (Query Model Capabilities) in the file qmc and fc2 (Initial System-Registers-Save Area) in the file save_area. Co-developed-by: Janosch Frank Signed-off-by: Janosch Frank Signed-off-by: Steffen Eiden --- arch/s390/kernel/aef.c | 86 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/s390/kernel/aef.c b/arch/s390/kernel/aef.c index 825e2643a892..2691f1ac63dc 100644 --- a/arch/s390/kernel/aef.c +++ b/arch/s390/kernel/aef.c @@ -40,6 +40,66 @@ const struct aef_info *aef_info(void) } EXPORT_SYMBOL(aef_info); =20 +static struct kset *aef_query_kset; +static struct kobject *aef_kobj; + +#define aef_sysfs_qval_def(_name) \ + static ssize_t _name##_show(struct kobject *kobj, \ + struct kobj_attribute *attr, \ + char *buf) \ + { \ + return sysfs_emit(buf, "%lx\n", info._name); \ + } \ + static struct kobj_attribute _name##_attr =3D __ATTR_RO(_name) + +#define aef_sysfs_qval_attr(_name) &_name##_attr.attr + +aef_sysfs_qval_def(arm_guest_supp); +aef_sysfs_qval_def(sae_avail); +aef_sysfs_qval_def(ptff_avail); +aef_sysfs_qval_def(supp_state_desc_formats); +aef_sysfs_qval_def(supp_save_area_formats); +aef_sysfs_qval_def(max_num_vcpu); + +static ssize_t qmc_read(struct file *filp, struct kobject *kobj, + const struct bin_attribute *attr, char *buf, loff_t off, + size_t count) +{ + return memory_read_from_buffer(buf, count, &off, &qmc, sizeof(qmc)); +} + +BIN_ATTR_RO(qmc, sizeof(qmc)); + +static ssize_t save_area_read(struct file *filp, struct kobject *kobj, + const struct bin_attribute *attr, char *buf, + loff_t off, size_t count) +{ + return memory_read_from_buffer(buf, count, &off, &save_area, + sizeof(save_area)); +} + +BIN_ATTR_RO(save_area, sizeof(save_area)); + +static struct attribute *aef_query_attrs[] =3D { + aef_sysfs_qval_attr(sae_avail), + aef_sysfs_qval_attr(ptff_avail), + aef_sysfs_qval_attr(supp_state_desc_formats), + aef_sysfs_qval_attr(supp_save_area_formats), + aef_sysfs_qval_attr(max_num_vcpu), + NULL, +}; + +static const struct bin_attribute *aef_query_bin_attrs[] =3D { + &bin_attr_qmc, + &bin_attr_save_area, + NULL, +}; + +static struct attribute_group aef_query_attr_group =3D { + .attrs =3D aef_query_attrs, + .bin_attrs =3D aef_query_bin_attrs, +}; + static int __init aef_init_save_area(void) { int ret; @@ -95,7 +155,33 @@ static int __init aef_sysfs_init(void) if (rc) return rc; =20 + aef_kobj =3D kobject_create_and_add("aef", firmware_kobj); + if (!aef_kobj) + return -ENOMEM; + + rc =3D sysfs_create_file(aef_kobj, aef_sysfs_qval_attr(arm_guest_supp)); + if (rc) + goto out_kobj; + + aef_query_kset =3D kset_create_and_add("query", NULL, aef_kobj); + if (!aef_query_kset) + goto out_arm_guest_supp; + + rc =3D sysfs_create_group(&aef_query_kset->kobj, &aef_query_attr_group); + if (rc) + goto out_kset; + return 0; + +out_kset: + kset_unregister(aef_query_kset); +out_arm_guest_supp: + sysfs_remove_file(aef_kobj, &arm_guest_supp_attr.attr); +out_kobj: + kobject_del(aef_kobj); + kobject_put(aef_kobj); + + return rc; } =20 arch_initcall(aef_sysfs_init); --=20 2.53.0