From nobody Sat Sep 26 19:35:59 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 50AE235BDCE; Mon, 31 Aug 2026 09:54:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788170085; cv=none; b=EP6V97uKKB8B8wpuEoU4kiy8zcojLYwM8jTlo07NMKAPONmnXxx0WKs45ikNKJL69lBfg1nX0+JbwgL2wsjedg9Alo09BCb3WhkomcCsqR5dW9GEeytaVCfK760yb+KIRMepBMscpg8gxe3h3ZtjFeOcUlVWGyOW4NYvNmCiLYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788170085; c=relaxed/simple; bh=nfjpZUMOYFDQLVcfDwAxQZxMqqvBDp/2lMAhNMXWNFE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r8316sGEXQfG6vyg4346nVn5TItqwgokxAw8OZJZ1C0Tm913LsAEN2amUEXZBgt/FqHOmgAlriFW4iVjMGcoJKnJxy+Q/g98dU898c68y0Zdydh+sVybF9L4hB/dBVXtQ1KAwwu57yWUleiL6VVV5xQWoqRx8rIuSog/8wKlJUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxW_BgT5Vqvt0GAA--.19424S3; Mon, 31 Aug 2026 17:54:40 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxKs5eT5VqDTYYAA--.20453S3; Mon, 31 Aug 2026 17:54:39 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] LoongArch: KVM: Add vmid support for stage2 MMU Date: Mon, 31 Aug 2026 17:47:14 +0800 Message-Id: <20260831094716.4016652-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260831094716.4016652-1-maobibo@loongson.cn> References: <20260831094716.4016652-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxKs5eT5VqDTYYAA--.20453S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" LoongArch KVM hypervisor supports two-level MMU, vpid index is used for stage1 MMU and vmid index is used for stage2 MMU. On 3A5000, vmid must be the same with vpid. On 3A6000 platform vmid may separate from vpid. If vCPU migrate to different physical CPUs, vpid need change however vmid can keep unchanged, so that TLB entries for stage2 MMU is valid still. Also vmid index of the whole VM machine is the same on one physical CPU, all vCPUs on the VM can share the same vmid index on one physical CPU. Similar with ASID, there is different ID management to support multiple VMs and vCPUs, the corresponding ID management function is __kvm_check_vpid() and __kvm_check_vmid(). Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_host.h | 3 +++ arch/loongarch/kernel/asm-offsets.c | 1 + arch/loongarch/kvm/main.c | 20 ++++++++++++++++++-- arch/loongarch/kvm/switch.S | 5 ++--- arch/loongarch/kvm/tlb.c | 5 ++++- 5 files changed, 28 insertions(+), 6 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include= /asm/kvm_host.h index 23cfbecebbd7..5c2f76d1e2f8 100644 --- a/arch/loongarch/include/asm/kvm_host.h +++ b/arch/loongarch/include/asm/kvm_host.h @@ -232,6 +232,9 @@ struct kvm_vcpu_arch { /* Cache for pages needed inside spinlock regions */ struct kvm_mmu_memory_cache mmu_page_cache; =20 + /* hw vmid info for guest VM */ + unsigned long tgid; + /* vcpu's vpid */ u64 vpid; gpa_t flush_gpa; diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/as= m-offsets.c index 1b861cbc5e10..f1ad3d57eadd 100644 --- a/arch/loongarch/kernel/asm-offsets.c +++ b/arch/loongarch/kernel/asm-offsets.c @@ -300,6 +300,7 @@ static void __used output_kvm_defines(void) OFFSET(KVM_ARCH_HSP, kvm_vcpu_arch, host_sp); OFFSET(KVM_ARCH_HTP, kvm_vcpu_arch, host_tp); OFFSET(KVM_ARCH_HPGD, kvm_vcpu_arch, host_pgd); + OFFSET(KVM_ARCH_VMID, kvm_vcpu_arch, tgid); OFFSET(KVM_ARCH_KVMPGD, kvm_vcpu_arch, kvm_pgd); OFFSET(KVM_ARCH_HANDLE_EXIT, kvm_vcpu_arch, handle_exit); OFFSET(KVM_ARCH_HEENTRY, kvm_vcpu_arch, host_eentry); diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index 3e1005526f4b..a98f0284134a 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -225,7 +225,7 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int = cpu) vcpu->arch.vpid =3D vpid; } =20 -void kvm_check_vpid(struct kvm_vcpu *vcpu) +static void __kvm_check_vpid(struct kvm_vcpu *vcpu) { int cpu; bool migrated; @@ -253,7 +253,6 @@ void kvm_check_vpid(struct kvm_vcpu *vcpu) kvm_update_vpid(vcpu, cpu); trace_kvm_vpid_change(vcpu, vcpu->arch.vpid); vcpu->cpu =3D cpu; - kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); =20 /* * LLBCTL is a separated guest CSR register from host, a general @@ -279,6 +278,23 @@ void kvm_check_vpid(struct kvm_vcpu *vcpu) } } =20 +static void __kvm_check_vmid(struct kvm_vcpu *vcpu) +{ + unsigned long vmid; + + vmid =3D vcpu->arch.vpid & vpid_mask; + if (vcpu->arch.tgid !=3D vmid) { + vcpu->arch.tgid =3D vcpu->arch.vpid & vpid_mask; + kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + } +} + +void kvm_check_vpid(struct kvm_vcpu *vcpu) +{ + __kvm_check_vpid(vcpu); + __kvm_check_vmid(vcpu); +} + void kvm_init_vmcs(struct kvm *kvm) { kvm->arch.vmcs =3D vmcs; diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S index 936e4ae3e408..af972394fd55 100644 --- a/arch/loongarch/kvm/switch.S +++ b/arch/loongarch/kvm/switch.S @@ -66,9 +66,8 @@ ld.d t0, a2, KVM_ARCH_KVMPGD csrwr t0, LOONGARCH_CSR_PGDL =20 - /* Mix GID and RID */ - csrrd t1, LOONGARCH_CSR_GSTAT - bstrpick.w t1, t1, CSR_GSTAT_GID_SHIFT_END, CSR_GSTAT_GID_SHIFT + /* Set VMID for gpa --> hpa mapping */ + ld.d t1, a2, KVM_ARCH_VMID csrrd t0, LOONGARCH_CSR_GTLBC bstrins.w t0, t1, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT csrwr t0, LOONGARCH_CSR_GTLBC diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c index ebdbe9264e9c..afcacb62988a 100644 --- a/arch/loongarch/kvm/tlb.c +++ b/arch/loongarch/kvm/tlb.c @@ -23,7 +23,10 @@ void kvm_flush_tlb_all(void) =20 void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa) { + unsigned int vmid; + lockdep_assert_irqs_disabled(); gpa &=3D (PAGE_MASK << 1); - invtlb(INVTLB_GID_ADDR, read_csr_gstat() & CSR_GSTAT_GID, gpa); + vmid =3D (vcpu->arch.tgid << CSR_GSTAT_GID_SHIFT) & CSR_GSTAT_GID; + invtlb(INVTLB_GID_ADDR, vmid, gpa); } --=20 2.39.3 From nobody Sat Sep 26 19:35:59 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 05A6D3CF201; Mon, 31 Aug 2026 09:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788170085; cv=none; b=AnStX+ZuEd712lhgp+BE8ZeKLDsWOk+BRFX2E63pqNU96PBXU14A6U5qhaKs8JmNO4nRsiUpCfpIiElAa4mLlQDX+qUPbw3zA4FBUHTJOC9ZbU6dLpRBn7mfhOwqU6N2lxrjKPTCXmmIE35oH7pk5LwAkyXzaCsyqUZMBBzfTpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788170085; c=relaxed/simple; bh=R3R1jTkrD7xCKzb6vZI8gU7hsmNtfk0+vBBFFAfVGJk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G8zYtAw7arw8xeUsCIvqJpTaQnZImbUZouv0MzbDlYrVm3ZphHPcwY9zvQ3jxO34Vs2pWZF8D/fqIliAAAnVZg2iVP4PVeYelRR8H4sehJz3TDXIwylbaoHQ3LyDW9dzW0Pf4qUEcjqXasMxVzEGPrh0/Caav0fmFo4YJvLW6q8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxLtNgT5Vqx90GAA--.19278S3; Mon, 31 Aug 2026 17:54:40 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxKs5eT5VqDTYYAA--.20453S4; Mon, 31 Aug 2026 17:54:39 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] LoongArch: KVM: Implement vmid updating logic Date: Mon, 31 Aug 2026 17:47:15 +0800 Message-Id: <20260831094716.4016652-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260831094716.4016652-1-maobibo@loongson.cn> References: <20260831094716.4016652-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxKs5eT5VqDTYYAA--.20453S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" VMID calculation method is the same with ASID on LoongArch, it is percpu vmid calculation method. For every physical CPU, VMID of different VM is different, and it is the same for different vCPUs of the same VM. When vCPU is scheduled on the physical CPU, it checked vmid of this VM and the global cached vmid, and judge whether it is valid or not. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_host.h | 7 ++++ arch/loongarch/kvm/main.c | 55 ++++++++++++++++++++++++--- arch/loongarch/kvm/mmu.c | 30 +++++++++++++-- arch/loongarch/kvm/tlb.c | 14 +++++++ 4 files changed, 97 insertions(+), 9 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include= /asm/kvm_host.h index 5c2f76d1e2f8..8273122604d8 100644 --- a/arch/loongarch/include/asm/kvm_host.h +++ b/arch/loongarch/include/asm/kvm_host.h @@ -79,6 +79,7 @@ struct kvm_arch_memory_slot { #define HOST_MAX_PMNUM 16 struct kvm_context { unsigned long vpid_cache; + unsigned long vmid_cache; struct kvm_vcpu *last_vcpu; /* Host PMU CSR */ u64 perf_ctrl[HOST_MAX_PMNUM]; @@ -132,6 +133,8 @@ struct kvm_arch { unsigned long kvm_features; =20 s64 time_offset; + cpumask_t tlb_flush_pending; + unsigned long vmid[NR_CPUS]; struct kvm_context __percpu *vmcs; struct loongarch_ipi *ipi; struct loongarch_dmsintc *dmsintc; @@ -319,6 +322,8 @@ bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu); int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); =20 /* MMU handling */ +void kvm_flush_tlb_all_stage1(void); +void kvm_flush_tlb_all_stage2(void); void kvm_flush_tlb_all(void); void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa); int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long badv, bool wr= ite, int ecode); @@ -353,6 +358,8 @@ static inline void kvm_arch_vcpu_block_finish(struct kv= m_vcpu *vcpu) {} static inline void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memor= y_slot *slot) {} void kvm_check_vpid(struct kvm_vcpu *vcpu); enum hrtimer_restart kvm_swtimer_wakeup(struct hrtimer *timer); +#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS +int kvm_arch_flush_remote_tlbs(struct kvm *kvm); void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, const struct kvm_= memory_slot *memslot); void kvm_init_vmcs(struct kvm *kvm); void kvm_exc_entry(void); diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index a98f0284134a..0099d0f0b803 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -218,7 +218,10 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int= cpu) ++vpid; /* vpid 0 reserved for root */ =20 /* start new vpid cycle */ - kvm_flush_tlb_all(); + if (!cpu_has_guestid) + kvm_flush_tlb_all(); + else + kvm_flush_tlb_all_stage1(); } =20 context->vpid_cache =3D vpid; @@ -278,15 +281,54 @@ static void __kvm_check_vpid(struct kvm_vcpu *vcpu) } } =20 -static void __kvm_check_vmid(struct kvm_vcpu *vcpu) +static void kvm_update_vmid(struct kvm_vcpu *vcpu, int cpu) { unsigned long vmid; + struct kvm_context *context; + + context =3D per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu); + vmid =3D context->vmid_cache + 1; + if (!(vmid & vpid_mask)) { + /* finish round of vmid loop */ + if (unlikely(!vmid)) + vmid =3D vpid_mask + 1; + + ++vmid; /* vmid 0 reserved for root */ + + /* start new vmid cycle */ + kvm_flush_tlb_all_stage2(); + } + + context->vmid_cache =3D vmid; + vcpu->kvm->arch.vmid[cpu] =3D vmid; +} =20 - vmid =3D vcpu->arch.vpid & vpid_mask; - if (vcpu->arch.tgid !=3D vmid) { - vcpu->arch.tgid =3D vcpu->arch.vpid & vpid_mask; - kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); +static void __kvm_check_vmid(struct kvm_vcpu *vcpu) +{ + int cpu; + unsigned long ver, old, vmid; + + /* On some machines like 3A5000, vmid needs the same with vpid */ + if (!cpu_has_guestid) { + vmid =3D vcpu->arch.vpid & vpid_mask; + if (vcpu->arch.tgid !=3D vmid) { + vcpu->arch.tgid =3D vcpu->arch.vpid & vpid_mask; + kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + } + return; } + + cpu =3D smp_processor_id(); + if (cpumask_test_and_clear_cpu(cpu, &vcpu->kvm->arch.tlb_flush_pending)) + vcpu->kvm->arch.vmid[cpu] =3D 0; + + /* Check if the vmid is out of an older version */ + ver =3D vcpu->kvm->arch.vmid[cpu] & ~vpid_mask; + old =3D this_cpu_ptr(vcpu->kvm->arch.vmcs)->vmid_cache & ~vpid_mask; + if (ver !=3D old) + kvm_update_vmid(vcpu, cpu); + + vcpu->arch.tgid =3D vcpu->kvm->arch.vmid[cpu] & vpid_mask; } =20 void kvm_check_vpid(struct kvm_vcpu *vcpu) @@ -392,6 +434,7 @@ static int kvm_loongarch_env_init(void) for_each_possible_cpu(cpu) { context =3D per_cpu_ptr(vmcs, cpu); context->vpid_cache =3D vpid_mask + 1; + context->vmid_cache =3D vpid_mask + 1; context->last_vcpu =3D NULL; } =20 diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c index e104897aa532..e07ba28cc565 100644 --- a/arch/loongarch/kvm/mmu.c +++ b/arch/loongarch/kvm/mmu.c @@ -893,7 +893,12 @@ static int kvm_map_page(struct kvm_vcpu *vcpu, unsigne= d long gpa, bool write) * there is invalid tlb with small page * need flush these invalid tlbs for current vcpu */ - kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); + if (!cpu_has_ptw) { + if (!cpu_has_guestid) + kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); + else + cpumask_set_cpu(vcpu->cpu, &vcpu->kvm->arch.tlb_flush_pending); + } ++kvm->stat.hugepages; } else if (kvm_pte_huge(*ptep) && write) ptep =3D kvm_split_huge(vcpu, ptep, gfn); @@ -929,8 +934,11 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigne= d long gpa, bool write, in * * With SW PTW, invalid TLB is added in TLB refill exception. */ - vcpu->arch.flush_gpa =3D gpa; - kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + if (!cpu_has_guestid) { + vcpu->arch.flush_gpa =3D gpa; + kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + } else + cpumask_set_cpu(vcpu->cpu, &vcpu->kvm->arch.tlb_flush_pending); } =20 return 0; @@ -940,6 +948,22 @@ void kvm_arch_sync_dirty_log(struct kvm *kvm, struct k= vm_memory_slot *memslot) { } =20 +int kvm_arch_flush_remote_tlbs(struct kvm *kvm) +{ + /* + * Queue a TLB invalidation for each CPU to perform on next + * vcpu loading + */ + if (cpu_has_guestid) { + cpumask_setall(&kvm->arch.tlb_flush_pending); + /* Be sure that other CPUS can watch the changes */ + smp_wmb(); + } + + /* Return 1 continue to send ipi to running vCPUs */ + return 1; +} + void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, const struct kvm_memory_slot *memslot) { diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c index afcacb62988a..994216c98ea2 100644 --- a/arch/loongarch/kvm/tlb.c +++ b/arch/loongarch/kvm/tlb.c @@ -21,6 +21,20 @@ void kvm_flush_tlb_all(void) local_irq_restore(flags); } =20 +/* Invalidate all stage1 TLB entries including GVA-->GPA mappings */ +void kvm_flush_tlb_all_stage1(void) +{ + lockdep_assert_irqs_disabled(); + invtlb_all(INVGTLB_ALLGID_GVA_TO_GPA, 0, 0); +} + +/* Invalidate all stage2 TLB entries including GPA-->HPA mappings */ +void kvm_flush_tlb_all_stage2(void) +{ + lockdep_assert_irqs_disabled(); + invtlb_all(INVTLB_ALLGID_GPA_TO_HPA, 0, 0); +} + void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa) { unsigned int vmid; --=20 2.39.3 From nobody Sat Sep 26 19:35:59 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 05B073DB645; Mon, 31 Aug 2026 09:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788170084; cv=none; b=sxzb+hXobklP/bNEZZmehn0u5sdoIkHVYtx1MFKvDbHoPdVaFh+cRqIx9JGAmfMOh79opFJWdl70BHlO5mfrsJwBy36ymYYcchrGVHN6v9blumGMjy/QYTrSuko7dTbOHI17AjPMIRNjc/QdVBA7amaDYUAa6yDI7f6LvCQkzuA= ARC-Message-Signature: i=1; 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Mon, 31 Aug 2026 17:54:40 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] LoongArch: KVM: Enable separate vmid feature Date: Mon, 31 Aug 2026 17:47:16 +0800 Message-Id: <20260831094716.4016652-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260831094716.4016652-1-maobibo@loongson.cn> References: <20260831094716.4016652-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxKs5eT5VqDTYYAA--.20453S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With CSR GTLBC shortname for Guest TLB Control Register, separate vmid feature will be enabled if bit 14 CSR_GTLBC_USES2TGID is set. Enable this if S2TGID feature is detected from cpucfg8. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/loongarch.h | 5 +++++ arch/loongarch/kernel/cpu-probe.c | 6 ++++++ arch/loongarch/kvm/main.c | 6 ++++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 2a6bc99177d8..88e3bdfd4971 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -138,6 +138,9 @@ #define CPUCFG6_PMBITS_SHIFT 8 #define CPUCFG6_UPM BIT(14) =20 +#define LOONGARCH_CPUCFG8 0x8 +#define CPUCFG8_S2TGID BIT(8) + #define LOONGARCH_CPUCFG16 0x10 #define CPUCFG16_L1_IUPRE BIT(0) #define CPUCFG16_L1_IUUNIFY BIT(1) @@ -350,6 +353,8 @@ #define CSR_GTLBC_TGID_WIDTH 8 #define CSR_GTLBC_TGID_SHIFT_END (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_W= IDTH - 1) #define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT) +#define CSR_GTLBC_USES2TGID_SHIFT 14 +#define CSR_GTLBC_USES2TGID (_ULCAST_(0x1) << CSR_GTLBC_USES2TGID_SHIFT) #define CSR_GTLBC_TOTI_SHIFT 13 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT) #define CSR_GTLBC_USETGID_SHIFT 12 diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 74d31f260dfd..e849ebacd268 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -241,6 +241,12 @@ static void cpu_probe_common(struct cpuinfo_loongarch = *c) if (config & CPUCFG6_PMP) c->options |=3D LOONGARCH_CPU_PMP; =20 + if (c->options & LOONGARCH_CPU_LVZ) { + config =3D read_cpucfg(LOONGARCH_CPUCFG8); + if (config & CPUCFG8_S2TGID) + c->options |=3D LOONGARCH_CPU_GUESTID; + } + config =3D csr_read32(LOONGARCH_CSR_ASID); config =3D (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT; asid_mask =3D GENMASK(config - 1, 0); diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index 0099d0f0b803..e43ed4c11d31 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -358,7 +358,7 @@ int kvm_arch_enable_virtualization_cpu(void) write_csr_gcfg(0); write_csr_gstat(0); write_csr_gintc(0); - clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI); + clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USES2TGID); =20 /* * Enable virtualization features granting guest direct control of @@ -381,6 +381,8 @@ int kvm_arch_enable_virtualization_cpu(void) =20 /* Enable using TGID */ set_csr_gtlbc(CSR_GTLBC_USETGID); + if (cpu_has_guestid) + set_csr_gtlbc(CSR_GTLBC_USES2TGID); kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx", read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc()); =20 @@ -399,7 +401,7 @@ void kvm_arch_disable_virtualization_cpu(void) write_csr_gcfg(0); write_csr_gstat(0); write_csr_gintc(0); - clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI); + clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USES2TGID); =20 /* Flush any remaining guest TLB entries */ kvm_flush_tlb_all(); --=20 2.39.3