From nobody Sat Sep 26 19:35:07 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 344153C1D62 for ; Mon, 31 Aug 2026 07:01:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788159709; cv=none; b=kYnZga7g3WbaIHQZsYUQ0mpqRNKU7OhS98Yk99GGpdWRegJtPQEfiAOwVJRoVYIkx0/mvoAxSyTOi0RFvbJZJ7Jj4xfflzjrzkVxKxz1p5ah0LARRXEYv7dPL2yhixL54dyoAqg3cvsscJDiqoD81spLLUQvdq00rGq5C4E6Myk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788159709; c=relaxed/simple; bh=jlX20ZSKwhf7V5jBoOYcaZ37EYu7IOXjGdlfLGsDv1c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CvPELXP2eHmlQevmX05LgXB4v4wDHWTJlBHmxaFZIm5ttAGU2zk9rSqwDzFsHZRoFJp2od8OlV99R7kEqI+dSSOsili/GTiZp6hVtWcdBLg8tjECiRr5odFd8z6xqqPX5ZVyx5znWmHb+pX7jlFxW660YUlny8O/3bkXHjFjCys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=c9hjm12x; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="c9hjm12x" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id BCD7B4E41465; Mon, 31 Aug 2026 07:01:45 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 881F1601E1; Mon, 31 Aug 2026 07:01:45 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EBA4E11C78A03; Mon, 31 Aug 2026 09:01:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1788159700; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=OXqMCRoQXVkihjLttQXA7lMF61U2RKr6mJhVeRjSKZ4=; b=c9hjm12xDvKljAIHLcp7vSBYOqe9hu9+BboALzGB//G67CoWn3vxznJ10hQjj9qBrM389Z aeRpqlbYYwQIGISmXHYaQ6bz0gVZp5i0OKF6lUFsOaE814/Doymm+Pl1wtxXvwI5G7LQd5 RuwgE1ymIvNdV/VHrShJU4d/hy6Bbfib6kKfJD90Wi9xorBXSMEM7V+EpTXx/7rP3bM4pZ oFBr4fd7VQRTQjTiY+V2UNVycQf/wwcmSrjyWpAejAX42ni41HfbfUgeITqxgmUnp2ZtzD 0z5Ic7FrcRSY74mmywP1tLY+CPIxYiA8g4gkemkdlfq0CXTqrzqq0jvmeBZZ2w== From: Maxime Chevallier To: Andrew Lunn , Jakub Kicinski , davem@davemloft.net, Eric Dumazet , Paolo Abeni , Simon Horman , Maxime Coquelin , Alexandre Torgue , Russell King Cc: Maxime Chevallier , thomas.petazzoni@bootlin.com, =?UTF-8?q?Alexis=20Lothor=C3=A9?= , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH net-next 1/2] net: stmmac: dwmac4: Read the UC filter size from hardware capabilities Date: Mon, 31 Aug 2026 09:01:19 +0200 Message-ID: <20260831070121.349778-2-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260831070121.349778-1-maxime.chevallier@bootlin.com> References: <20260831070121.349778-1-maxime.chevallier@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" dwmac4 has multiple banks of perfect filter entries, independently configurable during IP integration. The multi_addr bank reports a number between 0 and 31 corresponding to the actual number of entries in that bank, while the 32 and 64 banks are all-or-nothing. Expose these caps over debugfs as well. Signed-off-by: Maxime Chevallier Reviewed-by: Nicolai Buchwitz --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 4 +++- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ++++++++++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/eth= ernet/stmicro/stmmac/common.h index 927ea6230073..77bd47a83357 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -419,6 +419,8 @@ struct dma_features { unsigned int half_duplex; unsigned int hash_filter; unsigned int multi_addr; + unsigned int additional_32_addr; + unsigned int additional_64_addr; unsigned int pcs; unsigned int sma_mdio; unsigned int pmt_remote_wake_up; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/eth= ernet/stmicro/stmmac/dwmac4.h index 6382836828ba..89368e34a388 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -176,7 +176,9 @@ enum power_event { =20 /* MAC HW features0 bitmap */ #define GMAC_HW_FEAT_SAVLANINS BIT(27) -#define GMAC_HW_FEAT_ADDMAC BIT(18) +#define GMAC_HW_FEAT_MACADR64SEL BIT(24) +#define GMAC_HW_FEAT_MACADR32SEL BIT(23) +#define GMAC_HW_FEAT_ADDMAC GENMASK(22, 18) #define GMAC_HW_FEAT_RXCOESEL BIT(16) #define GMAC_HW_FEAT_TXCOSEL BIT(14) #define GMAC_HW_FEAT_EEESEL BIT(13) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_dma.c index 23ffe1adcd0d..14ac3f0e51f7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -388,6 +388,8 @@ static int dwmac4_get_hw_feature(void __iomem *ioaddr, dma_cap->half_duplex =3D (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; dma_cap->vlhash =3D (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; dma_cap->multi_addr =3D (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; + dma_cap->additional_32_addr =3D (hw_cap & GMAC_HW_FEAT_MACADR32SEL) >> 23; + dma_cap->additional_64_addr =3D (hw_cap & GMAC_HW_FEAT_MACADR64SEL) >> 24; dma_cap->pcs =3D (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; dma_cap->sma_mdio =3D (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; dma_cap->pmt_remote_wake_up =3D (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index f2fc89176654..a885f8cfef21 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -6580,6 +6580,18 @@ static int stmmac_dma_cap_show(struct seq_file *seq,= void *v) seq_printf(seq, "\tNumber of Additional MAC address registers: %d\n", priv->dma_cap.multi_addr); + } else if (priv->plat->core_type =3D=3D DWMAC_CORE_GMAC4) { + seq_printf(seq, + "\tNumber of MAC address registers (1-31): %d\n", + priv->dma_cap.multi_addr); + seq_printf(seq, + "\tAdditional 32 MAC address registers (32-63): %s\n", + priv->dma_cap.additional_32_addr ? "Y" : "N"); + seq_printf(seq, + "\tAdditional 64 MAC address registers (64-127): %s\n", + priv->dma_cap.additional_64_addr ? "Y" : "N"); + seq_printf(seq, "\tHash Filter: %s\n", + (priv->dma_cap.hash_filter) ? "Y" : "N"); } else { seq_printf(seq, "\tHash Filter: %s\n", (priv->dma_cap.hash_filter) ? "Y" : "N"); --=20 2.55.0 From nobody Sat Sep 26 19:35:07 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A76A3C1D48; Mon, 31 Aug 2026 07:01:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788159711; cv=none; b=Cb9eOT0qMAN0pvu8Sy6v1ZgB6A+WSYesyzde9vFwJTsi7W1yP5e9Qhf95wVZiqxETXYD/1/AlVzqm+A2e7mrfcEvsy8jgg6yTexu8b0FVT6k2QvfzjTkBiaA9ZthBFUSFYGCB9d/BGhqlfTwJPsOv2GvV+eXuAbgsMEbrSOKUT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788159711; c=relaxed/simple; bh=vr16G4wN7hEj/Zto23NchPROMzUplCl5PfKrXcV1gd4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GFkuVxkiyA9mWUYqctUKDBYL08KLtIEC7ux86oGA3uXz6xo/b3jytrtPcR8OJINUtvyEnHz24FQL8gr3c4tPzOusaWy9PgWr7YTRrOaY2VfpXOnlpW8XpOdn4CsCT+BN+omPDLQMy1HZ0h/NneCfiG7AuTFzigEqO66c4fxArTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=QmAmucBe; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="QmAmucBe" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 9AF954E41466; Mon, 31 Aug 2026 07:01:47 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6DA51601E1; Mon, 31 Aug 2026 07:01:47 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F138611C78A06; Mon, 31 Aug 2026 09:01:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1788159706; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=juuyW3Kt/fpD/0ZCK+TZEpPZ+AIKb80yrzD5yjL1arI=; b=QmAmucBeoad7CAsIQV1owfz7t1X9M7w0/cFKZwaq1BWL6Hdp+z7ZgHNRfb958CD4Hwh88m O+gfR+1hGmHA0Um2cxJ2CoBKrhwYzvULC+3lN9NObaKaegXDcGg7tAei7f5ldV4wx8zbCI Fi/Lq5Ft4voh03MRr/orqu7z61Z9aMpQglk6+zEiIwp5GokAcqN5W5C1+OOkDlQIQGX9W0 +8enFWGRMAI75thOjv1h7A746SUZo/K2Wt3wIvXq4Ivv23R1Bwg+rYfOPGOuDygzty8hKc jfRyl5F29YAn2TuxpT76YRShohUmEVWbZfZimE38iZxIt7sKGa0OvMKhG1c6bw== From: Maxime Chevallier To: Andrew Lunn , Jakub Kicinski , davem@davemloft.net, Eric Dumazet , Paolo Abeni , Simon Horman , Maxime Coquelin , Alexandre Torgue , Russell King Cc: Maxime Chevallier , thomas.petazzoni@bootlin.com, =?UTF-8?q?Alexis=20Lothor=C3=A9?= , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH net-next 2/2] net: stmmac: dwmac4: Use the full perfect filter ability for UC filter Date: Mon, 31 Aug 2026 09:01:20 +0200 Message-ID: <20260831070121.349778-3-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260831070121.349778-1-maxime.chevallier@bootlin.com> References: <20260831070121.349778-1-maxime.chevallier@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Contrary to dwmac1000 that gets its number of perfect filter entries through the 'snps,perfect-filter-entries' property, dwmac4 allows reading the filter size from the HW features registers. Perfect filter is used for Unicast filtering, and can contain up to 128 entries, each having its own set of registers to access it. The registers are always at the same location in the map, regardless whether or not the entry is implemented in hardware. Accessing a register for an un-implemented entry just doesn't do anything. The filter is made of one always-available entry, and 3 configurable banks : Entry 0 : Always implemented, stores the primary MAC address Entry 1 \ ... + -- Can contain between 0 and 31 entries. Number of available Entry 31 / entries in HW_Features0[18:22]. Entry 32 \ ... + -- Additional 32 entries, all or nothing. Availability is Entry 63 / specified by HW_Features0[23] Entry 64 \ ... + - Additional 64 entries, all or nothing. Availability is Entry 127 / specified by HW_Features0[24]. Each of the 3 configurable banks are independently selectable, meaning we can have gaps in the register banks. For instance, a setup with 50 addresses enabled will have 17 entries in the first bank and the additional 32 bank enabled (50 =3D 32 + 17 + 1). Another example with 70 addresses : 64 addr bank on, 5 addresses in the first bank (70 =3D 64 + 5 + 1). While I haven't seen HW with gaps in the banks, Synopsys confirmed this is a real possibility. Let's therefore introduce a dwmac4 helper to get the physical slot number of a given entry, allowing to configure the correct bank when populating the filter. As we need the HW feature-set to compute the index, store the bank info in the mac_device_info struct. The total number of available entries is computed based on the discovered parameters, instead of using the default value of 1. Results on HW that uses dwmac4 : - imx8mp : goes from 1 entry to 64 (1 + 31 + 32) - stm32mp1 : goes from 1 entry to 4 (1 + 3) - jh7110 : goes from 1 entry to 9 (1 + 8) - yt6801 : goes from 1 entry to hum, 1 entry (no extra addresses) Signed-off-by: Maxime Chevallier Reviewed-by: Nicolai Buchwitz --- drivers/net/ethernet/stmicro/stmmac/common.h | 3 + drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 2 - .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 60 +++++++++++++++---- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 27 +++++++++ 4 files changed, 80 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/eth= ernet/stmicro/stmmac/common.h index 77bd47a83357..1729fb29ece3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -629,6 +629,7 @@ struct mac_device_info { void __iomem *pcsr; /* vpointer to device CSRs */ unsigned int multicast_filter_bins; unsigned int unicast_filter_entries; + unsigned int multi_addr; unsigned int mcast_bits_log2; unsigned int rx_csum; unsigned int num_vlan; @@ -637,6 +638,8 @@ struct mac_device_info { u8 vlan_fail_q; bool hw_vlan_en; bool reverse_sgmii_enable; + bool additional_32_addr; + bool additional_64_addr; =20 /* This spinlock protects read-modify-write of the interrupt * mask/enable registers. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/eth= ernet/stmicro/stmmac/dwmac4.h index 89368e34a388..696846531229 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -75,8 +75,6 @@ #define GMAC_PACKET_FILTER_IPFE BIT(20) #define GMAC_PACKET_FILTER_RA BIT(31) =20 -#define GMAC_MAX_PERFECT_ADDRESSES 128 - /* MAC RX Queue Enable */ #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac4_core.c index 18b357b257cc..fb5b96a43505 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -365,22 +365,63 @@ static void dwmac4_pmt(struct mac_device_info *hw, un= signed long mode) writel(pmt, ioaddr + GMAC_PMT); } =20 +/** + * dwmac4_umac_addr_slot - Get the UC filter slot for the Nth MAC address + * @hw: The MAC device info + * @reg_n: The MAC address's index in the UC list + * + * On dwmac4 the slots available for Unicast MAC filtering are configured = when + * integrating the IP. + * + * - Slot 0 is always available, used to store the primary MAC address + * - From 1 to 31, the number of implemented slots is set in hw->multi_ad= dr + * - From 32 to 63, the range is available if hw->additional_32_addr + * is set + * - From 64 to 127, the range is available if hw->additional_64_addr is = set + * + * All the ranges can be configured independently (e.g. 64 -> 127 can be + * available, but not 32 -> 63) + * + * Returns: The physical slot index in the UC filter + */ +static unsigned int dwmac4_umac_addr_slot(struct mac_device_info *hw, + unsigned int reg_n) +{ + unsigned int empty_slots =3D 0; + + /* reg_n is in the 1-31 bank : 1 to 1 mapping */ + if (reg_n < (hw->multi_addr + 1)) + return reg_n; + + /* Gap between the last address in the 1->31 range and the next slot */ + if (hw->additional_32_addr) + empty_slots =3D 32 - (hw->multi_addr + 1); + else if (hw->additional_64_addr) + empty_slots =3D 64 - (hw->multi_addr + 1); + + return reg_n + empty_slots; +} + static void dwmac4_set_umac_addr(struct mac_device_info *hw, const unsigned char *addr, unsigned int reg_n) { void __iomem *ioaddr =3D hw->pcsr; + unsigned int slot; =20 - stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), - GMAC_ADDR_LOW(reg_n)); + slot =3D dwmac4_umac_addr_slot(hw, reg_n); + stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(slot), + GMAC_ADDR_LOW(slot)); } =20 static void dwmac4_get_umac_addr(struct mac_device_info *hw, unsigned char *addr, unsigned int reg_n) { void __iomem *ioaddr =3D hw->pcsr; + unsigned int slot; =20 - stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), - GMAC_ADDR_LOW(reg_n)); + slot =3D dwmac4_umac_addr_slot(hw, reg_n); + stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(slot), + GMAC_ADDR_LOW(slot)); } =20 static int dwmac4_set_lpi_mode(struct mac_device_info *hw, @@ -522,9 +563,6 @@ static void dwmac4_set_filter(struct mac_device_info *h= w, =20 /* Handle multiple unicast addresses */ if (netdev_uc_count(dev) + 1 > hw->unicast_filter_entries) { - /* Switch to promiscuous mode if more than 128 addrs - * are required - */ value |=3D GMAC_PACKET_FILTER_PR; } else { struct netdev_hw_addr *ha; @@ -535,9 +573,11 @@ static void dwmac4_set_filter(struct mac_device_info *= hw, reg++; } =20 - while (reg < GMAC_MAX_PERFECT_ADDRESSES) { - writel(0, ioaddr + GMAC_ADDR_HIGH(reg)); - writel(0, ioaddr + GMAC_ADDR_LOW(reg)); + while (reg < hw->unicast_filter_entries) { + unsigned int slot =3D dwmac4_umac_addr_slot(hw, reg); + + writel(0, ioaddr + GMAC_ADDR_HIGH(slot)); + writel(0, ioaddr + GMAC_ADDR_LOW(slot)); reg++; } } diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index a885f8cfef21..80413ba8df55 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -7492,6 +7492,33 @@ static int stmmac_hw_init(struct stmmac_priv *priv) priv->plat->tx_fifo_size =3D priv->dma_cap.tx_fifo_size; } =20 + /* On DWMAC4 we can get the exact number of perfect filter entries from + * the HW_Features. + */ + if (priv->plat->core_type =3D=3D DWMAC_CORE_GMAC4) { + priv->hw->multi_addr =3D priv->dma_cap.multi_addr; + priv->hw->additional_32_addr =3D + !!priv->dma_cap.additional_32_addr; + priv->hw->additional_64_addr =3D + !!priv->dma_cap.additional_64_addr; + + /* We always have one slot for the primary MAC */ + priv->hw->unicast_filter_entries =3D 1; + + /* How many slots in the 1 -> 31 range */ + priv->hw->unicast_filter_entries +=3D priv->hw->multi_addr; + + /* Additional 32 entries in the 32 -> 63 range */ + if (priv->hw->additional_32_addr) + priv->hw->unicast_filter_entries +=3D 32; + + /* Additional 64 entries in the 64 -> 127 range, can be enabled + * independently of the 32 -> 63 range + */ + if (priv->hw->additional_64_addr) + priv->hw->unicast_filter_entries +=3D 64; + } + priv->hw->vlan_fail_q_en =3D (priv->plat->flags & STMMAC_FLAG_VLAN_FAIL_Q_EN); priv->hw->vlan_fail_q =3D priv->plat->vlan_fail_q; --=20 2.55.0