From nobody Sat Sep 26 19:33:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64C9329B200; Mon, 31 Aug 2026 05:46:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788155199; cv=none; b=hLRaAMwa9I2d1VLym444KSiT6ubglqrUNAS886+gKPKJrG/FmVHsjKw799rV3Y+kqTgpIXa4i2SWzAmJmyFL5gHtRhRtwdsQKiROdutFdR4jqiKUIWKdCxWqJCeyv8de3utcHHkZZ8aUZaSWTB772xqH8cjHMn4hi6b2wMWQcOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788155199; c=relaxed/simple; bh=HTX8CF6dXgqyNjuJUEjUx5CUwE8Ol5zkKSsAQvuC7ro=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TInVjlrZVvYr2qO8v22j/RcEuVbC1I7xpIfbsxsCV0eSSvBPyjzXF6VJpKs8i5R2deiyQkxRBpoSiZjNt6AbeyaYKXVKl5si5je0WRxieokijteXhM9uSPgm9lRB773g5PbzN7jx0Sf6cRrNcpU4fgtUadLuzgT1ArR4fXMNYwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ELooOMza; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ELooOMza" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 851A21F00A3E; Mon, 31 Aug 2026 05:46:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788155198; bh=7yk+npu9o6FkhTV2JH+B6TOqdXF+2UHFz9x5wE6eyfI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ELooOMzaUECc7iI+okQhBtRnEGeRqyELRclh4xHwZFcRoZJqHJxdistHS1/R49asf 41xWHEFkltZHZz5wekjZhDm70eU6esjwr+KP6F4heRjFZjxynJ6eHjHchUsh/Fr+rn H2YjiF88820EbeNIWnEMHFDyMZSLwykxinpoSe+x9Gpw1EawDNzZ1bRPRdOBqTjNYb ikbtb4/6wUr+f6+H2bXM4PkMNqXsBqWRgXOV3zKSXXupU6ZfV3+jPjMktgS+RIqkYh KaG+azUxWLwSzdDW8/ApNNv1yj+uAhQ29I9LxcsnxJ5H3DHVWQ6ZjElNRPdBQ7AWDN QxV21BAyNSzUQ== From: "Mario Limonciello (AMD)" To: K Prateek Nayak Cc: Perry Yuan , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING FRAMEWORK), Vishal Badole , Richard Gong , "Mario Limonciello (AMD)" Subject: [PATCH 1/2] cpufreq/amd-pstate: Add per SoC and per core type EPP tuning values Date: Mon, 31 Aug 2026 00:46:29 -0500 Message-ID: <20260831054630.1745997-2-superm1@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831054630.1745997-1-superm1@kernel.org> References: <20260831054630.1745997-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On newer SoCs the behavior of the platform has changed, and using the same EPP values for everything will yield worse results than expected. Add a x86_cpu_id match table that allows setting policies on a per-SoC/per-core type basis. If a SoC is missing, fallback to legacy values that are used. Changes also: - Change epp_values array and amd_pstate_cpu_epp_values() from unsigned int to u8 - Add static_assert to ensure epp_values has rows for all CPU types - Fix show_energy_performance_preference() loop to exclude uninitialized EPP_INDEX_CUSTOM and EPP_INDEX_DYNAMIC slots - Add debug print statements - Remove amd_pstate_get_epp_from_platform_profile and inline the logic - Fix cleanup path in amd_pstate_set_dynamic_epp - Change show_energy_performance_preference to use for loop with preference tracking - Add debug prints in amd_pstate_init_epp_values Behavioral change: show_energy_performance_preference() now returns a numeric EPP value via sysfs when the cached EPP does not match any named preference, instead of returning -EINVAL as before. This provides visibility into custom EPP values set by hardware or BIOS. No new platforms are added in this commit. Signed-off-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate.c | 197 ++++++++++++++++++++++++++++------- 1 file changed, 160 insertions(+), 37 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d4ff8b228f86f..efac68f5e7658 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -55,10 +55,10 @@ #define AMD_PSTATE_TRANSITION_DELAY 1000 #define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600 =20 -#define AMD_CPPC_EPP_PERFORMANCE 0x00 -#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80 -#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF -#define AMD_CPPC_EPP_POWERSAVE 0xFF +#define AMD_CPPC_EPP_LEGACY_PERFORMANCE 0x00 +#define AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMANCE 0x80 +#define AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE 0xBF +#define AMD_CPPC_EPP_LEGACY_POWERSAVE 0xFF =20 static const char * const amd_pstate_mode_string[] =3D { [AMD_PSTATE_UNDEFINED] =3D "undefined", @@ -129,14 +129,102 @@ static const char * const energy_perf_strings[] =3D { }; static_assert(ARRAY_SIZE(energy_perf_strings) =3D=3D EPP_INDEX_MAX); =20 -static unsigned int epp_values[] =3D { - [EPP_INDEX_DEFAULT] =3D 0, - [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_PERFORMANCE, - [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_BALANCE_PERFORMANCE, - [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_BALANCE_POWERSAVE, - [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_POWERSAVE, +/* + * The numeric EPP value programmed for each named preference. First dimen= sion + * is CPU type (TOPO_CPU_TYPE_ANY for non-hybrid, TOPO_CPU_TYPE_PERFORMANC= E/ + * EFFICIENCY/LOW_POWER for hybrid). The initializer holds the legacy valu= es + * used as the fallback on any platform not listed in amd_pstate_epp_soc_i= ds[]; + * amd_pstate_init_epp_values() overwrites slots at boot when the running = SoC + * has a per-SoC (and potentially per-CPU-type) override. + */ +static u8 epp_values[][EPP_INDEX_MAX] =3D { + [TOPO_CPU_TYPE_ANY] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, + [TOPO_CPU_TYPE_PERFORMANCE] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, + [TOPO_CPU_TYPE_EFFICIENCY] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, + [TOPO_CPU_TYPE_LOW_POWER] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, +}; +static_assert(ARRAY_SIZE(epp_values) =3D=3D TOPO_CPU_TYPE_LOW_POWER + 1, + "epp_values must have entries for all CPU types up to TOPO_CPU_TYPE= _LOW_POWER"); + +/* + * Get the EPP value row for a given CPU, accounting for hybrid CPU types. + * Non-hybrid systems use TOPO_CPU_TYPE_ANY; hybrid systems use the CPU's + * actual type (PERFORMANCE/EFFICIENCY/LOW_POWER). + */ +static inline u8 *amd_pstate_cpu_epp_values(int cpu) +{ + enum x86_topology_cpu_type type =3D cpu_data(cpu).topo.cpu_type; + + if (type =3D=3D TOPO_CPU_TYPE_PERFORMANCE || + type =3D=3D TOPO_CPU_TYPE_EFFICIENCY || + type =3D=3D TOPO_CPU_TYPE_LOW_POWER) + return epp_values[type]; + + return epp_values[TOPO_CPU_TYPE_ANY]; +} + +/** + * struct amd_pstate_epp_values - EPP values for the four named preferences + * @performance: value for the "performance" preference + * @balance_performance: value for the "balance_performance" preference + * @balance_power: value for the "balance_power" preference + * @power: value for the "power" preference + */ +struct amd_pstate_epp_values { + u8 performance; + u8 balance_performance; + u8 balance_power; + u8 power; +}; + +/** + * struct amd_pstate_epp_soc - per-CPU-type EPP overrides for hybrid syste= ms + * @performance_core: values for TOPO_CPU_TYPE_PERFORMANCE cores + * @efficiency_core: values for TOPO_CPU_TYPE_EFFICIENCY cores + * @low_power_core: values for TOPO_CPU_TYPE_LOW_POWER cores + * + * Referenced from amd_pstate_epp_soc_ids[] to give a hybrid platform its = own + * numeric EPP values for the four named preferences, with distinct values= per + * CPU type. Non-hybrid systems are not listed in the table and always use= the + * legacy defaults. + */ +struct amd_pstate_epp_soc { + struct amd_pstate_epp_values performance_core; + struct amd_pstate_epp_values efficiency_core; + struct amd_pstate_epp_values low_power_core; +}; + +/* + * Per-CPU-type EPP overrides for hybrid systems. Only hybrid SoCs should = be + * listed here; non-hybrid systems always use the legacy defaults. + */ +static const struct x86_cpu_id amd_pstate_epp_soc_ids[] __initconst =3D { + {} }; -static_assert(ARRAY_SIZE(epp_values) =3D=3D EPP_INDEX_MAX - 2); =20 typedef int (*cppc_mode_transition_fn)(int); =20 @@ -1195,13 +1283,16 @@ static int amd_pstate_power_supply_notifier(struct = notifier_block *nb, static int amd_pstate_get_epp_from_platform_profile(struct cpufreq_policy = *policy, enum platform_profile_option profile) { + struct amd_cpudata *cpudata =3D policy->driver_data; + u8 *values =3D amd_pstate_cpu_epp_values(cpudata->cpu); + switch (profile) { case PLATFORM_PROFILE_PERFORMANCE: - return AMD_CPPC_EPP_PERFORMANCE; + return values[EPP_INDEX_PERFORMANCE]; case PLATFORM_PROFILE_BALANCED: return amd_pstate_get_balanced_epp(policy); case PLATFORM_PROFILE_LOW_POWER: - return AMD_CPPC_EPP_POWERSAVE; + return values[EPP_INDEX_POWERSAVE]; default: break; } @@ -1411,6 +1502,7 @@ ssize_t store_energy_performance_preference(struct cp= ufreq_policy *policy, const char *buf, size_t count) { struct amd_cpudata *cpudata =3D policy->driver_data; + u8 *values =3D amd_pstate_cpu_epp_values(policy->cpu); ssize_t ret; bool raw_epp =3D false; u8 epp; @@ -1445,12 +1537,13 @@ ssize_t store_energy_performance_preference(struct = cpufreq_policy *policy, } =20 if (ret) - epp =3D epp_values[ret]; + epp =3D values[ret]; else epp =3D cpudata->epp_default_dc; } =20 - if (epp > 0 && cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) { + if (epp > 0 && epp !=3D values[EPP_INDEX_PERFORMANCE] && + cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) { pr_debug("EPP cannot be set under performance policy\n"); return -EBUSY; } @@ -1475,34 +1568,31 @@ EXPORT_SYMBOL_FOR_PSTATE_UT(store_energy_performanc= e_preference); ssize_t show_energy_performance_preference(struct cpufreq_policy *policy, = char *buf) { struct amd_cpudata *cpudata =3D policy->driver_data; - u8 preference, epp; + u8 *values =3D amd_pstate_cpu_epp_values(policy->cpu); + u8 epp; + int i; =20 epp =3D FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached); =20 if (!cpudata->dynamic_epp && cpudata->raw_epp) return sysfs_emit(buf, "%u\n", epp); =20 - switch (epp) { - case AMD_CPPC_EPP_PERFORMANCE: - preference =3D EPP_INDEX_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_PERFORMANCE: - preference =3D EPP_INDEX_BALANCE_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_POWERSAVE: - preference =3D EPP_INDEX_BALANCE_POWERSAVE; - break; - case AMD_CPPC_EPP_POWERSAVE: - preference =3D EPP_INDEX_POWERSAVE; - break; - default: - return -EINVAL; - } + /* + * Map the cached EPP value back to a named preference. Skip the + * "default" slot (index 0) so an EPP of 0 reports as "performance". + * Stop at POWERSAVE; CUSTOM and DYNAMIC are not initialized in epp_value= s. + */ + for (i =3D EPP_INDEX_PERFORMANCE; i <=3D EPP_INDEX_POWERSAVE; i++) { + const char *name =3D energy_perf_strings[i]; =20 - if (cpudata->dynamic_epp) - return sysfs_emit(buf, "dynamic(profile:%s)\n", energy_perf_strings[pref= erence]); + if (epp =3D=3D values[i]) { + if (cpudata->dynamic_epp) + return sysfs_emit(buf, "dynamic(profile:%s)\n", name); + return sysfs_emit(buf, "%s\n", name); + } + } =20 - return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); + return sysfs_emit(buf, "%u\n", epp); } EXPORT_SYMBOL_FOR_PSTATE_UT(show_energy_performance_preference); =20 @@ -1944,9 +2034,11 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_po= licy *policy) cpudata->epp_default_ac =3D cpudata->epp_default_dc =3D default_epp; cpudata->current_profile =3D PLATFORM_PROFILE_PERFORMANCE; } else { + u8 *values =3D amd_pstate_cpu_epp_values(policy->cpu); + policy->policy =3D CPUFREQ_POLICY_POWERSAVE; - cpudata->epp_default_ac =3D AMD_CPPC_EPP_PERFORMANCE; - cpudata->epp_default_dc =3D AMD_CPPC_EPP_BALANCE_PERFORMANCE; + cpudata->epp_default_ac =3D values[EPP_INDEX_PERFORMANCE]; + cpudata->epp_default_dc =3D values[EPP_INDEX_BALANCE_PERFORMANCE]; cpudata->current_profile =3D PLATFORM_PROFILE_BALANCED; } =20 @@ -2245,6 +2337,34 @@ static bool amd_cppc_supported(void) return true; } =20 +/* + * Resolve the numeric EPP values for hybrid systems. Only hybrid SoCs are= listed + * in amd_pstate_epp_soc_ids[]; non-hybrid systems always use the legacy d= efaults. + */ +static inline void __init amd_pstate_set_epp_values(enum x86_topology_cpu_= type type, + const struct amd_pstate_epp_values *core) +{ + epp_values[type][EPP_INDEX_PERFORMANCE] =3D core->performance; + epp_values[type][EPP_INDEX_BALANCE_PERFORMANCE] =3D core->balance_perform= ance; + epp_values[type][EPP_INDEX_BALANCE_POWERSAVE] =3D core->balance_power; + epp_values[type][EPP_INDEX_POWERSAVE] =3D core->power; +} + +static void __init amd_pstate_init_epp_values(void) +{ + const struct x86_cpu_id *id =3D x86_match_cpu(amd_pstate_epp_soc_ids); + const struct amd_pstate_epp_soc *soc; + + if (!id || !id->driver_data) + return; + + soc =3D (const struct amd_pstate_epp_soc *)id->driver_data; + + amd_pstate_set_epp_values(TOPO_CPU_TYPE_PERFORMANCE, &soc->performance_co= re); + amd_pstate_set_epp_values(TOPO_CPU_TYPE_EFFICIENCY, &soc->efficiency_core= ); + amd_pstate_set_epp_values(TOPO_CPU_TYPE_LOW_POWER, &soc->low_power_core); +} + static int __init amd_pstate_init(void) { struct device *dev_root; @@ -2272,6 +2392,9 @@ static int __init amd_pstate_init(void) /* check if this machine need CPPC quirks */ dmi_check_system(amd_pstate_quirks_table); =20 + /* resolve per-SoC EPP values for the named preferences */ + amd_pstate_init_epp_values(); + /* * determine the driver mode from the command line or kernel config. * If no command line input is provided, cppc_state will be AMD_PSTATE_UND= EFINED. --=20 2.53.0 From nobody Sat Sep 26 19:33:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83E463ADBB4; Mon, 31 Aug 2026 05:46:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788155200; cv=none; b=cuo7eHUePGTCUjmHHbMMS3qrBY/MtZDf+hyWETC8XNlEtU4tZcd4cTHUYoGgAxiLQ9gno8GS6u7hnuq20kp83Gc0UKFXesfCoHPsNe0T8t4XGvE1Ci3zMvr+P4gCWvP4XbuLyLfZzkm5+t0E+JQlN+0BAQqymKM2II/5RjKZ1GQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788155200; c=relaxed/simple; bh=vqFp8l7iIfm3g7FU6UaU8UVsXj8nC+8aGqSGYBMhx/U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nwelPEOAwJOz3k3n72n8N04e8+KHbbzZxJxtC94+ZqLGkXgrFEHKXZbhvwxnLibur1XJXcZWNCtHrjfPcw30/1aZzFOv8DC/0EEf469NxSUbgI44stS96DWayToGhlxpyDjOMJjy4Ov1MjhvQCDO6YoJiGjvzhYosIL2GzkkMFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IWrpIhSN; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IWrpIhSN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 78FB91F000E9; Mon, 31 Aug 2026 05:46:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788155199; bh=0fOlXWJQejLO+aUMphkqY5oKCfMIBPuM+vyQPhtn980=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=IWrpIhSNX0nLGftFpKQA5CdmZsFD0+Ho7O1NcDi1Ppex2sVLEaITvFTzUIapBmWQL i7Y2bP72BTjoTZsNGkjrT75668avVGBr1WSUewPGDzSkM01hTFN/WczLdnDJ7Wxnv6 mLygboET5ubAYJ5VXT6iIpdWLsKFNePEsLtbo792yl07FZZTUu2HIZ9snNcd5CktKr P4maamnJIquTQbSN3/CBHR/CmKVCplADc+Pn+6daVRe3Ifmy4W2PtiKhz/H9XF2eFY RXKj/RcL3ZxxIv3qYqj34pBrJGb2gKbywO3K6VE+tgTVAfZbkgtJaNUo5WrAlNEvO/ JlQzM15R8M+ig== From: "Mario Limonciello (AMD)" To: K Prateek Nayak Cc: Perry Yuan , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING FRAMEWORK), Vishal Badole , Richard Gong , "Mario Limonciello (AMD)" Subject: [PATCH 2/2] cpufreq/amd-pstate: Add EPP tunings for Zen6 client platforms Date: Mon, 31 Aug 2026 00:46:30 -0500 Message-ID: <20260831054630.1745997-3-superm1@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831054630.1745997-1-superm1@kernel.org> References: <20260831054630.1745997-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Zen6 client platforms perform better with individual tunings for different core types. Add initial EPP tuning values for those platforms. Signed-off-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index efac68f5e7658..d2b4a8eba3052 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -222,7 +222,33 @@ struct amd_pstate_epp_soc { * Per-CPU-type EPP overrides for hybrid systems. Only hybrid SoCs should = be * listed here; non-hybrid systems always use the legacy defaults. */ +static const struct amd_pstate_epp_soc epp_soc_zen6_client __initconst =3D= { + .performance_core =3D { + .performance =3D 25, + .balance_performance =3D 51, + .balance_power =3D 64, + .power =3D 64, + }, + .efficiency_core =3D { + .performance =3D 25, + .balance_performance =3D 51, + .balance_power =3D 64, + .power =3D 115, + }, + .low_power_core =3D { + .performance =3D 25, + .balance_performance =3D 51, + .balance_power =3D 64, + .power =3D 115, + }, +}; + static const struct x86_cpu_id amd_pstate_epp_soc_ids[] __initconst =3D { + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x80, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x81, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x84, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x85, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0xe0, &epp_soc_zen6_client), {} }; =20 --=20 2.53.0