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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v11 1/5] net: dsa: yt921x: Check lock status with lockdep_assert_held_once() Date: Mon, 31 Aug 2026 12:38:54 +0800 Message-ID: <20260831044818.4103477-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831044818.4103477-1-mmyangfl@gmail.com> References: <20260831044818.4103477-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mutex_is_locked() was used to check the lock status. While it should not be triggered unless a bug is introduced, it does not warn on lock being held by another thread. Fix it with lockdep helpers. Fixes: 186623f4aa72 ("net: dsa: yt921x: Add support for Motorcomm YT921x") Signed-off-by: David Yang Reviewed-by: Andrew Lunn --- drivers/net/dsa/yt921x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 159b16606f6c..44fcdd47ffb5 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -198,14 +198,14 @@ static u32 ethaddr_lo2_to_u32(const unsigned char *ad= dr) =20 static int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) { - WARN_ON(!mutex_is_locked(&priv->reg_lock)); + lockdep_assert_held_once(&priv->reg_lock); =20 return priv->reg_ops->read(priv->reg_ctx, reg, valp); } =20 static int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) { - WARN_ON(!mutex_is_locked(&priv->reg_lock)); + lockdep_assert_held_once(&priv->reg_lock); =20 return priv->reg_ops->write(priv->reg_ctx, reg, val); } --=20 2.53.0 From nobody Sat Sep 26 20:28:07 2026 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADCE43C2774 for ; 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Sun, 30 Aug 2026 21:49:15 -0700 (PDT) Received: from d.home.yangfl.dn42 ([2a09:bac1:76a0:d30::4cf:2e]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b0fd5c34sm19345763a91.8.2026.08.30.21.49.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 21:49:15 -0700 (PDT) From: David Yang To: netdev@vger.kernel.org Cc: David Yang , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v11 2/5] net: dsa: motorcomm: Move to subdirectory Date: Mon, 31 Aug 2026 12:38:55 +0800 Message-ID: <20260831044818.4103477-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831044818.4103477-1-mmyangfl@gmail.com> References: <20260831044818.4103477-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" yt921x is already the longest single-file DSA driver, so it's time to split it into parts. Signed-off-by: David Yang Reviewed-by: Andrew Lunn --- MAINTAINERS | 2 +- drivers/net/dsa/Kconfig | 10 ++-------- drivers/net/dsa/Makefile | 2 +- drivers/net/dsa/motorcomm/Kconfig | 8 ++++++++ drivers/net/dsa/motorcomm/Makefile | 3 +++ drivers/net/dsa/{yt921x.c =3D> motorcomm/chip.c} | 2 +- drivers/net/dsa/{yt921x.h =3D> motorcomm/chip.h} | 0 7 files changed, 16 insertions(+), 11 deletions(-) create mode 100644 drivers/net/dsa/motorcomm/Kconfig create mode 100644 drivers/net/dsa/motorcomm/Makefile rename drivers/net/dsa/{yt921x.c =3D> motorcomm/chip.c} (99%) rename drivers/net/dsa/{yt921x.h =3D> motorcomm/chip.h} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 0b42e898f4d8..4b0254f62277 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18422,7 +18422,7 @@ M: David Yang L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml -F: drivers/net/dsa/yt921x.* +F: drivers/net/dsa/motorcomm/ F: net/dsa/tag_yt921x.c =20 MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index 676fb7dffe14..8d8edcf89f10 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -82,6 +82,8 @@ config NET_DSA_MV88E6060 =20 source "drivers/net/dsa/microchip/Kconfig" =20 +source "drivers/net/dsa/motorcomm/Kconfig" + source "drivers/net/dsa/mv88e6xxx/Kconfig" =20 source "drivers/net/dsa/mxl862xx/Kconfig" @@ -168,12 +170,4 @@ config NET_DSA_VITESSE_VSC73XX_PLATFORM This enables support for the Vitesse VSC7385, VSC7388, VSC7395 and VSC7398 SparX integrated ethernet switches, connected over a CPU-attached address bus and work in memory-mapped I/O mode. - -config NET_DSA_YT921X - tristate "Motorcomm YT9215 ethernet switch chip support" - select NET_DSA_TAG_YT921X - select NET_IEEE8021Q_HELPERS if DCB - help - This enables support for the Motorcomm YT9215 ethernet switch - chip. endmenu diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile index 6ceb78a755d7..df849cd0e640 100644 --- a/drivers/net/dsa/Makefile +++ b/drivers/net/dsa/Makefile @@ -15,11 +15,11 @@ obj-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) +=3D lan9303_md= io.o obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX) +=3D vitesse-vsc73xx-core.o obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM) +=3D vitesse-vsc73xx-platfo= rm.o obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) +=3D vitesse-vsc73xx-spi.o -obj-$(CONFIG_NET_DSA_YT921X) +=3D yt921x.o obj-y +=3D b53/ obj-y +=3D hirschmann/ obj-y +=3D lantiq/ obj-y +=3D microchip/ +obj-y +=3D motorcomm/ obj-y +=3D mv88e6xxx/ obj-y +=3D mxl862xx/ obj-y +=3D netc/ diff --git a/drivers/net/dsa/motorcomm/Kconfig b/drivers/net/dsa/motorcomm/= Kconfig new file mode 100644 index 000000000000..64ff7d07a91b --- /dev/null +++ b/drivers/net/dsa/motorcomm/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_YT921X + tristate "Motorcomm YT9215 ethernet switch chip support" + select NET_DSA_TAG_YT921X + select NET_IEEE8021Q_HELPERS if DCB + help + This enables support for the Motorcomm YT9215 ethernet switch + chip. diff --git a/drivers/net/dsa/motorcomm/Makefile b/drivers/net/dsa/motorcomm= /Makefile new file mode 100644 index 000000000000..bf99feb4c454 --- /dev/null +++ b/drivers/net/dsa/motorcomm/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_YT921X) +=3D yt921x.o +yt921x-objs :=3D chip.o diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/motorcomm/chip.c similarity index 99% rename from drivers/net/dsa/yt921x.c rename to drivers/net/dsa/motorcomm/chip.c index 44fcdd47ffb5..019b3a2d5d97 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -26,7 +26,7 @@ #include #include =20 -#include "yt921x.h" +#include "chip.h" =20 struct yt921x_mib_desc { unsigned int size; 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Sun, 30 Aug 2026 21:49:20 -0700 (PDT) Received: from d.home.yangfl.dn42 ([2a09:bac1:76a0:d30::4cf:2e]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b0fd5c34sm19345763a91.8.2026.08.30.21.49.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 21:49:19 -0700 (PDT) From: David Yang To: netdev@vger.kernel.org Cc: David Yang , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v11 3/5] net: dsa: motorcomm: Split SMI module Date: Mon, 31 Aug 2026 12:38:56 +0800 Message-ID: <20260831044818.4103477-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831044818.4103477-1-mmyangfl@gmail.com> References: <20260831044818.4103477-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SMI operations are going to be used across different modules. Minor changes are applied to fix build errors. Signed-off-by: David Yang Reviewed-by: Andrew Lunn --- drivers/net/dsa/motorcomm/Makefile | 1 + drivers/net/dsa/motorcomm/chip.c | 207 +---------------------------- drivers/net/dsa/motorcomm/smi.c | 180 +++++++++++++++++++++++++ drivers/net/dsa/motorcomm/smi.h | 61 +++++++++ 4 files changed, 243 insertions(+), 206 deletions(-) create mode 100644 drivers/net/dsa/motorcomm/smi.c create mode 100644 drivers/net/dsa/motorcomm/smi.h diff --git a/drivers/net/dsa/motorcomm/Makefile b/drivers/net/dsa/motorcomm= /Makefile index bf99feb4c454..9fa24929007c 100644 --- a/drivers/net/dsa/motorcomm/Makefile +++ b/drivers/net/dsa/motorcomm/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_NET_DSA_YT921X) +=3D yt921x.o yt921x-objs :=3D chip.o +yt921x-objs +=3D smi.o diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/c= hip.c index 019b3a2d5d97..6dee25b6754a 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -27,6 +26,7 @@ #include =20 #include "chip.h" +#include "smi.h" =20 struct yt921x_mib_desc { unsigned int size; @@ -155,9 +155,6 @@ static const struct yt921x_info yt921x_infos[] =3D { =20 #define YT921X_VID_UNWARE 4095 =20 -#define YT921X_POLL_SLEEP_US 10000 -#define YT921X_POLL_TIMEOUT_US 100000 - /* The interval should be small enough to avoid overflow of 32bit MIBs. * * Until we can read MIBs from stats64 call directly (i.e. sleep @@ -196,208 +193,6 @@ static u32 ethaddr_lo2_to_u32(const unsigned char *ad= dr) return (addr[4] << 8) | addr[5]; } =20 -static int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) -{ - lockdep_assert_held_once(&priv->reg_lock); - - return priv->reg_ops->read(priv->reg_ctx, reg, valp); -} - -static int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) -{ - lockdep_assert_held_once(&priv->reg_lock); - - return priv->reg_ops->write(priv->reg_ctx, reg, val); -} - -static int -yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) -{ - u32 val; - int res; - int ret; - - ret =3D read_poll_timeout(yt921x_reg_read, res, - res || (val & mask) =3D=3D *valp, - YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, - false, priv, reg, &val); - if (ret) - return ret; - if (res) - return res; - - *valp =3D val; - return 0; -} - -static int -yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 va= l) -{ - int res; - u32 v; - u32 u; - - res =3D yt921x_reg_read(priv, reg, &v); - if (res) - return res; - - u =3D v; - u &=3D ~mask; - u |=3D val; - if (u =3D=3D v) - return 0; - - return yt921x_reg_write(priv, reg, u); -} - -static int yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) -{ - return yt921x_reg_update_bits(priv, reg, 0, mask); -} - -static int yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 ma= sk) -{ - return yt921x_reg_update_bits(priv, reg, mask, 0); -} - -static int -yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool s= et) -{ - return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); -} - -/* Some multi-word registers, like VLANn_CTRL, should be treated as a sing= le - * long register. More specifically, writes to parts of its words won't be= come - * visible, until the last word is written. - * - * Here we require full read and write operations over these registers to - * eliminate potential issues, although partial reads/writes are also poss= ible. - */ - -static void update_ctrls_unaligned(u32 *lo, u32 *hi, u64 mask, u64 val) -{ - *lo &=3D ~lower_32_bits(mask); - *hi &=3D ~upper_32_bits(mask); - *lo |=3D lower_32_bits(val); - *hi |=3D upper_32_bits(val); -} - -static int -yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, - unsigned int num_regs) -{ - int res; - - for (unsigned int i =3D 0; i < num_regs; i++) { - res =3D yt921x_reg_read(priv, reg + 4 * i, &vals[i]); - if (res) - return res; - } - - return 0; -} - -static int -yt921x_regs_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, - unsigned int num_regs) -{ - int res; - - for (unsigned int i =3D 0; i < num_regs; i++) { - res =3D yt921x_reg_write(priv, reg + 4 * i, vals[i]); - if (res) - return res; - } - - return 0; -} - -static int -yt921x_regs_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *mask= s, - const u32 *vals, unsigned int num_regs) -{ - bool changed =3D false; - u32 vs[4]; - int res; - - BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); - - res =3D yt921x_regs_read(priv, reg, vs, num_regs); - if (res) - return res; - - for (unsigned int i =3D 0; i < num_regs; i++) { - u32 u =3D vs[i]; - - u &=3D ~masks[i]; - u |=3D vals[i]; - if (u !=3D vs[i]) - changed =3D true; - - vs[i] =3D u; - } - - if (!changed) - return 0; - - return yt921x_regs_write(priv, reg, vs, num_regs); -} - -static int -yt921x_regs_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, - unsigned int num_regs) -{ - bool changed =3D false; - u32 vs[4]; - int res; - - BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); - - res =3D yt921x_regs_read(priv, reg, vs, num_regs); - if (res) - return res; - - for (unsigned int i =3D 0; i < num_regs; i++) { - u32 u =3D vs[i]; - - u &=3D ~masks[i]; - if (u !=3D vs[i]) - changed =3D true; - - vs[i] =3D u; - } - - if (!changed) - return 0; - - return yt921x_regs_write(priv, reg, vs, num_regs); -} - -static int -yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) -{ - return yt921x_regs_write(priv, reg, vals, 2); -} - -static int -yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *mas= ks, - const u32 *vals) -{ - return yt921x_regs_update_bits(priv, reg, masks, vals, 2); -} - -static int -yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *mask= s) -{ - return yt921x_regs_clear_bits(priv, reg, masks, 2); -} - -static int -yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) -{ - return yt921x_regs_write(priv, reg, vals, 3); -} - static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) { struct yt921x_reg_mdio *mdio =3D context; diff --git a/drivers/net/dsa/motorcomm/smi.c b/drivers/net/dsa/motorcomm/sm= i.c new file mode 100644 index 000000000000..bf3adfd64165 --- /dev/null +++ b/drivers/net/dsa/motorcomm/smi.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 David Yang + */ + +#include + +#include "chip.h" +#include "smi.h" + +#define YT921X_POLL_SLEEP_US 10000 +#define YT921X_POLL_TIMEOUT_US 100000 + +int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) +{ + lockdep_assert_held_once(&priv->reg_lock); + + return priv->reg_ops->read(priv->reg_ctx, reg, valp); +} + +int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) +{ + lockdep_assert_held_once(&priv->reg_lock); + + return priv->reg_ops->write(priv->reg_ctx, reg, val); +} + +int yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) +{ + u32 val; + int res; + int ret; + + ret =3D read_poll_timeout(yt921x_reg_read, res, + res || (val & mask) =3D=3D *valp, + YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, + false, priv, reg, &val); + if (ret) + return ret; + if (res) + return res; + + *valp =3D val; + return 0; +} + +int yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u3= 2 val) +{ + int res; + u32 v; + u32 u; + + res =3D yt921x_reg_read(priv, reg, &v); + if (res) + return res; + + u =3D v; + u &=3D ~mask; + u |=3D val; + if (u =3D=3D v) + return 0; + + return yt921x_reg_write(priv, reg, u); +} + +static int +yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, + unsigned int num_regs) +{ + int res; + + for (unsigned int i =3D 0; i < num_regs; i++) { + res =3D yt921x_reg_read(priv, reg + 4 * i, &vals[i]); + if (res) + return res; + } + + return 0; +} + +static int +yt921x_regs_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, + unsigned int num_regs) +{ + int res; + + for (unsigned int i =3D 0; i < num_regs; i++) { + res =3D yt921x_reg_write(priv, reg + 4 * i, vals[i]); + if (res) + return res; + } + + return 0; +} + +static int +yt921x_regs_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *mask= s, + const u32 *vals, unsigned int num_regs) +{ + bool changed =3D false; + u32 vs[4]; + int res; + + BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); + + res =3D yt921x_regs_read(priv, reg, vs, num_regs); + if (res) + return res; + + for (unsigned int i =3D 0; i < num_regs; i++) { + u32 u =3D vs[i]; + + u &=3D ~masks[i]; + u |=3D vals[i]; + if (u !=3D vs[i]) + changed =3D true; + + vs[i] =3D u; + } + + if (!changed) + return 0; + + return yt921x_regs_write(priv, reg, vs, num_regs); +} + +static int +yt921x_regs_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + unsigned int num_regs) +{ + bool changed =3D false; + u32 vs[4]; + int res; + + BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); + + res =3D yt921x_regs_read(priv, reg, vs, num_regs); + if (res) + return res; + + for (unsigned int i =3D 0; i < num_regs; i++) { + u32 u =3D vs[i]; + + u &=3D ~masks[i]; + if (u !=3D vs[i]) + changed =3D true; + + vs[i] =3D u; + } + + if (!changed) + return 0; + + return yt921x_regs_write(priv, reg, vs, num_regs); +} + +int +yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) +{ + return yt921x_regs_write(priv, reg, vals, 2); +} + +int +yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *mas= ks, + const u32 *vals) +{ + return yt921x_regs_update_bits(priv, reg, masks, vals, 2); +} + +int +yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *mask= s) +{ + return yt921x_regs_clear_bits(priv, reg, masks, 2); +} + +int +yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) +{ + return yt921x_regs_write(priv, reg, vals, 3); +} diff --git a/drivers/net/dsa/motorcomm/smi.h b/drivers/net/dsa/motorcomm/sm= i.h new file mode 100644 index 000000000000..212e20f71d80 --- /dev/null +++ b/drivers/net/dsa/motorcomm/smi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2026 David Yang + */ + +#ifndef _YT_SMI_H +#define _YT_SMI_H + +#include +#include + +struct yt921x_priv; + +int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp); +int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val); +int yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp= ); +int yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, + u32 val); + +static inline int +yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) +{ + return yt921x_reg_update_bits(priv, reg, 0, mask); +} + +static inline int +yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 mask) +{ + return yt921x_reg_update_bits(priv, reg, mask, 0); +} + +static inline int +yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool s= et) +{ + return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); +} + +/* Some multi-word registers, like VLANn_CTRL, should be treated as a sing= le + * long register. More specifically, writes to parts of its words won't be= come + * visible, until the last word is written. + * + * Here we require full read and write operations over these registers to + * eliminate potential issues, although partial reads/writes are also poss= ible. + */ + +static inline void update_ctrls_unaligned(u32 *lo, u32 *hi, u64 mask, u64 = val) +{ + *lo &=3D ~lower_32_bits(mask); + *hi &=3D ~upper_32_bits(mask); + *lo |=3D lower_32_bits(val); + *hi |=3D upper_32_bits(val); +} + +int yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals); +int yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, + const u32 *masks, const u32 *vals); +int yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, + const u32 *masks); +int yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals); + +#endif --=20 2.53.0 From nobody Sat Sep 26 20:28:07 2026 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE95836E46C for ; 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Sun, 30 Aug 2026 21:49:23 -0700 (PDT) Received: from d.home.yangfl.dn42 ([2a09:bac1:76a0:d30::4cf:2e]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b0fd5c34sm19345763a91.8.2026.08.30.21.49.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 21:49:23 -0700 (PDT) From: David Yang To: netdev@vger.kernel.org Cc: David Yang , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v11 4/5] net: dsa: motorcomm: Add LED support Date: Mon, 31 Aug 2026 12:38:57 +0800 Message-ID: <20260831044818.4103477-5-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831044818.4103477-1-mmyangfl@gmail.com> References: <20260831044818.4103477-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Each port has at most 3 LEDs connected and can be declared using the standard LEDs structure. Currently, only parallel mode and strict 1:1 mapping (i.e. the HW default) are supported. Signed-off-by: David Yang Reviewed-by: Andrew Lunn --- drivers/net/dsa/motorcomm/Kconfig | 9 + drivers/net/dsa/motorcomm/Makefile | 1 + drivers/net/dsa/motorcomm/chip.c | 19 +- drivers/net/dsa/motorcomm/chip.h | 15 + drivers/net/dsa/motorcomm/leds.c | 641 +++++++++++++++++++++++++++++ drivers/net/dsa/motorcomm/leds.h | 118 ++++++ 6 files changed, 801 insertions(+), 2 deletions(-) create mode 100644 drivers/net/dsa/motorcomm/leds.c create mode 100644 drivers/net/dsa/motorcomm/leds.h diff --git a/drivers/net/dsa/motorcomm/Kconfig b/drivers/net/dsa/motorcomm/= Kconfig index 64ff7d07a91b..79cdd79a1fd2 100644 --- a/drivers/net/dsa/motorcomm/Kconfig +++ b/drivers/net/dsa/motorcomm/Kconfig @@ -6,3 +6,12 @@ config NET_DSA_YT921X help This enables support for the Motorcomm YT9215 ethernet switch chip. + +config NET_DSA_YT921X_LEDS + bool "LED support for Motorcomm YT9215" + default y + depends on NET_DSA_YT921X + depends on LEDS_CLASS=3Dy || LEDS_CLASS=3DNET_DSA_YT921X + help + This enables support for controlling the LEDs attached to the + Motorcomm YT9215 switch chips. diff --git a/drivers/net/dsa/motorcomm/Makefile b/drivers/net/dsa/motorcomm= /Makefile index 9fa24929007c..aeb12cb91f93 100644 --- a/drivers/net/dsa/motorcomm/Makefile +++ b/drivers/net/dsa/motorcomm/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_NET_DSA_YT921X) +=3D yt921x.o yt921x-objs :=3D chip.o +yt921x-$(CONFIG_NET_DSA_YT921X_LEDS) +=3D leds.o yt921x-objs +=3D smi.o diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/c= hip.c index 6dee25b6754a..d663af010f43 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -26,6 +26,7 @@ #include =20 #include "chip.h" +#include "leds.h" #include "smi.h" =20 struct yt921x_mib_desc { @@ -151,8 +152,6 @@ static const struct yt921x_info yt921x_infos[] =3D { {} }; =20 -#define YT921X_NAME "yt921x" - #define YT921X_VID_UNWARE 4095 =20 /* The interval should be small enough to avoid overflow of 32bit MIBs. @@ -4225,6 +4224,15 @@ static int yt921x_edata_read(struct yt921x_priv *pri= v, u8 addr, u8 *valp) return yt921x_edata_read_cont(priv, addr, valp); } =20 +static void yt921x_dsa_teardown(struct dsa_switch *ds) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + +#if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) + yt921x_leds_remove(priv); +#endif +} + static int yt921x_chip_detect(struct yt921x_priv *priv) { struct device *dev =3D to_device(priv); @@ -4581,6 +4589,12 @@ static int yt921x_dsa_setup(struct dsa_switch *ds) if (res) return res; =20 +#if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) + res =3D yt921x_leds_setup(priv); + if (res) + dev_warn(dev, "Failed to setup LEDs: %d\n", res); +#endif + return 0; } =20 @@ -4661,6 +4675,7 @@ static const struct dsa_switch_ops yt921x_dsa_switch_= ops =3D { .port_add_dscp_prio =3D yt921x_dsa_port_add_dscp_prio, #endif /* chip */ + .teardown =3D yt921x_dsa_teardown, .setup =3D yt921x_dsa_setup, }; =20 diff --git a/drivers/net/dsa/motorcomm/chip.h b/drivers/net/dsa/motorcomm/c= hip.h index 5f3b99e189c4..83cd454955dd 100644 --- a/drivers/net/dsa/motorcomm/chip.h +++ b/drivers/net/dsa/motorcomm/chip.h @@ -850,9 +850,14 @@ enum yt921x_fdb_entry_status { #define YT921X_ACL_NUM (YT921X_ACL_BLK_NUM * YT921X_ACL_ENT_PER_BLK) #define YT921X_UDF_NUM 8 =20 +#define YT921X_LED_GROUP_NUM 3 +#define YT921X_LED_PORT_NUM 10 + /* 8 internal + 2 external + 1 mcu */ #define YT921X_PORT_NUM 11 =20 +#define YT921X_NAME "yt921x" + #define yt921x_port_is_internal(port) ((port) < 8) #define yt921x_port_is_external(port) ((port) =3D=3D 8 || (port) =3D=3D 9) =20 @@ -938,6 +943,16 @@ struct yt921x_port { struct yt921x_mib mib; u64 rx_frames; u64 tx_frames; + +#if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) + unsigned char led_duty; + unsigned short led_cycle; + + unsigned char led_duty_mask; + unsigned char led_cycle_mask; + + struct yt921x_led *leds[YT921X_LED_GROUP_NUM]; +#endif }; =20 struct yt921x_reg_ops { diff --git a/drivers/net/dsa/motorcomm/leds.c b/drivers/net/dsa/motorcomm/l= eds.c new file mode 100644 index 000000000000..7d3c0f68d8ff --- /dev/null +++ b/drivers/net/dsa/motorcomm/leds.c @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 David Yang + */ + +#include + +#include "chip.h" +#include "leds.h" +#include "smi.h" + +#define to_yt921x_led(led_cdev) \ + container_of_const((led_cdev), struct yt921x_led, cdev) +#define to_yt921x_port(led) ((led)->port) +#define to_yt921x_priv(pp) \ + container_of_const((pp), struct yt921x_priv, ports[(pp)->index]) +#define to_device(priv) ((priv)->ds.dev) + +static u32 yt921x_led_regaddr(struct yt921x_priv *priv, int port, int grou= p) +{ + switch (group) { + case 0: + default: + return YT921X_LED0_PORTn(port); + case 1: + return YT921X_LED1_PORTn(port); + case 2: + return YT921X_LED2_PORTn(port); + } +} + +static int +yt921x_led_force_set(struct yt921x_priv *priv, int port, int group, bool o= n) +{ + struct yt921x_port *pp =3D &priv->ports[port]; + u32 ctrl; + u32 mask; + + /* No reversion - LED is sacrificed in case of IO error */ + pp->led_duty_mask &=3D ~BIT(group); + pp->led_cycle_mask &=3D ~BIT(group); + + mask =3D YT921X_LED2_PORT_FORCEn_M(group); + ctrl =3D on ? YT921X_LED2_PORT_FORCEn_ON(group) : + YT921X_LED2_PORT_FORCEn_OFF(group); + return yt921x_reg_update_bits(priv, YT921X_LED2_PORTn(port), mask, + ctrl); +} + +static int +yt921x_led_blink_select(const struct yt921x_priv *priv, unsigned long on, + unsigned long off, unsigned short *cyclep, + unsigned char *dutyp) +{ + static const unsigned char dutys[] =3D { + YT921X_LED_DUTY(1, 6), + YT921X_LED_DUTY(1, 4), + YT921X_LED_DUTY(1, 3), + YT921X_LED_DUTY(1, 2), + }; + unsigned int cycle_upper; + unsigned int cycle_req; + unsigned int duty_req; + unsigned int cycle; + unsigned int duty; + + cycle =3D YT921X_LED_BLINK_MAX; + cycle_upper =3D cycle * 11585 / 8192 + 1; /* M_SQRT2 * cycle */ + if (check_add_overflow(on, off, &cycle_req) || cycle_req >=3D cycle_upper) + return -EOPNOTSUPP; + + for (; cycle > YT921X_LED_BLINK_MIN; cycle_upper >>=3D 1, cycle >>=3D 1) + if (cycle_req >=3D cycle_upper >> 1) + break; + *cyclep =3D cycle; + + duty_req =3D DIV_ROUND_CLOSEST(YT921X_LED_DUTY_DENOM * + (on > off ? off : on), cycle_req); + for (unsigned int i =3D ARRAY_SIZE(dutys) - 1;; i--) + if (i =3D=3D 0 || duty_req >=3D (dutys[i - 1] + dutys[i]) / 2) { + duty =3D dutys[i]; + break; + } + if (on > off) + duty =3D YT921X_LED_DUTY_DENOM - duty; + *dutyp =3D duty; + + return 0; +} + +static int +yt921x_led_blink_set(struct yt921x_priv *priv, int port, int group, + unsigned long *onp, unsigned long *offp) +{ + struct yt921x_port *pp =3D &priv->ports[port]; + unsigned short cycle; + unsigned char duty; + bool use_cycle; + u32 ctrl; + u32 mask; + u32 val; + int res; + + if (!*onp && !*offp) { + cycle =3D YT921X_LED_BLINK_DEF; + duty =3D (pp->led_duty_mask & ~BIT(group)) ? pp->led_duty : + YT921X_LED_DUTY(1, 2); + + use_cycle =3D false; + } else { + res =3D yt921x_led_blink_select(priv, *onp, *offp, &cycle, &duty); + if (res) + return res; + + use_cycle =3D cycle < YT921X_LED_BLINK_DEF; + + if (use_cycle && cycle !=3D pp->led_cycle && + (pp->led_cycle_mask & ~BIT(group))) + return -EOPNOTSUPP; + if (duty !=3D pp->led_duty && (pp->led_duty_mask & ~BIT(group))) + return -EOPNOTSUPP; + } + + pp->led_cycle_mask &=3D ~BIT(group); + pp->led_duty_mask &=3D ~BIT(group); + + /* The chip seems to jam a while if changing duty directly */ + res =3D yt921x_reg_read(priv, YT921X_LED2_PORTn(port), &val); + if (res) + return res; + + ctrl =3D val & ~YT921X_LED2_PORT_FORCEn_M(group); + ctrl |=3D YT921X_LED2_PORT_FORCEn_OFF(group); + if (val !=3D ctrl) { + res =3D yt921x_reg_write(priv, YT921X_LED2_PORTn(port), ctrl); + if (res) + return res; + } + + mask =3D YT921X_LED1_PORT_BLINK_DUTY_M | YT921X_LED1_PORT_BLINK_DUTY_COMP; + switch (duty >=3D YT921X_LED_DUTY(1, 2) ? duty : + YT921X_LED_DUTY_DENOM - duty) { + default: + duty =3D YT921X_LED_DUTY(1, 2); + fallthrough; + case YT921X_LED_DUTY(1, 2): + ctrl =3D YT921X_LED1_PORT_BLINK_DUTY_1_2; + break; + case YT921X_LED_DUTY(2, 3): + ctrl =3D YT921X_LED1_PORT_BLINK_DUTY_2_3; + break; + case YT921X_LED_DUTY(3, 4): + ctrl =3D YT921X_LED1_PORT_BLINK_DUTY_3_4; + break; + case YT921X_LED_DUTY(5, 6): + ctrl =3D YT921X_LED1_PORT_BLINK_DUTY_5_6; + break; + } + if (duty < YT921X_LED_DUTY(1, 2)) + ctrl |=3D YT921X_LED1_PORT_BLINK_DUTY_COMP; + if (use_cycle) { + mask |=3D YT921X_LED1_PORT_OTHER_BLINK_M; + ctrl |=3D YT921X_LED1_PORT_OTHER_BLINK(9 - __fls(cycle)); + } + res =3D yt921x_reg_update_bits(priv, YT921X_LED1_PORTn(port), mask, ctrl); + if (res) + return res; + + ctrl =3D val & ~(YT921X_LED2_PORT_FORCEn_M(group) | + YT921X_LED2_PORT_FORCE_BLINKn_M(group)); + ctrl |=3D YT921X_LED2_PORT_FORCEn_BLINK(group); + if (use_cycle) + ctrl |=3D YT921X_LED2_PORT_FORCE_BLINKn_OTHER(group); + else + ctrl |=3D YT921X_LED2_PORT_FORCE_BLINKn(group, __fls(cycle) - 9); + res =3D yt921x_reg_write(priv, YT921X_LED2_PORTn(port), ctrl); + if (res) + return res; + + if (use_cycle) { + pp->led_cycle_mask |=3D BIT(group); + pp->led_cycle =3D cycle; + } + pp->led_duty_mask |=3D BIT(group); + pp->led_duty =3D duty; + + *onp =3D DIV_ROUND_CLOSEST(duty * cycle, YT921X_LED_DUTY_DENOM); + *offp =3D cycle - *onp; + return 0; +} + +struct yt921x_led_trigger_map { + unsigned long flags; + u32 mask; +}; + +static const struct yt921x_led_trigger_map yt921x_led_trigger_maps[] =3D { + {BIT(TRIGGER_NETDEV_LINK), + YT921X_LEDx_PORT_ACT_DUPLEX_HALF | YT921X_LEDx_PORT_ACT_DUPLEX_FULL}, + {BIT(TRIGGER_NETDEV_LINK_10), YT921X_LEDx_PORT_ACT_10M}, + {BIT(TRIGGER_NETDEV_LINK_100), YT921X_LEDx_PORT_ACT_100M}, + {BIT(TRIGGER_NETDEV_LINK_1000), YT921X_LEDx_PORT_ACT_1000M}, + {BIT(TRIGGER_NETDEV_HALF_DUPLEX), YT921X_LEDx_PORT_ACT_DUPLEX_HALF}, + {BIT(TRIGGER_NETDEV_FULL_DUPLEX), YT921X_LEDx_PORT_ACT_DUPLEX_FULL}, + {BIT(TRIGGER_NETDEV_TX), YT921X_LEDx_PORT_ACT_TX_BLINK}, + {BIT(TRIGGER_NETDEV_RX), YT921X_LEDx_PORT_ACT_RX_BLINK}, + {BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR), + YT921X_LEDx_PORT_ACT_COLLISION_BLINK}, +}; + +static bool +yt921x_led_trigger_is_supported(const struct yt921x_priv *priv, int port, + int group, unsigned long flags) +{ + if (!flags) + return true; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(yt921x_led_trigger_maps); i++) { + const struct yt921x_led_trigger_map *map =3D &yt921x_led_trigger_maps[i]; + + if ((flags & map->flags) =3D=3D map->flags) { + flags &=3D ~map->flags; + if (!flags) + return true; + } + } + + return false; +} + +static int +yt921x_led_trigger_get(struct yt921x_priv *priv, int port, int group, + unsigned long *flagsp) +{ + u32 addr; + u32 val; + int res; + + res =3D yt921x_reg_read(priv, YT921X_LED2_PORTn(port), &val); + if (res) + return res; + + if ((val & YT921X_LED2_PORT_FORCEn_M(group)) !=3D + YT921X_LED2_PORT_FORCEn_DONTCARE(group)) { + *flagsp =3D 0; + return 0; + } + + if (group !=3D 2) { + addr =3D yt921x_led_regaddr(priv, port, group); + res =3D yt921x_reg_read(priv, addr, &val); + if (res) + return res; + } + + *flagsp =3D 0; + for (unsigned int i =3D 0; i < ARRAY_SIZE(yt921x_led_trigger_maps); i++) { + const struct yt921x_led_trigger_map *map =3D &yt921x_led_trigger_maps[i]; + + if ((val & map->mask) =3D=3D map->mask) + *flagsp |=3D map->flags; + } + + return 0; +} + +static int +yt921x_led_trigger_set(struct yt921x_priv *priv, int port, int group, + unsigned long flags) +{ + struct yt921x_port *pp =3D &priv->ports[port]; + u32 addr; + u32 ctrl; + u32 mask; + int res; + + ctrl =3D 0; + for (unsigned int i =3D 0; i < ARRAY_SIZE(yt921x_led_trigger_maps); i++) { + const struct yt921x_led_trigger_map *map =3D &yt921x_led_trigger_maps[i]; + + if ((flags & map->flags) =3D=3D map->flags) { + flags &=3D ~map->flags; + ctrl |=3D map->mask; + if (!flags) + break; + } + } + if (flags) + return -EOPNOTSUPP; + + pp->led_duty_mask &=3D ~BIT(group); + pp->led_cycle_mask &=3D ~BIT(group); + + mask =3D !group ? YT921X_LED0_PORT_ACT_M : YT921X_LEDx_PORT_ACT_M; + if (group =3D=3D 2) { + mask |=3D YT921X_LED2_PORT_FORCEn_M(group); + ctrl |=3D YT921X_LED2_PORT_FORCEn_DONTCARE(group); + } + addr =3D yt921x_led_regaddr(priv, port, group); + res =3D yt921x_reg_update_bits(priv, addr, mask, ctrl); + if (res) + return res; + + if (group !=3D 2) { + mask =3D YT921X_LED2_PORT_FORCEn_M(group); + ctrl =3D YT921X_LED2_PORT_FORCEn_DONTCARE(group); + res =3D yt921x_reg_update_bits(priv, YT921X_LED2_PORTn(port), + mask, ctrl); + if (res) + return res; + } + + return 0; +} + +static int +yt921x_cled_brightness_set_blocking(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct yt921x_led *led =3D to_yt921x_led(led_cdev); + struct yt921x_port *pp =3D to_yt921x_port(led); + struct yt921x_priv *priv =3D to_yt921x_priv(pp); + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_led_force_set(priv, pp->index, led->group, brightness); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int +yt921x_cled_blink_set(struct led_classdev *led_cdev, unsigned long *delay_= on, + unsigned long *delay_off) +{ + struct yt921x_led *led =3D to_yt921x_led(led_cdev); + struct yt921x_port *pp =3D to_yt921x_port(led); + struct yt921x_priv *priv =3D to_yt921x_priv(pp); + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_led_blink_set(priv, pp->index, led->group, delay_on, + delay_off); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static struct device * __maybe_unused +yt921x_cled_hw_control_get_device(struct led_classdev *led_cdev) +{ + struct yt921x_led *led =3D to_yt921x_led(led_cdev); + struct yt921x_port *pp =3D to_yt921x_port(led); + struct yt921x_priv *priv =3D to_yt921x_priv(pp); + struct dsa_port *dp; + + dp =3D dsa_to_port(&priv->ds, pp->index); + if (!dp) + return NULL; + + if (dsa_port_is_user(dp)) + return !dp->user ? NULL : &dp->user->dev; + if (dsa_port_is_cpu(dp)) + return !dp->conduit ? NULL : &dp->conduit->dev; + + return NULL; +} + +static int __maybe_unused +yt921x_cled_hw_control_is_supported(struct led_classdev *led_cdev, + unsigned long flags) +{ + struct yt921x_led *led =3D to_yt921x_led(led_cdev); + struct yt921x_port *pp =3D to_yt921x_port(led); + struct yt921x_priv *priv =3D to_yt921x_priv(pp); + + if (yt921x_led_trigger_is_supported(priv, pp->index, led->group, flags)) + return 0; + return -EOPNOTSUPP; +} + +static int __maybe_unused +yt921x_cled_hw_control_get(struct led_classdev *led_cdev, unsigned long *f= lagsp) +{ + struct yt921x_led *led =3D to_yt921x_led(led_cdev); + struct yt921x_port *pp =3D to_yt921x_port(led); + struct yt921x_priv *priv =3D to_yt921x_priv(pp); + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_led_trigger_get(priv, pp->index, led->group, flagsp); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int __maybe_unused +yt921x_cled_hw_control_set(struct led_classdev *led_cdev, unsigned long fl= ags) +{ + struct yt921x_led *led =3D to_yt921x_led(led_cdev); + struct yt921x_port *pp =3D to_yt921x_port(led); + struct yt921x_priv *priv =3D to_yt921x_priv(pp); + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_led_trigger_set(priv, pp->index, led->group, flags); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int +yt921x_led_setup(struct yt921x_priv *priv, int port, + struct fwnode_handle *fwnode) +{ + struct yt921x_port *pp =3D &priv->ports[port]; + struct device *dev =3D to_device(priv); + struct led_init_data init_data; + struct led_classdev *led_cdev; + char name[LED_MAX_NAME_SIZE]; + enum led_default_state state; + struct yt921x_led *led; + bool force_high; + bool force_low; + u32 led2_val; + u32 inv_val; + u32 group; + u32 mask; + u32 ctrl; + bool on; + int res; + int ret; + + res =3D fwnode_property_read_u32(fwnode, "reg", &group); + if (res) { + dev_err(dev, "Missing LED reg for %pfw\n", fwnode); + return res; + } + if (group >=3D YT921X_LED_GROUP_NUM) { + dev_err(dev, "Invalid LED reg %u for port %d\n", group, port); + return -EINVAL; + } + if (pp->leds[group]) { + res =3D -EEXIST; + goto err; + } + + force_high =3D fwnode_property_read_bool(fwnode, "active-high"); + force_low =3D fwnode_property_read_bool(fwnode, "active-low"); + if (force_high && force_low) { + dev_err(dev, "Duplicate polarities for LED %02d:%02u\n", + port, group); + return -EINVAL; + } + + led =3D devm_kzalloc(dev, sizeof(*led), GFP_KERNEL); + if (!led) { + res =3D -ENOMEM; + goto err; + } + pp->leds[group] =3D led; + + led->port =3D pp; + led->group =3D group; + + state =3D led_init_default_state_get(fwnode); + + mutex_lock(&priv->reg_lock); + + /* Inversion is internal - force on will give low logic. + * In the rest of the file, treat LEDs as if active-low. + */ + inv_val =3D U32_MAX; + if (force_high || force_low) { + res =3D yt921x_reg_read(priv, YT921X_LED_PAR_INV, &inv_val); + if (res) + goto revoke_inv; + + mask =3D YT921X_LED_PAR_INV_INVnm(group, port); + ctrl =3D force_high ? inv_val | mask : inv_val & ~mask; + res =3D yt921x_reg_write(priv, YT921X_LED_PAR_INV, ctrl); + if (res) + goto revoke_inv; + } + + led2_val =3D U32_MAX; + res =3D yt921x_reg_read(priv, YT921X_LED2_PORTn(port), &led2_val); + if (res) + goto revoke_led2; + mask =3D YT921X_LED2_PORT_FORCEn_M(group); + + switch (state) { + case LEDS_DEFSTATE_OFF: + case LEDS_DEFSTATE_ON: + default: + on =3D state =3D=3D LEDS_DEFSTATE_ON; + ctrl =3D on ? YT921X_LED2_PORT_FORCEn_ON(group) : + YT921X_LED2_PORT_FORCEn_OFF(group); + res =3D yt921x_reg_write(priv, YT921X_LED2_PORTn(port), + (led2_val & ~mask) | ctrl); + if (res) + goto revoke_led2; + break; + case LEDS_DEFSTATE_KEEP: + on =3D (led2_val & mask) =3D=3D YT921X_LED2_PORT_FORCEn_ON(group); + led2_val =3D U32_MAX; + break; + } + + mutex_unlock(&priv->reg_lock); + + led_cdev =3D &led->cdev; + led_cdev->brightness =3D on; + led_cdev->max_brightness =3D 1; + led_cdev->flags =3D LED_RETAIN_AT_SHUTDOWN; + led_cdev->brightness_set_blocking =3D yt921x_cled_brightness_set_blocking; + led_cdev->blink_set =3D yt921x_cled_blink_set; +#ifdef CONFIG_LEDS_TRIGGERS + led_cdev->hw_control_trigger =3D "netdev"; + led_cdev->hw_control_get_device =3D yt921x_cled_hw_control_get_device; + led_cdev->hw_control_is_supported =3D yt921x_cled_hw_control_is_supported; + led_cdev->hw_control_get =3D yt921x_cled_hw_control_get; + led_cdev->hw_control_set =3D yt921x_cled_hw_control_set; +#endif + + snprintf(name, sizeof(name), YT921X_NAME "-%u:%02d:%02u", + priv->ds.index, port, group); + init_data =3D (typeof(init_data)){ + .fwnode =3D fwnode, + .default_label =3D ":port", + .devicename =3D name, + .devname_mandatory =3D true, + }; + res =3D devm_led_classdev_register_ext(dev, led_cdev, &init_data); + if (res) + goto revoke; + + return 0; + +revoke: + mutex_lock(&priv->reg_lock); +revoke_led2: + if (led2_val !=3D U32_MAX) { + ret =3D yt921x_reg_write(priv, YT921X_LED2_PORTn(port), led2_val); + if (ret) + dev_err(dev, + "Failed to restore %s for LED %02d:%02u: %d\n", + "LED2_PORT", port, group, ret); + } +revoke_inv: + if (inv_val !=3D U32_MAX) { + ret =3D yt921x_reg_write(priv, YT921X_LED_PAR_INV, inv_val); + if (ret) + dev_err(dev, + "Failed to restore %s for LED %02d:%02u: %d\n", + "LED_PAR_INV", port, group, ret); + } + mutex_unlock(&priv->reg_lock); + + pp->leds[group] =3D NULL; + devm_kfree(dev, led); + +err: + dev_err(dev, "Failed to initialize LED %02d:%02u: %d\n", + port, group, res); + return res; +} + +static void yt921x_leds_remove_port(struct yt921x_priv *priv, int port) +{ + struct yt921x_port *pp =3D &priv->ports[port]; + struct device *dev =3D to_device(priv); + + for (int group =3D 0; group < YT921X_LED_GROUP_NUM; group++) { + struct yt921x_led *led =3D pp->leds[group]; + + if (led) { + devm_led_classdev_unregister(dev, &led->cdev); + pp->leds[group] =3D NULL; + devm_kfree(dev, led); + } + } + + pp->led_duty_mask =3D 0; + pp->led_cycle_mask =3D 0; +} + +static int yt921x_leds_setup_port(struct yt921x_priv *priv, int port) +{ + struct device *dev =3D to_device(priv); + struct dsa_switch *ds =3D &priv->ds; + struct device_node *leds_np; + struct dsa_port *dp; + + dp =3D dsa_to_port(ds, port); + leds_np =3D of_get_child_by_name(dp->dn, "leds"); + if (!leds_np) + return 0; + + if (port >=3D YT921X_LED_PORT_NUM) { + dev_err(dev, "Cannot configure LEDs for port %d\n", port); + of_node_put(leds_np); + return -EINVAL; + } + + for_each_child_of_node_scoped(leds_np, led_np) { + yt921x_led_setup(priv, port, of_fwnode_handle(led_np)); + /* Allow partial configuration: LEDs are optional */ + } + + of_node_put(leds_np); + return 0; +} + +void yt921x_leds_remove(struct yt921x_priv *priv) +{ + for (int port =3D 0; port < YT921X_LED_PORT_NUM; port++) + yt921x_leds_remove_port(priv, port); +} + +int yt921x_leds_setup(struct yt921x_priv *priv) +{ + struct dsa_switch *ds =3D &priv->ds; + struct dsa_port *dp; + + /* LEDs are always enabled. There is no way to disable them altogether + * (as far as I know). + */ + + dsa_switch_for_each_port(dp, ds) { + int port =3D dp->index; + + if (!dp->dn) + continue; + + yt921x_leds_setup_port(priv, port); + /* Allow partial configuration: LEDs are optional */ + } + + return 0; +} diff --git a/drivers/net/dsa/motorcomm/leds.h b/drivers/net/dsa/motorcomm/l= eds.h new file mode 100644 index 000000000000..11df479ee581 --- /dev/null +++ b/drivers/net/dsa/motorcomm/leds.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2026 David Yang + */ + +#ifndef _YT_LEDS_H +#define _YT_LEDS_H + +#include +#include +#include +#include + +#define YT921X_LED_CTRL 0xd0000 +#define YT921X_LED_CTRL_UNK BIT(21) +#define YT921X_LED_CTRL_LOOPDETECT_BLINK_M GENMASK(20, 19) /* cycle =3D 5= 12 * x ms */ +#define YT921X_LED_CTRL_LOOPDETECT_BLINK(x) FIELD_PREP(YT921X_LED_CTRL_= LOOPDETECT_BLINK_M, (x)) +#define YT921X_LED_CTRL_PORT_NUM_M GENMASK(16, 13) +#define YT921X_LED_CTRL_PORT_NUM(x) FIELD_PREP(YT921X_LED_CTRL_PORT_NU= M_M, (x)) +#define YT921X_LED_CTRL_MODE_M GENMASK(1, 0) +#define YT921X_LED_CTRL_MODE(x) FIELD_PREP(YT921X_LED_CTRL_MODE_M, (x)) +#define YT921X_LED_CTRL_MODE_PARALLEL YT921X_LED_CTRL_MODE(0) +#define YT921X_LED_CTRL_MODE_SERIAL YT921X_LED_CTRL_MODE(2) +#define YT921X_LED0_PORTn(port) (0xd0004 + 4 * (port)) +#define YT921X_LED0_PORT_ACT_M GENMASK(17, 0) +#define YT921X_LED0_PORT_ACT_LINK_TRY_DIS BIT(17) +#define YT921X_LED0_PORT_ACT_COLLISION_BLINK_INDI BIT(16) +#define YT921X_LED1_PORTn(port) (0xd0040 + 4 * (port)) +#define YT921X_LED1_PORT_OTHER_BLINK_M GENMASK(31, 30) /* cycle =3D 512 = >> x ms */ +#define YT921X_LED1_PORT_OTHER_BLINK(x) FIELD_PREP(YT921X_LED1_PORT_OTH= ER_BLINK_M, (x)) +#define YT921X_LED1_PORT_EEE_BLINK_M GENMASK(29, 28) /* cycle =3D 512 >>= x ms */ +#define YT921X_LED1_PORT_EEE_BLINK(x) FIELD_PREP(YT921X_LED1_PORT_EEE_= BLINK_M, (x)) +#define YT921X_LED1_PORT_BLINK_DUTY_COMP BIT(27) +#define YT921X_LED1_PORT_BLINK_DUTY_M GENMASK(26, 25) +#define YT921X_LED1_PORT_BLINK_DUTY(x) FIELD_PREP(YT921X_LED1_PORT_BLIN= K_DUTY_M, (x)) +#define YT921X_LED1_PORT_BLINK_DUTY_1_2 YT921X_LED1_PORT_BLINK_DUTY(0) +#define YT921X_LED1_PORT_BLINK_DUTY_2_3 YT921X_LED1_PORT_BLINK_DUTY(1) +#define YT921X_LED1_PORT_BLINK_DUTY_3_4 YT921X_LED1_PORT_BLINK_DUTY(2) +#define YT921X_LED1_PORT_BLINK_DUTY_5_6 YT921X_LED1_PORT_BLINK_DUTY(3) +#define YT921X_LED2_PORTn(port) (0xd0080 + 4 * (port)) +#define YT921X_LED2_PORT_FORCEn_M(grp) GENMASK(4 * (grp) + 19, 4 * (grp)= + 18) +#define YT921X_LED2_PORT_FORCEn(grp, x) ((x) << (4 * (grp) + 18)) +#define YT921X_LED2_PORT_FORCEn_DONTCARE(grp) YT921X_LED2_PORT_FORCEn(g= rp, 0) +#define YT921X_LED2_PORT_FORCEn_BLINK(grp) YT921X_LED2_PORT_FORCEn(grp,= 1) +#define YT921X_LED2_PORT_FORCEn_ON(grp) YT921X_LED2_PORT_FORCEn(grp, 2) +#define YT921X_LED2_PORT_FORCEn_OFF(grp) YT921X_LED2_PORT_FORCEn(grp, 3) +#define YT921X_LED2_PORT_FORCE_BLINKn_M(grp) GENMASK(4 * (grp) + 17, 4 * = (grp) + 16) /* cycle =3D 512 << x ms */ +#define YT921X_LED2_PORT_FORCE_BLINKn(grp, x) ((x) << (4 * (grp) + 16)) +#define YT921X_LED2_PORT_FORCE_BLINKn_OTHER(grp) YT921X_LED2_PORT_FORCE_= BLINKn(grp, 3) +#define YT921X_LEDx_PORT_ACT_M GENMASK(15, 0) +#define YT921X_LEDx_PORT_ACT_EEE_BLINK BIT(15) +#define YT921X_LEDx_PORT_ACT_LOOPDETECT_BLINK BIT(14) +#define YT921X_LEDx_PORT_ACT_ACTIVE_BLINK BIT(13) +#define YT921X_LEDx_PORT_ACT_DUPLEX_FULL BIT(12) +#define YT921X_LEDx_PORT_ACT_DUPLEX_HALF BIT(11) +#define YT921X_LEDx_PORT_ACT_TX_BLINK BIT(10) +#define YT921X_LEDx_PORT_ACT_RX_BLINK BIT(9) +#define YT921X_LEDx_PORT_ACT_TX BIT(8) +#define YT921X_LEDx_PORT_ACT_RX BIT(7) +#define YT921X_LEDx_PORT_ACT_1000M BIT(6) +#define YT921X_LEDx_PORT_ACT_100M BIT(5) +#define YT921X_LEDx_PORT_ACT_10M BIT(4) +#define YT921X_LEDx_PORT_ACT_COLLISION_BLINK BIT(3) +#define YT921X_LEDx_PORT_ACT_1000M_BLINK BIT(2) +#define YT921X_LEDx_PORT_ACT_100M_BLINK BIT(1) +#define YT921X_LEDx_PORT_ACT_10M_BLINK BIT(0) +#define YT921X_LED_SER_CTRL 0xd0100 +#define YT921X_LED_SER_CTRL_UNK GENMASK(25, 24) /* delay? */ +#define YT921X_LED_SER_CTRL_ACTIVE_LOW BIT(4) +#define YT921X_LED_SER_CTRL_GRP_NUM_M GENMASK(1, 0) /* #grp - 1 */ +#define YT921X_LED_SER_CTRL_GRP_NUM(x) FIELD_PREP(YT921X_LED_SER_CTRL_G= RP_NUM_M, (x)) +#define YT921X_LED_SER_MAPnm(grp, port) (0xd0104 + 8 * (2 - (grp)) + 4 * (= (port) / 5)) +#define YT921X_LED_SER_MAP_DSTn_PORT_M(port) GENMASK(6 * ((port) % 5) + 5= , 6 * ((port) % 5) + 2) +#define YT921X_LED_SER_MAP_DSTn_PORT(port, x) ((x) << (6 * ((port) % 5)= + 2)) +#define YT921X_LED_SER_MAP_DSTn_LED_M(port) GENMASK(6 * ((port) % 5) + 1,= 6 * ((port) % 5)) +#define YT921X_LED_SER_MAP_DSTn_LED(port, x) ((x) << (6 * ((port) % 5))) +#define YT921X_LED_PAR_PORTS 0xd01c4 +#define YT921X_LED_PAR_INV 0xd01c8 +#define YT921X_LED_PAR_INV_INVnm(grp, port) BIT(10 * (grp) + (port)) +#define YT921X_LED_PAR_MAPn(port) (0xd01d0 + 4 * (port)) +#define YT921X_LED_PAR_MAP_DSTn_PORT_M(grp) GENMASK(6 * (grp) + 5, 6 * (g= rp) + 2) +#define YT921X_LED_PAR_MAP_DSTn_PORT(grp, x) ((x) << (6 * (grp) + 2)) +#define YT921X_LED_PAR_MAP_DSTn_LED_M(grp) GENMASK(6 * (grp) + 1, 6 * (gr= p)) +#define YT921X_LED_PAR_MAP_DSTn_LED(grp, x) ((x) << (6 * (grp))) + +#define YT921X_LED_BLINK_MIN 64 +#define YT921X_LED_BLINK_DEF 512 +#define YT921X_LED_BLINK_MAX 2048 + +/* 2 * lcm(2, 3, 4, 6) */ +#define YT921X_LED_DUTY_DENOM 24 +#define YT921X_LED_DUTY(nom, denom) (YT921X_LED_DUTY_DENOM * (nom) / (deno= m)) + +struct yt921x_priv; + +struct yt921x_led { + struct led_classdev cdev; + struct yt921x_port *port; + unsigned char group; +}; + +#if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) + +void yt921x_leds_remove(struct yt921x_priv *priv); +int yt921x_leds_setup(struct yt921x_priv *priv); + +#else + +static inline void yt921x_leds_remove(struct yt921x_priv *priv) {} + +static inline int yt921x_leds_setup(struct yt921x_priv *priv) +{ + return 0; +} + +#endif + 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v11 5/5] dt-bindings: net: dsa: yt921x: Add LEDs definition example Date: Mon, 31 Aug 2026 12:38:58 +0800 Message-ID: <20260831044818.4103477-6-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260831044818.4103477-1-mmyangfl@gmail.com> References: <20260831044818.4103477-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LEDs definition example for yt921x to describe how they should be defined for a correct usage. Signed-off-by: David Yang Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/dsa/motorcomm,yt921x.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yam= l b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml index 33a6552e46fc..93ba5b181205 100644 --- a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml +++ b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml @@ -21,6 +21,9 @@ description: | =20 Any port can be used as the CPU port. =20 + Each port has at most 3 LEDs connected and can be declared using the sta= ndard + LEDs structure. + properties: compatible: const: motorcomm,yt9215 @@ -59,6 +62,7 @@ unevaluatedProperties: false examples: - | #include + #include =20 mdio { #address-cells =3D <1>; @@ -113,6 +117,25 @@ examples: label =3D "lan1"; phy-mode =3D "internal"; phy-handle =3D <&sw_phy0>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + default-state =3D "keep"; + }; + }; }; =20 ethernet-port@1 { --=20 2.53.0