From nobody Sat Sep 26 19:36:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D882A3DAABD; Mon, 31 Aug 2026 09:31:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788168692; cv=none; b=i5otfqr2XzoTQlPvEZhaomqMrB0fKpQTzaKox9PDDts9zKRyASxk5w+R9EjaY2p8+/JSlRXR4VRce+Z2iDxWZClQqGB4wm/8uJBQU8LGBuPYeKOcqfDUS89hwsC1CJvDKzJlt45ghfFslrGJyxflczvSW5a1+wiNqBFk0WKxeqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788168692; c=relaxed/simple; bh=lmymNw9vRwFG8RLd1ooeMOy0Pe+zb0TvI05tu3fq76Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dpjkp2sPGUt3Y73vcEZtYUKQjY/Fra4SN95AXZyftkMgnFxqIppHSjEOedZB9XMdf2wYE00/nDZFoa3I1y59l/51JEzdAnAa82JOBv+BqHORMVUfQ2rq3XkX6kfTO7qytrUfsijZUwkycXJUhvFOFJFWEyHnVlSHtnaO7cP6kLs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ri+hEUGW; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ri+hEUGW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 031B01F000E9; Mon, 31 Aug 2026 09:31:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788168690; bh=GLiBEoEDVdWz7B9/oM3Z4DBrql9BwJ5kz4e26G6SP/4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Ri+hEUGWnZxD3+wKBpXFSfRBVENDPIEljRNNQuyP1oBBY6k4IfAmGXnHkf1zI2dBw 10d59Q5i1yBbbMMOabFfgwxhun2kdWbp1Fu07KINKU7DWrg71zuVxVHMluA6/XRfx1 8ZFpoQL85BKCw42/kO61VfIGOHBI/YzV+whEbSmDAWh/F/zSYRCoaB0ep36T3eDGTE SveZ7LU0DT3yP53cBFhG51KBaCcWA2b6kRqe4Te0EibuHuWs5cKfMu5skchlcmZ2oj f+mojMhwaW81lgDWwbcVrQeaSIrLpgP+BJ+2USctc8SoALq1woCuRk+vh3eaTCzyD3 SvGaW8KAghroA== From: Mattijs Korpershoek Date: Mon, 31 Aug 2026 11:31:21 +0200 Subject: [PATCH v2 1/2] dt-bindings: phy: Add sa8255p high-speed USB PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-phy-qcom-snps-femto-v2-8255-v2-1-dc6197ffde1b@kernel.org> References: <20260831-phy-qcom-snps-femto-v2-8255-v2-0-dc6197ffde1b@kernel.org> In-Reply-To: <20260831-phy-qcom-snps-femto-v2-8255-v2-0-dc6197ffde1b@kernel.org> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2753; i=mkorpershoek@kernel.org; h=from:subject:message-id; bh=lmymNw9vRwFG8RLd1ooeMOy0Pe+zb0TvI05tu3fq76Y=; b=owEBbQGS/pANAwAKARkNHbRmThk1AcsmYgBqlUnslx12Sfd7huEnIP1amezkYgjK1AzT4Vz9t 93peOJoDQeJATMEAAEKAB0WIQQu6UKnth9qvlMTrQAZDR20Zk4ZNQUCapVJ7AAKCRAZDR20Zk4Z NRcAB/9vlUeBgvfJYEvc/SmDoTKe7bX4/9c11+6LP4Ogzb7wmtKaNd9vDzWrzokvRsrh2nChHOG 4HdpO1z6kdAaNHlQ/urVGG/Kl9/B4Sb4iFNCj3Zzbbxr0V9jkxthtX7wHqmRaGwyHOlUOVP5TQi qHabwDartwW+asTblqRb9Ix3rTyVCWP2pEz/Ogr0zKb2lpjVGOfzPXg0ZGTyHljAO83bm368FNV pn4kYbQh04GxJeDO89IXbMTKhqJ+ZvAEmsjlD7PoK0+nVQFQ7/0Qq3sS2+MEFkq6b4U7lqJ96Ap Fi3KO7l/njHtE6JNc+NQLTkBW5Y0IZQMTkZsvvfwxZpbaWUm X-Developer-Key: i=mkorpershoek@kernel.org; a=openpgp; fpr=8234A35B45C0D26B31C1A2DA570338B018144F28 SA8255p platform abstracts resources such as resets, clocks and regulators in firmware. The SCMI firmware exposes multiple protocols to control such resources which are identified by protocol_id. For this USB phy, 2 SCMI protocols are exposed by the firmware: * power domain management protocol (protocol_id=3D0x11) * performance domain management protocol (protocol_id=3D0x13) The power domain has 2 indices: 'core' and 'transfer'. * core controls the regulators, the clocks and the reset * transfer only controls the clocks For example, to power on/off the PHY, we should use the 'core' domain. To disable data transfer and keeping power enabled, we should use the 'transfer' domain. Add a new binding for the Qualcomm SA8255p Synopsys Femto High-Speed USB PHY V2 found in SA8255P. Note: the performance domain (0x13) exposes opaques values (0xa to 0x11) for which we don't have any information. Since it is not mandatory for the PHY to be functional, we have ommited it from the bindings. We can document it (and make them part of the dt ABI) once we have more information. Signed-off-by: Mattijs Korpershoek Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/qcom,sa8255p-usb-hs-phy.yaml | 52 ++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sa8255p-usb-hs-phy.= yaml b/Documentation/devicetree/bindings/phy/qcom,sa8255p-usb-hs-phy.yaml new file mode 100644 index 000000000000..fff474a8345d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,sa8255p-usb-hs-phy.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,sa8255p-usb-hs-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8255p Synopsys Femto High-Speed USB PHY V2 + +maintainers: + - Mattijs Korpershoek + +properties: + compatible: + const: qcom,sa8255p-usb-hs-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: core + - const: transfer + +required: + - compatible + - reg + - "#phy-cells" + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + phy@88e4000 { + compatible =3D "qcom,sa8255p-usb-hs-phy"; + reg =3D <0x0 0x088e4000 0x0 0x120>; + #phy-cells =3D <0>; + power-domains =3D <&scmi12_pd 1>, <&scmi12_pd 0>; + power-domain-names =3D "core", "transfer"; + }; + }; --=20 2.55.0 From nobody Sat Sep 26 19:36:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E77043DC84C; Mon, 31 Aug 2026 09:31:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788168695; cv=none; b=b0Q6fCMgGLoheVJ/mI1wdIE8CAAQ2e9otQLXWMYmOuaUfqhN2+gcXAUAQr8abMqT7cYffXzYnlRK9Wt4khsCFvEEAy15ricaf3VTHnjzoZ18U6jspVM7mHqSgzUZr2mVMJ6DSQrvGzWjYLTH/hA3FF2jsTQGfSazT7nW6ItC+EA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788168695; c=relaxed/simple; bh=L8yVAuZ0p7R3TBgw4ucNT2BmgLAyvMjGHOlC5ZAv9+w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BtGTDzKyIWXSyr7KFaKsgp636R2fR8Lwz50Tv5oiq2fRWwk+uHGoYALMndK1ef5HjxBL0xYy5hIMlFJVvuUPRbK41aNPKwqxNumjjkJyA+RTKhwe4oyhxBZuk+TIvREWZaWF00/15E1yrTtrdLrY4EOY8HKbO348YW9bWR5Juac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kmIcq4xw; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kmIcq4xw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFB6D1F000E9; Mon, 31 Aug 2026 09:31:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788168693; bh=rTa8+V70YLvjFs5QyXjGxohUtO9HmQ9CMMNH0V1H63A=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=kmIcq4xwn4Mwy0UTX9sANvsmihZaeD740cawUoT2cNbmA5FSzYWijLnZiy8zaQ1MS bSdYIDqPWGweTVzAW6cNCn7rAkJ65+HLeSz/r25B4plU7UuyBsZpoCfPeJZmJFSRjA oS5Mfdtu7h/EeHyFGDwa9raCHx1DaJ2k3w6p2xenp88TWJkBK6NN1c+h8TTcFpmbHm ZWK639p/9HwSYw5nW4S6H2bDweFmMory4EQGNIE+nP0fPBRony3xofJ0643RNebKVZ qPEL5GeABDh+QJaadOzFzaCJSJef9BP9EYP7G+xYWKMVf/YQk8Pmlcs39LUdk9bupa uGxOpzMFF+C9Q== From: Mattijs Korpershoek Date: Mon, 31 Aug 2026 11:31:22 +0200 Subject: [PATCH v2 2/2] phy: qcom-snps-femto-v2: Add support for SA8255P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-phy-qcom-snps-femto-v2-8255-v2-2-dc6197ffde1b@kernel.org> References: <20260831-phy-qcom-snps-femto-v2-8255-v2-0-dc6197ffde1b@kernel.org> In-Reply-To: <20260831-phy-qcom-snps-femto-v2-8255-v2-0-dc6197ffde1b@kernel.org> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mattijs Korpershoek , Sriram Dash X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7802; i=mkorpershoek@kernel.org; h=from:subject:message-id; bh=+SZdJWp4P9AdsdwcvOOjWhPUODlk+eJzoogJOEbmKUk=; b=owEBbQGS/pANAwAKARkNHbRmThk1AcsmYgBqlUntiiMYkvsPFW0sFMvEVlCGgBeTIUqPtMAjv rFAwAkCV2qJATMEAAEKAB0WIQQu6UKnth9qvlMTrQAZDR20Zk4ZNQUCapVJ7QAKCRAZDR20Zk4Z Ne5ZCACoCFvgXBXlpS3KJKqr1tWznt7AsnM/dyMkHe8ap8NJEX1L+A9WNaIgaFcn+YMJLiJOtCs 4ry048VzhaTliB4nnHOmBBPTh1RlE7jOVd/Z6OYG2uCMzNAnYDmlr0nk9e7UHdAGOwbyr/3hNtr 0ytIkb1cy+gWg6jONlvkizdXdGjV9/9LVETMiyPMq0aSN0vhViV+BMQz008BcHfW/fGo7GiqueS 1AV0aCAyNmF8xSfCtELg5avkY7X2caYXYp+mMJDBi8Tdfk13FOAWQFknulVtp+QiCnr1Gb3PJma 2MOgBS31FhZOR36yBzje+IEK3UUfK9W36r/Yp9ghkGXyVpQB X-Developer-Key: i=mkorpershoek@kernel.org; a=openpgp; fpr=8234A35B45C0D26B31C1A2DA570338B018144F28 From: Sriram Dash The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power on/off. Power domain "core" controls the GDSC, resets, and TLMM (GPIOs) whereas power domain "transfer" controls clocks and interconnects. In this variant, two disjoint sets of resources are modeled against the power domain suppliers which can be turned on/off to achieve modeled device states. Two modeled low power states d1 and d3 are supported. transition: d0 <--> d3 :: both core and transfer suppliers transition: d0 <--> d1 :: only transfer supplier Signed-off-by: Sriram Dash Signed-off-by: Mattijs Korpershoek Reviewed-by: Neil Armstrong --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 127 ++++++++++++++++++++++= ++-- 1 file changed, 118 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qu= alcomm/phy-qcom-snps-femto-v2.c index 980ad1fb1e2e..9fdf7ae681b6 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,7 @@ struct override_param_map { u8 table_size; u8 reg_offset; u8 param_mask; + bool fw_managed; }; =20 struct phy_override_seq { @@ -121,6 +123,7 @@ struct phy_override_seq { * @phy_initialized: if PHY has been initialized correctly * @mode: contains the current mode the PHY is in * @update_seq_cfg: tuning parameters for phy init + * @pd_list: list of power domains associated with the device */ struct qcom_snps_hsphy { struct device *dev; @@ -136,8 +139,81 @@ struct qcom_snps_hsphy { bool phy_initialized; enum phy_mode mode; struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS]; + + struct dev_pm_domain_list *pd_list; }; =20 +static void qcom_snps_domain_detach(void *data) +{ + struct qcom_snps_hsphy *hsphy =3D data; + + dev_pm_domain_detach_list(hsphy->pd_list); +} + +static int qcom_snps_domain_attach(struct qcom_snps_hsphy *hsphy) +{ + struct dev_pm_domain_attach_data pd_data =3D { + .pd_flags =3D PD_FLAG_NO_DEV_LINK, + .pd_names =3D (const char*[]) { "core", "transfer" }, + .num_pd_names =3D 2, + }; + struct device *dev =3D hsphy->dev; + int ret; + + ret =3D dev_pm_domain_attach_list(dev, &pd_data, &hsphy->pd_list); + if (ret < 0) + return dev_err_probe(dev, ret, "domain attach failed\n"); + + return 0; +} + +/* d3_to_d0 transition by turning on all the suppliers */ +static int qcom_snps_d3_to_d0(struct qcom_snps_hsphy *hsphy) +{ + int ret; + + if (!hsphy->pd_list) + return 0; + + ret =3D pm_runtime_resume_and_get(hsphy->pd_list->pd_devs[0]); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(hsphy->pd_list->pd_devs[1]); + if (ret) + pm_runtime_put_sync(hsphy->pd_list->pd_devs[0]); + + return ret; +} + +/* d0_to_d3 transition by turning off all the suppliers */ +static void qcom_snps_d0_to_d3(struct qcom_snps_hsphy *hsphy) +{ + if (!hsphy->pd_list) + return; + + pm_runtime_put_sync(hsphy->pd_list->pd_devs[1]); + pm_runtime_put_sync(hsphy->pd_list->pd_devs[0]); +} + +/* d1_to_d0 transition by turning on the 'transfer' supplier */ +static int qcom_snps_d1_to_d0(struct qcom_snps_hsphy *hsphy) +{ + if (!hsphy->pd_list) + return 0; + + return pm_runtime_resume_and_get(hsphy->pd_list->pd_devs[1]); +} + +/* d0_to_d1 transition by turning off the 'transfer' supplier */ +static void qcom_snps_d0_to_d1(struct qcom_snps_hsphy *hsphy) +{ + if (!hsphy->pd_list) + return; + + pm_runtime_put_sync(hsphy->pd_list->pd_devs[1]); +} + static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy) { struct device *dev =3D hsphy->dev; @@ -196,6 +272,8 @@ static int qcom_snps_hsphy_suspend(struct qcom_snps_hsp= hy *hsphy) 0, USB2_AUTO_RESUME); } =20 + qcom_snps_d0_to_d1(hsphy); + return 0; } =20 @@ -203,7 +281,7 @@ static int qcom_snps_hsphy_resume(struct qcom_snps_hsph= y *hsphy) { dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n"); =20 - return 0; + return qcom_snps_d1_to_d0(hsphy); } =20 static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *d= ev) @@ -316,6 +394,10 @@ static const struct override_param ls_fs_output_impeda= nce_sc7280[] =3D { { 1310, 0 }, }; =20 +static const struct override_param_map sa8255p_snps_hs_phy =3D { + .fw_managed =3D true, +}; + static const struct override_param_map sc7280_snps_7nm_phy[] =3D { { "qcom,hs-disconnect-bp", @@ -390,9 +472,15 @@ static int qcom_snps_hsphy_init(struct phy *phy) =20 dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); =20 + ret =3D qcom_snps_d3_to_d0(hsphy); + if (ret < 0) { + dev_err(hsphy->dev, "Failed to transition to d0 state\n"); + return ret; + } + ret =3D regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); if (ret) - return ret; + goto transition_to_d3; =20 ret =3D clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks); if (ret) { @@ -472,6 +560,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); poweroff_phy: regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); +transition_to_d3: + qcom_snps_d0_to_d3(hsphy); =20 return ret; } @@ -485,6 +575,8 @@ static int qcom_snps_hsphy_exit(struct phy *phy) regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); hsphy->phy_initialized =3D false; =20 + qcom_snps_d0_to_d3(hsphy); + return 0; } =20 @@ -496,6 +588,10 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = =3D { }; =20 static const struct of_device_id qcom_snps_hsphy_of_match_table[] =3D { + { + .compatible =3D "qcom,sa8255p-usb-hs-phy", + .data =3D &sa8255p_snps_hs_phy, + }, { .compatible =3D "qcom,sm8150-usb-hs-phy", }, { .compatible =3D "qcom,usb-snps-hs-5nm-phy", }, { @@ -565,6 +661,7 @@ static int qcom_snps_hsphy_probe(struct platform_device= *pdev) { struct device *dev =3D &pdev->dev; struct qcom_snps_hsphy *hsphy; + const struct override_param_map *cfg; struct phy_provider *phy_provider; struct phy *generic_phy; int ret, i; @@ -580,14 +677,26 @@ static int qcom_snps_hsphy_probe(struct platform_devi= ce *pdev) if (IS_ERR(hsphy->base)) return PTR_ERR(hsphy->base); =20 - ret =3D qcom_snps_hsphy_clk_init(hsphy); - if (ret) - return dev_err_probe(dev, ret, "failed to initialize clocks\n"); + cfg =3D of_device_get_match_data(dev); + + if (cfg && cfg->fw_managed) { + ret =3D qcom_snps_domain_attach(hsphy); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, qcom_snps_domain_detach, hsphy); + if (ret) + return ret; + } else { + ret =3D qcom_snps_hsphy_clk_init(hsphy); + if (ret) + return dev_err_probe(dev, ret, "failed to initialize clocks\n"); =20 - hsphy->phy_reset =3D devm_reset_control_get_exclusive(&pdev->dev, NULL); - if (IS_ERR(hsphy->phy_reset)) { - dev_err(dev, "failed to get phy core reset\n"); - return PTR_ERR(hsphy->phy_reset); + hsphy->phy_reset =3D devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(hsphy->phy_reset)) { + dev_err(dev, "failed to get phy core reset\n"); + return PTR_ERR(hsphy->phy_reset); + } } =20 num =3D ARRAY_SIZE(hsphy->vregs); --=20 2.55.0