From nobody Sat Sep 26 16:22:53 2026 Received: from mail-106111.protonmail.ch (mail-106111.protonmail.ch [79.135.106.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55A9641CB20; Mon, 31 Aug 2026 13:28:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.111 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182889; cv=none; b=M7PSpZfAKGpAZeDUYeaaBr2yBH2n7YVAikJRhYvlt0W1ExtDjL9y4qi1QIF8iuivnJszeXT+eCqToHjedNYFHgK4QvFLDSUFlpEbRHWCu1CyQtsejx44aF1xWVuy+AMUbmsdEpcjsCGopm8aa0yvv/vKHAxNvL69xoA0y8togJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182889; c=relaxed/simple; bh=Cm0XJSNXpJMzO5ie7uX5yADJaQR/hPQbPioD/AbZ2rs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nFHJ7wpiP+zbzALT36iHCqYxYoCNtzVbTnvRtuAum1xflm4NTErR4xtg2NFdUp/K0+u/eycnKdntb6o6LqcOmMoMJuTL5aZtdb8P2trp+hy6mZI/H1Z63tCaTeRc4as0zdx+pGSDRD39az697fS+GUQl6kr5a+rmMvXHAX+MH8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com; spf=pass smtp.mailfrom=geanix.com; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b=N34wkR1S; arc=none smtp.client-ip=79.135.106.111 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=geanix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b="N34wkR1S" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=geanix.com; s=protonmail; t=1788182882; x=1788442082; bh=dCIzJ7auFLsAAuxTb9FPaGJ0CJxz0+3pHeAEI1munHQ=; h=From:Date:Subject:Message-Id:References:In-Reply-To:To:Cc:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=N34wkR1S6ysVvrC1PZSiYeyCvlzweQUPwhARHLy2fsVDesUPBtr8FJ8qioRL4N6oX SxtVPQ1F0Hp7qljqtwFQPri5sortF2qsBUrSeGzKYgMaC9ywaWDQJyGkScCe2v8igO 6Kf47xrPQN00OYIMan+ZXjhlnnls+O88hlEwTIXALmwgafx2E0eHq2pDM5aA5s5RYo 8xZj2DNZUCf7S7iG2JGT/E4KzzHbqxL2n32cGdftH+FKY0s1XVFD/qx0di+T5AQtDW hSlX1NIW0i79mqj0FZnjfpyb9+tPKMndwqfPKGnXd+p+esd0vt80D3dPHIyRBgUjzs L4Vzc+dxlZfag== X-Pm-Submission-Id: 4hYVDH1zmLz2Scht From: Esben Haabendal Date: Mon, 31 Aug 2026 15:27:43 +0200 Subject: [PATCH v4 1/4] drm/bridge: nwl-dsi: Cleanup endpoint mux control selection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-nwl-dsi-fixes-v4-1-6a2a1cb23910@geanix.com> References: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> In-Reply-To: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , =?utf-8?q?Guido_G=C3=BCnther?= , Fabio Estevam , Robert Chiras , Sam Ravnborg Cc: Esben Haabendal , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788182874; l=2014; i=esben@geanix.com; s=20240523; h=from:subject:message-id; bh=Cm0XJSNXpJMzO5ie7uX5yADJaQR/hPQbPioD/AbZ2rs=; b=RGSYE/R38haixbJ8KT9D+ANay1cfgJXSJswzBtm/VZvOnZfYxvgmID3+XocY7QeO9hF/mUIRq cc+mUBmAsIgBE4eTsS9qpwmKtUQfoXAG1ASaH8TMqQ344Q9nh+PnjNl X-Developer-Key: i=esben@geanix.com; a=ed25519; pk=PbXoezm+CERhtgVeF/QAgXtEzSkDIahcWfC7RIXNdEk= Using the endpoint define values makes it more clear that the argument to mux_control_try_select() must be valid state integers, and not something that looks like a boolean. The endpoint value is kept, as it will be used in a following patch that changes behavior slightly based on which endpoint is selected. Cc: stable@vger.kernel.org Reviewed-by: Luca Ceresoli Signed-off-by: Esben Haabendal --- drivers/gpu/drm/bridge/nwl-dsi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-= dsi.c index 09992529f3d8..80e26a947ae6 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -110,6 +110,8 @@ struct nwl_dsi { int error; =20 struct nwl_dsi_transfer *xfer; + + unsigned int endpoint; }; =20 static const struct regmap_config nwl_dsi_regmap_config =3D { @@ -1088,13 +1090,12 @@ static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) static int nwl_dsi_select_input(struct nwl_dsi *dsi) { struct device_node *remote; - u32 use_dcss =3D 1; int ret; =20 remote =3D of_graph_get_remote_node(dsi->dev->of_node, 0, NWL_DSI_ENDPOINT_LCDIF); if (remote) { - use_dcss =3D 0; + dsi->endpoint =3D NWL_DSI_ENDPOINT_LCDIF; } else { remote =3D of_graph_get_remote_node(dsi->dev->of_node, 0, NWL_DSI_ENDPOINT_DCSS); @@ -1103,11 +1104,12 @@ static int nwl_dsi_select_input(struct nwl_dsi *dsi) "No valid input endpoint found\n"); return -EINVAL; } + dsi->endpoint =3D NWL_DSI_ENDPOINT_DCSS; } =20 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", - (use_dcss) ? "DCSS" : "LCDIF"); - ret =3D mux_control_try_select(dsi->mux, use_dcss); + (dsi->endpoint =3D=3D NWL_DSI_ENDPOINT_DCSS) ? "DCSS" : "LCDIF"); + ret =3D mux_control_try_select(dsi->mux, dsi->endpoint); if (ret < 0) DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); =20 --=20 2.55.0 From nobody Sat Sep 26 16:22:53 2026 Received: from mail-244107.protonmail.ch (mail-244107.protonmail.ch [109.224.244.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DDEA41D118 for ; Mon, 31 Aug 2026 13:28:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182890; cv=none; b=rDjBCxKzByjx1zmP1ggOSEw5r+Ql55W7qZKqEcMW25o7MQ14+7JqPVe/wNb9z30aI1znpbi6S6Uk5cWVmG3WTRHVG3HRzTagNkhlUYlIcr2PA6/gyGM9SfZc+L+HH1mv3Lq4Ly51lp7PDhR16ReGIEFsCAFoV2nyoVJY+yeWIl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182890; c=relaxed/simple; bh=ag01qXAa2aIW3dSq2m0vudZwjm5eb/Q95y5o2MKYx18=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cgk1iUnjas7rLanxiS3wamjh6/fStnJvVNAGBJmvGdImRxfUFhnB953DB4VUuQfhpSzRy0sASp8WO09gIdoQuNZ9Z6GEUqDLFXzXt5Hut7ICPN7UsRuTNTezJxJNsUJIuuzmXCp6sdCfc4hbDvArOTe79KaNTPa7/K0gzqkJk6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com; spf=pass smtp.mailfrom=geanix.com; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b=15Anndom; arc=none smtp.client-ip=109.224.244.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=geanix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b="15Anndom" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=geanix.com; s=protonmail; t=1788182883; x=1788442083; bh=a5dpSaLKghfNIm4oSZMav4+4dz7CwzYx+GQqHJE+ad8=; h=From:Date:Subject:Message-Id:References:In-Reply-To:To:Cc:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=15AnndomcQFJjI+63GmKI7hnFfJg8BKCE5mCs9tIEIGW6Fn9+AkeAB8mcjeOG7pmg SDWZcw8triAo+lur3/PgKL9BngIO6gkrtQ6VVL5LzhipEvvgn2wGl9+Uznohx4/dks HkZXqlCzL4TOHZ45SWdjblAkBOIpDSA3eCuLWAMXYqbstVQ3EAYzi9v+IXWe1SaACR PxlR8NTAY6tXKj/Bctz0mQp2WgKyxQkJ1PEa5rJCrPsejLhjSMklZhlLLM6FW6hh69 H6U41nIeeTi2gl7iz3Gaz3pqeCdN0vauqU+7S9vUq23NBg85irR9RndJ2ezJ7j9rWZ SGKN4fv7lesNg== X-Pm-Submission-Id: 4hYVDK60C3z2ScPH From: Esben Haabendal Date: Mon, 31 Aug 2026 15:27:44 +0200 Subject: [PATCH v4 2/4] drm/bridge: nwl-dsi: Limit LCDIF specific sync override Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-nwl-dsi-fixes-v4-2-6a2a1cb23910@geanix.com> References: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> In-Reply-To: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , =?utf-8?q?Guido_G=C3=BCnther?= , Fabio Estevam , Robert Chiras , Sam Ravnborg Cc: Esben Haabendal , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788182874; l=1455; i=esben@geanix.com; s=20240523; h=from:subject:message-id; bh=ag01qXAa2aIW3dSq2m0vudZwjm5eb/Q95y5o2MKYx18=; b=6jJFi+dt9uiYSGDebCufHHjPIhcbOINyJPUGDfpXKjz0h3IVZ0FRbMU7RBVTy8rlHQRktqGOG WP3woXbTAZKAdjsRYGJEDJ4pDm7Ooh3niy82qejff+aJVwJCYP/Rjgc X-Developer-Key: i=esben@geanix.com; a=ed25519; pk=PbXoezm+CERhtgVeF/QAgXtEzSkDIahcWfC7RIXNdEk= When using DCSS with NWL, overriding the mode flags to enforce active high sync is preventing the use of active low with downstream bridges, such as ti-sn65dsi83, which will not see such mode flags set by the panel. Fixes: 44cfc6233447 ("drm/bridge: Add NWL MIPI DSI host controller support") Cc: stable@vger.kernel.org Signed-off-by: Esben Haabendal --- drivers/gpu/drm/bridge/nwl-dsi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-= dsi.c index 80e26a947ae6..1aab46e1a168 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -823,10 +823,13 @@ static int nwl_dsi_bridge_atomic_check(struct drm_bri= dge *bridge, struct drm_connector_state *conn_state) { struct drm_display_mode *adjusted_mode =3D &crtc_state->adjusted_mode; + struct nwl_dsi *dsi =3D bridge_to_dsi(bridge); =20 /* At least LCDIF + NWL needs active high sync */ - adjusted_mode->flags |=3D (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); - adjusted_mode->flags &=3D ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + if (dsi->endpoint =3D=3D NWL_DSI_ENDPOINT_LCDIF) { + adjusted_mode->flags |=3D (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + adjusted_mode->flags &=3D ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + } =20 /* * Do a full modeset if crtc_state->active is changed to be true. --=20 2.55.0 From nobody Sat Sep 26 16:22:53 2026 Received: from mail-244106.protonmail.ch (mail-244106.protonmail.ch [109.224.244.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 168B241D4D4; Mon, 31 Aug 2026 13:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182893; cv=none; b=D9AS7KkbJd4yOU0QNlhG2orFIdciubqaozNjxdCX0r6gLcqRH2NFCNuB9Z35ljyZ0gTSZDwjeH1HNsGNtzqV18gE3HbfkRPD1UODxHYj8Xd3tyjbOK2RHNQ9wkMFDXK9YOnvjYBJEeDxs3DvJfaSB/Qau1mngI1V39P8fhxhw84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182893; c=relaxed/simple; bh=XdjEUinjNT2C3KAlMGkOLvsEZ1P9NxDmJt7rE0Z6cwE=; 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h=From:Date:Subject:Message-Id:References:In-Reply-To:To:Cc:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=K9Zzub1Zv7IOGRfiJhTGBQ17DTzjIBPXUQNAr7NY1lAofHTvNfuq63F+pAm0tGslJ 3zRBAYGioljz+tzjdbRNL3ewWRDZrxNVn+HZ4uY3yRXbvwXHE+uMeQ+DPqpfFeF10e yzfOyUYT+AixfJzCBn4B4HXhuLPOzrpQJrP8/E+oyntf+UZuCHPPWcfs1rV8j7rSTy PCiHn7+1hmu0qLBAo6Ozxgrz4BZJRQuXmC65wQ4diPFH9maxaBXXzp3golHOLb/LDm NhW/vWp0C7ykkcD47e3BByZxRZSn0ObXhG0kkGKw3WPuk7EtlwyWyUqTxXawOG9TqN FmeoVmNIkTGSA== X-Pm-Submission-Id: 4hYVDN0s33z2ScWl From: Esben Haabendal Date: Mon, 31 Aug 2026 15:27:45 +0200 Subject: [PATCH v4 3/4] drm/bridge: nwl-dsi: Correct auto-insert EOTP behavior Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-nwl-dsi-fixes-v4-3-6a2a1cb23910@geanix.com> References: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> In-Reply-To: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , =?utf-8?q?Guido_G=C3=BCnther?= , Fabio Estevam , Robert Chiras , Sam Ravnborg Cc: Esben Haabendal , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Laurentiu Palcu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788182874; l=1534; i=esben@geanix.com; s=20240523; h=from:subject:message-id; bh=kKsffolI3Qs7QhM0aRcvOCyPsNNcZdkiD1A5b8xHohA=; b=J4LsSxC5aITLgDQB/KpUb10mwQ9+TU75DNKgkf9gtJnRagL/g2POMbhlVmoQqvkvItbnynqH2 i5az424w6E/DhIa1tfFb3tBZQqNqn10NIkJGysG1ivPL90VWoiN3f+5 X-Developer-Key: i=esben@geanix.com; a=ed25519; pk=PbXoezm+CERhtgVeF/QAgXtEzSkDIahcWfC7RIXNdEk= From: Robert Chiras In order to respect the DSI protocol, make sure that auto-insert EOTP is enabled according to the NO_EOT_PACKET flag instead of the CLOCK_NON_CONTINUOUS flag. Fixes: 44cfc6233447 ("drm/bridge: Add NWL MIPI DSI host controller support") Cc: stable@vger.kernel.org Signed-off-by: Esben Haabendal Cc: Robert Chiras Cc: Laurentiu Palcu --- drivers/gpu/drm/bridge/nwl-dsi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-= dsi.c index 1aab46e1a168..f3f4334136c0 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -222,13 +222,15 @@ static int nwl_dsi_config_host(struct nwl_dsi *dsi) DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes); nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1); =20 - if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01); - nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01); - } else { + else nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00); + + if (dsi->dsi_mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00); - } + else + nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01); =20 /* values in byte clock cycles */ cycles =3D ui2bc(cfg->clk_pre); --=20 2.55.0 From nobody Sat Sep 26 16:22:53 2026 Received: from mail-43170.protonmail.ch (mail-43170.protonmail.ch [185.70.43.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F49041BA63 for ; Mon, 31 Aug 2026 13:28:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182897; cv=none; b=sseCJv5O2naGIAzLVdgp33QWdsHb9Nz/fmTwsmg/tj11NbSoae9uOdOsINmWgxLrYxRG2syHeJd4TL9dL961tFKt1qM0AMhqi9AucPEh3rvego8pSKvKMZxKXKqeQvaTxm7Q7YTmX4UUM7WVcS8IBZ3tyDBoUy1GInKWZ0pwVec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788182897; c=relaxed/simple; bh=64K2cghv9Pu2xpnXUBYhri9wjrzdmxCfnbz+dJ+v7CA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TIQQXHsb35TZsVlSW9MmUVLXjP+60y5+ID5R7HfDjYiJ5phSiHdz2khDDDevcuWSJbatBfvTkIXxArVEDUsgTOrJNesMcmqoDY/jDZGpgQMB3C0z2DCQijKKRK6Rk1WiFTnlwW5vjLQ+8McmY5Ju2ZygmzPNbZzC2dPSCTfjUDs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com; spf=pass smtp.mailfrom=geanix.com; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b=CMLcfY9L; arc=none smtp.client-ip=185.70.43.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=geanix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b="CMLcfY9L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=geanix.com; s=protonmail; t=1788182888; x=1788442088; bh=3fdS3EZrph4HPHI4SWA+jBFn4XLmDsXX2TCBKNHGKYY=; h=From:Date:Subject:Message-Id:References:In-Reply-To:To:Cc:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=CMLcfY9LMqElBerz4Y0gbbLazZXPBSBZdl0dTTKpUV/lc3HJaSca8he9IjoHfBibw QUUYhsdcaLRdk4Kir3R4e9Qrl4/LZmE3vwT5aZGuJpVyy/hfVj5hyAvm9+5//xKQMH tDof5RSTyxK5wRDIvDhixY9WPbi7lw6kZ/buAbIGv5Se+HkR7AubplOtmIOR13FExE GzhJQHv7DKCvk9OzX3WbKRVjF6dLBjGn4YxeBug6Y8OvWtAYqzFGIQTMIBwoPqXy1H KG5rP0qQtzZauMnj1T50lKnCV6IS2Xruk5hP4C6XRtzr0vOUYHEFAUPGDaKRfIH4dK p/FaToipswH0w== X-Pm-Submission-Id: 4hYVDQ0gLBz2Schm From: Esben Haabendal Date: Mon, 31 Aug 2026 15:27:46 +0200 Subject: [PATCH v4 4/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-nwl-dsi-fixes-v4-4-6a2a1cb23910@geanix.com> References: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> In-Reply-To: <20260831-nwl-dsi-fixes-v4-0-6a2a1cb23910@geanix.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , =?utf-8?q?Guido_G=C3=BCnther?= , Fabio Estevam , Robert Chiras , Sam Ravnborg Cc: Esben Haabendal , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, "Oliver F. Brown" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788182874; l=4295; i=esben@geanix.com; s=20240523; h=from:subject:message-id; bh=64K2cghv9Pu2xpnXUBYhri9wjrzdmxCfnbz+dJ+v7CA=; b=YLqsr0ZSDA2TJ+CpZrx6XWdrlH2XyAh4K5+wi1c98Erjem/qUGO+Q4MF61X2YPRl5dky0V533 +05wNbV9QW3BJaTdchwTc/YmIC3Y97qeheTxN+xOm5QAjliWl0Xap0k X-Developer-Key: i=esben@geanix.com; a=ed25519; pk=PbXoezm+CERhtgVeF/QAgXtEzSkDIahcWfC7RIXNdEk= The NWL MIPI Host controller registers specifies the horizontal front porch, sync pulse, and back porch in DSI packet payload size in bytes (ie. not in pixel clocks). The calculation for this is (mostly) described in section 13.6.3.5.1.2 of the i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual (rev. 3.1). The formula shown there does not take packet header size into account though. The formula implemented here converts the hfp, hsa, and hbp to DSI packet bytes and then subtracts the number of packet header bytes. It is worth noting that these values only needs to match approximately, according to the reference manual. Based on commit in NXP vendor tree commit f2a61699749d ("LF-7981-4: drm/bridge: nwl-dsi: Correct MIPI DSI hori= zontal sync timing") Signed-off-by: Esben Haabendal Cc: Robert Chiras Cc: Oliver F. Brown --- drivers/gpu/drm/bridge/nwl-dsi.c | 60 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-= dsi.c index f3f4334136c0..eb604733eea0 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include #include @@ -264,6 +265,9 @@ static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) bool burst_mode; int hfront_porch, hback_porch, vfront_porch, vback_porch; int hsync_len, vsync_len; + int hfp, hbp, hsa; + u64 hs_clk_rate, pclk_rate; + int h_blank, pkt_hdr_len, pkt_len; =20 hfront_porch =3D dsi->mode.hsync_start - dsi->mode.hdisplay; hsync_len =3D dsi->mode.hsync_end - dsi->mode.hsync_start; @@ -317,9 +321,59 @@ static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) dsi->mode.hdisplay); } =20 - nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch); - nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch); - nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len); + hs_clk_rate =3D dsi->phy_cfg.mipi_dphy.hs_clk_rate; + pclk_rate =3D (u64)dsi->mode.clock * 1000; + DRM_DEV_DEBUG_DRIVER(dsi->dev, "hs_clk_rate: %llu Hz\n", hs_clk_rate); + + /* + * Calculate the bytes needed, according to the RM formula: + * Time of DPI event =3D time to transmit x number of bytes on the DSI in= terface + * dpi_event_size * dpi_pclk_period =3D dsi_bytes * 8 * hs_bit_period / n= um_lanes + * =3D=3D=3D> + * dsi_bytes =3D dpi_event_size * dpi_pclk_period * num_lanes / (8 * hs_b= it_period) + * =3D=3D=3D> (substituting period =3D 1 / rate) + * dsi_bytes =3D dpi_event_size * num_lanes * hs_clk_rate / (8 * dpi_pclk= _rate) + */ + hfp =3D DIV64_U64_ROUND_UP((u64)hfront_porch * dsi->lanes * hs_clk_rate, = 8 * pclk_rate); + hbp =3D DIV64_U64_ROUND_UP((u64)hback_porch * dsi->lanes * hs_clk_rate, 8= * pclk_rate); + hsa =3D DIV64_U64_ROUND_UP((u64)hsync_len * dsi->lanes * hs_clk_rate, 8 *= pclk_rate); + + /* Make sure horizontal blankins are even numbers */ + hfp =3D roundup(hfp, 2); + hbp =3D roundup(hbp, 2); + hsa =3D roundup(hsa, 2); + + /* + * We need to subtract the packet header length: 32 + * In order to make sure we don't get negative values, + * subtract a proportional value to the total length of the + * horizontal blanking duration. + */ + h_blank =3D hfp + hbp + hsa; + + if (h_blank) { + pkt_len =3D min(hfp, roundup(((hfp * 100 / h_blank) * 32) / 100, 2)); + pkt_hdr_len =3D pkt_len; + hfp -=3D pkt_len; + + pkt_len =3D min(hbp, roundup(((hbp * 100 / h_blank) * 32) / 100, 2)); + pkt_hdr_len +=3D pkt_len; + hbp -=3D pkt_len; + + pkt_len =3D min(hsa, 32 - pkt_hdr_len); + pkt_hdr_len +=3D pkt_len; + hsa -=3D pkt_len; + if (pkt_hdr_len !=3D 32) + dev_warn(dsi->dev, + "Unable to subtract packet header length fully: %d left\n", + 32 - pkt_hdr_len); + } + + DRM_DEV_DEBUG_DRIVER(dsi->dev, "Register values: hfp=3D%d hbp=3D%d hsa=3D= %d\n", hfp, hbp, hsa); + + nwl_dsi_write(dsi, NWL_DSI_HFP, hfp); + nwl_dsi_write(dsi, NWL_DSI_HBP, hbp); + nwl_dsi_write(dsi, NWL_DSI_HSA, hsa); =20 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0); nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1); --=20 2.55.0