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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:17:38 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:18 +0800 Subject: [PATCH v6 01/29] drm/msm/dp: move link-level teardown from display_disable to display_unprepare Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-1-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=2701; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=qcRrf3REEES67vfWVVl9C/KGWotx0DutXL36uVlj3Wg=; b=wzu/q03Cgn+niwJ4swCE42LwrJHPsyifdwT7QnCxcc/uaRyQ8KOcoYRcyXpyzYw5m8bOLiC8s OKTp2I503j/BwmbbLj7MTIJUwjF3Q1gAkgr8xc2K4SjpGoD5FMyajce X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: OnbS5koVVmS7yFD2OSa5uZsOppt21s45 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX1n4QZ4t44MKd aLC+ZHeT9761SJF52q9cHUWEpN4yo/gSf2auGUEZqDWzaXBLXhtLC4JGejNRuvKwg/KlrPeUG2M +/wyMRfXkVAwt33uftzTCxiz68nt0cKxt322vThjdu+Sh9h/TLFM9qfo9nz79HZoSWV4l1gg9ac Saap0aAtyu77uscufSfWWpu35fBMHLGJA/HAcHk99aGRl3AFT/DUknGnf8D8YUG8L6ENLdTC0qO 15eN5XpIdQTPYjLBX+GQ9jpkHXU/embj61qablZ0FyqTfU72NTt3BlCvxpVQUfRAGvUn9ejgfNE +x7DTMXb/PJQJWcd2DfThFUhBXqbA4d6SbLrQaU2ZiAmDf6HX4IOswS+7mX9oWJ0FRsDhFzYIVB 3b5LBogdQ+QBn/xzb+O6Vr/pNfB+ookDfh0gDFHNx6hLO0SLcmYpndB+YG+7IpkgSplEqfJ8yHr Dfuje9nOhWV92ioJdsg== X-Proofpoint-GUID: OnbS5koVVmS7yFD2OSa5uZsOppt21s45 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX+PBzFtFD5Ydx GPtjDQTcHH1eM8D52UIelx37RZz1CLWGFJodFeZ5Rrc5iqVYhVGRjjPY9RPOgti+EWJ2P+2NQLQ YX9p82COJygzlw77W2ifcnUlIEJC0no= X-Authority-Analysis: v=2.4 cv=a5kAM0SF c=1 sm=1 tr=0 ts=6a9538a3 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=a95-bzEMD9sxZBs1_CcA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar msm_dp_display_disable() currently mixes stream-level shutdown (disable VSC SDP, off pixel clk, clear power_on) with link-level teardown (PSM config when sink_count=3D=3D0, off_link, PHY re-init or host PHY exit). For DP MST the same link is shared across multiple streams, so disabling one stream must not tear down the link. Move the link-level steps into msm_dp_display_unprepare() so that display_disable() handles only the per-stream sequence, mirroring the split already present on the prepare path (display_prepare_link vs display_set_mode / display_enable). SST behaviour is unchanged: atomic_post_disable() still calls display_disable() followed by display_unprepare() in the same order, and the cached dp->panel used inside unprepare is the same panel that was previously passed in. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index bc646d172abe..a7b0196bb1c7 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -722,20 +722,6 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp, =20 msm_dp_ctrl_off_pixel_clk(dp->ctrl); =20 - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count =3D=3D 0) - msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); - - msm_dp_ctrl_off_link(dp->ctrl, msm_dp_panel); - - if (dp->link->sink_count =3D=3D 0) - /* re-init the PHY so that we can listen to Dongle disconnect */ - msm_dp_ctrl_reinit_phy(dp->ctrl); - else - msm_dp_display_host_phy_exit(dp); - - msm_dp_display->power_on =3D false; - drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); return 0; } @@ -1465,6 +1451,20 @@ static void msm_dp_display_unprepare(struct msm_dp_d= isplay_private *dp) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count =3D=3D 0) + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + + msm_dp_ctrl_off_link(dp->ctrl, dp->panel); + + if (dp->link->sink_count =3D=3D 0) + /* re-init the PHY so that we can listen to Dongle disconnect */ + msm_dp_ctrl_reinit_phy(dp->ctrl); + else + msm_dp_display_host_phy_exit(dp); + + msm_dp_display->power_on =3D false; + pm_runtime_put_sync(&msm_dp_display->pdev->dev); =20 drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DB2F3D25C2 for ; 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This lets config_msa() use panel->stream_id when writing SOFTWARE_MVID/NVID for MST streams, added by a later patch. No functional change. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 59070f399e2d..1ed713b957c6 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2463,14 +2463,14 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_c= trl_private *ctrl, } =20 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, - u32 rate, u32 stream_rate_khz, - bool is_ycbcr_420) + struct msm_dp_panel *panel, u32 rate) { u32 pixel_m, pixel_n; u32 mvid, nvid, pixel_div, dispcc_input_rate; u32 const nvid_fixed =3D DP_LINK_CONSTANT_N_VALUE; u32 const link_rate_hbr2 =3D 540000; u32 const link_rate_hbr3 =3D 810000; + u32 stream_rate_khz =3D panel->msm_dp_mode.drm_mode.clock; unsigned long den, num; =20 switch (rate) { @@ -2516,7 +2516,7 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl= _private *ctrl, nvid =3D temp; } =20 - if (is_ycbcr_420) + if (panel->msm_dp_mode.out_fmt_is_yuv_420) mvid /=3D 2; =20 if (link_rate_hbr2 =3D=3D rate) @@ -2573,15 +2573,13 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, struct msm_dp_panel * bool mainlink_ready =3D false; struct msm_dp_ctrl_private *ctrl; unsigned long pixel_rate; - unsigned long pixel_rate_orig; =20 if (!msm_dp_ctrl) return -EINVAL; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate_orig =3D panel->msm_dp_mode.drm_mode.clock; - pixel_rate =3D pixel_rate_orig; + pixel_rate =3D panel->msm_dp_mode.drm_mode.clock; =20 if (msm_dp_ctrl->wide_bus_en || panel->msm_dp_mode.out_fmt_is_yuv_420) pixel_rate >>=3D 1; @@ -2604,10 +2602,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, struct msm_dp_panel * =20 msm_dp_ctrl_configure_source_params(ctrl, panel); =20 - msm_dp_ctrl_config_msa(ctrl, - ctrl->link->link_params.rate, - pixel_rate_orig, - panel->msm_dp_mode.out_fmt_is_yuv_420); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:17:48 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:20 +0800 Subject: [PATCH v6 03/29] drm/msm/dp: drop redundant config_ctrl_link() from msm_dp_ctrl_on_stream() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-3-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=888; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=K08RSR7jFMIU1z3Wf63hI19PHcL0gXlgR6VRva1a4mo=; b=JiH+b0PUcxR9TZDRGECUHDy8hG1r9PNwZcW+rV8WYP5iMs8wXbkI9XMuK9Q/ZskgO/YIEsqMt y+gBOKOYN6EBulj7OEfmbDAC8XvHo/R/cHC1xPsbKNjpN/NJyPvTHP+ X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: RhP9bovTGaqRzRhXZpdZ7-DYgzMmI3GA X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX5oDL1XrTYeND +bl6Gp/BsSYkVAWKRJUDf9PwUurW4L5mVqf4QYrMrk/nG6diF7U9/bKtSTPOMo9x5v0QSiDNa3T IV89fiZbGOa8oWmFivJBIKuiODRnw18= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX0zVMspu6z0g+ Fsi2NvQJYUPB2M+a3lDA/c635vNw+++/hWBGsfwfb8nNpU1QWIjenMlfDkSRKt23zmUhCAEBNnn ILWsGPSM2pj/GGoVXjgGLVCy1OG9K06EPOjLmtQpMQ+yzJzI+smJ6G5bIDK/eMd0sl4j5dnlp/4 qKblwy6yweUl+0moUwrPx1WpE/AuUfontYiXeKs5QPuLEj1W7bpATKmNqsW7mYvfQ7Kp4in82gz kvvXUt1Q+vQTNcX7LisRKW+Ej1oASk7v98Nvfga0r4AM8q0SRtwWlryVpn/iJMLpIggRQh5Sj1D 2Ct+h/KsCvxqqfnqXvt5UMiQyFkywRCaqe67z+x9+7/Ir467iEt4Oa8cSP2+VOhWrHTqOIvIXaw 173har0/qLb+w+eAaQ5AM2yYrJUk2cYVWc+j8gbw9w3gJa4M1Hp9IghzFLD0E0SOWtrJ1e2So1w qonCDt2Y8lisOhvN/8A== X-Authority-Analysis: v=2.4 cv=ZOPnX37b c=1 sm=1 tr=0 ts=6a9538ad cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=P3NwbF1cJ5UVZmgLWE8A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: RhP9bovTGaqRzRhXZpdZ7-DYgzMmI3GA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 REG_DP_CONFIGURATION_CTRL contains link-wide state and is already programmed during link training. Calling config_ctrl_link() from msm_dp_ctrl_on_stream() rewrites the same configuration and is unnecessary. Remove the redundant call. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 1ed713b957c6..e7bb9558c0b4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2598,7 +2598,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl_link(ctrl, panel); =20 msm_dp_ctrl_configure_source_params(ctrl, panel); =20 --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 306C33CF20A for ; Mon, 31 Aug 2026 08:17:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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There shall be one dp_panel for each stream but the dp_display object shall be shared among them. To represent this abstraction, add a stream_id field to struct msm_dp_panel and introduce the msm_dp_stream_id enum. For SST, the field is initialized to DP_STREAM_0. In the MST path, each panel will be assigned an actual stream_id at stream-enable time by the MST layer (added in later patches). Use the stream ID to control the pixel clock of that respective stream by extending the clock handles and state tracking of the DP pixel clock to an array of max supported streams. The maximum streams currently is 4. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 70 +++++++++++++++++++++++----------= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- drivers/gpu/drm/msm/dp/dp_panel.c | 1 + drivers/gpu/drm/msm/dp/dp_panel.h | 11 ++++++ 5 files changed, 57 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index e7bb9558c0b4..67f1da46b973 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -126,7 +126,8 @@ struct msm_dp_ctrl_private { unsigned int num_link_clks; struct clk_bulk_data *link_clks; =20 - struct clk *pixel_clk; + struct clk *pixel_clk[DP_STREAM_MAX]; + unsigned int num_pixel_clks; =20 union phy_configure_opts phy_opts; =20 @@ -138,7 +139,7 @@ struct msm_dp_ctrl_private { =20 bool core_clks_on; bool link_clks_on; - bool stream_clks_on; + bool stream_clks_on[DP_STREAM_MAX]; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -1750,7 +1751,7 @@ int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *m= sm_dp_ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); =20 @@ -1769,7 +1770,7 @@ void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl = *msm_dp_ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); } @@ -1800,7 +1801,7 @@ static int msm_dp_ctrl_link_clk_enable(struct msm_dp_= ctrl *msm_dp_ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); =20 @@ -1819,7 +1820,7 @@ static void msm_dp_ctrl_link_clk_disable(struct msm_d= p_ctrl *msm_dp_ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); } @@ -2190,38 +2191,39 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struc= t msm_dp_ctrl_private *ctrl) return success; } =20 -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate) +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate, + enum msm_dp_stream_id stream_id) { int ret; =20 - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + ret =3D clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); return ret; } =20 - if (WARN_ON_ONCE(ctrl->stream_clks_on)) - return 0; + if (WARN_ON_ONCE(ctrl->stream_clks_on[stream_id])) + return -EINVAL; =20 - ret =3D clk_prepare_enable(ctrl->pixel_clk); + ret =3D clk_prepare_enable(ctrl->pixel_clk[stream_id]); if (ret) { DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); return ret; } - ctrl->stream_clks_on =3D true; + ctrl->stream_clks_on[stream_id] =3D true; =20 return ret; } =20 -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id) { struct msm_dp_ctrl_private *ctrl; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; + if (ctrl->stream_clks_on[stream_id]) { + clk_disable_unprepare(ctrl->pixel_clk[stream_id]); + ctrl->stream_clks_on[stream_id] =3D false; } } =20 @@ -2242,7 +2244,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl, panel); =20 ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, panel); @@ -2252,7 +2254,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl } =20 pixel_rate =3D panel->msm_dp_mode.drm_mode.clock; - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, panel->stream_id); if (ret) return ret; =20 @@ -2546,9 +2548,8 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes); =20 - drm_dbg_dp(ctrl->drm_dev, - "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", - ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); + drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d\n", + ctrl->core_clks_on, ctrl->link_clks_on); =20 if (!ctrl->link_clks_on) { /* link clk is off */ ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); @@ -2586,7 +2587,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); =20 - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, panel->stream_id); if (ret) return ret; =20 @@ -2643,8 +2644,6 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl, ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(panel); - msm_dp_ctrl_mainlink_disable(ctrl); =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); @@ -2714,6 +2713,13 @@ static const char *ctrl_clks[] =3D { "ctrl_link_iface", }; =20 +static const char * const pixel_clks[] =3D { + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel", +}; + static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -2747,9 +2753,19 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *= msm_dp_ctrl) if (rc) return rc; =20 - ctrl->pixel_clk =3D devm_clk_get(dev, "stream_pixel"); - if (IS_ERR(ctrl->pixel_clk)) - return PTR_ERR(ctrl->pixel_clk); + ctrl->pixel_clk[0] =3D devm_clk_get(dev, pixel_clks[0]); + if (IS_ERR(ctrl->pixel_clk[0])) + return PTR_ERR(ctrl->pixel_clk[0]); + ctrl->num_pixel_clks =3D 1; + + for (i =3D DP_STREAM_1; i < DP_STREAM_MAX; i++) { + ctrl->pixel_clk[i] =3D devm_clk_get_optional(dev, pixel_clks[i]); + if (IS_ERR(ctrl->pixel_clk[i])) + return PTR_ERR(ctrl->pixel_clk[i]); + if (!ctrl->pixel_clk[i]) + break; + ctrl->num_pixel_clks++; + } =20 return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 5902cf7e746a..be0d89d60914 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -24,7 +24,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm= _dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index a7b0196bb1c7..fb6607f65ded 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -720,7 +720,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp, =20 msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 - msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); =20 drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index e76dad0f6663..745ee6976897 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -723,6 +723,7 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux =20 msm_dp_panel =3D &panel->msm_dp_panel; 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Introduce the helper functions msm_dp_re= ad_pn and msm_dp_write_pn for pixel register programming. All pixel clocks share the same register layout but use different base addresses. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 + drivers/gpu/drm/msm/dp/dp_display.c | 40 ++++++++++++----- drivers/gpu/drm/msm/dp/dp_panel.c | 90 ++++++++++++++++++---------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 2 +- 5 files changed, 87 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 67f1da46b973..c0f5226dc383 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2770,6 +2770,16 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *= msm_dp_ctrl) return 0; } =20 +bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + return ctrl->stream_clks_on[stream_id]; +} + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, struct drm_dp_aux *aux, struct phy *phy, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index be0d89d60914..bf593f4a4480 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -55,4 +55,6 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ct= rl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); =20 void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); +bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *dp_ctrl, + enum msm_dp_stream_id stream_id); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index fb6607f65ded..3dce9334d0c2 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -85,8 +85,8 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; =20 - void __iomem *p0_base; - size_t p0_len; + void __iomem *pixel_base[DP_STREAM_MAX]; + size_t pixel_len; }; =20 struct msm_dp_desc { @@ -562,7 +562,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >p0_base); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >pixel_base[0]); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); @@ -843,8 +843,13 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state= , struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, - msm_dp_display->p0_base, "dp_p0"); + + for (int i =3D 0; i < DP_STREAM_MAX; i++) { + if (!msm_dp_ctrl_stream_clks_on(msm_dp_display->ctrl, i)) + continue; + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[i], "dp_p%d", i); + } } =20 void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1124,6 +1129,7 @@ static void __iomem *msm_dp_ioremap(struct platform_d= evice *pdev, int idx, size_ static int msm_dp_display_get_io(struct msm_dp_display_private *display) { struct platform_device *pdev =3D display->msm_dp_display.pdev; + int i; =20 display->ahb_base =3D msm_dp_ioremap(pdev, 0, &display->ahb_len); if (IS_ERR(display->ahb_base)) @@ -1153,8 +1159,8 @@ static int msm_dp_display_get_io(struct msm_dp_displa= y_private *display) display->aux_len =3D DP_DEFAULT_AUX_SIZE; display->link_base =3D display->ahb_base + DP_DEFAULT_LINK_OFFSET; display->link_len =3D DP_DEFAULT_LINK_SIZE; - display->p0_base =3D display->ahb_base + DP_DEFAULT_P0_OFFSET; - display->p0_len =3D DP_DEFAULT_P0_SIZE; + display->pixel_base[0] =3D display->ahb_base + DP_DEFAULT_P0_OFFSET; + display->pixel_len =3D DP_DEFAULT_P0_SIZE; =20 return 0; } @@ -1165,10 +1171,22 @@ static int msm_dp_display_get_io(struct msm_dp_disp= lay_private *display) return PTR_ERR(display->link_base); } =20 - display->p0_base =3D msm_dp_ioremap(pdev, 3, &display->p0_len); - if (IS_ERR(display->p0_base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); - return PTR_ERR(display->p0_base); + display->pixel_base[0] =3D msm_dp_ioremap(pdev, 3, &display->pixel_len); + if (IS_ERR(display->pixel_base[0])) + return PTR_ERR(display->pixel_base[0]); + + for (i =3D DP_STREAM_1; i < DP_STREAM_MAX; i++) { + display->pixel_base[i] =3D msm_dp_ioremap(pdev, i + 3, &display->pixel_l= en); + if (IS_ERR(display->pixel_base[i])) { + int ret =3D PTR_ERR(display->pixel_base[i]); + + if (ret =3D=3D -EINVAL) { + /* optional resource not present in DT */ + display->pixel_base[i] =3D NULL; + break; + } + return ret; + } } =20 return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 745ee6976897..7b5fc5bb16de 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,7 +25,7 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *p0_base; + void __iomem *pixel_base; bool panel_on; }; =20 @@ -44,24 +44,24 @@ static inline void msm_dp_write_link(struct msm_dp_pane= l_private *panel, writel(data, panel->link_base + offset); } =20 -static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, - u32 offset, u32 data) +static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, + u32 offset, u32 data) { /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() + * Use writel() instead of writel_relaxed() to ensure the interface + * register write reaches the hardware before subsequent operations. */ - writel(data, panel->p0_base + offset); + writel(data, panel->pixel_base + offset); } =20 -static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, - u32 offset) +static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, + u32 offset) { /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() + * Only reads a configuration register: no DMA or memory ordering is + * required, so readl_relaxed() is sufficient. */ - return readl_relaxed(panel->p0_base + offset); + return readl_relaxed(panel->pixel_base + offset); } =20 static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) @@ -367,34 +367,34 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_pan= el *msm_dp_panel, display_hctl =3D (hsync_end_x << 16) | hsync_start_x; =20 =20 - msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, + DP_TPG_CHECKERED_RECT_PATTERN); + msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, + DP_TPG_VIDEO_CONFIG_BPP_8BIT | + DP_TPG_VIDEO_CONFIG_RGB); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, + DP_BIST_ENABLE_DPBIST_EN); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, + DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } =20 @@ -403,9 +403,9 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_pane= l *msm_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); =20 - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } =20 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e) @@ -439,7 +439,7 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *ms= m_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); =20 - msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); } =20 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) @@ -629,7 +629,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blankin= g); msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); =20 - reg =3D msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); + reg =3D msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; else @@ -637,7 +637,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) =20 drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", wide_bus_en, r= eg); =20 - msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -701,7 +701,7 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *m= sm_dp_panel, struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base) + void __iomem *pixel_base) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; @@ -719,7 +719,7 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux panel->aux =3D aux; panel->link =3D link; panel->link_base =3D link_base; - panel->p0_base =3D p0_base; + panel->pixel_base =3D pixel_base; =20 msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 50a721401751..218a09a2fa65 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -102,5 +102,5 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base); 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Keeping the register definitions and translation helper together ensures that all supported mappings are defined in one place. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_panel.c | 65 +++++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ drivers/gpu/drm/msm/dp/dp_reg.h | 56 +++++++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 7b5fc5bb16de..504d7542d30a 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -29,6 +29,71 @@ struct msm_dp_panel_private { bool panel_on; }; =20 +u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg) +{ + bool is_s1 =3D (id =3D=3D DP_STREAM_1); + + if (id =3D=3D DP_STREAM_0) + return reg; + + switch (reg) { + case REG_DP_STATE_CTRL: + return is_s1 ? REG_DP_STATE_CTRL : REG_DP_MSTLINK_STATE_CTRL; + case REG_DP_CONFIGURATION_CTRL: + return is_s1 ? REG_DP1_CONFIGURATION_CTRL : REG_DP_MSTLINK_CONFIGURATION= _CTRL; + case REG_DP_SOFTWARE_MVID: + return is_s1 ? REG_DP1_SOFTWARE_MVID : REG_DP_MSTLINK_SOFTWARE_MVID; + case REG_DP_SOFTWARE_NVID: + return is_s1 ? REG_DP1_SOFTWARE_NVID : REG_DP_MSTLINK_SOFTWARE_NVID; + case REG_DP_TOTAL_HOR_VER: + return is_s1 ? REG_DP1_TOTAL_HOR_VER : REG_DP_MSTLINK_TOTAL_HOR_VER; + case REG_DP_START_HOR_VER_FROM_SYNC: + return is_s1 ? REG_DP1_START_HOR_VER_FROM_SYNC + : REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC; + case REG_DP_HSYNC_VSYNC_WIDTH_POLARITY: + return is_s1 ? REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY + : REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY; + case REG_DP_ACTIVE_HOR_VER: + return is_s1 ? REG_DP1_ACTIVE_HOR_VER : REG_DP_MSTLINK_ACTIVE_HOR_VER; + case REG_DP_MISC1_MISC0: + return is_s1 ? REG_DP1_MISC1_MISC0 : REG_DP_MSTLINK_MISC1_MISC0; + case REG_DP_DP0_TIMESLOT_1_32: + return is_s1 ? REG_DP_DP1_TIMESLOT_1_32 : REG_DP_MSTLINK_TIMESLOT_1_32; + case REG_DP_DP0_TIMESLOT_33_63: + return is_s1 ? REG_DP_DP1_TIMESLOT_33_63 : REG_DP_MSTLINK_TIMESLOT_33_63; + case REG_DP_DP0_RG: + return is_s1 ? REG_DP_DP1_RG : REG_DP_MSTLINK_DP_RG; + case MMSS_DP_SDP_CFG: + return is_s1 ? MMSS_DP1_SDP_CFG : MMSS_DP_MSTLINK_SDP_CFG; + case MMSS_DP_SDP_CFG2: + return is_s1 ? MMSS_DP1_SDP_CFG2 : MMSS_DP_MSTLINK_SDP_CFG2; + case MMSS_DP_SDP_CFG3: + return is_s1 ? MMSS_DP1_SDP_CFG3 : MMSS_DP_MSTLINK_SDP_CFG3; + case MMSS_DP_GENERIC0_0: + return is_s1 ? MMSS_DP1_GENERIC0_0 : MMSS_DP_MSTLINK_GENERIC0_0; + case MMSS_DP_GENERIC0_1: + return is_s1 ? MMSS_DP1_GENERIC0_1 : MMSS_DP_MSTLINK_GENERIC0_1; + case MMSS_DP_GENERIC0_2: + return is_s1 ? MMSS_DP1_GENERIC0_2 : MMSS_DP_MSTLINK_GENERIC0_2; + case MMSS_DP_GENERIC0_3: + return is_s1 ? MMSS_DP1_GENERIC0_3 : MMSS_DP_MSTLINK_GENERIC0_3; + case MMSS_DP_GENERIC0_4: + return is_s1 ? MMSS_DP1_GENERIC0_4 : MMSS_DP_MSTLINK_GENERIC0_4; + case MMSS_DP_GENERIC0_5: + return is_s1 ? MMSS_DP1_GENERIC0_5 : MMSS_DP_MSTLINK_GENERIC0_5; + case MMSS_DP_GENERIC0_6: + return is_s1 ? MMSS_DP1_GENERIC0_6 : MMSS_DP_MSTLINK_GENERIC0_6; + case MMSS_DP_GENERIC0_7: + return is_s1 ? MMSS_DP1_GENERIC0_7 : MMSS_DP_MSTLINK_GENERIC0_7; + case MMSS_DP_GENERIC0_8: + return is_s1 ? MMSS_DP1_GENERIC0_8 : MMSS_DP_MSTLINK_GENERIC0_8; + case MMSS_DP_GENERIC0_9: + return is_s1 ? MMSS_DP1_GENERIC0_9 : MMSS_DP_MSTLINK_GENERIC0_9; + default: + return reg; + } +} + static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32= offset) { return readl_relaxed(panel->link_base + offset); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 218a09a2fa65..75b23c106a99 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -99,6 +99,8 @@ static inline bool is_lane_count_valid(u32 lane_count) lane_count =3D=3D 4); } =20 +u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg); + struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index dda4b642c81b..265da58e064c 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -302,6 +302,35 @@ #define MMSS_DP_VSCEXT_8 (0x000002F0) #define MMSS_DP_VSCEXT_9 (0x000002F4) =20 +/* Stream 1 (DP1) registers, relative to link_base. */ +#define REG_DP1_CONFIGURATION_CTRL (0x00000400) +#define REG_DP_DP0_TIMESLOT_1_32 (0x00000404) +#define REG_DP_DP0_TIMESLOT_33_63 (0x00000408) +#define REG_DP_DP1_TIMESLOT_1_32 (0x0000040C) +#define REG_DP_DP1_TIMESLOT_33_63 (0x00000410) +#define REG_DP1_SOFTWARE_MVID (0x00000414) +#define REG_DP1_SOFTWARE_NVID (0x00000418) +#define REG_DP1_TOTAL_HOR_VER (0x0000041c) +#define REG_DP1_START_HOR_VER_FROM_SYNC (0x00000420) +#define REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY (0x00000424) +#define REG_DP1_ACTIVE_HOR_VER (0x00000428) +#define REG_DP1_MISC1_MISC0 (0x0000042c) +#define MMSS_DP1_GENERIC0_0 (0x00000490) +#define MMSS_DP1_GENERIC0_1 (0x00000494) +#define MMSS_DP1_GENERIC0_2 (0x00000498) +#define MMSS_DP1_GENERIC0_3 (0x0000049c) +#define MMSS_DP1_GENERIC0_4 (0x000004a0) +#define MMSS_DP1_GENERIC0_5 (0x000004a4) +#define MMSS_DP1_GENERIC0_6 (0x000004a8) +#define MMSS_DP1_GENERIC0_7 (0x000004ac) +#define MMSS_DP1_GENERIC0_8 (0x000004b0) +#define MMSS_DP1_GENERIC0_9 (0x000004b4) +#define MMSS_DP1_SDP_CFG (0x000004e0) +#define MMSS_DP1_SDP_CFG2 (0x000004e4) +#define MMSS_DP1_SDP_CFG3 (0x000004e8) +#define REG_DP_DP0_RG (0x000004f8) +#define REG_DP_DP1_RG (0x000004fc) + #define MMSS_DP_BIST_ENABLE (0x00000000) #define DP_BIST_ENABLE_DPBIST_EN (0x00000001) =20 @@ -334,6 +363,33 @@ #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) =20 +/* Streams 2/3 registers, relative to mst2link_base / mst3link_base. */ +#define REG_DP_MSTLINK_STATE_CTRL (0x00000000) +#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) +#define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) +#define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003c) +#define REG_DP_MSTLINK_SOFTWARE_MVID (0x00000040) +#define REG_DP_MSTLINK_SOFTWARE_NVID (0x00000044) +#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) +#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004c) +#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) +#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) +#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) +#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000bc) +#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000c0) +#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000c4) +#define MMSS_DP_MSTLINK_GENERIC0_3 (0x000000c8) +#define MMSS_DP_MSTLINK_GENERIC0_4 (0x000000cc) +#define MMSS_DP_MSTLINK_GENERIC0_5 (0x000000d0) +#define MMSS_DP_MSTLINK_GENERIC0_6 (0x000000d4) +#define MMSS_DP_MSTLINK_GENERIC0_7 (0x000000d8) +#define MMSS_DP_MSTLINK_GENERIC0_8 (0x000000dc) +#define MMSS_DP_MSTLINK_GENERIC0_9 (0x000000e0) +#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) +#define MMSS_DP_MSTLINK_SDP_CFG2 (0x00000110) +#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) +#define REG_DP_MSTLINK_DP_RG (0x0000011C) + #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) =20 #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 314EC3D0BE4 for ; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:18:09 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:24 +0800 Subject: [PATCH v6 07/29] drm/msm/dp: add stream-aware link register accessors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-7-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=12701; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=9VpXdKX5WvjhOg7NrJO4/hZ1EJd5dXWP7ykt8AQMJ1Y=; b=PLWMmy9dTlNadABriOB9vpmhWbBOosKISG6w8NQBTQp9L9WUzQZUgeGHGJgn2zeSkOPoHnkiV ThE3ESo0DhsD3FzB4F5YtOJ54LacepQWBlQx1hdP8fCtluLDjL1mpnd X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX50tzX8AfYQb9 jy/PVTT43MHb312cFWegfKhfXkqT0wJcocMFvGOOJWdYRU4v739d3IylyKOH6Rv7phlfiSEZBAs W47QPi0jGkcWUz6/EJVVIYkZkuk2soU= X-Authority-Analysis: v=2.4 cv=O7sJeh9W c=1 sm=1 tr=0 ts=6a9538c3 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=qYFs1fq_Vji6wCC2nv8A:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: eRi4eekabxCEpWXYJjcg891UCjuiLywv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX80sf3xsLH4ch yiR59euAHOppHl0hORZUxcIxyAMaMWXcQ081kwHJLboh4ZThbLS9H22UC29KUPUDjVGLHsxKF3f JPRfcYEkQNkN6+LD+uvKf1FaBwZ7ZYep7QUzYOzkpx5W2KWTdECHyZooTPqYwESoC4aH9Jj1UXN NGgaxAy/LKQ/ADZS2tWR4o1Pab6Q6aRbAJIP2QMMeHk/wZVkfrHdeZW7lbZhGwjYvRi2Jdiixg7 SYWwJIXen3EJ3gkn9zxBx8450M0UQAyU0l5EJJHkECQ+lOIi9vQUmM3AcPkMTSfl5cwjqP+xqdt Gv1bo1LQRH+EuthybNY0wN9uPZJW+iM9LSVTzZp93XO1vnYwvCIlGz476T8SQurm4h9PFrCv/HM yNbtGquMh1+pBp00QEznOgqDxdEq8y4RLqJR5pxktplRSuR6VNA84NvtKFs77F4ZJENl87RN4Rq ItdvwgowacIdsWSEuTg== X-Proofpoint-GUID: eRi4eekabxCEpWXYJjcg891UCjuiLywv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 suspectscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 DisplayPort MST uses multiple stream-specific register spaces. Streams 0 and 1 share the primary link register block with different register offsets, while streams 2 and 3 use dedicated MST link register blocks. Add stream-aware register access helpers that translate stream-specific register offsets and route accesses to the appropriate register space based on the stream id. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 64 +++++++++++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 ++- drivers/gpu/drm/msm/dp/dp_display.c | 38 ++++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_panel.c | 37 +++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 5 files changed, 133 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index c0f5226dc383..e1614bc49a7c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -117,6 +117,8 @@ struct msm_dp_ctrl_private { struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; =20 struct phy *phy; =20 @@ -172,6 +174,49 @@ static inline void msm_dp_write_link(struct msm_dp_ctr= l_private *ctrl, writel(data, ctrl->link_base + offset); } =20 +static inline u32 msm_dp_read_stream_link(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset) +{ + offset =3D msm_dp_stream_reg(stream_id, offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(ctrl->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(ctrl->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(ctrl->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } +} + +static inline void msm_dp_write_stream_link(struct msm_dp_ctrl_private *ct= rl, + enum msm_dp_stream_id stream_id, u32 offset, u32 data) +{ + /* + * To make sure link reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + offset =3D msm_dp_stream_reg(stream_id, offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, ctrl->link_base + offset); + break; + case DP_STREAM_2: + writel(data, ctrl->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, ctrl->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } +} + static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, struct msm_dp_link_info *link) { @@ -397,7 +442,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_= dp_ctrl_private *ctrl, * RMW: called from atomic_enable(), serialized by the DRM atomic framewo= rk. * Clear stream-specific fields before OR-ing to avoid bit accumulation. */ - config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + config =3D msm_dp_read_stream_link(ctrl, msm_dp_panel->stream_id, + REG_DP_CONFIGURATION_CTRL); config &=3D ~(DP_CONFIGURATION_CTRL_RGB_YUV_MASK | DP_CONFIGURATION_CTRL_BPC_MASK | DP_CONFIGURATION_CTRL_SEND_VSC); @@ -415,7 +461,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_= dp_ctrl_private *ctrl, =20 drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); =20 - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_CONFIGURAT= ION_CTRL, config); } =20 static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl, @@ -472,7 +518,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_d= p_ctrl_private *ctrl, msm_dp_panel->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); =20 - misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); + misc_val =3D msm_dp_read_stream_link(ctrl, msm_dp_panel->stream_id, REG_D= P_MISC1_MISC0); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -482,7 +528,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_d= p_ctrl_private *ctrl, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_MISC1_MISC= 0, misc_val); } =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, @@ -2528,8 +2574,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl= _private *ctrl, nvid *=3D 3; =20 drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_MVID, mv= id); + msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_NVID, nv= id); } =20 int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, @@ -2784,7 +2830,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, - void __iomem *link_base) + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base) { struct msm_dp_ctrl_private *ctrl; int ret; @@ -2823,6 +2871,8 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->phy =3D phy; ctrl->ahb_base =3D ahb_base; ctrl->link_base =3D link_base; + ctrl->mst2link_base =3D mst2link_base; + ctrl->mst3link_base =3D mst3link_base; =20 ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index bf593f4a4480..80d9258501b4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -35,7 +35,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, - void __iomem *link_base); + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base); =20 void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 3dce9334d0c2..d0fc4ff508dc 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -85,6 +85,12 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; =20 + void __iomem *mst2link_base; + size_t mst2link_len; + + void __iomem *mst3link_base; + size_t mst3link_len; + void __iomem *pixel_base[DP_STREAM_MAX]; size_t pixel_len; }; @@ -562,7 +568,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >pixel_base[0]); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, + dp->mst2link_base, dp->mst3link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); @@ -571,7 +578,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) } =20 dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->aux, - phy, dp->ahb_base, dp->link_base); + phy, dp->ahb_base, dp->link_base, + dp->mst2link_base, dp->mst3link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); @@ -843,6 +851,12 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state= , struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); + if (msm_dp_display->mst2link_base) + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len, + msm_dp_display->mst2link_base, "dp_mst2link"); + if (msm_dp_display->mst3link_base) + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len, + msm_dp_display->mst3link_base, "dp_mst3link"); =20 for (int i =3D 0; i < DP_STREAM_MAX; i++) { if (!msm_dp_ctrl_stream_clks_on(msm_dp_display->ctrl, i)) @@ -1189,6 +1203,26 @@ static int msm_dp_display_get_io(struct msm_dp_displ= ay_private *display) } } =20 + display->mst2link_base =3D msm_dp_ioremap(pdev, 7, &display->mst2link_len= ); + if (IS_ERR(display->mst2link_base)) { + int ret =3D PTR_ERR(display->mst2link_base); + + if (ret !=3D -EINVAL) + return ret; + /* optional resource not present in DT */ + display->mst2link_base =3D NULL; + } + + display->mst3link_base =3D msm_dp_ioremap(pdev, 8, &display->mst3link_len= ); + if (IS_ERR(display->mst3link_base)) { + int ret =3D PTR_ERR(display->mst3link_base); + + if (ret !=3D -EINVAL) + return ret; + /* optional resource not present in DT */ + display->mst3link_base =3D NULL; + } + return 0; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 504d7542d30a..d3468b73fdc3 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,6 +25,8 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; void __iomem *pixel_base; bool panel_on; }; @@ -96,7 +98,19 @@ u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg) =20 static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32= offset) { - return readl_relaxed(panel->link_base + offset); + offset =3D msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(panel->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(panel->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(panel->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } =20 static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, @@ -106,7 +120,22 @@ static inline void msm_dp_write_link(struct msm_dp_pan= el_private *panel, * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->link_base + offset); + offset =3D msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, panel->link_base + offset); + break; + case DP_STREAM_2: + writel(data, panel->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, panel->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } =20 static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, @@ -766,6 +795,8 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *m= sm_dp_panel, struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base) { struct msm_dp_panel_private *panel; @@ -785,6 +816,8 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux panel->link =3D link; panel->link_base =3D link_base; panel->pixel_base =3D pixel_base; + panel->mst2link_base =3D mst2link_base; + panel->mst3link_base =3D mst3link_base; =20 msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 75b23c106a99..dc046fec24fc 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -104,5 +104,7 @@ u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg= ); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:18:15 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:25 +0800 Subject: [PATCH v6 08/29] drm/msm/dp: add support to send ACT packets for MST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-8-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=6775; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=U2HJX94D2BMOjeBdupbd3D8LR09HYGpVTExDGNEh2ho=; b=pbf2MwbOo3Vwp5OzIsEgs/kPMFt+AgoN8+PQ7up6iAA7/eZdBLAI/773tfEXX4Ymp7AKORHyA 2sjX0sOrwsuCZ7num2gN2SmaqmJhkLU/+HAGFrDZ0u0k7jo9YCyej7u X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: ZYy_Qyrc7tlUj5clgio96KuUFL7L0_hJ X-Proofpoint-GUID: ZYy_Qyrc7tlUj5clgio96KuUFL7L0_hJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX7F3KyLCioe5K OdGkHc6mhBhH/tcoTIbUSEhTQQv0FxnNXAec4rwZOzTr1igFDXKwvCHgNEU2KR2HOUCTg+y+2iN HZn2FbBGGBhIzlYXPkXL936adcCjAZATX/NbA+ekCKY5fTfY8qVVhPMM8MW4uIeKHkBORB4sMlJ /E4uCjx1M2meZGcUBCdZkeu63n9P4TGgm9+FVkjv9imC12fNi/6PnkFr9ISR/hPrZJhQaeASHHZ a2n4uMNewW+MLef4Kl4ncoc1MpsXfj2mCeKJv1exhWvjy/emwf1eleFW439bVx+2et8ZtKSHkgX HBDbUQhFHnyfHzI1MqC6ZFk2MAF2kv4Ys+rY0XEjvPr7Msd7MjG4kQ/ZsJYV90SO++OZf0D6YFo G+4Sw7/+voj5Ztq4iAnTqiA9U/iNoH/7IuZih6y6ACEYQ1e+IMotZgOfmTBPhHnHq/3YdbE+nK6 e7+eyoICL3jEZfWUjHg== X-Authority-Analysis: v=2.4 cv=S8/pBosP c=1 sm=1 tr=0 ts=6a9538c9 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=F2S7ry5v5sxRTjZyeP4A:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX7QNGoGyaCnsE PZlLrV7vKx9teimXSI/1GkM+0qMXK9+eo/oUGQXk07bquHmiK9rAlGM0vdcsETxilo7pCTPSndn SiBbpwGMc/x4pWpuTOmiMaPohWnVjgM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar Whenever virtual channel slot allocation changes, the DP source must send the action control trigger sequence to notify the sink about the same. This would be applicable during the start and stop of the pixel stream. Add the infrastructure to be able to send ACT packets for the DP controller when operating in MST mode. Add REG_DP_MST_ACT, the ACT trigger register used by this sequence. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 44 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_ctrl.h | 5 ++++- drivers/gpu/drm/msm/dp/dp_display.c | 3 ++- drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 1 + 5 files changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index e1614bc49a7c..65d22505c2b6 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -142,6 +142,7 @@ struct msm_dp_ctrl_private { bool core_clks_on; bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; + bool mst_active; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -244,6 +245,37 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux= *aux, return err; } =20 +int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) +{ + struct msm_dp_ctrl_private *ctrl; + const struct drm_display_mode *mode; + u32 frame_time_ms; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (!ctrl->mst_active) + return 0; + + mode =3D &panel->msm_dp_mode.drm_mode; + frame_time_ms =3D DIV_ROUND_UP((u64)mode->htotal * mode->vtotal, + mode->clock) + 1; + + msm_dp_write_link(ctrl, REG_DP_MST_ACT, 0x1); + /* make sure ACT signal is performed */ + wmb(); + + msleep(frame_time_ms); + + /* Hardware clears this bit after sending 4 ACT headers */ + if (msm_dp_read_link(ctrl, REG_DP_MST_ACT)) { + drm_dbg_dp(ctrl->drm_dev, "MST ACT trigger complete failed\n"); + return -EINVAL; + } + + return 0; +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2614,7 +2646,8 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, return ret; } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel) +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel, + bool mst_active) { int ret =3D 0; bool mainlink_ready =3D false; @@ -2626,6 +2659,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 + ctrl->mst_active =3D mst_active; + pixel_rate =3D panel->msm_dp_mode.drm_mode.clock; =20 if (msm_dp_ctrl->wide_bus_en || panel->msm_dp_mode.out_fmt_is_yuv_420) @@ -2657,6 +2692,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, struct msm_dp_panel * =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 + ret =3D msm_dp_ctrl_mst_send_act(msm_dp_ctrl, panel); + if (ret) + return ret; + ret =3D msm_dp_ctrl_wait4video_ready(ctrl); if (ret) return ret; @@ -2694,6 +2733,8 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl, =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 + ctrl->mst_active =3D false; + msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 phy_power_off(phy); @@ -2873,6 +2914,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->link_base =3D link_base; ctrl->mst2link_base =3D mst2link_base; ctrl->mst3link_base =3D mst3link_base; + ctrl->mst_active =3D false; =20 ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 80d9258501b4..41a69447001c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -18,7 +18,8 @@ struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel, + bool mst_active); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel, bool force_link_train); @@ -59,4 +60,6 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_c= trl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *dp_ctrl, enum msm_dp_stream_id stream_id); +int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index d0fc4ff508dc..52c13823e8d7 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -672,7 +672,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp, return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel, msm_dp_display->mst_= active); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -1497,6 +1497,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *dp) msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 msm_dp_ctrl_push_idle(msm_dp_display->ctrl); + msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl, msm_dp_display->panel); } =20 static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 83117e7619f3..472429d09200 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -19,6 +19,7 @@ struct msm_dp { struct drm_bridge *bridge; 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 16 ++++++++++++++++ drivers/gpu/drm/msm/dp/dp_reg.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 65d22505c2b6..cd6ae0d5372c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -276,6 +276,19 @@ int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_d= p_ctrl, return 0; } =20 +static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool = enable) +{ + u32 mainlink_ctrl; + + mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + if (enable) + mainlink_ctrl |=3D DP_MAINLINK_CTRL_MST_EN; + else + mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_MST_EN; + + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2680,6 +2693,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); + if (ctrl->mst_active) + msm_dp_ctrl_mst_config(ctrl, true); =20 msm_dp_ctrl_configure_source_params(ctrl, panel); =20 @@ -2730,6 +2745,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl, phy =3D ctrl->phy; =20 msm_dp_ctrl_mainlink_disable(ctrl); + msm_dp_ctrl_mst_config(ctrl, false); =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 9263e61c794c..cc74b1ed628e 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -128,6 +128,10 @@ #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUS= H_MODE_MASK, 1) #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CT= RL_FLUSH_MODE_MASK, 3) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) +#define DP_MAINLINK_CTRL_ECF_MODE BIT(26) +#define DP_MAINLINK_CTRL_MST_ACTIVE BIT(8) +#define DP_MAINLINK_CTRL_MST_EN (DP_MAINLINK_CTRL_ECF_MODE | \ + DP_MAINLINK_CTRL_MST_ACTIVE) =20 #define REG_DP_STATE_CTRL (0x00000004) #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C6893D9543 for ; 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Skip the TU programming for MST cases. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index cd6ae0d5372c..77506e840883 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2703,7 +2703,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_panel_clear_dsc_dto(panel); =20 - msm_dp_ctrl_setup_tr_unit(ctrl, panel); + if (!ctrl->mst_active) + msm_dp_ctrl_setup_tr_unit(ctrl, panel); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B957D3D332A for ; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:18:31 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:28 +0800 Subject: [PATCH v6 11/29] drm/msm/dp: always program MST_FIFO_CONSTANT_FILL for MST use cases Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-11-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=2539; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=mtZ1HCvBc/lbpNSY8CTLdvHlrW0O7SuiIwZF96PT1pI=; b=STO9GwinFhcQSFq0MNtOu3KI0vWHHsIUt8A6GJA77uEm9psDlpyVubXkRIn8eJJRV4AXy9qsO N1ponTqrGlKCr5PxDrTcgo4WEZlcrnwjV0nY/Jl41/oCdspYwXbBZWF X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX6cmMQMeL5hQx 0W27qDPPlIqpdlsS1wRil023+/VBc+B31EcQvTlJRuuheidkkv5q2mxtD5TzUXvXYzRT6L2yHtC 2QK2DyRTHdXMlDHwLCR11xOBLXSAWGA= X-Authority-Analysis: v=2.4 cv=O7sJeh9W c=1 sm=1 tr=0 ts=6a9538d9 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=_o_Q1azn2oY438DeJ5EA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: NaUhCDdY3W-WKB65_r-pH67yZBDAw8M4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfXzgwDuxARgges KqWl6vPzNnbT5ZMYkMfXO8salfWDomK3z4ZAxi6yIshgV7jwtF/m/jjyri13SdhYd48LejxHRMR KP6kjmTjRUqN6IFAsevCHpmzpeZy6D6h3Lau78aOd24Hfbun4h2Il4A/eAQA5ar9jUOYv+b8Lyq KVPDyBDZ7niQCod7xWnCy8jzx64TRoKn9Vgk37QF2CphNyiIiS+9wBczLclwNXDhH/70XSwB9xs SGTHC1h4av71BDcRrGF8WVGDGNIkrkQrgvKHZVWOi8dWso8k+e2+vnK7C0prjS7cdIJlne9VM7u 5S+myRD3QyEw4yp8pzIl7qjPOSoZdbjyCnS/AA1yvmOFj0zfMqn+JKXF7e49VmNadxhI8BNiTlV e2wvZG8d1JkoeF8iqngsxMtYJ3gyvDw6ePk20ARgg5CQQ7dl/yajgbHtV6NEK3/+HlhbneyFcA2 7ttjlRiABYqKbHnl2SQ== X-Proofpoint-GUID: NaUhCDdY3W-WKB65_r-pH67yZBDAw8M4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 suspectscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar As per the hardware programming guide, MST_FIFO_CONSTANT_FILL must always be programmed when operating in MST mode. Ensure the register is configured accordingly. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 12 ++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 77506e840883..9a0c9737e6d0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -584,6 +584,8 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl msm_dp_ctrl_config_misc1_misc0(ctrl, panel); =20 msm_dp_panel_timing_cfg(panel, ctrl->msm_dp_ctrl.wide_bus_en); + + msm_dp_panel_mst_async_fifo(panel, ctrl->mst_active); } =20 /* diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index d3468b73fdc3..bc7bad5ca3b1 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -741,6 +741,18 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_d= p_panel, bool wide_bus_en) return 0; } =20 +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool m= st_en) +{ + struct msm_dp_panel_private *panel; + + panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); + + if (mst_en) + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); + else + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); +} + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, const struct drm_display_mode *adjusted_mode, u32 bpp) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index dc046fec24fc..04938b9d2091 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -72,6 +72,8 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_= dp_panel); void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct= dp_sdp *vsc_sdp); void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); =20 +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool m= st_en); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:18:38 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:29 +0800 Subject: [PATCH v6 12/29] drm/msm/dp: add support for sending VCPF packets in DP controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-12-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=7068; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=TniWeqxzjHoUl2Z3h7/YCZNFywxvXf4ceE4t73tCJCc=; b=qvDy7lMpOnpszVhD3L+WiNxUE3NqJDnIcENXmR2Ui59izzpeCUZou3gN9+M0+leMVtmjV69r2 7F2DyzHWk3zAVe2BQC90AvBHx55M3RgEHqYSEtOYm1KbhQ3zFp9m8iv X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: CxP2TVbN-UrLtMA4tI3DIMxw8dw0oIB_ X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX1PFo9gePVP3y tMezOAUV4idDpaYv/XmmcIynmxy0R526cOkjoXTYZvNVyn7leiYuKSs8Wif7YWfWTcuPJpH8UnZ cHs13KqY3wQJCiwAYrPOoGL+Eqgbi9M= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX+ALKs/0r7vfD xLpiC5aFUB58vN1aY4L/TFkcK2ni5Dq89IjzyfwwhAegxZ32G6m8vsLN0egHHhdT7qkhBd6Ex0P D/LL/+GmS04weZhVwM75zkIrmVuSJZDR25xGgaqydQzyY1wJWwfx2WvMgJ4OY5z1acGj9HUMPwu oPkFO68DCiuYunIS1/uScGoxL/NXP528ErNhmS+XTJlS3K153xvwKFeit8gZJP7WrYJsrXx3WeB XXVMX8nJ8ZE93z4YrYwiYtpw+gMI0PmLZkaI88GKHuHU3oAUsaY1N0kFuB9r4l1RUi4gP0L8txa tWHpxOHxn13QsFL/bLu2f4Gs1q7noAhOKafbwHftO5cSpgkVCMiVJBbTvsBYf5hZa25j996rD82 4PA2agbCo1lBUYDSor0b/KhuJgosfTJQNf6iyVnppPXP+195ruLO4T5J4UUgcZctzzR1KN5KoKo HxxdgReX6wWJaanKp9g== X-Authority-Analysis: v=2.4 cv=ZOPnX37b c=1 sm=1 tr=0 ts=6a9538e1 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=a1Xw59hMvoynOX_QUlAA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: CxP2TVbN-UrLtMA4tI3DIMxw8dw0oIB_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar The VC Payload Fill (VCPF) sequence is inserted by the DP controller when stream symbols are absent, typically before a stream is disabled. Add support for triggering the VCPF sequence in the MSM DP controller. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 57 +++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 1 + drivers/gpu/drm/msm/dp/dp_display.c | 2 +- drivers/gpu/drm/msm/dp/dp_reg.h | 8 ++++++ 4 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 9a0c9737e6d0..109a84167599 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -65,6 +65,11 @@ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) =20 +#define DP_INTERRUPT_STATUS5 \ + (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT) +#define DP_INTERRUPT_STATUS5_MASK \ + (DP_INTERRUPT_STATUS5 << DP_INTERRUPT_STATUS_MASK_SHIFT) + #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) =20 @@ -351,6 +356,8 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_= ctrl) DP_INTERRUPT_STATUS1_MASK); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + DP_INTERRUPT_STATUS5_MASK); } =20 void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) @@ -360,6 +367,7 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp= _ctrl) =20 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, 0x00); } =20 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) @@ -379,6 +387,20 @@ static void msm_dp_ctrl_config_psr_interrupt(struct ms= m_dp_ctrl_private *ctrl) msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); } =20 +static u32 msm_dp_ctrl_get_mst_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS5); + intr &=3D ~DP_INTERRUPT_STATUS5_MASK; + intr_ack =3D (intr & DP_INTERRUPT_STATUS5) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + intr_ack | DP_INTERRUPT_STATUS5_MASK); + + return intr; +} + static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) { u32 val; @@ -478,6 +500,34 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_= ctrl) drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); } =20 +/* Must be called with msm_dp_mst::mst_lock held */ +void msm_dp_ctrl_push_vcpf(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_= panel *msm_dp_panel) +{ + struct msm_dp_ctrl_private *ctrl; + u32 state =3D 0x0; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (!ctrl->mst_active) + state |=3D DP_STATE_CTRL_PUSH_IDLE; + else if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) + state |=3D DP_STATE_CTRL_DP0_PUSH_VCPF; + else if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + state |=3D DP_STATE_CTRL_DP1_PUSH_VCPF; + else + state |=3D DP_MSTLINK_PUSH_VCPF; + + reinit_completion(&ctrl->idle_comp); + + msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_STATE_CTRL= , state); + + if (!wait_for_completion_timeout(&ctrl->idle_comp, + IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) + pr_warn("PUSH_VCPF pattern timedout\n"); + + drm_dbg_dp(ctrl->drm_dev, "vcpf sent\n"); +} + static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ct= rl, struct msm_dp_panel *msm_dp_panel) { @@ -2801,6 +2851,13 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_= dp_ctrl, ret =3D IRQ_HANDLED; } =20 + isr =3D msm_dp_ctrl_get_mst_interrupt(ctrl); + if (isr & (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT)) { + drm_dbg_dp(ctrl->drm_dev, "vcpf sent\n"); + complete(&ctrl->idle_comp); + ret =3D IRQ_HANDLED; + } + /* DP aux isr */ isr =3D msm_dp_ctrl_get_aux_interrupt(ctrl); if (isr) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 41a69447001c..84ea37d8db2e 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -27,6 +27,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_push_vcpf(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_= panel *panel); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl, diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 52c13823e8d7..00c9b55925f9 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1496,7 +1496,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *dp) =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_ctrl_push_idle(msm_dp_display->ctrl); + msm_dp_ctrl_push_vcpf(msm_dp_display->ctrl, msm_dp_display->panel); msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl, msm_dp_display->panel); } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index cc74b1ed628e..e37a05c2963a 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -42,6 +42,9 @@ #define DP_INTR_FRAME_END BIT(6) #define DP_INTR_CRC_UPDATED BIT(9) =20 +#define DP_INTR_DP0_VCPF_SENT BIT(0) +#define DP_INTR_DP1_VCPF_SENT BIT(3) + #define REG_DP_INTR_STATUS3 (0x00000028) =20 #define REG_DP_INTR_STATUS4 (0x0000002C) @@ -58,6 +61,8 @@ #define PSR_UPDATE_ERROR_MASK (0x00000008) #define PSR_WAKE_ERROR_MASK (0x00000010) =20 +#define REG_DP_INTR_STATUS5 (0x00000034) + #define REG_DP_DP_HPD_CTRL (0x00000000) #define DP_DP_HPD_CTRL_HPD_EN (0x00000001) =20 @@ -143,6 +148,8 @@ #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (0x00000040) #define DP_STATE_CTRL_SEND_VIDEO (0x00000080) #define DP_STATE_CTRL_PUSH_IDLE (0x00000100) +#define DP_STATE_CTRL_DP0_PUSH_VCPF BIT(12) +#define DP_STATE_CTRL_DP1_PUSH_VCPF BIT(14) =20 #define REG_DP_CONFIGURATION_CTRL (0x00000008) #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) @@ -370,6 +377,7 @@ =20 /* Streams 2/3 registers, relative to mst2link_base / mst3link_base. */ #define REG_DP_MSTLINK_STATE_CTRL (0x00000000) +#define DP_MSTLINK_PUSH_VCPF BIT(12) #define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) #define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) #define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003c) --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C2323DAABE for ; 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Add support for calculating the rate governor, slot allocation, and slot reservation in the DP controller. Each MST stream can reserve its slots by calling msm_dp_display_set_stream_info() from its bridge callbacks. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 187 ++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 + drivers/gpu/drm/msm/dp/dp_display.c | 13 +++ drivers/gpu/drm/msm/dp/dp_display.h | 2 + 4 files changed, 206 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 109a84167599..73aabd219125 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -78,6 +78,7 @@ #define MR_LINK_PRBS7 0x100 #define MR_LINK_CUSTOM80 0x200 #define MR_LINK_TRAINING4 0x40 +#define DP_MAX_TIME_SLOTS 64 =20 enum { DP_TRAINING_NONE, @@ -114,6 +115,12 @@ struct msm_dp_vc_tu_mapping_table { u8 tu_size_minus1; }; =20 +struct msm_dp_mst_ch_slot_info { + u32 start_slot; + u32 tot_slots; + u32 pbn; +}; + struct msm_dp_ctrl_private { struct msm_dp_ctrl msm_dp_ctrl; struct drm_device *drm_dev; @@ -148,6 +155,8 @@ struct msm_dp_ctrl_private { bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; bool mst_active; + + struct msm_dp_mst_ch_slot_info mst_ch_info[DP_STREAM_MAX]; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -294,6 +303,37 @@ static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_= private *ctrl, bool enable msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 +static void msm_dp_ctrl_mst_update_timeslot(struct msm_dp_ctrl_private *ct= rl, + enum msm_dp_stream_id stream_id, u32 ch_start_slot, + u32 tot_slot_cnt) +{ + u32 slot_reg_1 =3D 0, slot_reg_2 =3D 0; + + drm_dbg_dp(ctrl->drm_dev, "stream_id %d, start_slot %d, tot_slot %d\n", + stream_id, ch_start_slot, tot_slot_cnt); + + if (ch_start_slot && tot_slot_cnt) { + u64 mask =3D GENMASK_ULL(ch_start_slot + tot_slot_cnt - 2, ch_start_slot= - 1); + + slot_reg_1 =3D mask & 0xFFFFFFFF; + slot_reg_2 =3D (mask >> 32) & 0xFFFFFFFF; + } + + msm_dp_write_stream_link(ctrl, stream_id, REG_DP_DP0_TIMESLOT_1_32, slot_= reg_1); + msm_dp_write_stream_link(ctrl, stream_id, REG_DP_DP0_TIMESLOT_33_63, slot= _reg_2); +} + +static void msm_dp_ctrl_update_rg(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 x_int, u32 y_frac_enum) +{ + u32 rg =3D y_frac_enum | (x_int << 16); + + drm_dbg_dp(ctrl->drm_dev, "stream_id: %d x_int:%d y_frac_enum:%d rg:%d\n", + stream_id, x_int, y_frac_enum, rg); + + msm_dp_write_stream_link(ctrl, stream_id, REG_DP_DP0_RG, rg); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2675,6 +2715,117 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ct= rl_private *ctrl, msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_NVID, nv= id); } =20 +/* + * Calculate MST Rate Governor parameters x_int and y_frac_enum. + * + * The RG paces symbol delivery per MTP via: M =3D x_int + y_frac_enum/256 + * where M is the target symbol count per MTP across all lanes. + * + * min_slot_cnt =3D (pclk * bpp/8) / (lclk * lanes) * 64 -- slots at 1.0= x BW + * max_slot_cnt =3D pbn * 54 / (lclk * lanes) -- slots at PB= N limit + * raw_target_sc =3D (min + max) / 2 -- midpoint (~= 1.003x) + * + * Quantize raw_target_sc to 1/(256*lanes) steps, then: + * M =3D Chosen_TARGET_Slot_Count * lanes + * x_int =3D INT(M) + * y_frac_enum =3D CEIL(256 * MOD(M, 1)) + */ +static void msm_dp_ctrl_mst_calculate_rg(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, + u32 *p_x_int, u32 *p_y_frac_enum) +{ + u64 min_slot_cnt, max_slot_cnt; + u64 raw_target_sc, target_sc_fixp; + u64 ts_denom, ts_enum, ts_int; + u64 pclk =3D panel->msm_dp_mode.drm_mode.clock; + u64 lclk =3D 0; + u64 lanes =3D ctrl->link->link_params.num_lanes; + u64 bpp =3D panel->msm_dp_mode.bpp; + u64 pbn =3D ctrl->mst_ch_info[panel->stream_id].pbn; + u64 numerator, denominator, temp, temp1, temp2; + u32 x_int =3D 0, y_frac_enum =3D 0; + u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp; + + lclk =3D ctrl->link->link_params.rate; + + /* min_slot_cnt */ + numerator =3D pclk * bpp * 64 * 1000; + denominator =3D lclk * lanes * 8 * 1000; + min_slot_cnt =3D drm_fixp_from_fraction(numerator, denominator); + + /* max_slot_cnt */ + numerator =3D pbn * 54 * 1000; + denominator =3D lclk * lanes; + max_slot_cnt =3D drm_fixp_from_fraction(numerator, denominator); + + /* raw_target_sc */ + numerator =3D max_slot_cnt + min_slot_cnt; + denominator =3D drm_fixp_from_fraction(2, 1); + raw_target_sc =3D drm_fixp_div(numerator, denominator); + + /* target_sc */ + temp =3D drm_fixp_from_fraction(256 * lanes, 1); + numerator =3D drm_fixp_mul(raw_target_sc, temp); + denominator =3D drm_fixp_from_fraction(256 * lanes, 1); + target_sc_fixp =3D drm_fixp_div(numerator, denominator); + + ts_enum =3D 256 * lanes; + ts_denom =3D drm_fixp_from_fraction(256 * lanes, 1); + ts_int =3D drm_fixp2int(target_sc_fixp); + + temp =3D drm_fixp2int_ceil(raw_target_sc); + if (temp !=3D ts_int) { + temp =3D drm_fixp_from_fraction(ts_int, 1); + temp1 =3D raw_target_sc - temp; + temp2 =3D drm_fixp_mul(temp1, ts_denom); + ts_enum =3D drm_fixp2int(temp2); + } + + /* target_strm_sym */ + ts_int_fixp =3D drm_fixp_from_fraction(ts_int, 1); + ts_frac_fixp =3D drm_fixp_from_fraction(ts_enum, drm_fixp2int(ts_denom)); + temp =3D ts_int_fixp + ts_frac_fixp; + temp1 =3D drm_fixp_from_fraction(lanes, 1); + target_strm_sym =3D drm_fixp_mul(temp, temp1); + + /* x_int */ + x_int =3D drm_fixp2int(target_strm_sym); + + /* y_enum_frac */ + temp =3D drm_fixp_from_fraction(x_int, 1); + temp1 =3D target_strm_sym - temp; + temp2 =3D drm_fixp_from_fraction(256, 1); + y_frac_enum_fixp =3D drm_fixp_mul(temp1, temp2); + + temp1 =3D drm_fixp2int(y_frac_enum_fixp); + temp2 =3D drm_fixp2int_ceil(y_frac_enum_fixp); + + y_frac_enum =3D (u32)((temp1 =3D=3D temp2) ? temp1 : temp1 + 1); + + *p_x_int =3D x_int; + *p_y_frac_enum =3D y_frac_enum; + + drm_dbg_dp(ctrl->drm_dev, "MST lane_cnt:%llu, rate:%llu x_int:%d, y_frac:= %d\n", + lanes, lclk, x_int, y_frac_enum); +} + +static void msm_dp_ctrl_mst_stream_setup(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) +{ + u32 x_int, y_frac_enum; + + if (!ctrl->mst_active) + return; + + drm_dbg_dp(ctrl->drm_dev, "MST stream channel allocation\n"); + + msm_dp_ctrl_mst_timeslot_setup(&ctrl->msm_dp_ctrl); + + msm_dp_ctrl_mst_calculate_rg(ctrl, panel, &x_int, &y_frac_enum); + + msm_dp_ctrl_update_rg(ctrl, panel->stream_id, x_int, y_frac_enum); +} + int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel, bool force_link_train) @@ -2758,6 +2909,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * if (!ctrl->mst_active) msm_dp_ctrl_setup_tr_unit(ctrl, panel); =20 + msm_dp_ctrl_mst_stream_setup(ctrl, panel); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 ret =3D msm_dp_ctrl_mst_send_act(msm_dp_ctrl, panel); @@ -2809,6 +2962,40 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp= _ctrl, phy_power_off(phy); } =20 +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots, u32 pbn) +{ + struct msm_dp_ctrl_private *ctrl; + + if (!msm_dp_ctrl || stream_id >=3D DP_STREAM_MAX) { + DRM_ERROR("invalid input\n"); + return; + } + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + ctrl->mst_ch_info[stream_id].start_slot =3D start_slot; + ctrl->mst_ch_info[stream_id].tot_slots =3D tot_slots; + ctrl->mst_ch_info[stream_id].pbn =3D pbn; +} + +void msm_dp_ctrl_mst_timeslot_setup(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + int i; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (!ctrl->mst_active) + return; + + for (i =3D DP_STREAM_0; i < ctrl->num_pixel_clks; i++) { + msm_dp_ctrl_mst_update_timeslot(ctrl, i, ctrl->mst_ch_info[i].start_slot, + ctrl->mst_ch_info[i].tot_slots); + } +} + irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 84ea37d8db2e..e8b445c552f7 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -63,4 +63,8 @@ bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *dp_ct= rl, enum msm_dp_stream_id stream_id); int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); +void msm_dp_ctrl_mst_timeslot_setup(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots, u32 pbn); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 00c9b55925f9..6f79328c8b79 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -734,6 +734,18 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp, return 0; } =20 +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct m= sm_dp_panel *panel, + u32 start_slot, u32 num_slots, u32 pbn) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_ctrl_set_mst_channel_info(dp->ctrl, panel->stream_id, start_slot, = num_slots, pbn); + + return 0; +} + /** * msm_dp_display_mode_valid - callback to determine if specified mode is = valid * @dp: Pointer to dp display structure @@ -1497,6 +1509,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *dp) msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 msm_dp_ctrl_push_vcpf(msm_dp_display->ctrl, msm_dp_display->panel); + msm_dp_ctrl_mst_timeslot_setup(msm_dp_display->ctrl); msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl, msm_dp_display->panel); } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 472429d09200..317c19b809ec 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -43,5 +43,7 @@ void msm_dp_display_atomic_enable(struct msm_dp *dp_displ= ay, enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:18:50 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:31 +0800 Subject: [PATCH v6 14/29] drm/msm/dp: replace power_on with active_stream_cnt Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-14-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=5066; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=GJl85rX2L2niNbZCL3wSxiXdb4cNZLP4ul7aPSHeeOA=; b=+2hL6IQ3VElIQ/yZhfXkp9lmDPPVrFdPBO2Y5nH0HquFxi9q4TGI0Ti25+gLW/4tGHIuzugxD VWttT4J9ihwBfICdYCr66++KIdtbGWaZKjLSoANI8MXOSzCAJhLQ0DX X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: TKy0K3DJR3VHvmwLoTFD_t9wAyhSMsK1 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX52qgdbyF/5fO BiVXeD6Ostrw2TYuiajFX7ai0g8G1ISasXWEfXG1D4IsSHKDF8mzi1cUurCNr1KO1+qUrZxNBEm KtZFXa9TZg9HwrJq6tnwQLlTL4y11AE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX3YQZksAqMbGs 5N6yWgINKfAZLlmHMyVQIrfd+gUAgZNJ9BBzWKMullqSdyMZ7FNElg+fMxecR8U8XyjXuODEkVi Xkwva4k775kKCw6IV0NlMmiEu/1c4kTy7D6Z1BHDJfu7NfP6wogaJafuKquEx8J+cMUCPCfxKax ue5/S6nu24Pd4tUPQwP9G50N7sCLjsarlAz7SHueD4JtjcaO2o5ogK6cpdyW9QyPjMnC8l/alIQ 7DmJlvfJ247TJdWW45cC4eleUNeNWevel8E8WtRGINDvk4OtFnBF+V/eNQJO8Fjr8SvS2CTM0P1 42MLiV1Dprfftg06ZzqurtaRWU1vdZlikeLcDQDxydiPQWZRQ/MnUhIU0TV5OX6R4cKFJRfl82L wEgq08q1ZKV3AJrxuq101/t7dvrbKOnVdJLByUAuQEGJuCMqmPkwXC8FDV1jvSaGehjHvUylQQa ei/wk0KUNz9t12/u5lg== X-Authority-Analysis: v=2.4 cv=ZOPnX37b c=1 sm=1 tr=0 ts=6a9538ec cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=pA7EhmVi1NdrnwtGoTUA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: TKy0K3DJR3VHvmwLoTFD_t9wAyhSMsK1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar The power_on boolean cannot represent DP MST, where multiple streams share a single link and its associated resources. Replace power_on with active_stream_cnt and use it to track the lifetime of the shared link. Link initialization is performed when enabling the first stream, while link teardown is deferred until the last stream is disabled. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_audio.c | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 38 ++++++++++++++++++---------------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 2 +- 3 files changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index df222943ae57..8118130a3220 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -284,7 +284,7 @@ int msm_dp_audio_prepare(struct drm_bridge *bridge, * such cases check for connection status and bail out if not * connected. */ - if (!msm_dp_display->power_on) + if (!msm_dp_display->active_stream_cnt) goto end; =20 audio =3D msm_dp_audio_get_data(msm_dp_display); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 6f79328c8b79..9c5563dcb856 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -645,16 +645,16 @@ static int msm_dp_display_prepare_link(struct msm_dp_= display_private *dp) if (dp->link->sink_count =3D=3D 0) return -ENOTCONN; =20 - if (!msm_dp_display->power_on) { + if (!msm_dp_display->active_stream_cnt) { msm_dp_display_host_phy_init(dp); force_link_train =3D true; - } =20 - rc =3D msm_dp_ctrl_on_link(dp->ctrl, dp->panel); - if (rc) { - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - // TODO: schedule drm_connector_set_link_status_property() - return rc; + rc =3D msm_dp_ctrl_on_link(dp->ctrl, dp->panel); + if (rc) { + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + return rc; + } } =20 return msm_dp_ctrl_prepare_stream_on(dp->ctrl, dp->panel, force_link_trai= n); @@ -667,14 +667,10 @@ static int msm_dp_display_enable(struct msm_dp_displa= y_private *dp, struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); - if (msm_dp_display->power_on) { - drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); - return 0; - } =20 rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel, msm_dp_display->mst_= active); - if (!rc) - msm_dp_display->power_on =3D true; + + msm_dp_display->active_stream_cnt++; =20 return rc; } @@ -723,13 +719,12 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp, { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 - if (!msm_dp_display->power_on) - return 0; - msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); =20 + msm_dp_display->active_stream_cnt--; + drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); return 0; } @@ -851,10 +846,10 @@ void msm_dp_snapshot(struct msm_disp_state *disp_stat= e, struct msm_dp *dp) * if we are reading registers we need the link clocks to be on * however till DP cable is connected this will not happen as we * do not know the resolution to power up with. Hence check the - * power_on status before dumping DP registers to avoid crash due + * active_stream_cnt status before dumping DP registers to avoid crash due * to unclocked access */ - if (!dp->power_on) + if (!dp->active_stream_cnt) return; =20 msm_disp_snapshot_add_block(disp_state, msm_dp_display->ahb_len, @@ -1517,6 +1512,11 @@ static void msm_dp_display_unprepare(struct msm_dp_d= isplay_private *dp) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 + if (msm_dp_display->active_stream_cnt) { + drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); + return; + } + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); @@ -1529,8 +1529,6 @@ static void msm_dp_display_unprepare(struct msm_dp_di= splay_private *dp) else msm_dp_display_host_phy_exit(dp); =20 - msm_dp_display->power_on =3D false; - pm_runtime_put_sync(&msm_dp_display->pdev->dev); =20 drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:18:57 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:32 +0800 Subject: [PATCH v6 15/29] drm/msm/dp: factor out _helper variants of bridge ops accepting a panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-15-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=8728; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=1N9xzYGqZoDTt/jPgVPDArOtr64Id99x27L296/XRaI=; b=6o4QOJEGHLdVKFONb9/sm1Dq0+aodwMvWEDe/v0b6jKNzBgmf1MFhvcUg/jvHj41L/Mur5xot XQ2SUAf4oKiB4HftA/sxCdlWdRHLIJBjKS8ZRzFTfnoQOTjaiBwv012 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: Xyy6PlU1cAo49nZIY_KSSQDfSjP-S2eF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX8X46NvP3Az3h k4TyrohvaeDikDMLuQ3VqVy4x1bmJejHFX29bscRKLoYnOb7bGIu7IzGVE9cw1sF2Uh3UXh1B/x 6LTWYEhB3iGRMp8gKw9V5D9yDvLMAKCwBQYhQwFMLzEH+2LzZ0Cc55izaNurTZ/CIen18m/x0Uc KXMxN+AWvNNSVvafppgF6SjFG6Klxmjfz8wWtE2NM5LhM2y5g4WeytVhPcbwELk1SzridI1YjB+ Y4d3GYIrrAMTEG2BnWj/wlPw9zKoZC8YxZbkrnZCTUi1Da5eZShbRYCHYEP9L/4Mb3VPWYD+FU+ lEnYgiwAEzXyYkAbiiXVL9cA8cxrj/wRl/Z2SCCtDXeZwXpbfGe/758JztC4lVoizuGlfKQ+knp d14da3Fd53gTBrYezTOYnC49G/kloXw4j9+BpuiW3YRTYG2b6V62cyVZKEr5NJUpNttKcjeyVt/ U0yh9fhbeATNp0x7r3w== X-Proofpoint-GUID: Xyy6PlU1cAo49nZIY_KSSQDfSjP-S2eF X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfXxSvmaoUOTC0s S4ZNeHo3E796C+eXdW3vd2bQyAE4WdcWxjeYKa69mElO29KoFZ23BqK7koWrbr0mV+isjyKj6+B eTNJ5SGZO5RdYjaQTHx078iqZNPsJzk= X-Authority-Analysis: v=2.4 cv=a5kAM0SF c=1 sm=1 tr=0 ts=6a9538f4 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=mu3EkBhnCEQeHIwj90QA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar The atomic bridge callbacks (set_mode / enable / disable / post_disable) on dp_display currently hard-code dp->panel. For DP MST every stream has its own msm_dp_panel that the MST encoder owns, so the same enable/disable sequence needs to be invokable against an arbitrary panel. Introduce *_helper variants that take struct msm_dp_panel * and reduce the existing atomic_* callbacks to thin wrappers that pass dp->panel. No SST-path behaviour change. Also drop the static qualifier from msm_dp_display_prepare_link() and msm_dp_display_unprepare() and change them to take struct msm_dp * so the upcoming MST encoder code can drive link-level prepare/unprepare uniformly through the public API. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 100 +++++++++++++++++++++++++-------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 12 +++++ 2 files changed, 82 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 9c5563dcb856..6103fa67f3ee 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -625,12 +625,14 @@ static int msm_dp_display_set_mode(struct msm_dp *msm= _dp_display, return 0; } =20 -static int msm_dp_display_prepare_link(struct msm_dp_display_private *dp) +int msm_dp_display_prepare_link(struct msm_dp *msm_dp_display) { - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + struct msm_dp_display_private *dp; int rc =3D 0; bool force_link_train =3D false; =20 + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); =20 if (msm_dp_display->is_edp) @@ -1448,69 +1450,98 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_displ= ay, struct drm_device *dev, return 0; } =20 -void msm_dp_display_atomic_pre_enable(struct msm_dp *msm_dp_display, - struct drm_atomic_commit *state) +int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state, + struct drm_encoder *drm_encoder, + struct msm_dp_panel *msm_dp_panel) { - struct msm_dp_display_private *dp; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; =20 - dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); - - crtc =3D drm_atomic_get_new_crtc_for_encoder(state, msm_dp_display->bridg= e->encoder); + crtc =3D drm_atomic_get_new_crtc_for_encoder(state, drm_encoder); if (!crtc) - return; + return 0; crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); =20 - /* - * The DPU encoder's .atomic_enable() reads the mode's YUV420 / wide bus - * state and runs before the bridge's .atomic_enable(), so the mode must - * be programmed here, in .atomic_pre_enable(). - */ - msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode, dp->p= anel); + return msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode= , msm_dp_panel); } =20 -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_pre_enable(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state) { int rc =3D 0; struct msm_dp_display_private *dp; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - rc =3D msm_dp_display_prepare_link(dp); + rc =3D msm_dp_display_set_mode_helper(msm_dp_display, state, + msm_dp_display->bridge->encoder, dp->panel); if (rc) { - DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); + DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; } =20 - rc =3D msm_dp_display_enable(dp, dp->panel); + rc =3D msm_dp_display_prepare_link(msm_dp_display); + if (rc) + DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); +} + +void msm_dp_display_enable_helper(struct msm_dp *msm_dp_display, struct ms= m_dp_panel *msm_dp_panel) +{ + int rc =3D 0; + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + rc =3D msm_dp_display_enable(dp, msm_dp_panel); if (rc) DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp, dp->panel); + msm_dp_display_disable(dp, msm_dp_panel); } =20 drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_display_enable_helper(msm_dp_display, dp->panel); +} + +void msm_dp_display_disable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_ctrl_push_vcpf(dp->ctrl, msm_dp_panel); + msm_dp_ctrl_mst_timeslot_setup(dp->ctrl); + msm_dp_ctrl_mst_send_act(dp->ctrl, msm_dp_panel); +} + void msm_dp_display_atomic_disable(struct msm_dp *dp) { struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_ctrl_push_vcpf(msm_dp_display->ctrl, msm_dp_display->panel); - msm_dp_ctrl_mst_timeslot_setup(msm_dp_display->ctrl); - msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl, msm_dp_display->panel); + msm_dp_display_disable_helper(dp, msm_dp_display->panel); } =20 -static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +void msm_dp_display_unprepare(struct msm_dp *msm_dp_display) { - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 if (msm_dp_display->active_stream_cnt) { drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); @@ -1530,11 +1561,9 @@ static void msm_dp_display_unprepare(struct msm_dp_d= isplay_private *dp) msm_dp_display_host_phy_exit(dp); =20 pm_runtime_put_sync(&msm_dp_display->pdev->dev); - - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); } =20 -void msm_dp_display_atomic_post_disable(struct msm_dp *dp) +void msm_dp_display_atomic_post_disable_helper(struct msm_dp *dp, struct m= sm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *msm_dp_display; =20 @@ -1545,7 +1574,18 @@ void msm_dp_display_atomic_post_disable(struct msm_d= p *dp) =20 msm_dp_display_audio_notify_disable(msm_dp_display); =20 - msm_dp_display_disable(msm_dp_display, msm_dp_display->panel); + msm_dp_display_disable(msm_dp_display, msm_dp_panel); + + drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); +} + +void msm_dp_display_atomic_post_disable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_display_atomic_post_disable_helper(msm_dp_display, dp->panel); =20 msm_dp_display_unprepare(msm_dp_display); } diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 7bd510cecb44..9ecd5025fe4a 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -45,5 +45,17 @@ enum drm_mode_status msm_dp_display_mode_valid(struct ms= m_dp *dp, const struct drm_display_mode *mode); int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct m= sm_dp_panel *panel, u32 start_slot, u32 num_slots, u32 pbn); +void msm_dp_display_enable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel); +void msm_dp_display_disable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel); +void msm_dp_display_atomic_post_disable_helper(struct msm_dp *msm_dp_displ= ay, + struct msm_dp_panel *msm_dp_panel); +int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state, + struct drm_encoder *drm_encoder, + struct msm_dp_panel *msm_dp_panel); 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Track a link_ready state so msm_dp_display_prepare_link() runs only once per link and repeated calls are skipped. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 33 +++++++++++++++++++++++++-------- drivers/gpu/drm/msm/dp/dp_display.h | 1 + 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 6103fa67f3ee..90e3d2c4ef47 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -638,6 +638,10 @@ int msm_dp_display_prepare_link(struct msm_dp *msm_dp_= display) if (msm_dp_display->is_edp) msm_dp_hpd_plug_handle(dp); =20 + /* Serialized by modeset lock or mst_lock. */ + if (msm_dp_display->link_ready) + return 0; + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); if (rc) { DRM_ERROR("failed to pm_runtime_resume\n"); @@ -659,7 +663,11 @@ int msm_dp_display_prepare_link(struct msm_dp *msm_dp_= display) } } =20 - return msm_dp_ctrl_prepare_stream_on(dp->ctrl, dp->panel, force_link_trai= n); + rc =3D msm_dp_ctrl_prepare_stream_on(dp->ctrl, dp->panel, force_link_trai= n); + if (!rc) + msm_dp_display->link_ready =3D true; + + return rc; } =20 static int msm_dp_display_enable(struct msm_dp_display_private *dp, @@ -1493,14 +1501,16 @@ void msm_dp_display_enable_helper(struct msm_dp *ms= m_dp_display, struct msm_dp_p =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - rc =3D msm_dp_display_enable(dp, msm_dp_panel); - if (rc) - DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); + if (msm_dp_display->link_ready) { + rc =3D msm_dp_display_enable(dp, msm_dp_panel); + if (rc) + DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 - rc =3D msm_dp_display_post_enable(msm_dp_display); - if (rc) { - DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp, msm_dp_panel); + rc =3D msm_dp_display_post_enable(msm_dp_display); + if (rc) { + DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); + msm_dp_display_disable(dp, msm_dp_panel); + } } =20 drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); @@ -1543,6 +1553,11 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_= display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 + if (!msm_dp_display->link_ready) { + drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); + return; + } + if (msm_dp_display->active_stream_cnt) { drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); return; @@ -1561,6 +1576,8 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_d= isplay) msm_dp_display_host_phy_exit(dp); =20 pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + msm_dp_display->link_ready =3D false; } =20 void msm_dp_display_atomic_post_disable_helper(struct msm_dp *dp, struct m= sm_dp_panel *msm_dp_panel) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 9ecd5025fe4a..51eace1d1346 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -20,6 +20,7 @@ struct msm_dp { bool audio_enabled; u32 active_stream_cnt; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:19:08 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:34 +0800 Subject: [PATCH v6 17/29] drm/msm/dp: add msm_dp_display_get_panel() to initialize DP panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-17-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=3826; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=WB3JEW4F3W0Nb4YZZ57tBhLxCoKYBW7PUps9LAMtJN8=; b=CROqjXteH0mUBcQP9g57bVnwYJgCdbRhRQYMKcKyZpYZkrxlX8gamFJM3qttKaqfJoa3b4Ftf yaFiAgwOGu1C24Hq+Vp+l/p6ScXCuCHyajbRMmxg4wrwplDbOfchDSn X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: Z1rqzCCa5TIDPuJdygyTbaZRVdSUyHFM X-Proofpoint-ORIG-GUID: Z1rqzCCa5TIDPuJdygyTbaZRVdSUyHFM X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX9wYRgj8lqceX fwNDnrWB3LYPzYievyf5yrG0A2YHhBOXnVbJiDL0eNZOIDs7s8Z97p2PYEMokelB9buQHtFJayB lUu+MEO4HGpLjrAYoYw4/iL/7sb4dE0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX5psAPW5gqIey vSs3FHCYszcPIQNlaLMt47sN0BWoJ8P/KeBNb07Ao1wr9pXSYwg+3Kpv6waj99kz1YfR5MkrS74 wuCAIi7fQoT3eudLyvyPtDbBZ/40xH3Nh+uUk3UCp2NoEz6sxcjNI3MPdd7lHebcr8xoalya++w ACtMOKEUt9BDZzWjd3KC0JhdYeXNqyG4up0fl+bk6rXulDnodEwAwiflvzWY45r5R47fatuNxzV 5flDtNrCDKpM1mtCxTkk99ZTnOymGO+BZ0DBwRgoLsvdJR6yyGiwnVNEmn5/Dby1pcRtyyVDg3z GogJukBC4hEhVyZHQJ/Zz0Thsk2FPHdBj5KckU+9EEv5fVBL9wRxuLW76c+kBZvBjv/uqzbe12J QvtUg70expUB9b0F7UJgSvyBtI0iRJOHbGHojiruuXaCMWNIDJ7KoPNEAbtvCximD1T/4Y+2T+4 NST5alsDhOmxxi8hlaw== X-Authority-Analysis: v=2.4 cv=YKKvDxGx c=1 sm=1 tr=0 ts=6a9538fe cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=kCKOgzAXqFYlHSlaV6AA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar Add an API msm_dp_display_get_panel() to initialize and return a DP panel to be used by DP MST module. Since some of the fields of DP panel are private, dp_display module needs to initialize these parts and return the panel back. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 9 +++++++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 1 + drivers/gpu/drm/msm/dp/dp_display.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ 4 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 73aabd219125..c4936e8ba48f 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -3130,6 +3130,15 @@ bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *= msm_dp_ctrl, return ctrl->stream_clks_on[stream_id]; } =20 +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + return ctrl->num_pixel_clks; +} + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, struct drm_dp_aux *aux, struct phy *phy, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index e8b445c552f7..111300784edd 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -61,6 +61,7 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_c= trl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *dp_ctrl, enum msm_dp_stream_id stream_id); +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); void msm_dp_ctrl_mst_timeslot_setup(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 90e3d2c4ef47..6952f83db006 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -529,6 +529,33 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display= _private *dp) return rc; } =20 +struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_displa= y, + enum msm_dp_stream_id stream_id) +{ + struct msm_dp_display_private *dp; + struct msm_dp_panel *dp_panel; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + if (stream_id >=3D msm_dp_ctrl_get_stream_cnt(dp->ctrl)) { + DRM_ERROR("invalid stream_id %d\n", stream_id); + return NULL; + } + + dp_panel =3D msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp-= >link, + dp->link_base, dp->mst2link_base, dp->mst3link_base, + dp->pixel_base[stream_id]); + + if (IS_ERR(dp_panel)) { + DRM_ERROR("failed to initialize panel\n"); + return NULL; + } + + dp_panel->stream_id =3D stream_id; + + return dp_panel; +} + static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_privat= e *dp) { msm_dp_audio_put(dp->audio); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 51eace1d1346..4d4349068c2f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -59,4 +59,6 @@ int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_= display, int msm_dp_display_prepare_link(struct msm_dp *msm_dp_display); void msm_dp_display_unprepare(struct msm_dp *dp); =20 +struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_displa= y, + enum msm_dp_stream_id stream_id); #endif /* _DP_DISPLAY_H_ */ --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85DBE3DDDBE for ; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:19:13 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:35 +0800 Subject: [PATCH v6 18/29] drm/msm/dp: introduce dp_mst_drm module Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-18-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=7475; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=Oy4ARw4by0kYhD1OMSYIGPR7NRvIQSR0y1PyXC2S8d0=; b=cv4mVv8fysTUD1NECx0J/+HKVOjxbEKrANbL7lmNviNfPOcg8pNJLUTDlXbrC8itDrucGGVgs PR8TXeBkZ0VDBGXMMcSY1BP14K70OdGEP62vdBoCIFV/GnvyTQ8b5bJ X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: Jt2n8aChDNbT8IXu4eN_5iDstvXXVyA_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfXzyvFdMGxlDcd hfQq//Hh1KEcYyo6IdfWxhXgeGHYBPUQJ09MYD2VZnakHNRiJpqMCKJ0uxPr9AC01GFPDRe8JW2 YD+ygZO2roN8uOhEZ7JzT8mhy65xSAgdRoWoyH1ig3LcuZ3F2g6tJXd/K1XSiGpte+aGZ5es3qf agDAh21VK/iXw/rrFPE+wScz96QWzGJqzMjgwhGNYC38DrQ8juy2cA3Q6utT4e1Nto3dHNRyj5i RPmIgUYwhdQ2gbRxVuL/mXOqDk1lA2t9U/2TMCgVymV5yRQT/G2sh2KjYqTBpsD7X+7BXltExND at0iBQoRdeFGIRNH2PIvNZPHoqpMUstCvEMLRTZXEWu6F8Aq6UEorGeyMmXDlaQN6lozmcLW5ei 8YTR2feut+UFf/TdnHiNXjrIbe3GXAaRU7bGa1Uxh3Rd87i1EXR7yewnxLVBkM31oLkHgx8oi1b tB97PTPeJFJc7vWQv0w== X-Proofpoint-GUID: Jt2n8aChDNbT8IXu4eN_5iDstvXXVyA_ X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX6fQfOC94G4lX ykLluGS76HaahEGZZFSvqMXAJ9s3blNPlLbaTVqlY18DSdUgWhDwO5QkD23HCAeMPvAPK/VZCeN 8Ub3Ps9o5kIOu31nfIvAOzfX/IJ8TIk= X-Authority-Analysis: v=2.4 cv=a5kAM0SF c=1 sm=1 tr=0 ts=6a953903 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=YtzpOVx_IWpl17dmJv8A:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 Add the dp_mst_drm module and the core MST manager data structures. Introduce the MST manager object, per-stream encoder state and the initialization path for creating a DRM MST topology manager associated with a DP controller. Also add the registration hooks used to initialize the MST manager during DP device setup. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +++++++- drivers/gpu/drm/msm/dp/dp_display.c | 19 ++++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 4 +++ drivers/gpu/drm/msm/dp/dp_mst_drm.c | 54 +++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 12 ++++++++ drivers/gpu/drm/msm/msm_drv.h | 12 ++++++++ 7 files changed, 114 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index d0c3a4c6703b..31a15636958c 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -145,7 +145,8 @@ msm-display-$(CONFIG_DRM_MSM_DP)+=3D dp/dp_aux.o \ dp/dp_link.o \ dp/dp_panel.o \ dp/dp_audio.o \ - dp/dp_utils.o + dp/dp_utils.o \ + dp/dp_mst_drm.o =20 msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) +=3D hdmi/hdmi_hdcp.o =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index da3556eb6ecc..66cabac0a726 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -655,7 +655,7 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, struct msm_display_info info; bool yuv_supported; int rc; - int i; + int i, stream_cnt; =20 for (i =3D 0; i < ARRAY_SIZE(priv->kms->dp); i++) { if (!priv->kms->dp[i]) @@ -678,6 +678,16 @@ static int _dpu_kms_initialize_displayport(struct drm_= device *dev, DPU_ERROR("modeset_init failed for DP, rc =3D %d\n", rc); return rc; } + + stream_cnt =3D msm_dp_get_mst_max_stream(priv->kms->dp[i]); + + if (stream_cnt > 1) { + rc =3D msm_dp_mst_register(priv->kms->dp[i]); + if (rc) { + DPU_ERROR("dp_mst_init failed for DP, rc =3D %d\n", rc); + return rc; + } + } } =20 return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 6952f83db006..c015af868801 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -27,6 +27,7 @@ #include "dp_drm.h" #include "dp_audio.h" #include "dp_debug.h" +#include "dp_mst_drm.h" =20 static bool psr_enabled =3D false; module_param(psr_enabled, bool, 0); @@ -1270,6 +1271,24 @@ static int msm_dp_display_get_io(struct msm_dp_displ= ay_private *display) return 0; } =20 +int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + return msm_dp_ctrl_get_stream_cnt(dp->ctrl); +} + +int msm_dp_mst_register(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + return msm_dp_mst_mgr_init(msm_dp_display, msm_dp_ctrl_get_stream_cnt(dp-= >ctrl), dp->aux); +} + static int msm_dp_display_probe(struct platform_device *pdev) { int rc =3D 0; diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 4d4349068c2f..ca2faf478c95 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -24,6 +24,8 @@ struct msm_dp { unsigned int connector_type; bool is_edp; =20 + void *msm_dp_mst; + struct msm_dp_audio *msm_dp_audio; bool psr_supported; }; @@ -59,6 +61,8 @@ int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_= display, int msm_dp_display_prepare_link(struct msm_dp *msm_dp_display); void msm_dp_display_unprepare(struct msm_dp *dp); =20 +int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display); +int msm_dp_mst_register(struct msm_dp *msm_dp_display); struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_displa= y, enum msm_dp_stream_id stream_id); #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c new file mode 100644 index 000000000000..648d3ec72a1d --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "dp_mst_drm.h" +#include "dp_panel.h" + +struct msm_dp_mst_encoder { + struct drm_encoder *enc; + int stream_id; + struct msm_dp_panel *dp_panel; +}; + +struct msm_dp_mst { + struct drm_dp_mst_topology_mgr mst_mgr; + struct msm_dp_mst_encoder mst_encoders[DP_STREAM_MAX]; + struct msm_dp *msm_dp; + struct drm_dp_aux *dp_aux; + u32 max_streams; +}; + +int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 max_streams, struct= drm_dp_aux *drm_aux) +{ + struct drm_device *dev =3D dp_display->drm_dev; + struct msm_dp_mst *mst; + int ret; + + mst =3D devm_kzalloc(dev->dev, sizeof(*mst), GFP_KERNEL); + if (!mst) + return -ENOMEM; + + mst->msm_dp =3D dp_display; + mst->max_streams =3D max_streams; + mst->dp_aux =3D drm_aux; + + ret =3D drm_dp_mst_topology_mgr_init(&mst->mst_mgr, dev, + drm_aux, + 16, + max_streams, + dp_display->connector->base.id); + if (ret) { + drm_err(dev, "[MST] topology manager init failed\n"); + return ret; + } + + dp_display->msm_dp_mst =3D mst; + return 0; +} diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h new file mode 100644 index 000000000000..e54d49cf3499 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DP_MST_DRM_H_ +#define _DP_MST_DRM_H_ + +#include "dp_display.h" + +int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 max_streams, struct= drm_dp_aux *drm_aux); + +#endif /* _DP_MST_DRM_H_ */ diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index eb4bbae8557b..8e98f7eb8724 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -357,6 +357,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state,= struct msm_dp *dp_displa bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); +int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); +int msm_dp_mst_register(struct msm_dp *dp_display); =20 #else static inline int __init msm_dp_register(void) @@ -389,6 +391,16 @@ static inline bool msm_dp_wide_bus_available(const str= uct msm_dp *dp_display) return false; } =20 +static inline int msm_dp_get_mst_max_stream(struct msm_dp *dp_display) +{ + return -EINVAL; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:19:19 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:36 +0800 Subject: [PATCH v6 19/29] drm/msm/dp: add MST connector creation and topology callbacks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-19-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=9219; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=px59kpsO7tsSyV4f/l2yftQVlV9sM3n3ZimludNAFe0=; b=ysv27kLKsgP/cUyOyOfHVX7CAMARqeTblZloiYCKvE+eJxr0KQtIjz7Tvar67T1dyVJ6KCwlV yYNZgAjzhXmCYjDyKSGwJHQolefWf4b9gALdEaVd5WUe5drur5GsrB+ X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=DY0nbPtW c=1 sm=1 tr=0 ts=6a95390a cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=n5AsotsA7IsgDgQ4TjYA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfXylf2HfmnLy8T 70yM0seKH/4Ml3JfTq7Bz58DtOJjr10ZHiONPxigyhaxc10egwO+QHuoDC0dHSACbQAwMHjlbL9 r/BQv3fMUY2rsy5TUGYk/VpPo50xXamO/3MO1UgNKfpYfbn/pi7kVjip1stvUqj8+SmQOTCtTnZ OogEZmfcv41FrLM1cAnkmfzLWlUGzcyg2TYF4ox+4EMWw5idJ+UctAYCt1HgEsqD+dlTXTcER5k eNNYvsSF4K5BEaqPviF3q1ZjPVJC4phwQKN0cHOih9zNQgk/L+f0fd6viQHOPRhUPXsBq/Ga1Z5 M/qY1yiBuCuhrOeIIHFtjm2ECTtrE2j/bCXALXS8T1iWP2kmvQtaY1FuF6nnVe3Y8l6GoPOqXGA NLycGOy8AV8I6heApvQ5NChqSEAfilIqq4ezADjSVbp1xXVJa1G/+b3Irmk7/VBq0C/fjON9GCc PmPDim4SzQfoLm9YOKQ== X-Proofpoint-ORIG-GUID: iOMNrXbCC3i_5ttoYHQkMDN-JPfV5IMv X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX8D2L0XQVbsEF XNYDrDBtkql582MKU969x3xkNvcG0epVn64PmsuEB1LP+ELUUqXLbuRuCra4xjdCnzZSPm5fFUl fF9fAJ3dIh/Nl0nowh5nG2AyvL+Z6D8= X-Proofpoint-GUID: iOMNrXbCC3i_5ttoYHQkMDN-JPfV5IMv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 Register the add_connector topology callback with the DRM MST manager to create DRM connectors dynamically for MST ports as they appear. Each MST port is represented by a DRM connector. The connectors are attached to all available MST stream encoders, allowing encoder assignment to be determined dynamically rather than being permanently associated with a specific stream. This enables MST sink ports to be exposed as DRM connectors. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 240 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 240 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 648d3ec72a1d..94a717ba7c82 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -7,10 +7,20 @@ #include #include #include +#include =20 #include "dp_mst_drm.h" #include "dp_panel.h" =20 +#define to_dp_mst_connector(x) \ + container_of((x), struct msm_dp_mst_connector, connector) + +struct msm_dp_mst_connector { + struct drm_connector connector; + struct drm_dp_mst_port *mst_port; + struct msm_dp_mst *dp_mst; +}; + struct msm_dp_mst_encoder { struct drm_encoder *enc; int stream_id; @@ -25,6 +35,235 @@ struct msm_dp_mst { u32 max_streams; }; =20 +static void dp_mst_connector_destroy(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + + drm_connector_cleanup(connector); + drm_dp_mst_put_port_malloc(mst_conn->mst_port); + kfree(mst_conn); +} + +static const struct drm_connector_funcs msm_dp_drm_mst_connector_funcs =3D= { + .reset =3D drm_atomic_helper_connector_reset, + .destroy =3D dp_mst_connector_destroy, + .fill_modes =3D drm_helper_probe_single_connector_modes, + .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, +}; + +/* DP MST Connector OPs */ +static int +msm_dp_mst_connector_detect(struct drm_connector *connector, + struct drm_modeset_acquire_ctx *ctx, + bool force) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct msm_dp *dp_display =3D mst->msm_dp; + struct device *dev =3D dp_display->drm_dev->dev; + enum drm_connector_status status =3D connector_status_disconnected; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return status; + + if (dp_display->mst_active) + status =3D drm_dp_mst_detect_port(connector, + ctx, &mst->mst_mgr, mst_conn->mst_port); + + pm_runtime_put_autosuspend(dev); + + return status; +} + +static int msm_dp_mst_connector_get_modes(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + const struct drm_edid *drm_edid; + int rc; + + drm_edid =3D drm_dp_mst_edid_read(connector, &mst->mst_mgr, mst_conn->mst= _port); + drm_edid_connector_update(connector, drm_edid); + + rc =3D drm_edid_connector_add_modes(connector); + + drm_edid_free(drm_edid); + + return rc; +} + +static enum drm_mode_status msm_dp_mst_connector_mode_valid(struct drm_con= nector *connector, + const struct drm_display_mode *mode) +{ + struct msm_dp_mst_connector *mst_conn; + struct drm_dp_mst_port *mst_port; + struct msm_dp *dp_display; + int required_pbn; + + if (drm_connector_is_unregistered(connector)) + return 0; + + mst_conn =3D to_dp_mst_connector(connector); + mst_port =3D mst_conn->mst_port; + dp_display =3D mst_conn->dp_mst->msm_dp; + + /* Use minimum possible bpp (6bpc RGB, 8b10b) to avoid rejecting modes + * that would be feasible at the actual link bpp. mode_valid must not + * depend on negotiated parameters. + */ + required_pbn =3D drm_dp_calc_pbn_mode(mode->clock, (6 * 3) << 4); + + if (required_pbn > mst_port->full_pbn) { + drm_dbg_dp(dp_display->drm_dev, "mode:%s not supported.\n", mode->name); + return MODE_CLOCK_HIGH; + } + + return msm_dp_display_mode_valid(dp_display, &connector->display_info, mo= de); +} + +static int msm_dp_mst_connector_atomic_check(struct drm_connector *connect= or, + struct drm_atomic_commit *state) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + + return drm_dp_atomic_release_time_slots(state, &mst->mst_mgr, mst_conn->m= st_port); +} + +static int msm_dp_mst_encoder_stream_id(struct msm_dp_mst *mst, + struct drm_encoder *enc) +{ + int i; + + for (i =3D 0; i < mst->max_streams; i++) { + if (mst->mst_encoders[i].enc =3D=3D enc) + return mst->mst_encoders[i].stream_id; + } + return -1; +} + +static struct drm_encoder * +msm_dp_mst_atomic_best_encoder(struct drm_connector *connector, struct drm= _atomic_commit *state) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct drm_connector_state *conn_state; + struct drm_connector *iter; + struct drm_connector_list_iter conn_iter; + u32 stream_mask =3D 0; + u32 i; + + conn_state =3D drm_atomic_get_new_connector_state(state, connector); + if (!conn_state) + return NULL; + + if (conn_state->best_encoder) + return conn_state->best_encoder; + + drm_connector_list_iter_begin(connector->dev, &conn_iter); + drm_for_each_connector_iter(iter, &conn_iter) { + struct drm_connector_state *peer_state; + int stream_id; + + if (iter =3D=3D connector || + iter->funcs !=3D &msm_dp_drm_mst_connector_funcs || + to_dp_mst_connector(iter)->dp_mst !=3D mst) + continue; + + peer_state =3D drm_atomic_get_new_connector_state(state, iter) ?: iter->= state; + if (!peer_state || !peer_state->crtc || !peer_state->best_encoder) + continue; + + stream_id =3D msm_dp_mst_encoder_stream_id(mst, peer_state->best_encoder= ); + if (stream_id >=3D 0 && stream_id < mst->max_streams) + stream_mask |=3D BIT(stream_id); + } + drm_connector_list_iter_end(&conn_iter); + + for (i =3D 0; i < mst->max_streams; i++) { + if (!(stream_mask & BIT(i))) { + conn_state->best_encoder =3D mst->mst_encoders[i].enc; + return mst->mst_encoders[i].enc; + } + } + + return NULL; +} + +/* DRM MST callbacks */ +static const struct drm_connector_helper_funcs msm_dp_drm_mst_connector_he= lper_funcs =3D { + .get_modes =3D msm_dp_mst_connector_get_modes, + .detect_ctx =3D msm_dp_mst_connector_detect, + .mode_valid =3D msm_dp_mst_connector_mode_valid, + .atomic_best_encoder =3D msm_dp_mst_atomic_best_encoder, + .atomic_check =3D msm_dp_mst_connector_atomic_check, +}; + +static struct drm_connector * +msm_dp_mst_add_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, const char *pathprop) +{ + struct msm_dp_mst *mst =3D container_of(mgr, struct msm_dp_mst, mst_mgr); + struct drm_device *dev =3D mst->msm_dp->drm_dev; + struct msm_dp_mst_connector *mst_conn; + struct drm_connector *connector; + int rc, i; + + mst_conn =3D kzalloc_obj(*mst_conn); + if (!mst_conn) + return NULL; + + connector =3D &mst_conn->connector; + rc =3D drm_connector_dynamic_init(dev, connector, + &msm_dp_drm_mst_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort, NULL); + if (rc) + goto err_free; + + mst_conn->dp_mst =3D mst; + + drm_connector_helper_add(connector, &msm_dp_drm_mst_connector_helper_func= s); + connector->funcs->reset(connector); + + /* add all encoders as possible encoders */ + for (i =3D 0; i < mst->max_streams; i++) { + rc =3D drm_connector_attach_encoder(connector, mst->mst_encoders[i].enc); + if (rc) { + drm_err(dev, "[MST] failed to attach encoder:%u to conn:%d rc:%d\n", + mst->mst_encoders[i].enc->base.id, + connector->base.id, rc); + goto err_connector; + } + } + + mst_conn->mst_port =3D port; + drm_dp_mst_get_port_malloc(port); + + drm_object_attach_property(&connector->base, + dev->mode_config.path_property, 0); + drm_object_attach_property(&connector->base, + dev->mode_config.tile_property, 0); + drm_connector_set_path_property(connector, pathprop); + + drm_dbg_kms(dev, "[MST] add_connector done conn:%d max_streams:%u\n", + connector->base.id, mst->max_streams); + + return connector; + +err_connector: + drm_connector_cleanup(connector); +err_free: + kfree(mst_conn); + return NULL; +} + +static const struct drm_dp_mst_topology_cbs msm_dp_mst_drm_cbs =3D { + .add_connector =3D msm_dp_mst_add_connector, +}; + int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 max_streams, struct= drm_dp_aux *drm_aux) { struct drm_device *dev =3D dp_display->drm_dev; @@ -35,6 +274,7 @@ int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 m= ax_streams, struct drm_d if (!mst) return -ENOMEM; =20 + mst->mst_mgr.cbs =3D &msm_dp_mst_drm_cbs; mst->msm_dp =3D dp_display; mst->max_streams =3D max_streams; mst->dp_aux =3D drm_aux; --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A7C3D8911 for ; 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This removes a redundant argument and keeps all interface selection parameters in msm_display_info. No functional change. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 1f20695f81e3..91cbb0ca521b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1437,15 +1437,16 @@ static void dpu_encoder_virt_atomic_disable(struct = drm_encoder *drm_enc, =20 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg = *catalog, struct dpu_rm *dpu_rm, - enum dpu_intf_type type, u32 controller_id) + struct msm_display_info *disp_info, int index) { int i =3D 0; + u32 controller_id =3D disp_info->h_tile_instance[index]; =20 - if (type =3D=3D INTF_WB) + if (disp_info->intf_type =3D=3D INTF_WB) return NULL; =20 for (i =3D 0; i < catalog->intf_count; i++) { - if (catalog->intf[i].type =3D=3D type + if (catalog->intf[i].type =3D=3D disp_info->intf_type && catalog->intf[i].controller_id =3D=3D controller_id) { return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); 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Add stream_id to msm_display_info and use it to select the matching interface for a stream. For DSI, eDP and SST configurations, stream_id remains zero and behavior is unchanged. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 91cbb0ca521b..004d5fc460a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1439,17 +1439,18 @@ static struct dpu_hw_intf *dpu_encoder_get_intf(con= st struct dpu_mdss_cfg *catal struct dpu_rm *dpu_rm, struct msm_display_info *disp_info, int index) { - int i =3D 0; + int i =3D 0, cnt =3D 0; u32 controller_id =3D disp_info->h_tile_instance[index]; + int stream_id =3D disp_info->stream_id; =20 if (disp_info->intf_type =3D=3D INTF_WB) return NULL; =20 for (i =3D 0; i < catalog->intf_count; i++) { if (catalog->intf[i].type =3D=3D disp_info->intf_type - && catalog->intf[i].controller_id =3D=3D controller_id) { + && catalog->intf[i].controller_id =3D=3D controller_id + && cnt++ =3D=3D stream_id) return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); - } } =20 return NULL; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.h index 4942097e7613..9972e209bd58 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -28,6 +28,7 @@ * @h_tile_instance: Controller instance used per tile. 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:19:34 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:39 +0800 Subject: [PATCH v6 22/29] drm/msm/dpu: add per-stream MST encoders Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-22-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=5897; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=xQT+vbjgJJMddsLQ5y+pc+pr1hM+97dd6In2F3g2ICU=; b=n2lt27MLpS+yw6X0SsgY+ko9lqYC5SswbreVbllOdiGTMXoxP8dNxFQN7MCfY+62DBzAmm9hu Yiot1iZMhovBw3zhd8vZANTLnu6/Zybbam7CJA/lzmt7t7yfDbCMq82 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=E9f9Y6dl c=1 sm=1 tr=0 ts=6a953918 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=aoVTMipVTiCx4Xnk7jUA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX9hrlX76N88iy 5s14Cc/QJXOTLO3OsGNy8A8DK9vjvh4DuyaLFVu/d9uPYIZ74s0wJWCGNFhaY2kXu6fB5nUy74k hg01DZ4vT5k8Tky3CMqSn+CARSGWOyA= X-Proofpoint-ORIG-GUID: UB0zyXcrDTwI-J1vJg2NLYyGWU_p1Lfr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX8b5d0nSU3+Kz nvLVcyyhE0AvlCArnMgf84nrhKMXWYvmRXpNmxmRV8IXmYhYQmUMc/+RqSbN4NK9YhV07USDRc4 iHD/ZsVx6PxmhViihcyLlpz+8tdm9kswctNCVFRYUTPRcTfINVXGetJIcvkX8puqpEPVOgqJtBg PtUTpgMFYoSuez5ebyIxnf6vwvO2BSY1qBLGOKAkqlzsUV1NsoF+3+/g0ZdiZDZh9V15PKrDl8j a4TcJ9M/Q5uTFaurIZy/7mx0VzFkfT3SvUI0gZFvZGAH3gmp12aMNhB87Mul/O3KbLqjyi6vNqc CqgYfp8USCiDKBhkmYQBdC1m4Pr+ai9dVSpkY/OzfjfO5X/AXu+d12ZTSYfB+u8Zj7LRFRqWfY/ L+qnqKLKRaLXW55RhOiM0iIX7+dnvi4P0fbCx5YUg/Idb7dhP7x6pzpVxlu1JUNEl/h95JXUagu jKMZuWF5CtdrFOeFZ7A== X-Proofpoint-GUID: UB0zyXcrDTwI-J1vJg2NLYyGWU_p1Lfr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 Unlike SST, where a DP controller is represented by a single encoder, MST requires an encoder instance for each stream. Create one DRM encoder per MST stream, associate it with a stream ID, and initialize it with MST-specific encoder helper callbacks. This establishes the per-stream encoder infrastructure required for DP MST support. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 23 ++++++++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 15 +++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.c | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 2 ++ drivers/gpu/drm/msm/msm_drv.h | 9 +++++++++ 5 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 004d5fc460a8..533109b4365c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2744,6 +2744,24 @@ static const struct drm_encoder_helper_funcs dpu_enc= oder_helper_funcs =3D { .atomic_enable =3D dpu_encoder_virt_atomic_enable, }; =20 +static void dpu_encoder_mst_atomic_enable(struct drm_encoder *enc, + struct drm_atomic_commit *state) +{ + dpu_encoder_virt_atomic_enable(enc, state); +} + +static void dpu_encoder_mst_atomic_disable(struct drm_encoder *enc, + struct drm_atomic_commit *state) +{ + dpu_encoder_virt_atomic_disable(enc, state); +} + +static const struct drm_encoder_helper_funcs dpu_mst_encoder_helper_funcs = =3D { + .atomic_mode_set =3D dpu_encoder_virt_atomic_mode_set, + .atomic_enable =3D dpu_encoder_mst_atomic_enable, + .atomic_disable =3D dpu_encoder_mst_atomic_disable, +}; + static const struct drm_encoder_funcs dpu_encoder_funcs =3D { .debugfs_init =3D dpu_encoder_debugfs_init, }; @@ -2769,7 +2787,10 @@ struct drm_encoder *dpu_encoder_init(struct drm_devi= ce *dev, if (IS_ERR(dpu_enc)) return ERR_CAST(dpu_enc); =20 - drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); + if (drm_enc_mode =3D=3D DRM_MODE_ENCODER_DPMST) + drm_encoder_helper_add(&dpu_enc->base, &dpu_mst_encoder_helper_funcs); + else + drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); =20 spin_lock_init(&dpu_enc->enc_spinlock); dpu_enc->enabled =3D false; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 66cabac0a726..d6182cec06d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -688,6 +688,21 @@ static int _dpu_kms_initialize_displayport(struct drm_= device *dev, return rc; } } + + for (int stream_id =3D 0; stream_cnt > 1 && stream_id < stream_cnt; stre= am_id++) { + info.stream_id =3D stream_id; + encoder =3D dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); + if (IS_ERR(encoder)) { + DPU_ERROR("encoder init failed for dp mst display\n"); + return PTR_ERR(encoder); + } + + rc =3D msm_dp_mst_attach_encoder(priv->kms->dp[i], stream_id, encoder); + if (rc) { + DPU_ERROR("dp_mst attach_encoder failed, rc =3D %d\n", rc); + return rc; + } + } } =20 return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 94a717ba7c82..93536b6936cb 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -145,6 +145,26 @@ static int msm_dp_mst_encoder_stream_id(struct msm_dp_= mst *mst, return -1; } =20 +int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, unsigned int stre= am_id, + struct drm_encoder *encoder) +{ + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct msm_dp_panel *dp_panel; + + dp_panel =3D msm_dp_display_get_panel(dp_display, stream_id); + if (!dp_panel) { + drm_err(dp_display->drm_dev, + "[MST] failed to allocate panel for stream %d\n", stream_id); + return -ENOMEM; + } + + mst->mst_encoders[stream_id].enc =3D encoder; + mst->mst_encoders[stream_id].stream_id =3D stream_id; + mst->mst_encoders[stream_id].dp_panel =3D dp_panel; + + return 0; +} + static struct drm_encoder * msm_dp_mst_atomic_best_encoder(struct drm_connector *connector, struct drm= _atomic_commit *state) { diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h index e54d49cf3499..89f73b1db2e7 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -8,5 +8,7 @@ #include "dp_display.h" =20 int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 max_streams, struct= drm_dp_aux *drm_aux); +int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, unsigned int stre= am_id, + struct drm_encoder *encoder); =20 #endif /* _DP_MST_DRM_H_ */ diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 8e98f7eb8724..6c6a1546478d 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -359,6 +359,8 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_= display, bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:19:40 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:40 +0800 Subject: [PATCH v6 23/29] drm/msm/dp: add atomic stream handling for MST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-23-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=10460; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=oxxFLGz51w9qXVS0OffsM5JGTewECkY9VNmCDbwCrDo=; b=G+FGjToGrlKba9HFOKRkneVL8KhMZNnJDlyS7EsjW6S0sl9ZY9HttYjqKjEEbYYGpVRmrBj+X E6ACj4pDH2XBVlxxyhwtBuqfx/pDT/YzSvpstMSUrwh4RYPhxOFsIyW X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: vDSyk9wnAk3QEQYPKYV_Evf_uXE5a6Ou X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX3q023mNrDH2F Ddh0ChcTNWliC9rtZUeYwJgPuzC34w2Mw/D6G+0nvr8//taaoG+2X5wtvTiAzwp2cNaaAK+PJd2 bbALhAiYJSERlhWaaONQAa8cBURLZc0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX1eLIexVXFHpj CKjhGtmTz207zRzcUtACRewRDWFULMtLncpPh6a3VjEqdfL6usCfKsSUf+G67Cb0oS7I1yNt+zJ BXbLvwy3ocbksppXZMyY54Fefb/KVZ+Of3QvWkDZiLzS9ft9GOGQWSYw1KqLC+jSWEG2OTdO4OA vk3KkHxpYBkopN/lk0xuW6isuDv/1u1s15S0GhwixVCjS2JhiEEnzOYEk24gVn2smURMM5z0rKn 4CHqmH0iUC1Prw8HFY7OjJ0Je0UBuPy7TEFsWsG05VFQrOKJxkuQVJq252K3Kh58BudFM7MpIYv x2exFilcuqIdXTtDejcSUu/V56AhdrBMIjEzfK4GWAFkVkUZHGPIf9AwWc7Xc1M1LMezMPm3cZ4 arKPWhZges+CtnbtipB5utL8Ek/fMmDk4+FqhvZfOYKOziXfCGCoSJp4noO+ek4FfUXShmPOSP9 ScQgCRQmP1S+x6nFGTw== X-Authority-Analysis: v=2.4 cv=ZOPnX37b c=1 sm=1 tr=0 ts=6a95391e cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=BM7BldANtbQ-uxA6OcgA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: vDSyk9wnAk3QEQYPKYV_Evf_uXE5a6Ou X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 Add the atomic check, enable and disable operations for MST streams. Reserve VC payload bandwidth based on the negotiated link parameters, and update the MST payload when enabling or disabling each DP stream. Serialize stream updates that access the shared MST link state. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++ drivers/gpu/drm/msm/dp/dp_mst_drm.c | 162 ++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/msm_drv.h | 19 ++++ 3 files changed, 192 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 533109b4365c..00b0da33f446 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2747,16 +2747,27 @@ static const struct drm_encoder_helper_funcs dpu_en= coder_helper_funcs =3D { static void dpu_encoder_mst_atomic_enable(struct drm_encoder *enc, struct drm_atomic_commit *state) { + msm_dp_mst_stream_enable(enc, state); dpu_encoder_virt_atomic_enable(enc, state); } =20 static void dpu_encoder_mst_atomic_disable(struct drm_encoder *enc, struct drm_atomic_commit *state) { + msm_dp_mst_stream_disable(enc, state); dpu_encoder_virt_atomic_disable(enc, state); + msm_dp_mst_stream_post_disable(enc, state); +} + +static int dpu_encoder_mst_atomic_check(struct drm_encoder *enc, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + return msm_dp_mst_stream_atomic_check(enc, crtc_state, conn_state); } =20 static const struct drm_encoder_helper_funcs dpu_mst_encoder_helper_funcs = =3D { + .atomic_check =3D dpu_encoder_mst_atomic_check, .atomic_mode_set =3D dpu_encoder_virt_atomic_mode_set, .atomic_enable =3D dpu_encoder_mst_atomic_enable, .atomic_disable =3D dpu_encoder_mst_atomic_disable, diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 93536b6936cb..03f9c95ca686 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -33,6 +33,9 @@ struct msm_dp_mst { struct msm_dp *msm_dp; struct drm_dp_aux *dp_aux; u32 max_streams; + /* Serializes concurrent stream link-state access across streams. */ + struct mutex mst_lock; + struct msm_dp_link_info link_info; }; =20 static void dp_mst_connector_destroy(struct drm_connector *connector) @@ -133,6 +136,18 @@ static int msm_dp_mst_connector_atomic_check(struct dr= m_connector *connector, return drm_dp_atomic_release_time_slots(state, &mst->mst_mgr, mst_conn->m= st_port); } =20 +static struct msm_dp_panel *msm_dp_mst_panel_from_encoder(struct msm_dp_ms= t *mst, + struct drm_encoder *enc) +{ + int i; + + for (i =3D 0; i < mst->max_streams; i++) { + if (mst->mst_encoders[i].enc =3D=3D enc) + return mst->mst_encoders[i].dp_panel; + } + return NULL; +} + static int msm_dp_mst_encoder_stream_id(struct msm_dp_mst *mst, struct drm_encoder *enc) { @@ -145,6 +160,152 @@ static int msm_dp_mst_encoder_stream_id(struct msm_dp= _mst *mst, return -1; } =20 +void msm_dp_mst_stream_enable(struct drm_encoder *encoder, + struct drm_atomic_commit *state) +{ + struct drm_connector *connector =3D + drm_atomic_get_new_connector_for_encoder(state, encoder); + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct msm_dp *dp_display =3D mst->msm_dp; + struct msm_dp_panel *panel =3D msm_dp_mst_panel_from_encoder(mst, encoder= ); + struct drm_dp_mst_port *port =3D mst_conn->mst_port; + struct drm_dp_mst_topology_state *mst_state =3D + drm_atomic_get_new_mst_topology_state(state, &mst->mst_mgr); + struct drm_dp_mst_atomic_payload *payload =3D + drm_atomic_get_mst_payload_state(mst_state, port); + int rc; + + guard(mutex)(&mst->mst_lock); + + drm_connector_get(connector); + panel->connector =3D connector; + + rc =3D msm_dp_display_set_mode_helper(dp_display, state, encoder, panel); + if (rc) { + drm_err(dp_display->drm_dev, + "[MST] stream:%u set_mode failed rc=3D%d\n", panel->stream_id, rc); + return; + } + + rc =3D msm_dp_display_prepare_link(dp_display); + if (rc) { + drm_err(dp_display->drm_dev, + "[MST] stream:%u prepare_link failed rc=3D%d\n", panel->stream_id, rc); + msm_dp_display_unprepare(dp_display); + return; + } + + drm_dp_mst_update_slots(mst_state, DP_CAP_ANSI_8B10B); + + rc =3D drm_dp_add_payload_part1(&mst->mst_mgr, mst_state, payload); + if (rc) + return; + + msm_dp_display_set_stream_info(mst->msm_dp, panel, + payload->vc_start_slot, + payload->time_slots, payload->pbn); + drm_dbg_kms(dp_display->drm_dev, + "[MST] stream:%u timeslots vc_start:%d slots:%d pbn:%d\n", + panel->stream_id, payload->vc_start_slot, + payload->time_slots, payload->pbn); + + msm_dp_display_enable_helper(dp_display, panel); + + drm_dp_check_act_status(&mst->mst_mgr); + + drm_dp_add_payload_part2(&mst->mst_mgr, payload); +} + +void msm_dp_mst_stream_disable(struct drm_encoder *encoder, + struct drm_atomic_commit *state) +{ + struct drm_connector *connector =3D drm_atomic_get_old_connector_for_enco= der(state, encoder); + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct msm_dp_panel *panel =3D msm_dp_mst_panel_from_encoder(mst, encoder= ); + struct drm_dp_mst_topology_state *old_mst_state =3D + drm_atomic_get_old_mst_topology_state(state, &mst->mst_mgr); + struct drm_dp_mst_topology_state *new_mst_state =3D + drm_atomic_get_new_mst_topology_state(state, &mst->mst_mgr); + struct drm_dp_mst_atomic_payload *old_payload =3D + drm_atomic_get_mst_payload_state(old_mst_state, mst_conn->mst_port); + struct drm_dp_mst_atomic_payload *new_payload =3D + drm_atomic_get_mst_payload_state(new_mst_state, mst_conn->mst_port); + + guard(mutex)(&mst->mst_lock); + + drm_dp_remove_payload_part1(&mst->mst_mgr, new_mst_state, new_payload); + + drm_dp_remove_payload_part2(&mst->mst_mgr, new_mst_state, old_payload, ne= w_payload); + + msm_dp_display_set_stream_info(mst->msm_dp, panel, 0, 0, 0); + drm_dbg_kms(mst->msm_dp->drm_dev, + "[MST] stream:%u timeslots vc_start:%d slots:%d pbn:%d\n", + panel->stream_id, new_payload->vc_start_slot, + new_payload->time_slots, new_payload->pbn); + + msm_dp_display_disable_helper(mst->msm_dp, panel); + + drm_dp_check_act_status(&mst->mst_mgr); +} + +void msm_dp_mst_stream_post_disable(struct drm_encoder *encoder, + struct drm_atomic_commit *state) +{ + struct drm_connector *connector =3D drm_atomic_get_old_connector_for_enco= der(state, encoder); + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct msm_dp_panel *panel =3D msm_dp_mst_panel_from_encoder(mst, encoder= ); + + guard(mutex)(&mst->mst_lock); + + msm_dp_display_atomic_post_disable_helper(mst->msm_dp, panel); + + if (!mst->msm_dp->mst_active) + msm_dp_display_unprepare(mst->msm_dp); + + panel->connector =3D NULL; + + drm_connector_put(connector); +} + +int msm_dp_mst_stream_atomic_check(struct drm_encoder *enc, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct msm_dp_mst_connector *mst_conn =3D to_dp_mst_connector(conn_state-= >connector); + struct msm_dp_mst *mst =3D mst_conn->dp_mst; + struct drm_dp_mst_topology_state *mst_state; + int bpp, pbn, slots; + + if (!conn_state->crtc) + return 0; + + if (!drm_atomic_crtc_needs_modeset(crtc_state) || !crtc_state->active) + return 0; + + bpp =3D (conn_state->connector->display_info.bpc * 3) ?: 24; /* fallback:= assume 8bpc */ + pbn =3D drm_dp_calc_pbn_mode(crtc_state->mode.clock, bpp << 4); + + mst_state =3D drm_atomic_get_mst_topology_state(crtc_state->state, &mst->= mst_mgr); + if (IS_ERR(mst_state)) + return PTR_ERR(mst_state); + + if (!dfixed_trunc(mst_state->pbn_div)) { + mst_state->pbn_div =3D + drm_dp_get_vc_payload_bw(mst->link_info.rate, + mst->link_info.num_lanes); + } + + slots =3D drm_dp_atomic_find_time_slots(crtc_state->state, &mst->mst_mgr, + mst_conn->mst_port, pbn); + if (slots < 0) + return slots; + + return 0; +} + int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, unsigned int stre= am_id, struct drm_encoder *encoder) { @@ -309,6 +470,7 @@ int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 = max_streams, struct drm_d return ret; } =20 + mutex_init(&mst->mst_lock); dp_display->msm_dp_mst =3D mst; return 0; } diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 6c6a1546478d..e9a7c9332707 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -361,6 +361,12 @@ int msm_dp_get_mst_max_stream(struct msm_dp *dp_displa= y); int msm_dp_mst_register(struct msm_dp *dp_display); int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, unsigned int stre= am_id, struct drm_encoder *encoder); +void msm_dp_mst_stream_enable(struct drm_encoder *enc, struct drm_atomic_c= ommit *state); +void msm_dp_mst_stream_disable(struct drm_encoder *enc, struct drm_atomic_= commit *state); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:19:45 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:41 +0800 Subject: [PATCH v6 24/29] drm/msm/dp: add HPD callback for dp MST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-24-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=5866; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=BbNlDqCJNiGbUB7FO4KoLqLxFy+/jxUEkwHF+8lImVQ=; b=+sq47yHGy9lKZu3Jf5gVP2ZS5N9oOOOf7FlvlLNtHA5RrL9sNU9+ozhC6HiCWz0lFsVz2NUoq 8qP9lH5R70zBoYSVMp5uLJK5E0z5k7VLNz11uh7hl8upJ6Z7VckSSwA X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: CsEGIP_znB1sdk2rnkr1bdvT-FOXESMQ X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfXw6N+aqSfnvxr 8PT3El4gTo+askz6CNbCVRQAtr4DtY6UwXSKjNsHjOHGzYNUW+kXhALw6Eo6+dSiDUYw2JLl0gD GlIhI0Te5JkC8ywq0dh8gUzNlHou3jc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX+iQhOD6+urDj 4fMVoZM7vo7Lp9S13bMZXWzkdPs8MDv23vRphxoIHgOB4IrhB3OZ0dwZOY+3DXbk2tkRRN0GxRV DtB0f34K2sBjecNTi+ni401LL0efLOzRp7p1RHDxPxIYZwxZ6pklzljA7N48x3x1xDMDbhP3g2E BDxVOtUm0Ps3gN3kGPrXj48aXq5Fe7rXMSikiU7v5YGhdB4Gpqtutcmpm3pYp/bGPp8fgXSp+uv IuMR35A3417NvLOER9L4v2uCNWfaUnPNXJSWUizpd59LQ8rOBW1WOg3Y2njKBytmeUGDCKeZW/g JxATskkQoa9c9b0/45ypGq+A9M5LB+YJQ3MAPYznZ96Yo79GwRmpKrV4k3/dIxsMID2Sp0OVB9d W6Wd+AIBdEgcD3XEM1cDB3M5NV9TQSAk2mh6/ur+JyIR9Upg+VinbmQ8lehoqcr4az6D6O4p+kk q/+wo8wZXILdqfGZh0w== X-Authority-Analysis: v=2.4 cv=ZOPnX37b c=1 sm=1 tr=0 ts=6a953923 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=aoVTMipVTiCx4Xnk7jUA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: CsEGIP_znB1sdk2rnkr1bdvT-FOXESMQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar Add HPD callback for the MST module which shall be invoked from the dp_display's HPD handler to perform MST specific operations in case of HPD. In MST case, route the HPD messages to MST module. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 26 +++++++++++++++++----- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 44 +++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 1 + 3 files changed, 66 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index c015af868801..22b925277462 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -416,6 +416,9 @@ static int msm_dp_hpd_plug_handle(struct msm_dp_display= _private *dp) dp->msm_dp_display.connector_type, dp->link->sink_count); =20 + if (dp->plugged && dp->msm_dp_display.mst_active) + return 0; + guard(mutex)(&dp->plugged_lock); =20 ret =3D pm_runtime_resume_and_get(&pdev->dev); @@ -506,12 +509,18 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_displa= y_private *dp) { u32 sink_request; int rc =3D 0; + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 /* irq_hpd can happen at either connected or disconnected state */ drm_dbg_dp(dp->drm_dev, "Before, type=3D%d, sink_count=3D%d\n", dp->msm_dp_display.connector_type, dp->link->sink_count); =20 + if (msm_dp_display->mst_active) { + msm_dp_mst_display_hpd_irq(&dp->msm_dp_display); + return 0; + } + /* check for any test request issued by sink */ rc =3D msm_dp_link_process_request(dp->link); if (!rc) { @@ -1056,10 +1065,16 @@ static irqreturn_t msm_dp_display_irq_thread(int ir= q, void *dev_id) drm_bridge_hpd_notify(dp->msm_dp_display.bridge, connector_status_connected); =20 - /* Send HPD as connected and distinguish it in the notifier */ - if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) - drm_bridge_hpd_notify(dp->msm_dp_display.bridge, - connector_status_connected); + /* Temporary until DRM IRQ support is finalized, then switch to + * drm_bridge_hpd_notify(). + */ + if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { + if (dp->msm_dp_display.mst_active) + msm_dp_irq_hpd_handle(dp); + else + drm_bridge_hpd_notify(dp->msm_dp_display.bridge, + connector_status_connected); + } =20 ret =3D IRQ_HANDLED; =20 @@ -1717,7 +1732,8 @@ void msm_dp_bridge_hpd_notify(struct drm_bridge *brid= ge, msm_dp_hpd_plug_handle(dp); } } else { - msm_dp_hpd_unplug_handle(dp); + if (hpd_link_status =3D=3D ISR_DISCONNECTED) + msm_dp_hpd_unplug_handle(dp); } =20 pm_runtime_put_sync(&msm_dp_display->pdev->dev); diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 03f9c95ca686..2e625a7db981 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -35,6 +35,8 @@ struct msm_dp_mst { u32 max_streams; /* Serializes concurrent stream link-state access across streams. */ struct mutex mst_lock; + /* Serializes HPD IRQ handling between IRQ handler and poll_hpd_irq. */ + struct mutex hpd_irq_lock; struct msm_dp_link_info link_info; }; =20 @@ -326,6 +328,39 @@ int msm_dp_mst_attach_encoder(struct msm_dp *dp_displa= y, unsigned int stream_id, return 0; } =20 +void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display) +{ + int rc; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + u8 ack[8] =3D {}; + u8 esi[4]; + unsigned int esi_res =3D DP_SINK_COUNT_ESI + 1; + bool handled; + + guard(mutex)(&mst->hpd_irq_lock); + + rc =3D drm_dp_dpcd_read_data(mst->dp_aux, DP_SINK_COUNT_ESI, esi, 4); + if (rc < 0) { + DRM_ERROR("DPCD sink status read failed, rlen=3D%d\n", rc); + return; + } + + drm_dbg_dp(dp_display->drm_dev, "MST HPD IRQ: esi=3D%*ph\n", 4, esi); + + rc =3D drm_dp_mst_hpd_irq_handle_event(&mst->mst_mgr, esi, ack, &handled); + + if (handled) { + rc =3D drm_dp_dpcd_write_byte(mst->dp_aux, esi_res, ack[1]); + if (rc < 0) { + DRM_ERROR("DPCD esi_res failed. rc=3D%d\n", rc); + return; + } + + drm_dp_mst_hpd_irq_send_new_request(&mst->mst_mgr); + } + drm_dbg_dp(dp_display->drm_dev, "MST display hpd_irq handled:%d rc:%d\n",= handled, rc); +} + static struct drm_encoder * msm_dp_mst_atomic_best_encoder(struct drm_connector *connector, struct drm= _atomic_commit *state) { @@ -441,8 +476,16 @@ msm_dp_mst_add_connector(struct drm_dp_mst_topology_mg= r *mgr, return NULL; } =20 +static void msm_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) +{ + struct msm_dp_mst *mst =3D container_of(mgr, struct msm_dp_mst, mst_mgr); + + msm_dp_mst_display_hpd_irq(mst->msm_dp); +} + static const struct drm_dp_mst_topology_cbs msm_dp_mst_drm_cbs =3D { .add_connector =3D msm_dp_mst_add_connector, + .poll_hpd_irq =3D msm_dp_mst_poll_hpd_irq, }; =20 int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 max_streams, struct= drm_dp_aux *drm_aux) @@ -471,6 +514,7 @@ int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 = max_streams, struct drm_d } =20 mutex_init(&mst->mst_lock); + mutex_init(&mst->hpd_irq_lock); dp_display->msm_dp_mst =3D mst; return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h index 89f73b1db2e7..8546214cbca1 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -10,5 +10,6 @@ int msm_dp_mst_mgr_init(struct msm_dp *dp_display, u32 max_streams, struct= drm_dp_aux *drm_aux); int msm_dp_mst_attach_encoder(struct msm_dp *dp_display, unsigned int stre= am_id, struct drm_encoder *encoder); +void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display); 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Hook the MST helpers into atomic_commit_setup() and atomic_commit_tail() to support non-blocking atomic commits for DisplayPort MST, and ensure MST commits properly wait for dependencies. For SST, non-blocking commits are already handled via commit_tail(), which waits for dependencies in the DRM core. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_atomic.c | 14 +++++++++++++- drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_kms.c | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_ato= mic.c index a8babf1dbe0d..e70e5088cfe5 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -4,6 +4,7 @@ * Author: Rob Clark */ =20 +#include #include #include =20 @@ -207,7 +208,11 @@ int msm_atomic_check(struct drm_device *dev, struct dr= m_atomic_commit *state) if (ret) return ret; =20 - return drm_atomic_helper_check(dev, state); + ret =3D drm_atomic_helper_check(dev, state); + if (ret) + return ret; + + return drm_dp_mst_atomic_check(state); } =20 void msm_atomic_commit_tail(struct drm_atomic_commit *state) @@ -221,6 +226,8 @@ void msm_atomic_commit_tail(struct drm_atomic_commit *s= tate) =20 trace_msm_atomic_commit_tail_start(async, crtc_mask); =20 + drm_dp_mst_atomic_wait_for_dependencies(state); + kms->funcs->enable_commit(kms); =20 /* @@ -322,3 +329,8 @@ void msm_atomic_commit_tail(struct drm_atomic_commit *s= tate) =20 trace_msm_atomic_commit_tail_finish(async, crtc_mask); } + +int msm_atomic_commit_setup(struct drm_atomic_commit *state) +{ + return drm_dp_mst_atomic_setup_commit(state); +} diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e9a7c9332707..fd0675797fd1 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -211,6 +211,7 @@ int msm_atomic_init_pending_timer(struct msm_pending_ti= mer *timer, struct msm_kms *kms, int crtc_idx); void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); void msm_atomic_commit_tail(struct drm_atomic_commit *state); +int msm_atomic_commit_setup(struct drm_atomic_commit *state); int msm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *sta= te); struct drm_atomic_commit *msm_atomic_state_alloc(struct drm_device *dev); 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In MST mode, connector detection is handled by MST bridges. Skip detection for the SST bridge when MST is active, matching the behavior of other DP MST implementations. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 22b925277462..f350c1d03b06 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -959,6 +959,10 @@ enum drm_connector_status msm_dp_bridge_detect(struct = drm_bridge *bridge, priv =3D container_of(dp, struct msm_dp_display_private, msm_dp_display); =20 guard(mutex)(&priv->plugged_lock); + + if (dp->mst_active) + return status; + ret =3D pm_runtime_resume_and_get(&dp->pdev->dev); if (ret) { DRM_ERROR("failed to pm_runtime_resume\n"); --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 988AB3CF202 for ; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.19.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:20:03 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:44 +0800 Subject: [PATCH v6 27/29] drm/msm/dp: enable MST on capable sinks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-27-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=6893; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=mcUALd6iaRGlrPJ5zk1Qq/kc9K8hnA46zdrjtFBolVA=; b=iH4w4T7aWISCno+nXOlT4cFopuM323XTtUezd1kX0b9gpLZLGstz3sFM85Ugw9lx2wEWOsCYs 6MxN7IGAVLDBCCpyECzyy1SW/XLRO2bRiLh82qMuwL/1LZKwT0wik5+ X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: tjQFWIP-nYcWa0sejviBb-qeVMcI5N3J X-Proofpoint-GUID: tjQFWIP-nYcWa0sejviBb-qeVMcI5N3J X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfXwtnKDVo+Xefs AuLnvI9DnHS+IDLI7GsBpfD9+mAaLwEw5oTDQHhst6d/K2w8p94QJBCw59h33bXQsUgsKxV40ls 8BEhw8HaehBa3yRjgm3PKtSJRLEGJlatntNZLm/MOzGpQNcpIXFx46ZdRUg6FV7hZWRC2hLlpA9 uElshUGur3nMT/IxrhHsjNZfzlsN1RLJJivP/uGi4620Sn3qewaIbfNREX0B3wWl71BWvLXXFxt 4F17JXwUbgCcKyWcRCdfM40KsZE5xnxX5Q7a5dyEtelX0iE3AI808ZBwYhNEHiH7a2jNeotdDrI VKfVkF62zuXcSnJUBIybP1o6+cfo+w+QnMuRUSLZ/RTQ+6FYB53YinTKRRswb9VIoYn7NHw7bzC 6lXaJzUYeb6UlC3LY2hqYU9zVl1jYxcdkZRtLwqfprRSqaxrtpJ8KNqnjIJRN51jVf1KBV4OyCo +OSwQmQgN7+uxkVlglg== X-Authority-Analysis: v=2.4 cv=S8/pBosP c=1 sm=1 tr=0 ts=6a953934 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=7j1SYuFnmNb8ZMggdUIA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX0N0a90WeRt2Z BebVH8S7HTOHPHpzuJG0GvntKwFV0PIjVS1l78oxuCaeQy8JzVMUnA9Afus8FkamfFXFEqtmkul sHuBYsVcz4tkDU2HrSnf2ypnhyWaMV0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar MST topology discovery requires the sink to operate in MST mode. Enable MST on sinks that advertise MST capability and are connected to a multi-stream capable DP controller. Once MST is enabled, downstream sink discovery and EDID retrieval are handled through the MST topology rather than the primary DP connector. Activate the MST topology manager on connect and disable it on disconnect to track the sink topology lifecycle. Snapshot the negotiated link parameters when MST is enabled so subsequent MST payload allocation can derive bandwidth information from a stable link configuration. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 59 ++++++++++++++++++++++++++++++++-= ---- drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ drivers/gpu/drm/msm/dp/dp_mst_drm.c | 18 +++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 1 + 4 files changed, 73 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index f350c1d03b06..dbc0e82d333a 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 #include "msm_drv.h" @@ -269,6 +270,29 @@ static int msm_dp_display_lttpr_init(struct msm_dp_dis= play_private *dp, u8 *dpcd return lttpr_count; } =20 +static void msm_dp_display_mst_enable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp =3D &dp->msm_dp_display; + int ret; + + /* Clear any pre-existing MST state before enabling MST. */ + ret =3D drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, 0); + if (ret < 0) { + DRM_ERROR("failed to clear DP_MSTM_CTRL, ret=3D%d\n", ret); + return; + } + + ret =3D drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); + if (ret < 0) { + DRM_ERROR("sink MST enablement failed\n"); + return; + } + + msm_dp->mst_active =3D true; + msm_dp_mst_display_set_mgr_state(msm_dp, true); +} + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *= dp) { struct drm_connector *connector =3D dp->msm_dp_display.connector; @@ -287,14 +311,17 @@ static int msm_dp_display_process_hpd_high(struct msm= _dp_display_private *dp) if (rc) goto end; =20 - drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); - drm_edid_connector_update(connector, drm_edid); + if (msm_dp_ctrl_get_stream_cnt(dp->ctrl) <=3D 1 || + !drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd)) { + drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); =20 - if (!drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(dp->aux)) - return -ETIMEDOUT; + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } } =20 msm_dp_link_process_request(dp->link); @@ -316,6 +343,10 @@ static int msm_dp_display_process_hpd_high(struct msm_= dp_display_private *dp) */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, false); =20 + if (msm_dp_ctrl_get_stream_cnt(dp->ctrl) > 1 && + drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd)) + msm_dp_display_mst_enable(dp); + msm_dp_link_reset_phy_params_vx_px(dp->link); =20 end: @@ -490,6 +521,11 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_disp= lay_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); =20 + if (dp->msm_dp_display.mst_active) { + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, false); + dp->msm_dp_display.mst_active =3D false; + } + /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); =20 @@ -566,6 +602,15 @@ struct msm_dp_panel *msm_dp_display_get_panel(struct m= sm_dp *msm_dp_display, return dp_panel; } =20 +void msm_dp_display_get_link_info(struct msm_dp *msm_dp_display, + struct msm_dp_link_info *link_info) +{ + struct msm_dp_display_private *dp =3D + container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_displ= ay); + + memcpy(link_info, &dp->panel->link_info, sizeof(*link_info)); +} + static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_privat= e *dp) { msm_dp_audio_put(dp->audio); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index ca2faf478c95..96b53d5b6090 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -65,4 +65,6 @@ int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_displ= ay); int msm_dp_mst_register(struct msm_dp *msm_dp_display); struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_displa= y, enum msm_dp_stream_id stream_id); +void msm_dp_display_get_link_info(struct msm_dp *msm_dp_display, + struct msm_dp_link_info *link_info); #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 2e625a7db981..b2905c894ce5 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -328,6 +328,24 @@ int msm_dp_mst_attach_encoder(struct msm_dp *dp_displa= y, unsigned int stream_id, return 0; } =20 +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) +{ + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + int rc; + + rc =3D drm_dp_mst_topology_mgr_set_mst(&mst->mst_mgr, state); + if (rc < 0) { + drm_err(dp_display->drm_dev, + "[MST] failed to set topology mgr state to %d rc:%d\n", state, rc); + } + + if (state) + msm_dp_display_get_link_info(dp_display, &mst->link_info); + + drm_dbg_kms(dp_display->drm_dev, "[MST] set_mgr_state state:%d\n", state); + return rc; +} + void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display) { int rc; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.20.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:20:07 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:45 +0800 Subject: [PATCH v6 28/29] drm/msm/dp: mark the SST bridge disconnected when an MST-capable sink is present Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-28-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=1360; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=FtG0OtAF0cEV+melS90shLLkD3JKef4yMUSpzTrvG9o=; b=MAsD4O/FZCIw+md7L0Mbc7jZOxHxc3x02AYpVe088cK6PBce079tY51MoNdgezu/eyHlnTIg3 CY1micG7rFhBNpDJk0ulGpI/QzDEfMaODS7egHsxGwNdPegiXikUJFt X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=DY0nbPtW c=1 sm=1 tr=0 ts=6a95393a cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=E_DJWZ853T03DlUWG8wA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX63QOIYf8a8Py iGj4Q6UvyLrxkqbL5cmfFhTiNhiw8JziEM2pIQ4CgrR+g6zvACbgCnniQSloVYcl9TEE/X57XjC L5BafAm/YuRZU3i2UHLzPeH99WL3LdOsrsMB89Vl07x1FJ8IohNVDtbTxiGqo7U6eRQg6z3SLMK QP0/+IgjCaZzOoXgqqCyXWo3213gHkhR2Et6xVBgWdL41uS1TdwTkidrexRPgaYCrGb04Xc3RIT z4waIedkdxf0OEUBp0lFAU/WqTFNUUdUBGiMcNYH1OmQ1bU8qg/HkHqvj25bU+vyU/ptPC63iQo Co1AlsAdptfUuvwmhtc4EjWaFP6DkyOs7EpRtfQ+I6i+VyvoDk/ME4lisoRokJdtnoFtF0RTx4J GcZPJA/Nukz+65sQLUK1m2f0jOWketcPHwGcTi68us6zVOh0yuo5MZI33jlYUuDIXypHmM5IeUy CR5b7AOD3ikMOrhdGVA== X-Proofpoint-ORIG-GUID: XKZ-Oly0OMC_mfRd0S-x5vhrHMAmKSfy X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfXycAU4YELNnNg cbPCPr2ShjchoQ00O+bhLlL5JrzSuCk2SJKBw0w1PE6ZcUl5EUKdiCMTZHSx8kdcH33dgJ/c83d xRWmy7o9gIW86RjocT2NfstJH/QbnvI= X-Proofpoint-GUID: XKZ-Oly0OMC_mfRd0S-x5vhrHMAmKSfy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 From: Abhinav Kumar When a DP cable is already attached at boot, msm_dp_bridge_detect() runs from the connector notify path before MST has been activated on the sink. The DPCD capability read at that point already indicates that the sink supports MST. Return connector_status_disconnected from the SST bridge whenever the controller supports multi-stream (stream_cnt > 1) and the sink reports MST capability, so that connector detection is handled by MST connectors instead of the SST bridge. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index dbc0e82d333a..d2b2c7141db0 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1052,6 +1052,10 @@ enum drm_connector_status msm_dp_bridge_detect(struc= t drm_bridge *bridge, status =3D connector_status_disconnected; } =20 + /* Mark SST connector as disconnected in DP boot-up case*/ + if (msm_dp_ctrl_get_stream_cnt(priv->ctrl) > 1 && drm_dp_read_mst_cap(pri= v->aux, dpcd)) + status =3D connector_status_disconnected; + end: /* * If we detected the DPRX, leave the controller on so that it doesn't --=20 2.43.0 From nobody Sat Sep 26 19:35:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA9B83DA5C1 for ; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93917236b86sm735974285a.13.2026.08.31.01.20.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 01:20:12 -0700 (PDT) From: Yongxing Mou Date: Mon, 31 Aug 2026 16:17:46 +0800 Subject: [PATCH v6 29/29] drm/msm/dp: mark the SST connector disconnected when MST is enabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-msm-dp-mst-v6-29-c91d35d6fb9e@oss.qualcomm.com> References: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> In-Reply-To: <20260831-msm-dp-mst-v6-0-c91d35d6fb9e@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788164246; l=1197; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=JnaNlH0Fbk6AgAHQMZ5A3xTfTA+9VjQZ/fVSomodQWI=; b=J9YDz4tmwpF2ajXWoB2k267qD9qlr4g1jmtUrDs/9cH/UAmGr5x9l1EQFiVH5Qp/TWMttKC70 8Ahed/E2IqQD2LAHoRSPDhQJmVpbtKnl+38TdGc0oachX+ye4FTkRtV X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: KkwVCoLdIEPMLn0OA5lY2VEqqTg7MxCr X-Proofpoint-ORIG-GUID: KkwVCoLdIEPMLn0OA5lY2VEqqTg7MxCr X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX0gyZda452fU+ KdeM6NoECa8NHQtBvnFzMLz+lliOnESB/oR7lyXIujuCuStG5WTVT4dI/mx2b1h1nr8VnHCZnjb mmFVG+TO0dLNi/RwT+gmyFtG536wcF4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MCBTYWx0ZWRfX2/J2LSt7e4w2 p6vuY/95tZ41R0H29StEM/QOYjvRYJ3kvssV5nFFSAER4333Y+DkWviEf1Q2n0IzQ04hPGVIR8g doaozXNLu975UgtlMnxprfL1Vofax9WwB0mfipUnqrjxWrhj7fJo9ZDNc0XNrvr6n2TfhhJG+8j HPuZreLNLcVCtzbCHUwEMiu48vIwbHILBdhzTk56EksHqURNz6LBOzU5+iX5Hhq8XjvnauIOB5R dGmgdIpmRlBM02WhfC44HkXzgLQWgnQBG/nE48sj1KE0UzccPyikI+wbb3sZ1yB7EDqMydrMuIy /M2+66xZFbxDBSARZXvjcDpOWrslJVLfxRTkmiiHEBhlHWXCumcL4ZYUkpGBT9YH2av5IjfQmCL HiG7bKvyRo3iFRIf4kq9/lkKQOrr4T3XMz2b1nWgnsjppuH4boZgqe+skfFonuCzO82AfP9i+7W rs3G98YUeKJJjDKJyPg== X-Authority-Analysis: v=2.4 cv=YKKvDxGx c=1 sm=1 tr=0 ts=6a95393d cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=VuhzylXr5gTqft-DN9kA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310070 When MST becomes active, the initial HPD plug notification updates the SST connector state to connected. However, the subsequent SST connector detect path reports disconnected while MST is enabled. This connected -> disconnected transition is then observed by the polling logic and may result in an unnecessary hotplug event. Set the SST connector state to disconnected immediately after MST is initialized so that the detect path does not introduce a transient state change. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index d2b2c7141db0..d207ec3ca8bf 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -290,6 +290,10 @@ static void msm_dp_display_mst_enable(struct msm_dp_di= splay_private *dp) } =20 msm_dp->mst_active =3D true; + + scoped_guard(mutex, &msm_dp->connector->dev->mode_config.mutex) + msm_dp->connector->status =3D connector_status_disconnected; + msm_dp_mst_display_set_mgr_state(msm_dp, true); } =20 --=20 2.43.0