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Mon, 31 Aug 2026 09:46:25 -0400 (EDT) From: Janne Grunau Date: Mon, 31 Aug 2026 15:46:08 +0200 Subject: [PATCH v2 1/2] dt-bindings: iommu: dart: Support specifying the DMA aperture Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-iommu-apple-dart-aperture-v2-1-d16ce3770299@jannau.net> References: <20260831-iommu-apple-dart-aperture-v2-0-d16ce3770299@jannau.net> In-Reply-To: <20260831-iommu-apple-dart-aperture-v2-0-d16ce3770299@jannau.net> To: Sven Peter , Neal Gompa , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2153; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=8Rv9OVc1AW97l/UiCVzPt+gRZOTmtkExTv7zaq6GYSo=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhqyprWtub7LOiK28Fp1ceuGM2+b9CXY6AjlaT34JLuSb5 K26ad75jlIWBjEuBlkxRZYk7ZcdDKtrFGNqH4TBzGFlAhnCwMUpABMR62b4799/j//EIikur0+d 2tcP8ch5JR0V0EgR+vvq+z7xMz8fLmFk6IybsIptVuTx5fw+c3ju9dUGByZ4ewdfaC+aYX3GNeo AMwA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Apple DARTs are often connected directly to devices that expect only a portion of their address space to be used for DMA (for example, because other ranges are mapped directly to something else). Follow the "#iommu-cells =3D <4>" example from iommu.txt and allow specifying the DMA aperture via additional cells. Since DART is used on 64-bit Apple silicon systems use two cells to specify the start and length of the aperture. A common aperture starts at 0x100_0000_0000 and spans a 36-bit address space. This corresponds to the vm-base and vm-size properties on the Apple device tree side of things. As not all devices require this and to keep compatibility with existing device trees allow 1 and 5 as values for #iommu-cells. Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/iommu/apple,dart.yaml | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Docu= mentation/devicetree/bindings/iommu/apple,dart.yaml index 47ec7fa52c3a..6efbe732b4ce 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -44,10 +44,12 @@ properties: Optional since not all IOMMUs are attached to a clock gate. =20 '#iommu-cells': - const: 1 + enum: [ 1, 5 ] description: - Has to be one. The single cell describes the stream id emitted by - a master to the IOMMU. + Has to be one or five. The first cell describes the stream id emitte= d by + a master to the IOMMU. The optional second and third cell describe t= he + aperture start of a master's DMA window and fourth and fifth cell de= scribe + the size of DMA window. =20 power-domains: maxItems: 1 @@ -66,11 +68,11 @@ examples: compatible =3D "apple,t8103-dart"; reg =3D <0x82f80000 0x4000>; interrupts =3D <1 781 4>; - #iommu-cells =3D <1>; + #iommu-cells =3D <5>; }; =20 master1 { - iommus =3D <&dart1 0>; + iommus =3D <&dart1 0 0x100 0x0 0x10 0x0>; }; =20 - |+ --=20 2.55.0 From nobody Sat Sep 26 14:40:51 2026 Received: from fhigh-a6-smtp.messagingengine.com (fhigh-a6-smtp.messagingengine.com [103.168.172.157]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A00D354B1B7; Mon, 31 Aug 2026 13:46:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.157 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788183995; cv=none; b=nCTQ/RTtWKKiGYAhhzhFBEJsNlmv7bMbPMXMNNAEJTR44aUcf7hwYUkE8voYxc5TrSUxkCEgr4jbcQt2LVbSU93UtvAMU+6CINjl51sbU+7C5qQD6sVIilnlTHXbkPAB8+32YWOS9y6mjxag88DrXajU6aCsBjAbLkHZJYB3+ro= ARC-Message-Signature: i=1; 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Mon, 31 Aug 2026 09:46:27 -0400 (EDT) From: Janne Grunau Date: Mon, 31 Aug 2026 15:46:09 +0200 Subject: [PATCH v2 2/2] iommu: apple-dart: Support specifying the DMA aperture in the DT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-iommu-apple-dart-aperture-v2-2-d16ce3770299@jannau.net> References: <20260831-iommu-apple-dart-aperture-v2-0-d16ce3770299@jannau.net> In-Reply-To: <20260831-iommu-apple-dart-aperture-v2-0-d16ce3770299@jannau.net> To: Sven Peter , Neal Gompa , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Hector Martin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6603; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=W0l5gsiaGlNx1eXeXcuBJF6lf9NaAtRUFj6LLSrbp68=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhqyprWt+xfOdeLD/yZY/nJrP8+SblGY6Vml9Zbb9fKl4m tpdqWk7OkpZGMS4GGTFFFmStF92MKyuUYypfRAGM4eVCWQIAxenAExk2VNGhlOL/0a73Vw6r545 1rdW4NfK1CsaTxbNjPx7w9x136dvdcIM/zQLw6b9Uz63/afdFp7P+5v/aXy+/zPFwLApZY3U6Yf 3pdkB X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Apple DARTs are often connected directly to devices that expect only a portion of their address space to be used for DMA (for example, because other ranges are mapped directly to something else). Devices can specify the start and end of the aperture via "iommus" args if the DART device node specifies "#iommu-cells =3D <5>. Aperture start and length are 64-bit values as apertures above and larger than 4GB are used. Limit compile testing to 64-bit architectures to avoid warnings in the calculation of 64-bit dma_addr_t values. This range *can* be outside of the DART's IAS. In that case, it is assumed that the hardware truncates addresses and the page tables will only map the lower bits of the address. However, the specified range cannot straddle an IAS boundary (you cannot cover more than IAS worth of address space nor wrap). This corresponds to the vm-base and vm-size properties on the Apple device tree side of things. Co-developed-by: Hector Martin Signed-off-by: Hector Martin Signed-off-by: Janne Grunau Reviewed-by: Sven Peter --- drivers/iommu/apple-dart.c | 74 ++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 65 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index b160fb464c5f..ebf4547d32b4 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -267,6 +268,7 @@ struct apple_dart_domain { struct io_pgtable_ops *pgtbl_ops; =20 bool finalized; + u64 mask; struct mutex init_lock; struct apple_dart_atomic_stream_map stream_maps[MAX_DARTS_PER_DEVICE]; =20 @@ -285,6 +287,13 @@ struct apple_dart_master_cfg { /* Intersection of DART capabilitles */ u32 supports_bypass : 1; =20 + /* + * DMA aperture start and end to be overridden by "iommus"' phandle + * args. By default determined by DART's ias but may be outside of it. + */ + dma_addr_t dma_min; + dma_addr_t dma_max; + struct apple_dart_stream_map stream_maps[MAX_DARTS_PER_DEVICE]; }; =20 @@ -537,7 +546,7 @@ static phys_addr_t apple_dart_iova_to_phys(struct iommu= _domain *domain, if (!ops) return 0; =20 - return ops->iova_to_phys(ops, iova); + return ops->iova_to_phys(ops, iova & dart_domain->mask); } =20 static int apple_dart_map_pages(struct iommu_domain *domain, unsigned long= iova, @@ -551,8 +560,8 @@ static int apple_dart_map_pages(struct iommu_domain *do= main, unsigned long iova, if (!ops) return -ENODEV; =20 - return ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, gfp, - mapped); + return ops->map_pages(ops, iova & dart_domain->mask, paddr, pgsize, + pgcount, prot, gfp, mapped); } =20 static size_t apple_dart_unmap_pages(struct iommu_domain *domain, @@ -563,7 +572,8 @@ static size_t apple_dart_unmap_pages(struct iommu_domai= n *domain, struct apple_dart_domain *dart_domain =3D to_dart_domain(domain); struct io_pgtable_ops *ops =3D dart_domain->pgtbl_ops; =20 - return ops->unmap_pages(ops, iova, pgsize, pgcount, gather); + return ops->unmap_pages(ops, iova & dart_domain->mask, pgsize, pgcount, + gather); } =20 static void @@ -590,6 +600,7 @@ static int apple_dart_finalize_domain(struct apple_dart= _domain *dart_domain, { struct apple_dart *dart =3D cfg->stream_maps[0].dart; struct io_pgtable_cfg pgtbl_cfg; + u32 ias =3D min_t(u32, dart->ias, fls64(cfg->dma_max)); int ret =3D 0; int i, j; =20 @@ -610,7 +621,7 @@ static int apple_dart_finalize_domain(struct apple_dart= _domain *dart_domain, =20 pgtbl_cfg =3D (struct io_pgtable_cfg){ .pgsize_bitmap =3D dart->pgsize, - .ias =3D dart->ias, + .ias =3D ias, .oas =3D dart->oas, .coherent_walk =3D 1, .iommu_dev =3D dart->dev, @@ -623,10 +634,10 @@ static int apple_dart_finalize_domain(struct apple_da= rt_domain *dart_domain, goto done; } =20 + dart_domain->mask =3D DMA_BIT_MASK(pgtbl_cfg.ias); dart_domain->domain.pgsize_bitmap =3D pgtbl_cfg.pgsize_bitmap; - dart_domain->domain.geometry.aperture_start =3D 0; - dart_domain->domain.geometry.aperture_end =3D - (dma_addr_t)DMA_BIT_MASK(pgtbl_cfg.ias); + dart_domain->domain.geometry.aperture_start =3D cfg->dma_min; + dart_domain->domain.geometry.aperture_end =3D cfg->dma_max; dart_domain->domain.geometry.force_aperture =3D true; =20 dart_domain->finalized =3D true; @@ -803,20 +814,65 @@ static int apple_dart_of_xlate(struct device *dev, struct platform_device *iommu_pdev =3D of_find_device_by_node(args->np); struct apple_dart *dart =3D platform_get_drvdata(iommu_pdev); struct apple_dart *cfg_dart; + dma_addr_t dma_max =3D DMA_BIT_MASK(dart->ias); + dma_addr_t dma_min =3D 0; int i, sid; =20 put_device(&iommu_pdev->dev); =20 - if (args->args_count !=3D 1) + if (args->args_count !=3D 1 && args->args_count !=3D 5) return -EINVAL; + sid =3D args->args[0]; =20 + if (args->args_count =3D=3D 5) { + dma_addr_t length =3D ((dma_addr_t)args->args[3] << 32) | args->args[4]; + + if (!length) + return -EINVAL; + + dma_min =3D ((dma_addr_t)args->args[1] << 32) | args->args[2]; + + if (!IS_ALIGNED(dma_min, dart->pgsize) || + !IS_ALIGNED(length, dart->pgsize)) { + dev_err(dev, "Unaligned DMA window %pad, %pad (0x%x)\n", + &dma_min, &length, dart->pgsize); + return -EINVAL; + } + if (check_add_overflow(dma_min, length - 1, &dma_max)) { + dev_err(dev, "DMA window length (%pad) overflows range for start %pad\n= ", + &length, &dma_min); + return -EINVAL; + } + + /* + * Ensure that the DMA window does not exceed the DART's ias. + */ + if ((dma_min ^ dma_max) & ~DMA_BIT_MASK(dart->ias)) { + dev_err(dev, "Invalid DMA window for ias=3D%d\n", + dart->ias); + return -EINVAL; + } + } + if (!cfg) { cfg =3D kzalloc_obj(*cfg); if (!cfg) return -ENOMEM; /* Will be ANDed with DART capabilities */ cfg->supports_bypass =3D true; + /* Will be merged with other DARTs to the common range. */ + cfg->dma_min =3D dma_min; + cfg->dma_max =3D dma_max; + } else { + if (dma_min >=3D cfg->dma_max || cfg->dma_min >=3D dma_max) { + dev_err(dev, "non-overlapping DMA windows: %pad..%pad, %pad..%pad\n", + &dma_min, &dma_max, + &cfg->dma_min, &cfg->dma_max); + return -EINVAL; + } + cfg->dma_min =3D max(dma_min, cfg->dma_min); + cfg->dma_max =3D min(dma_max, cfg->dma_max); } dev_iommu_priv_set(dev, cfg); =20 --=20 2.55.0