From nobody Sat Sep 26 19:35:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A08983BD659; Mon, 31 Aug 2026 06:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788159132; cv=none; b=XyCpwuRPY220nJ8hJqjwk98T6RoTMLgga06Xf4ycRqG4EBF8byP/nP+vC9f5NPtjyri+AB46iBBtrWQPseSV8oD6jIsAQkdcQm2xWARq8bhsYeupTp0YYsxHzAd28QOX5KWF9rUUPGXlN7mZVfz4CGUkcnsgNb6lJ49C1WihC28= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788159132; c=relaxed/simple; bh=qMmsDNh6HE/JXh1j0Z6LUrZIrSkIc8Sgl8/m315HZEI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nwJlvhasY/QYTuBIWTJ4UKxx3b+NHNpJFgOIQgAtVJzULj0lbLGjjQqs0AhwrWmIGzH81TZBxigsP2TdJudXmQaJy+M+qdVx/Vemwn54sC7NL0QTqQMwkEIu9tnNetrPK4pSno3cT6nMrii27SQOkMgcxeypwDfsoCwSD94iPe4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PRrjnjTQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PRrjnjTQ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0337BC2BCF4; Mon, 31 Aug 2026 06:52:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788159131; bh=qMmsDNh6HE/JXh1j0Z6LUrZIrSkIc8Sgl8/m315HZEI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PRrjnjTQ0gmGnSF9CISiNkhi9sxOiG4x6A8RBhyNcsgRYvF3dxNqSomdA19ocHgId nQhjuMARfVNOySevWpgmfgPVGa+gRfxZqvEnTsCJ83rk54XbnBo4EXMfe7Bg2FvrTl vy2ejKyQcmhr37GlcIGbrtmWH0u/pQ4vm4kMmB0XCmvT/1eYZOptBpHpVGDWOJQDfn jU9zPBThACiaUXM10PgtzCvs/1/i0BslUIuk78gMrz0SG0S4MzlLz8YuVEjOIEpg+e jCbq9+Z+h9y61e6tM1iYZ6tOwF2qGVNXAXvi735s7e6TaMum98+LHmRhn2/YhpzVYm WyQDy7kPwGnTQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE4A1C61DD3; Mon, 31 Aug 2026 06:52:10 +0000 (UTC) From: Congcong Yao via B4 Relay Date: Mon, 31 Aug 2026 14:52:06 +0800 Subject: [PATCH v4 1/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260831-8189-smi-support-v4-1-8ae66dd3eeed@mediatek.com> References: <20260831-8189-smi-support-v4-0-8ae66dd3eeed@mediatek.com> In-Reply-To: <20260831-8189-smi-support-v4-0-8ae66dd3eeed@mediatek.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Congcong Yao , Zhengnan Chen X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788159129; l=4285; i=congcong.yao@mediatek.com; s=20260722; h=from:subject:message-id; bh=ZF8KkSLsu9zOPR4yaUhFcqIyHzmeP14MmlF5WXU/Mkg=; b=w6tfEJj1nGx+w3aW53I4RyfZzi8umc3Td7D9o1Y6YQHDeHdqJubX3vaGIgAmy9Dh5dBMIMxbB pO8Ok1iYfGKCUOC37ZrtK1ChYIzqbXUXBjTtYwYuhx1pYG++/8MR9dx X-Developer-Key: i=congcong.yao@mediatek.com; a=ed25519; pk=tIrmGxKQQxnfyb48iCCd19063tppPj89U3nupGYAIxg= X-Endpoint-Received: by B4 Relay for congcong.yao@mediatek.com/20260722 with auth_id=889 X-Original-From: Congcong Yao Reply-To: congcong.yao@mediatek.com From: Zhengnan Chen Add the SMI LARB, common and sub-common binding descriptions for MT8189. MT8189 adds an SMI sub-common block. Document this topology in mediatek,smi-common.yaml. Signed-off-by: Zhengnan Chen Signed-off-by: Congcong Yao Acked-by: Krzysztof Kozlowski --- .../memory-controllers/mediatek,smi-common.yaml | 21 +++++++++++++++++= +++- .../memory-controllers/mediatek,smi-larb.yaml | 3 +++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/medi= atek,smi-common.yaml index 0762e0ff66ef..33c989f7fc33 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml @@ -16,7 +16,7 @@ description: | MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt= 8192 and mt8195. + generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt= 8189, mt8192 and mt8195. =20 There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. B= ut @@ -25,6 +25,21 @@ description: | SMI generation 1 to transform the smi clock into emi clock domain, but t= hat is not needed for SMI generation 2. =20 + The smi-common connects with smi-larb and IOMMU. The maximum inputs numb= er of + a smi-common is 8. In SMI generation 2, the engines number may be over 8. + In this case, we use a smi-sub-common to merge some larbs. + The block diagram something is like: + + IOMMU + | | + smi-common + --------------------------- + | | ... + larb0 sub-common ... <-max number is 8 + ---------------- + | | ... + larb1 larbX ... <-max number is 8 + properties: compatible: oneOf: @@ -40,6 +55,8 @@ properties: - mediatek,mt8186-smi-common - mediatek,mt8188-smi-common-vdo - mediatek,mt8188-smi-common-vpp + - mediatek,mt8189-smi-common + - mediatek,mt8189-smi-sub-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -108,6 +125,7 @@ allOf: compatible: contains: enum: + - mediatek,mt8189-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: @@ -157,6 +175,7 @@ allOf: - mediatek,mt6795-smi-common - mediatek,mt8167-smi-common - mediatek,mt8173-smi-common + - mediatek,mt8189-smi-common =20 then: properties: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediat= ek,smi-larb.yaml index 2e7fac4b5094..9a5dafd7c07e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-lar= b.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-lar= b.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb =20 @@ -85,6 +86,7 @@ allOf: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8195-smi-larb =20 then: @@ -119,6 +121,7 @@ allOf: - mediatek,mt6779-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb =20 --=20 2.43.0 From nobody Sat Sep 26 19:35:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D52E3ACA7C; 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Enable the GALS clock for the MT8189 SMI sub-common. Signed-off-by: Zhengnan Chen Signed-off-by: Congcong Yao Reviewed-by: Yong Wu --- drivers/memory/mtk-smi.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index aaeba8ab211e..8c4606cbd73d 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -401,6 +401,30 @@ static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PO= RT_NR_MAX] =3D { [25] =3D {0x01}, }; =20 +static const u8 mtk_smi_larb_mt8189_ostd[][SMI_LARB_PORT_NR_MAX] =3D { + [0] =3D {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10,}, + [1] =3D {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10,}, + [2] =3D {0x7, 0x7, 0x4, 0x4, 0x1, 0x1, 0x2, 0x2, 0x7, 0x7,}, + [4] =3D {0x2f, 0x1e, 0x9, 0x1, 0x1, 0x1, 0x1, 0x2, 0x2, 0x5, 0x1, 0x17,}, + [7] =3D {0x20, 0x2, 0x1, 0x1, 0x1, 0x4, 0x2, 0x1, 0x1, 0x2, 0x3, 0x2, + 0xa, 0xf, 0x4, 0x6, 0x5, 0x1,}, + [9] =3D {0x6, 0x3, 0xc, 0x6, 0x1, 0x4, 0x3, 0x1, 0x2, 0x4, 0x5, 0x2, + 0x4, 0x2, 0x3, 0xb, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1,}, + [11] =3D {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1, 0x1, 0xb, 0x1, 0x4, 0x6, 0x5, 0x6, 0x1, 0x5, 0x2, + 0x9, 0x5,}, + [13] =3D {0x2, 0x8, 0x8, 0x8, 0x4, 0x4, 0x4, 0x4, 0x4, 0xe, 0x4, 0x1, + 0x6, 0x6, 0x2,}, + [14] =3D {0x1, 0x1, 0x1, 0x20, 0xe, 0x4, 0x8, 0x8, 0x6, 0x4,}, + [16] =3D {0x1e, 0xc, 0x2, 0x8, 0xe, 0x2, 0x1e, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [17] =3D {0x1e, 0xc, 0x2, 0x8, 0xe, 0x2, 0x1e, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [19] =3D {0x2, 0x1, 0x3, 0x1,}, + [20] =3D {0x7, 0x7, 0x3, 0x3, 0x1, 0x1,}, +}; + static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] =3D { [0] =3D {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,}, [1] =3D {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,}, @@ -533,6 +557,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt81= 88 =3D { .ostd =3D mtk_smi_larb_mt8188_ostd, }; =20 +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8189 =3D { + .config_port =3D mtk_smi_larb_config_port_gen2_general, + .flags_general =3D MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW= _FLAG | + MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, + .ostd =3D mtk_smi_larb_mt8189_ostd, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 =3D { .config_port =3D mtk_smi_larb_config_port_gen2_general, .ostd =3D mtk_smi_larb_mt8192_ostd, @@ -556,6 +587,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = =3D { {.compatible =3D "mediatek,mt8183-smi-larb", .data =3D &mtk_smi_larb_mt81= 83}, {.compatible =3D "mediatek,mt8186-smi-larb", .data =3D &mtk_smi_larb_mt81= 86}, {.compatible =3D "mediatek,mt8188-smi-larb", .data =3D &mtk_smi_larb_mt81= 88}, + {.compatible =3D "mediatek,mt8189-smi-larb", .data =3D &mtk_smi_larb_mt81= 89}, {.compatible =3D "mediatek,mt8192-smi-larb", .data =3D &mtk_smi_larb_mt81= 92}, {.compatible =3D "mediatek,mt8195-smi-larb", .data =3D &mtk_smi_larb_mt81= 95}, {} @@ -808,6 +840,17 @@ static const struct mtk_smi_common_plat mtk_smi_common= _mt8188_vpp =3D { .init =3D mtk_smi_common_mt8195_init, }; =20 +static const struct mtk_smi_common_plat mtk_smi_common_mt8189 =3D { + .type =3D MTK_SMI_GEN2, + .bus_sel =3D F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | + F_MMU1_LARB(7), +}; + +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8189 =3D { + .type =3D MTK_SMI_GEN2_SUB_COMM, + .has_gals =3D true, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 =3D { .type =3D MTK_SMI_GEN2, .has_gals =3D true, @@ -852,6 +895,8 @@ static const struct of_device_id mtk_smi_common_of_ids[= ] =3D { {.compatible =3D "mediatek,mt8186-smi-common", .data =3D &mtk_smi_common_= mt8186}, {.compatible =3D "mediatek,mt8188-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8188_vdo}, {.compatible =3D "mediatek,mt8188-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8188_vpp}, + {.compatible =3D "mediatek,mt8189-smi-common", .data =3D &mtk_smi_com= mon_mt8189}, + {.compatible =3D "mediatek,mt8189-smi-sub-common", .data =3D &mtk_smi_sub= _common_mt8189}, {.compatible =3D "mediatek,mt8192-smi-common", .data =3D &mtk_smi_common_= mt8192}, {.compatible =3D "mediatek,mt8195-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8195_vdo}, {.compatible =3D "mediatek,mt8195-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8195_vpp}, --=20 2.43.0