From nobody Sat Sep 26 20:31:24 2026 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41D113BA246; Sun, 30 Aug 2026 16:17:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788106683; cv=none; b=KRFvVPGRj6pBgmUSIM1RIDcKTa3PnQVUoeiSrDNnDTXp9u2fuQna12n8ZJpbNRRGmIS+ynO23SwFK8OiBYb6FhIlfA5F9ah1fxKOhj2xnhuMvK4oo6RW/o/Y6K0IaMwfq3FfbmBr9M3p5puXaMd/eSCr4aRHB34W3tWuK93aEZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788106683; c=relaxed/simple; bh=S6ALsO99Mf8b4MLFFIHQIICD0ef6Ggwu0gNDps+5sOk=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=er+jc34NWjzcoizBsIZz8oGGwbCYKG5CFLKzDEUjx6w0/pBMkIT9roB+xYfahgDFu41vZEM2KbvkAQLj+wLi41tgDFOC5AMEwpK9wq2jb83rMCrggJtRTykRMPVTDaiyriRtLrokW8IfNRflyNi++KaVtFHgBCKL/QBz5/bBw28= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=seu.edu.cn; spf=pass smtp.mailfrom=seu.edu.cn; dkim=pass (1024-bit key) header.d=seu.edu.cn header.i=@seu.edu.cn header.b=C6adnRX8; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=seu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=seu.edu.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=seu.edu.cn header.i=@seu.edu.cn header.b="C6adnRX8" Received: from PC-202605011814.localdomain (unknown [58.241.16.34]) by smtp.qiye.163.com (Hmail) with ESMTP id 4bd7e97c7; Mon, 31 Aug 2026 00:17:54 +0800 (GMT+08:00) From: Runyu Xiao To: Dipen Patel , Thierry Reding , Jonathan Hunter Cc: timestamp@lists.linux.dev, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, runyu.xiao@seu.edu.cn, jianhao.xu@seu.edu.cn, stable@vger.kernel.org Subject: [PATCH] hte: tegra194: Initialize slice locks before registering chip Date: Mon, 31 Aug 2026 00:17:47 +0800 Message-Id: <20260830161747.2719220-1-runyu.xiao@seu.edu.cn> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0aa05376928703a1kunmb280507910715e X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlDSU1LVhlPGB5LTBodHh4ZSVYeHw 5VEwETFhoSFyQUDg9ZV1kYEgtZQVlOQ1VJT0pVSk1VSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpPSE xVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=C6adnRX8KIlM01g51zYlO58R1tJ0paYcKBbJRkU5m8eyH/dDIohFCii/CGeEnjXBDSu7Wkk+rucYsqYm4wggBz7x8rHeH17KpOztjUrFAqS2VZAI0hzkuj2Kb8IT7SfiibPRaNYV0SIG7qUNvKgHx16d9K/gh1ZAsvR2xgBE6q4=; s=default; c=relaxed/relaxed; d=seu.edu.cn; v=1; bh=+bGYSb5ANbtpow/T618bsKBQwWGrOFAzrHSouwdqQFY=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Registering the HTE chip publishes its request callbacks to consumers. Initialize every slice lock before registration so a concurrent HTE request cannot use an uninitialized lock. Signed-off-by: Runyu Xiao Fixes: 09574cca6ad6 ("hte: Add Tegra194 HTE kernel provider") Cc: stable@vger.kernel.org Acked-by: Dipen Patel --- drivers/hte/hte-tegra194.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 4a7702b32..1612812ab 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -910,17 +910,17 @@ static int tegra_hte_probe(struct platform_device *pd= ev) =20 hte_dev->chip =3D gc; =20 + for (i =3D 0; i < slices; i++) { + hte_dev->sl[i].flags =3D 0; + spin_lock_init(&hte_dev->sl[i].s_lock); + } + ret =3D devm_hte_register_chip(hte_dev->chip); if (ret) { dev_err(gc->dev, "hte chip register failed"); return ret; } =20 - for (i =3D 0; i < slices; i++) { - hte_dev->sl[i].flags =3D 0; - spin_lock_init(&hte_dev->sl[i].s_lock); - } - val =3D HTE_TECTRL_ENABLE_ENABLE | (HTE_TECTRL_INTR_ENABLE << HTE_TECTRL_INTR_SHIFT) | (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); --=20 2.34.1