From nobody Sat Sep 26 21:59:57 2026 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA99C3B4EB6 for ; Sat, 29 Aug 2026 17:05:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023158; cv=none; b=UqiAIiGOjk02FamVsg9vz+Ctuf50RyhGg5TTC2ZoHS/IF78Pmw8CAuY7Ceq3rZ503pjf/fhvllz2Qxw9d4dl+RD46D2oXWo6fez9183olocNLOd1bImdBNlTqYtime/WAPuLHOL9B153V0MSRwVYceJQsBVPE5+TjViqM2DxmyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023158; c=relaxed/simple; bh=EwN2Ufrk3JZ1LOcr39JKvze/sQpqpgu7i1kuyfgBogA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sTxicxPT54FfEIAHtqFLzYP+kvKrxKF9rGscwgQKKYPovybwvXYx23bUYMxC/t/LWyQll8gCTkfvbQiP/ZlMWD637Cq/ZnLy7sG4inV6uoxsotnSUl7qQ3pB4EEifNR8St0DbVGbos0/GZTJTTuPCBtIVL6dh+iZ6ieRsZ6QyeY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IAYjA0Lu; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IAYjA0Lu" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-c25344a8c6cso257461766b.0 for ; Sat, 29 Aug 2026 10:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788023152; x=1788627952; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=W+xOVsFk+EtrsGYFgTGdtYSvPsI3GoZT83F/GKM9fnU=; b=IAYjA0Luub0LcHKgk7TP/vrW9Vxz3HDMFu9CHhnhyO/WMFVWLAriNt3Gljqc8Qq6R+ E4mBkWbl/zea+FA37ZVPKZctWAUrsXTGrO++/zWGTsKtGw2O+XXh8pOMQa7aD6lIbhFf NJ4Wg19igUzLlVPbgTV77mkLAx1PAUEe7RCuvy8UmjcsY+wffomUD9FyFet7JkJJzsfR 8oMZeyxBG5amkF3aJF6iYAA7zoWCXuXIzN3aCHiMB/+jiogYohT8fLL6Fgky0M1jg64k OhgWlC9v3Xwv8l2C295ZbPzdsCMP+nif/QUkdK3Yr4oAcIn2iK1xb2UbR7gY7T2HOpqW demA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788023152; x=1788627952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=W+xOVsFk+EtrsGYFgTGdtYSvPsI3GoZT83F/GKM9fnU=; b=i6/8rtsRdwy7Jg0Hj08UlRMDuWmasPd8anMmWxxjdnrQjiVP2NLKTWMQWN7rmy/Ndq h5O5QGJqIJL4StGGOAaELgPG0Y2bFVXfkEXkO/x0yC90/okKkfhD6JTLPZsR94Y1UgOz PSKLq9rkEONbk4AMKUqZcscG7jMkEKiFLPM+UvScmtIfyDw4vjo+vYhkK/oiz45NSDAG 9c/f99SKGaEtQwjkk14Y+yt4gwqKv31ymVIJef1/WsvrcFf76uoZ1vjaQpXwJF2GfWra pNzuZborDcpp57O8ZCGrcaUTR1l8xyoAyVd4aEDn0nVeYBK8yYSVvm2IeRDE7klrXcuE Nk8w== X-Forwarded-Encrypted: i=1; AHgh+RqC9BUIUAG3rNJA7iW/gjs7L5rEh3i4JvW4F/iODctxMT0f3XVMDvuVzuM8H8j9dU+X7iO7FwUMK4v7m/Y=@vger.kernel.org X-Gm-Message-State: AFuF++mFYuew40ZInMFra9Yqq4gbQcN8ZFa7PU/CHI7Phw17al243xM+ LN9moBhRTUfyl030xbJlWNNo4euj7zDKCFBrCM2dD+lQc14yMEIJEyLy X-Gm-Gg: AR+sD10ec5Drp009nb9vhpIbgm/Tcz9QhFcqRzOf0fpvmyy4q0CflqjYmUdhLOjsfQs hexVvkvPSeNKLnZf5v+2pQeO9SzlrqWqBjXvaugQ5pYhbZyayJzMgNKDJUCxLO+l+ujGULdKNqz rLYTKGbbqKMe+5rAdIE1Zu806eNhYzMK2uh/G1SThLcXV0mgJqhJX7OK8clm38WeABxQoKelTaZ Is+jOA2Ww6+59+ZamtwNknJKXJU6/AoIJgt1rTCY7r1EFKZcyYTJ6kPjLldSWCx3f79ujLfpsbh Fu16g316mneFeKWj0O/woWtgx4ORkpTMh4XXPK1Yo4Q/AR7rXgb5pGBCegl57SCneBcmN5EsAyH OHLauSCOouVq3ZBp9z1WFTLAzWkhADJ1Iae//S9mD7PaAnBNZ7c+4kY5j7kdKVALLTEaV/Sxv1h N4xzekq8F1DQNZHvKzZRQXBHgDSTvO0N2j7OvUWF4OZqda+qk+LM35u73a4Q1yrzoeaSPRmLi+E sqyw3UQ0Xvpeoo7 X-Received: by 2002:a17:907:e1c4:20b0:c25:33db:939e with SMTP id a640c23a62f3a-c2556be4184mr773861266b.4.1788023151911; Sat, 29 Aug 2026 10:05:51 -0700 (PDT) Received: from localhost ([2603:5004:20a0:100c:cf7b:6b6c:bc26:7dfa]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255f29a9dfsm222290266b.63.2026.08.29.10.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Aug 2026 10:05:51 -0700 (PDT) From: Jerome Tollet To: Jean Delvare , Guenter Roeck Cc: linux-hwmon@vger.kernel.org, Benoit Masson , Jonathan Corbet , Shuah Khan , Randy Dunlap , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Tollet Subject: [PATCH v5 1/4] hwmon: it87: describe per-chip temperature resources Date: Sat, 29 Aug 2026 19:05:42 +0200 Message-ID: <20260829170545.33401-2-jerome.tollet@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260829170545.33401-1-jerome.tollet@gmail.com> References: <20260829170545.33401-1-jerome.tollet@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "benoit.masson" Add per-chip temp limit/offset/map counts and wire the driver to use them. This keeps existing chips on the previous defaults while allowing newer chips to advertise larger resources. Signed-off-by: benoit.masson Signed-off-by: Jerome Tollet --- drivers/hwmon/it87.c | 151 ++++++++++++++++++++++++++++++++----------- 1 file changed, 114 insertions(+), 37 deletions(-) diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 87edb1b60..1c77f6c97 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -247,7 +247,7 @@ static const u8 IT87_REG_FAN[] =3D { 0x0d, 0x0e= , 0x0f, 0x80, 0x82, 0x4c }; static const u8 IT87_REG_FAN_MIN[] =3D { 0x10, 0x11, 0x12, 0x84, 0x86,= 0x4e }; static const u8 IT87_REG_FANX[] =3D { 0x18, 0x19, 0x1a, 0x81, 0x83,= 0x4d }; static const u8 IT87_REG_FANX_MIN[] =3D { 0x1b, 0x1c, 0x1d, 0x85, 0x87,= 0x4f }; -static const u8 IT87_REG_TEMP_OFFSET[] =3D { 0x56, 0x57, 0x59 }; +static const u8 IT87_REG_TEMP_OFFSET[] =3D { 0x56, 0x57, 0x59, 0x5a, 0x90,= 0x91 }; =20 #define IT87_REG_FAN_MAIN_CTRL 0x13 #define IT87_REG_FAN_CTL 0x14 @@ -282,7 +282,6 @@ static const u8 IT87_REG_AUTO_BASE[] =3D { 0x60, 0x68, = 0x70, 0x78, 0xa0, 0xa8 }; #define NUM_VIN_LIMIT 8 #define NUM_TEMP 6 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) -#define NUM_TEMP_LIMIT 3 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) #define NUM_FAN_DIV 3 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) @@ -292,6 +291,9 @@ struct it87_devices { const char *name; const char * const model; u32 features; + u8 num_temp_limit; + u8 num_temp_offset; + u8 num_temp_map; u8 peci_mask; u8 old_peci_mask; u8 smbus_bitmap; /* SMBus enable bits in extra config register */ @@ -302,7 +304,6 @@ struct it87_devices { #define FEAT_NEWER_AUTOPWM BIT(1) #define FEAT_OLD_AUTOPWM BIT(2) #define FEAT_16BIT_FANS BIT(3) -#define FEAT_TEMP_OFFSET BIT(4) #define FEAT_TEMP_PECI BIT(5) #define FEAT_TEMP_OLD_PECI BIT(6) #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ @@ -335,43 +336,61 @@ static const struct it87_devices it87_devices[] =3D { .model =3D "IT87F", .features =3D FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF, /* may need to overwrite */ + .num_temp_limit =3D 3, + .num_temp_offset =3D 0, + .num_temp_map =3D 3, }, [it8712] =3D { .name =3D "it8712", .model =3D "IT8712F", .features =3D FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF, /* may need to overwrite */ + .num_temp_limit =3D 3, + .num_temp_offset =3D 0, + .num_temp_map =3D 3, }, [it8716] =3D { .name =3D "it8716", .model =3D "IT8716F", - .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID + .features =3D FEAT_16BIT_FANS | FEAT_VID | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, }, [it8718] =3D { .name =3D "it8718", .model =3D "IT8718F", - .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID + .features =3D FEAT_16BIT_FANS | FEAT_VID | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .old_peci_mask =3D 0x4, }, [it8720] =3D { .name =3D "it8720", .model =3D "IT8720F", - .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID + .features =3D FEAT_16BIT_FANS | FEAT_VID | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .old_peci_mask =3D 0x4, }, [it8721] =3D { .name =3D "it8721", .model =3D "IT8721F", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x05, .old_peci_mask =3D 0x02, /* Actually reports PCH */ }, @@ -379,18 +398,24 @@ static const struct it87_devices it87_devices[] =3D { .name =3D "it8728", .model =3D "IT8728F", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS + | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 6, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, }, [it8732] =3D { .name =3D "it8732", .model =3D "IT8732F", .features =3D FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, .old_peci_mask =3D 0x02, /* Actually reports PCH */ }, @@ -398,73 +423,97 @@ static const struct it87_devices it87_devices[] =3D { .name =3D "it8771", .model =3D "IT8771E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, /* PECI: guesswork */ /* 12mV ADC (OHM) */ /* 16 bit fans (OHM) */ /* three fans, always 16 bit (guesswork) */ + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, }, [it8772] =3D { .name =3D "it8772", .model =3D "IT8772E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, /* PECI (coreboot) */ /* 12mV ADC (HWSensors4, OHM) */ /* 16 bit fans (HWSensors4, OHM) */ /* three fans, always 16 bit (datasheet) */ + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, }, [it8781] =3D { .name =3D "it8781", .model =3D "IT8781F", - .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OFFSET + .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .old_peci_mask =3D 0x4, }, [it8782] =3D { .name =3D "it8782", .model =3D "IT8782F", - .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OFFSET + .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .old_peci_mask =3D 0x4, }, [it8783] =3D { .name =3D "it8783", .model =3D "IT8783E/F", - .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OFFSET + .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .old_peci_mask =3D 0x4, }, [it8786] =3D { .name =3D "it8786", .model =3D "IT8786E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, }, [it8790] =3D { .name =3D "it8790", .model =3D "IT8790E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF | FEAT_NOCONF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, }, [it8792] =3D { .name =3D "it8792", .model =3D "IT8792E/IT8795E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF | FEAT_NOCONF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, .old_peci_mask =3D 0x02, /* Actually reports PCH */ }, @@ -472,54 +521,72 @@ static const struct it87_devices it87_devices[] =3D { .name =3D "it8603", .model =3D "IT8603E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_AVCC3 | FEAT_PWM_FREQ2, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 4, .peci_mask =3D 0x07, }, [it8620] =3D { .name =3D "it8620", .model =3D "IT8620E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS + | FEAT_TEMP_PECI | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, }, [it8622] =3D { .name =3D "it8622", .model =3D "IT8622E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS + | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_FOUR_TEMP, - .peci_mask =3D 0x07, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 4, + .peci_mask =3D 0x0f, .smbus_bitmap =3D BIT(1) | BIT(2), }, [it8628] =3D { .name =3D "it8628", .model =3D "IT8628E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS + | FEAT_TEMP_PECI | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 6, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, }, [it8689] =3D { .name =3D "it8689", .model =3D "IT8689E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_SIX_FANS | FEAT_IN7_INTERNAL + | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_AVCC3 | FEAT_FANCTL_ONOFF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .smbus_bitmap =3D BIT(1) | BIT(2), }, [it87952] =3D { .name =3D "it87952", .model =3D "IT87952E", .features =3D FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF | FEAT_NOCONF, + .num_temp_limit =3D 3, + .num_temp_offset =3D 3, + .num_temp_map =3D 3, .peci_mask =3D 0x07, .old_peci_mask =3D 0x02, /* Actually reports PCH */ }, @@ -530,7 +597,6 @@ static const struct it87_devices it87_devices[] =3D { #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) -#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ ((data)->peci_mask & BIT(nr))) #define has_temp_old_peci(data, nr) \ @@ -589,6 +655,9 @@ struct it87_data { int sioaddr; enum chips type; u32 features; + u8 num_temp_limit; + u8 num_temp_offset; + u8 num_temp_map; u8 peci_mask; u8 old_peci_mask; =20 @@ -937,12 +1006,12 @@ static struct it87_data *it87_update_device(struct d= evice *dev) data->temp[i][0] =3D it87_read_value(data, IT87_REG_TEMP(i)); =20 - if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) + if (i < data->num_temp_offset) data->temp[i][3] =3D it87_read_value(data, IT87_REG_TEMP_OFFSET[i]); =20 - if (i >=3D NUM_TEMP_LIMIT) + if (i >=3D data->num_temp_limit) continue; =20 data->temp[i][1] =3D @@ -1693,16 +1762,18 @@ static ssize_t show_pwm_temp_map(struct device *dev, struct sensor_device_attribute *sensor_attr =3D to_sensor_dev_attr(attr); struct it87_data *data =3D it87_update_device(dev); int nr =3D sensor_attr->index; + u8 num_map; int map; =20 if (IS_ERR(data)) return PTR_ERR(data); =20 + num_map =3D data->num_temp_map; map =3D data->pwm_temp_map[nr]; - if (map >=3D 3) + if (map >=3D num_map) map =3D 0; /* Should never happen */ - if (nr >=3D 3) /* pwm channels 3..6 map to temp4..6 */ - map +=3D 3; + if (nr >=3D num_map) /* pwm channels 3..6 map to temp4..6 */ + map +=3D num_map; =20 return sprintf(buf, "%d\n", (int)BIT(map)); } @@ -1714,6 +1785,7 @@ static ssize_t set_pwm_temp_map(struct device *dev, struct sensor_device_attribute *sensor_attr =3D to_sensor_dev_attr(attr); struct it87_data *data =3D dev_get_drvdata(dev); int nr =3D sensor_attr->index; + u8 num_map =3D data->num_temp_map; long val; int err; u8 reg; @@ -1721,8 +1793,8 @@ static ssize_t set_pwm_temp_map(struct device *dev, if (kstrtol(buf, 10, &val) < 0) return -EINVAL; =20 - if (nr >=3D 3) - val -=3D 3; + if (nr >=3D num_map) + val -=3D num_map; =20 switch (val) { case BIT(0): @@ -2376,7 +2448,7 @@ static umode_t it87_temp_is_visible(struct kobject *k= obj, return attr->mode; } =20 - if (a =3D=3D 5 && !has_temp_offset(data)) + if (a =3D=3D 5 && i >=3D data->num_temp_offset) return 0; =20 if (a =3D=3D 6 && !data->has_beep) @@ -3268,7 +3340,7 @@ static void it87_check_limit_regs(struct it87_data *d= ata) if (reg =3D=3D 0xff) it87_write_value(data, IT87_REG_VIN_MIN(i), 0); } - for (i =3D 0; i < NUM_TEMP_LIMIT; i++) { + for (i =3D 0; i < data->num_temp_limit; i++) { reg =3D it87_read_value(data, IT87_REG_TEMP_HIGH(i)); if (reg =3D=3D 0xff) it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); @@ -3461,6 +3533,7 @@ static int it87_probe(struct platform_device *pdev) struct resource *res; struct device *dev =3D &pdev->dev; struct it87_sio_data *sio_data =3D dev_get_platdata(dev); + const struct it87_devices *chip; int enable_pwm_interface; struct device *hwmon_dev; int err; @@ -3483,9 +3556,13 @@ static int it87_probe(struct platform_device *pdev) data->type =3D sio_data->type; data->smbus_bitmap =3D sio_data->smbus_bitmap; data->ec_special_config =3D sio_data->ec_special_config; - data->features =3D it87_devices[sio_data->type].features; - data->peci_mask =3D it87_devices[sio_data->type].peci_mask; - data->old_peci_mask =3D it87_devices[sio_data->type].old_peci_mask; + chip =3D &it87_devices[sio_data->type]; + data->features =3D chip->features; + data->peci_mask =3D chip->peci_mask; + data->old_peci_mask =3D chip->old_peci_mask; + data->num_temp_limit =3D chip->num_temp_limit; + data->num_temp_offset =3D chip->num_temp_offset; + data->num_temp_map =3D chip->num_temp_map; /* * IT8705F Datasheet 0.4.1, 3h =3D=3D Version G. * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h =3D=3D Version J. --=20 2.55.0 From nobody Sat Sep 26 21:59:57 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2F75402BAA for ; Sat, 29 Aug 2026 17:05:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023161; cv=none; b=G0OZKz+34+8x53Z3mQ8tGsBM0aOMACndylVPEoZ5YKhHjgw/NlaDo6nEaDSRfb4IFAEL6tkrutrbViJc8dVuVsVebI9IyKgi8hPCz19ZnNstdkja5Qeo291Nx5vMFc4yjVuyUioYSxNEms+eyeY6hfNh3vTPq9oTdtIJEq+qx7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023161; c=relaxed/simple; bh=0RQP6CHUutwhiHKR91TIkYyESgo602mMx5QJZYTve2c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nvj/X2WiJuJMNKVuY71G/WsHqkESW4kCUQ8/oUSouabqSljXyI5obmJ5r6v3T2B2eQUbnP56QEy+JGKD/xv8N0XZAsr9P0CFTilIoysdtI25tXM36Dd0VQjeE47WqwhQKhaHTHZiHrYvKzncLX/UD2Cv1X7OWwSnW+c9TyZA0B8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=q2k1GSh2; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="q2k1GSh2" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-c250f28f1cdso324192866b.0 for ; Sat, 29 Aug 2026 10:05:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788023154; x=1788627954; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=WVU/NL9OcCsh7NoMimF9YpAzSlDIoJEBxaWLFhSnYHY=; b=q2k1GSh2QxReOp6RlIAVenLRBDC2C3NP8Yi+m7bhVXvNwOU03rrRAxOahJhBYUIKx+ E1zCey5yiDcYc4vxdvrTaJAvwJIi59D4+oU7RByAyrf4SInG/45SUm+vMMkb8BoWdnmV vXS4P2edQBUo9w/s22LK5VVvqQBVWDoArkYIOTP7EthgvwgBHHZVUgMWF5b5FUBb1GMG 8Pi/DgBID40UseTd3v6dtSaN0suk9kLV7XskAn2IscxSDvX6yUZyzBsmiugZJuhphsOO xhBNnPDhC4zjZQFxWN8SC1e0jIYmlBLiCO5e/C8g8KnDlZVaurh830tYwWfnAqCti9mZ T7XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788023154; x=1788627954; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=WVU/NL9OcCsh7NoMimF9YpAzSlDIoJEBxaWLFhSnYHY=; b=LwCtWJnOfJhGhmWGuX9us3sMySzbMF0bDGSmOFVyOEgZ6mttEUe7i8TkSMOz4wAn/K fYv01GngoMnW4+fGBlFdsrKoFkU+eA5vAKu08jXj+tLcJVHPWKcpqC9uc9UKnP1RZTnM KEz+vwwJ4xA+julBeSMfdIl+RYVCtJ/ZJtYDKQP+f+akziIIzYWSvJ+CjVe2LTXdVFxO eV3KM/MWhRdZYF3w7f6u2unT37rOjQ+Dq97uhQ27qjCGxI4FRj/jSVOncuTec3gBUowF +9y8oWfc08eE57yIIx+RVYN9UrZaqbY/S8Hz/eNqo1Z1OZlR/pGT9LndbA+rYbwtVw/0 UDVQ== X-Forwarded-Encrypted: i=1; AHgh+RpyCQZdrbQmx3goZW7N2ZkH1510eKgS7odFBZ+hxc1NEX0ERPraAv2hzcvlfIZWi+/mnq/prh9gs/wQQpI=@vger.kernel.org X-Gm-Message-State: AFuF++nZb/5qUD8wcmmiIukyi27iYipM7dfhWBUnpJAQu4+4Vyd0dnXr +KjYcZE9+dM5/SqGR6E3ezffwWU7kxUOoqkRwH7GeiIq14ruERH7YwLG X-Gm-Gg: AR+sD10+qzl6nClgsopXNW1LeXvGsNI8EJN3YnujIVcWg5m44kAweBn/NVqXh8oRJd7 UfpSDcJ3ciVdu2cQCPmFg7JKQQVXYkOKjaev49mW34Y0cT6UJ+TdAU6Vt76nt8T5fK0MKM0yEZ+ 5iRBc+0VVQJyU4ccpRLGIKJzlvapiBrTXMj+g8QACfPALLsNtG0jOl6Rg7Hb2wf2TRuxx4yfEwN wML/z6WMZ8tGUMKVW0HZP87QNNQUpe6h5MY5cLCEaPQKUMj3zCZF1HqlN0qTeQ6sEbMrjF12CMe et1M5E8m0GFNo9CNF05L/pRXpnnYvqZ9Yv+MvXFEsUUVjYcZFIJHmPKqKDCXGn5RsDYHIp6yGWx BtxhBHQULx7nb8EmCx5K3QdnkNXw5OAuLdHzyYHqSc8XHkzcLYsVSBTljHfTOeTDx//njaQS+yn 2/I5EHdfG4eOTHKG1DrQQtLzvYwQV46DAFf5t5i3frLbbRd5Fi0uV/3uRxmY930MP4pkM4NYSa1 a/mrKChHmNF1qrW X-Received: by 2002:a17:907:930e:b0:c12:3059:4071 with SMTP id a640c23a62f3a-c25571a8f8dmr1145815566b.15.1788023154114; Sat, 29 Aug 2026 10:05:54 -0700 (PDT) Received: from localhost ([2603:5004:20a0:100c:cf7b:6b6c:bc26:7dfa]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2822esm213925366b.17.2026.08.29.10.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Aug 2026 10:05:53 -0700 (PDT) From: Jerome Tollet To: Jean Delvare , Guenter Roeck Cc: linux-hwmon@vger.kernel.org, Benoit Masson , Jonathan Corbet , Shuah Khan , Randy Dunlap , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Tollet Subject: [PATCH v5 2/4] hwmon: it87: prepare for extended PWM temp maps Date: Sat, 29 Aug 2026 19:05:43 +0200 Message-ID: <20260829170545.33401-3-jerome.tollet@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260829170545.33401-1-jerome.tollet@gmail.com> References: <20260829170545.33401-1-jerome.tollet@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "benoit.masson" Introduce helper logic for PWM-to-temperature mappings so newer register layouts can be supported without affecting legacy chips. Signed-off-by: benoit.masson Signed-off-by: Jerome Tollet --- drivers/hwmon/it87.c | 199 +++++++++++++++++++++++++++++++++---------- 1 file changed, 154 insertions(+), 45 deletions(-) diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 1c77f6c97..e077adbb3 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -252,6 +252,7 @@ static const u8 IT87_REG_TEMP_OFFSET[] =3D { 0x56, 0x57= , 0x59, 0x5a, 0x90, 0x91 }; #define IT87_REG_FAN_MAIN_CTRL 0x13 #define IT87_REG_FAN_CTL 0x14 static const u8 IT87_REG_PWM[] =3D { 0x15, 0x16, 0x17, 0x7f, 0xa7,= 0xaf }; +static const u8 IT87_REG_PWM_8665[] =3D { 0x15, 0x16, 0x17, 0x1e, 0x1f,= 0x92 }; static const u8 IT87_REG_PWM_DUTY[] =3D { 0x63, 0x6b, 0x73, 0x7b, 0xa3,= 0xab }; =20 static const u8 IT87_REG_VIN[] =3D { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0= x26, @@ -282,6 +283,7 @@ static const u8 IT87_REG_AUTO_BASE[] =3D { 0x60, 0x68, = 0x70, 0x78, 0xa0, 0xa8 }; #define NUM_VIN_LIMIT 8 #define NUM_TEMP 6 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) +#define IT87_PWM_OLD_NUM_TEMP 3 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) #define NUM_FAN_DIV 3 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) @@ -291,6 +293,7 @@ struct it87_devices { const char *name; const char * const model; u32 features; + const u8 *reg_pwm; u8 num_temp_limit; u8 num_temp_offset; u8 num_temp_map; @@ -329,6 +332,7 @@ struct it87_devices { #define FEAT_FOUR_PWM BIT(21) /* Supports four fan controls */ #define FEAT_FOUR_TEMP BIT(22) #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */ +#define FEAT_NEW_TEMPMAP BIT(24) /* PWM uses extended temp map */ =20 static const struct it87_devices it87_devices[] =3D { [it87] =3D { @@ -336,6 +340,7 @@ static const struct it87_devices it87_devices[] =3D { .model =3D "IT87F", .features =3D FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF, /* may need to overwrite */ + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 0, .num_temp_map =3D 3, @@ -345,6 +350,7 @@ static const struct it87_devices it87_devices[] =3D { .model =3D "IT8712F", .features =3D FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF, /* may need to overwrite */ + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 0, .num_temp_map =3D 3, @@ -355,6 +361,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_16BIT_FANS | FEAT_VID | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -365,6 +372,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_16BIT_FANS | FEAT_VID | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -376,6 +384,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_16BIT_FANS | FEAT_VID | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -388,6 +397,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -401,6 +411,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 6, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -413,6 +424,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -429,6 +441,7 @@ static const struct it87_devices it87_devices[] =3D { /* 12mV ADC (OHM) */ /* 16 bit fans (OHM) */ /* three fans, always 16 bit (guesswork) */ + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -444,6 +457,7 @@ static const struct it87_devices it87_devices[] =3D { /* 12mV ADC (HWSensors4, OHM) */ /* 16 bit fans (HWSensors4, OHM) */ /* three fans, always 16 bit (datasheet) */ + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -455,6 +469,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -466,6 +481,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -477,6 +493,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -488,6 +505,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -499,6 +517,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF | FEAT_NOCONF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -511,6 +530,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF | FEAT_NOCONF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -523,6 +543,7 @@ static const struct it87_devices it87_devices[] =3D { .features =3D FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_AVCC3 | FEAT_PWM_FREQ2, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 4, @@ -535,6 +556,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_PECI | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -547,6 +569,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_FOUR_TEMP, + .reg_pwm =3D IT87_REG_PWM_8665, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 4, @@ -560,6 +583,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_PECI | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 6, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -572,6 +596,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_AVCC3 | FEAT_FANCTL_ONOFF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -584,6 +609,7 @@ static const struct it87_devices it87_devices[] =3D { | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF | FEAT_NOCONF, + .reg_pwm =3D IT87_REG_PWM, .num_temp_limit =3D 3, .num_temp_offset =3D 3, .num_temp_map =3D 3, @@ -626,6 +652,7 @@ static const struct it87_devices it87_devices[] =3D { #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ FEAT_10_9MV_ADC)) #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF) +#define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP) =20 struct it87_sio_data { int sioaddr; @@ -655,6 +682,7 @@ struct it87_data { int sioaddr; enum chips type; u32 features; + const u8 *reg_pwm; u8 num_temp_limit; u8 num_temp_offset; u8 num_temp_map; @@ -704,7 +732,9 @@ struct it87_data { u8 has_pwm; /* Bitfield, pwm control enabled */ u8 pwm_ctrl[NUM_PWM]; /* Register value */ u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ - u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ + u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping */ + u8 pwm_temp_map_mask; + u8 pwm_temp_map_shift; =20 /* Automatic fan speed control registers */ u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ @@ -786,6 +816,71 @@ static int pwm_from_reg(const struct it87_data *data, = u8 reg) return (reg & 0x7f) << 1; } =20 +static inline u8 pwm_temp_map_get(const struct it87_data *data, u8 ctrl) +{ + return (ctrl >> data->pwm_temp_map_shift) & + data->pwm_temp_map_mask; +} + +static inline u8 pwm_temp_map_set(const struct it87_data *data, u8 ctrl, + u8 map) +{ + ctrl &=3D ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift); + return ctrl | ((map & data->pwm_temp_map_mask) + << data->pwm_temp_map_shift); +} + +static inline u8 pwm_num_temp_map(const struct it87_data *data) +{ + return data->num_temp_map; +} + +static unsigned int pwm_temp_channel(const struct it87_data *data, + int nr, u8 map) +{ + if (has_new_tempmap(data)) { + u8 num =3D pwm_num_temp_map(data); + + if (map >=3D num) + map =3D 0; + return map; + } + + if (map >=3D IT87_PWM_OLD_NUM_TEMP) + map =3D 0; + + if (nr >=3D IT87_PWM_OLD_NUM_TEMP) + map +=3D IT87_PWM_OLD_NUM_TEMP; + + return map; +} + +static int pwm_temp_map_from_channel(const struct it87_data *data, int nr, + unsigned int channel, u8 *map) +{ + if (has_new_tempmap(data)) { + u8 num =3D pwm_num_temp_map(data); + + if (channel >=3D num) + return -EINVAL; + *map =3D channel; + return 0; + } + + if (nr >=3D IT87_PWM_OLD_NUM_TEMP) { + if (channel < IT87_PWM_OLD_NUM_TEMP || + channel >=3D 2 * IT87_PWM_OLD_NUM_TEMP) + return -EINVAL; + channel -=3D IT87_PWM_OLD_NUM_TEMP; + } else { + if (channel >=3D IT87_PWM_OLD_NUM_TEMP) + return -EINVAL; + } + + *map =3D channel; + return 0; +} + static int DIV_TO_REG(int val) { int answer =3D 0; @@ -797,6 +892,11 @@ static int DIV_TO_REG(int val) =20 #define DIV_FROM_REG(val) BIT(val) =20 +static inline u16 it87_reg_pwm(const struct it87_data *data, int nr) +{ + return data->reg_pwm[nr]; +} + /* * PWM base frequencies. The frequency has to be divided by either 128 or = 256, * depending on the chip type, to calculate the actual PWM frequency. @@ -877,14 +977,22 @@ static void it87_write_value(struct it87_data *data, = u8 reg, u8 value) =20 static void it87_update_pwm_ctrl(struct it87_data *data, int nr) { - data->pwm_ctrl[nr] =3D it87_read_value(data, IT87_REG_PWM[nr]); + data->pwm_ctrl[nr] =3D it87_read_value(data, it87_reg_pwm(data, nr)); if (has_newer_autopwm(data)) { - data->pwm_temp_map[nr] =3D data->pwm_ctrl[nr] & 0x03; + data->pwm_temp_map[nr] =3D + pwm_temp_map_get(data, data->pwm_ctrl[nr]); + if (has_new_tempmap(data) && + data->pwm_temp_map[nr] >=3D pwm_num_temp_map(data)) + data->pwm_temp_map[nr] =3D 0; data->pwm_duty[nr] =3D it87_read_value(data, IT87_REG_PWM_DUTY[nr]); } else { if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ - data->pwm_temp_map[nr] =3D data->pwm_ctrl[nr] & 0x03; + data->pwm_temp_map[nr] =3D + pwm_temp_map_get(data, data->pwm_ctrl[nr]); + if (has_new_tempmap(data) && + data->pwm_temp_map[nr] >=3D pwm_num_temp_map(data)) + data->pwm_temp_map[nr] =3D 0; else /* Manual mode */ data->pwm_duty[nr] =3D data->pwm_ctrl[nr] & 0x7f; } @@ -1617,6 +1725,8 @@ static ssize_t set_pwm_enable(struct device *dev, str= uct device_attribute *attr, if (err) return err; =20 + it87_update_pwm_ctrl(data, nr); + if (val =3D=3D 0) { if (nr < 3 && has_fanctl_onoff(data)) { int tmp; @@ -1636,27 +1746,30 @@ static ssize_t set_pwm_enable(struct device *dev, s= truct device_attribute *attr, data->pwm_duty[nr]); /* and set manual mode */ if (has_newer_autopwm(data)) { - ctrl =3D (data->pwm_ctrl[nr] & 0x7c) | - data->pwm_temp_map[nr]; + ctrl =3D pwm_temp_map_set(data, + data->pwm_ctrl[nr] & + ~0x80, + data->pwm_temp_map[nr]); } else { ctrl =3D data->pwm_duty[nr]; } data->pwm_ctrl[nr] =3D ctrl; - it87_write_value(data, IT87_REG_PWM[nr], ctrl); + it87_write_value(data, it87_reg_pwm(data, nr), ctrl); } } else { u8 ctrl; =20 if (has_newer_autopwm(data)) { - ctrl =3D (data->pwm_ctrl[nr] & 0x7c) | - data->pwm_temp_map[nr]; + ctrl =3D pwm_temp_map_set(data, + data->pwm_ctrl[nr] & ~0x80, + data->pwm_temp_map[nr]); if (val !=3D 1) ctrl |=3D 0x80; } else { ctrl =3D (val =3D=3D 1 ? data->pwm_duty[nr] : 0x80); } data->pwm_ctrl[nr] =3D ctrl; - it87_write_value(data, IT87_REG_PWM[nr], ctrl); + it87_write_value(data, it87_reg_pwm(data, nr), ctrl); =20 if (has_fanctl_onoff(data) && nr < 3) { /* set SmartGuardian mode */ @@ -1707,7 +1820,7 @@ static ssize_t set_pwm(struct device *dev, struct dev= ice_attribute *attr, */ if (!(data->pwm_ctrl[nr] & 0x80)) { data->pwm_ctrl[nr] =3D data->pwm_duty[nr]; - it87_write_value(data, IT87_REG_PWM[nr], + it87_write_value(data, it87_reg_pwm(data, nr), data->pwm_ctrl[nr]); } } @@ -1762,20 +1875,14 @@ static ssize_t show_pwm_temp_map(struct device *dev, struct sensor_device_attribute *sensor_attr =3D to_sensor_dev_attr(attr); struct it87_data *data =3D it87_update_device(dev); int nr =3D sensor_attr->index; - u8 num_map; - int map; + unsigned int channel; =20 if (IS_ERR(data)) return PTR_ERR(data); =20 - num_map =3D data->num_temp_map; - map =3D data->pwm_temp_map[nr]; - if (map >=3D num_map) - map =3D 0; /* Should never happen */ - if (nr >=3D num_map) /* pwm channels 3..6 map to temp4..6 */ - map +=3D num_map; + channel =3D pwm_temp_channel(data, nr, data->pwm_temp_map[nr]); =20 - return sprintf(buf, "%d\n", (int)BIT(map)); + return sprintf(buf, "%d\n", (int)BIT(channel)); } =20 static ssize_t set_pwm_temp_map(struct device *dev, @@ -1785,45 +1892,34 @@ static ssize_t set_pwm_temp_map(struct device *dev, struct sensor_device_attribute *sensor_attr =3D to_sensor_dev_attr(attr); struct it87_data *data =3D dev_get_drvdata(dev); int nr =3D sensor_attr->index; - u8 num_map =3D data->num_temp_map; long val; int err; - u8 reg; + unsigned int channel; + u8 map; =20 - if (kstrtol(buf, 10, &val) < 0) + if (kstrtol(buf, 10, &val) < 0 || val <=3D 0 || !is_power_of_2(val)) return -EINVAL; =20 - if (nr >=3D num_map) - val -=3D num_map; - - switch (val) { - case BIT(0): - reg =3D 0x00; - break; - case BIT(1): - reg =3D 0x01; - break; - case BIT(2): - reg =3D 0x02; - break; - default: + channel =3D __ffs(val); + if (pwm_temp_map_from_channel(data, nr, channel, &map)) return -EINVAL; - } =20 err =3D it87_lock(data); if (err) return err; =20 it87_update_pwm_ctrl(data, nr); - data->pwm_temp_map[nr] =3D reg; + data->pwm_temp_map[nr] =3D map; /* * If we are in automatic mode, write the temp mapping immediately; * otherwise, just store it for later use. */ if (data->pwm_ctrl[nr] & 0x80) { - data->pwm_ctrl[nr] =3D (data->pwm_ctrl[nr] & 0xfc) | - data->pwm_temp_map[nr]; - it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); + data->pwm_ctrl[nr] =3D pwm_temp_map_set(data, + data->pwm_ctrl[nr], + data->pwm_temp_map[nr]); + it87_write_value(data, it87_reg_pwm(data, nr), + data->pwm_ctrl[nr]); } it87_unlock(data); return count; @@ -3422,7 +3518,10 @@ static void it87_init_device(struct platform_device = *pdev) * manual duty cycle. */ for (i =3D 0; i < NUM_AUTO_PWM; i++) { - data->pwm_temp_map[i] =3D i; + if (has_new_tempmap(data)) + data->pwm_temp_map[i] =3D 0; + else + data->pwm_temp_map[i] =3D i % IT87_PWM_OLD_NUM_TEMP; data->pwm_duty[i] =3D 0x7f; /* Full speed */ data->auto_pwm[i][3] =3D 0x7f; /* Full speed, hard-coded */ } @@ -3494,7 +3593,8 @@ static int it87_check_pwm(struct device *dev) =20 for (i =3D 0; i < ARRAY_SIZE(pwm); i++) pwm[i] =3D it87_read_value(data, - IT87_REG_PWM[i]); + it87_reg_pwm(data, + i)); =20 /* * If any fan is in automatic pwm mode, the polarity @@ -3509,7 +3609,8 @@ static int it87_check_pwm(struct device *dev) tmp | 0x87); for (i =3D 0; i < 3; i++) it87_write_value(data, - IT87_REG_PWM[i], + it87_reg_pwm(data, + i), 0x7f & ~pwm[i]); return 1; } @@ -3558,11 +3659,19 @@ static int it87_probe(struct platform_device *pdev) data->ec_special_config =3D sio_data->ec_special_config; chip =3D &it87_devices[sio_data->type]; data->features =3D chip->features; + data->reg_pwm =3D chip->reg_pwm; data->peci_mask =3D chip->peci_mask; data->old_peci_mask =3D chip->old_peci_mask; data->num_temp_limit =3D chip->num_temp_limit; data->num_temp_offset =3D chip->num_temp_offset; data->num_temp_map =3D chip->num_temp_map; + if (has_new_tempmap(data)) { + data->pwm_temp_map_mask =3D 0x07; + data->pwm_temp_map_shift =3D 3; + } else { + data->pwm_temp_map_mask =3D 0x03; + data->pwm_temp_map_shift =3D 0; + } /* * IT8705F Datasheet 0.4.1, 3h =3D=3D Version G. * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h =3D=3D Version J. --=20 2.55.0 From nobody Sat Sep 26 21:59:57 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D02C7418368 for ; Sat, 29 Aug 2026 17:06:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023164; cv=none; b=pWT2mpM1bJftDQ3LfLwO2csmqkZp4sgp8SKU6cDn633Ir2wHJUazBnFuT7S4Oy4nMI6e+dVUKCzFiah2kNQP/hZul5ioYbinJEiFQwPMK+vhoPY/Q7la4MuLrFuhM2zPeAAHCmx3vZAM8sjqRIwElJAYCSYOV8t9qTGMBQ12GYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023164; c=relaxed/simple; bh=+T3SUvIdlpcApYIWZh4RPOenYo/eds0ZgRRRsx4ineI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Udps/DYqHmnE1C9TqelgqVjOd7joVWtjoWUVI3nUO8HtnXlVRfB4BpA77lz2TIZ3UZ8yOeibMBmuvU7FJsRL4XmYsVYlWjDsoliQ+pM0ZI/lR/nTmLmms8H+tQOpIABAFknUFprLqAp7MmsNy3RIW0xFFZr6p/GjeteI+XHv/6I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kLoKVRQT; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kLoKVRQT" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-c197e7e4e94so291434966b.2 for ; Sat, 29 Aug 2026 10:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788023157; x=1788627957; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=HTn/4/0+Yqcb2yJiGCQLjeFpCyIkZvplKqCgdVt4fEY=; b=kLoKVRQTD77672gi+Q+eyzycfVY4HI3jl/phORUTdJLDEFhhScIWyIXPqfSM43BHFn oHEhfJ7bBvtSBWpeBMy8kR703FVjwLc3h8td9fYT8rJYZUoo7uM07Wy/2BPVPpAXGHd6 wRLGZy5uYHDLoa5PzhuY6bvZBFdugCeiWNYHR23+5iTu1tLaBjb97KUXAzauewLBJKE0 R3dGzrt9y6QlBcUxRHmK8l14tJ1bdYtfK6ieOKH7mDuJN0rV7SptPVdMcWeDu1WtP1ag /NwLV3rND/2OIGGjX43r8TKj84abW/No2l1w0uzUSQm9olGV5/hO+LbleO8BD/Hw+gJG D7lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788023157; x=1788627957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=HTn/4/0+Yqcb2yJiGCQLjeFpCyIkZvplKqCgdVt4fEY=; b=e2HWvGOuee6awVOR1EcNSTgLgTi+CXivUBTZLWjTDIS6U9QWENuTbITqlH/8vjXpGw fVZSGxshXLS+rC/fJKJDxzDow1+0p7nyUYocPq5b2Z9gX1wNwhFy0xFjVNdXzsH2J7xG OY8zEIVNw5MXlYkV90Qml1p1yKcBi3tCxhYbtVn2A2X1eAU27N54HQkVxxT2lahboY4+ b2NiKP4rVfkOx9CZZRcPWNZri23bCoDpxfO84/+lz78senlHd+v4b7S9dfwyL33TFMku DFXHWf6/EcD1VdmH+ir7tRB3XDWyKOLBDjocsr4vA1M4S0h6QsFkycZh4X1pdjdUmmIc eOig== X-Forwarded-Encrypted: i=1; AHgh+Rqtnsf2JHSIOVfhmzk2MAWIYfEZXv+UQvW1GD28P/tRRvaJymC4kMxNSv+7zCgFSqmTv0UTIFtbzl7svMY=@vger.kernel.org X-Gm-Message-State: AFuF++nE4BJNRbcEAjIPN6y20Ri9SG41cAugYa5TA6sQkeggM1rxiGi2 fQNih7L7L1qkWdJghUx2iMyQjkB97DoEezfPoW7pMWi5fADpogEstMR9 X-Gm-Gg: AR+sD13PXkSG4Pcn+CG+yhWY+GZpVaftajJU+eenld0ULfVbLKU8PFqiZPtty7na/Ww Xgu3mWLvuZnLWrKMMwxNXix0gUJ6IbAK0XLW/kE12IRuwMwIpI1TYM1SoCnkY+KwO6n+rN3MUOK RXOntZAkd4rdGEicDWzNzGHqRuyltdkEbFsNvqAKBaPFyy28QANujSe+EqdouxE1Af7uJVnbxyp UnfH1iUt0Fd29hHiY7R35nEtz+7qpXPD96i5twCUIJxDc0wfznCu9YHuBNKGM9dJ5ANbsQfeVzw NBdiW0COZTwWYA8WeTIQh30oaueCOgf32H+gqwJCwSlVNnwpycSonOaEKoCuyXJ9/ygM8d8yN6k tCPyxCR4pmzflYMeO91D1vPNdnZB50zru1YxPNqQs2fbdbw9YiFfrPTXD70vPs1XH1pzRSSRgDI k4VXn/v+uFPDMJkGYaE+CI108Px3HIZ/wkPAvQTujXfXY4smqwtlUYdICmXCYBr5zwvCWKxxPYZ UEVv9RtT75fGx84GoiAjAb4lQ== X-Received: by 2002:a17:907:6d25:b0:c20:2d38:e518 with SMTP id a640c23a62f3a-c2556c61d72mr1008446466b.2.1788023157326; Sat, 29 Aug 2026 10:05:57 -0700 (PDT) Received: from localhost ([2603:5004:20a0:100c:4701:1ac4:1c21:4a1]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee288afsm213294766b.23.2026.08.29.10.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Aug 2026 10:05:55 -0700 (PDT) From: Jerome Tollet To: Jean Delvare , Guenter Roeck Cc: linux-hwmon@vger.kernel.org, Benoit Masson , Jonathan Corbet , Shuah Khan , Randy Dunlap , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Tollet Subject: [PATCH v5 3/4] hwmon: it87: expose additional temperature limits Date: Sat, 29 Aug 2026 19:05:44 +0200 Message-ID: <20260829170545.33401-4-jerome.tollet@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260829170545.33401-1-jerome.tollet@gmail.com> References: <20260829170545.33401-1-jerome.tollet@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "benoit.masson" Expose extra temp min/max/offset/type/alarm attributes when a chip reports more than three temperature resources. Signed-off-by: benoit.masson Signed-off-by: Jerome Tollet --- drivers/hwmon/it87.c | 58 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index e077adbb3..e44ec65c7 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -1349,8 +1349,26 @@ static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_I= WUSR, show_temp, set_temp, static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, set_temp, 2, 3); static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); +static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, + 3, 1); +static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, + 3, 2); +static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, + set_temp, 3, 3); static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); +static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, + 4, 1); +static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, + 4, 2); +static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, + set_temp, 4, 3); static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); +static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, + 5, 1); +static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, + 5, 2); +static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, + set_temp, 5, 3); =20 static int get_temp_type(struct it87_data *data, int index) { @@ -1476,6 +1494,12 @@ static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IW= USR, show_temp_type, set_temp_type, 1); static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, set_temp_type, 2); +static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, + set_temp_type, 3); +static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, + set_temp_type, 4); +static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, + set_temp_type, 5); =20 /* 6 Fans */ =20 @@ -2308,6 +2332,9 @@ static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_a= larm, NULL, 7); static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); +static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19); +static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20); +static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21); static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, show_alarm, clear_intrusion, 4); =20 @@ -2368,6 +2395,9 @@ static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWU= SR, show_beep, set_beep, 2); static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); +static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2); +static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2); +static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2); =20 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2530,14 +2560,12 @@ static umode_t it87_temp_is_visible(struct kobject = *kobj, int i =3D index / 7; /* temperature index */ int a =3D index % 7; /* attribute index */ =20 - if (index >=3D 21) { - i =3D index - 21 + 3; - a =3D 0; - } - if (!(data->has_temp & BIT(i))) return 0; =20 + if (a && i >=3D data->num_temp_limit) + return 0; + if (a =3D=3D 3) { if (get_temp_type(data, i) =3D=3D 0) return 0; @@ -2579,8 +2607,28 @@ static struct attribute *it87_attributes_temp[] =3D { &sensor_dev_attr_temp3_beep.dev_attr.attr, =20 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ + &sensor_dev_attr_temp4_max.dev_attr.attr, + &sensor_dev_attr_temp4_min.dev_attr.attr, + &sensor_dev_attr_temp4_type.dev_attr.attr, + &sensor_dev_attr_temp4_alarm.dev_attr.attr, + &sensor_dev_attr_temp4_offset.dev_attr.attr, + &sensor_dev_attr_temp4_beep.dev_attr.attr, + &sensor_dev_attr_temp5_input.dev_attr.attr, + &sensor_dev_attr_temp5_max.dev_attr.attr, + &sensor_dev_attr_temp5_min.dev_attr.attr, + &sensor_dev_attr_temp5_type.dev_attr.attr, + &sensor_dev_attr_temp5_alarm.dev_attr.attr, + &sensor_dev_attr_temp5_offset.dev_attr.attr, + &sensor_dev_attr_temp5_beep.dev_attr.attr, + &sensor_dev_attr_temp6_input.dev_attr.attr, + &sensor_dev_attr_temp6_max.dev_attr.attr, + &sensor_dev_attr_temp6_min.dev_attr.attr, + &sensor_dev_attr_temp6_type.dev_attr.attr, + &sensor_dev_attr_temp6_alarm.dev_attr.attr, + &sensor_dev_attr_temp6_offset.dev_attr.attr, + &sensor_dev_attr_temp6_beep.dev_attr.attr, NULL }; =20 --=20 2.55.0 From nobody Sat Sep 26 21:59:57 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 973124137BA for ; Sat, 29 Aug 2026 17:06:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023166; cv=none; b=BXTjfRe5R+tgTEJKCJPOfy9KJoGd3TrbAptRdpj7mdlMF8vm4Uydk4LZT4dqtNjCVrOtl+3exjB+OFhjvvTv2kUW8inWyUiUSzqsxmyZsdOasB0ASfMoQgcJa3lSz7554j13oSkCtXnnG+QYDEwMmbVlqDkajiPIDRsvDtLPDHk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788023166; c=relaxed/simple; bh=/ESLAF9xL9OgW79vd2hVpl4AEXYy9EUVtkY1xmIQ9z8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hP/zKxD4AuxjaeifzOFbyrnYKFYRCYMaPLFFPixc683nEFFPEQMdHukXPaqBHpwCTr+kW2sFc/w27zmbYAqqnGMmHqUBRNPrkPqe7Uh/Jui9O5Gv+ZJKKkC2fXXmFU/ur4rXOa9gqkxhWouYCWcq8ebFKwG29iFNra0M2VZnpow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jTuNIaO1; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jTuNIaO1" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-c25099bb1fbso276908166b.3 for ; Sat, 29 Aug 2026 10:06:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788023160; x=1788627960; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=t+O3FjPNkpZ9C9VUnIRaSGoxe9eYJb6Pa5F8ITJvBpI=; b=jTuNIaO1r97Ogg4ZzVzZx2QPIAccnX/8GyC246cns04CU4bbtbgOTCT4EeTlASi3ON 23FBiq0WsrhECRbHipItl+V6ZKfJQ80tQfdSjYvBPrcZ32ouvv7Hq7AMr0mO4kpN9DdT qgdJqF8MDQTgttvh3hF7ip/LBiaVvCSUga0bR7kmt/CLQZOZfCGuzcPcv8rvK82Nzk4M YhvIW84QcYD9yeRuloC1Sx8I1jH0LqpWGCq1a+EFYgkPRIgTxd7GqWTQibeRVj0XBoKl B7BwtGj98gusr4BaoIS2OsBT6XaCcRub8dPwrdHQj6Rl2mLzMCX45s3izkt6AodTFtnM VoRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788023160; x=1788627960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=t+O3FjPNkpZ9C9VUnIRaSGoxe9eYJb6Pa5F8ITJvBpI=; b=msuWfT8eayyixwpuZwx0c07hvxNz9DAtsB2Qe7AVHhzBk0awWMWusHUAocL3Qqq+QT OI+GS2NkIEbyy0xBdVVsQdgNwsTyeDukhxAayvqRMFqrA6DGhLC/1HP5NGZajIKoxg3F uw2YEL1z1Y4o5rUxUwWmP1/HfH30iF3dQn0qrmCgxi1Q8fgltO9WWDVPbx/Xr83zyuUi XsUM8x07+nFg2aLV1jmQXB1uA8CIrDwucK2cMH/AhGD/Bloo4eaY5nK815zRyzL7mjeB uPdNGKksEZ31MjQT82Biz3XXLyQBhkBCTvjbmzHUNiDNxzNqw+VjPGfjpllE3kcpha7Y rcyg== X-Forwarded-Encrypted: i=1; AHgh+RplOTKT7FrkK/qsT5BqbnvjfpKhPCvYfd9Hk9RU7nRGBUPCXVX3dJuSW5qLuc6lPNbTuLaN53j/4t1uzDA=@vger.kernel.org X-Gm-Message-State: AFuF++nbUIbpHfsVmrOoibNLQsY1Tm22QnZyFvEuxfMmQXDOH3FOTLvm WjsA4wOKvQoMCQ6DzuErgy1YCVZa8Pgr7Xklm3sGa1byqNT5N3xtDj2Y X-Gm-Gg: AR+sD11sdC/XQiZ1Biy7KWdwxW4tPiKsQB3FQhQFMSEUQU/Gyv5kJklecp74X/t6Y32 LaYxQJVfuunRceuNnKfyNOtZkmbgoqcrBK0RaFm5YcWFW6RAqPkYAqSldYA7PYTqWyQwaU64eKT lg+bMfokGpwQd8UsupTltEwVfMY5G0fFNj9BoFo12+q2cdF+rFZHsEdhuX7cT3xzk4NhSecUh0U 4p6x0PdrjzasfiC0s48k2Ce9q7vSJAQ2GfUUtiqOkgHEA+orVSTQ2U/5Dk0FmmV/KE+4rFNfuEx l1Jpuu+4Ajmge+bHWA6wKH6KXEvagTxJoZSIai+1hJtTqI61R9sPPStb4ZyxZxYu1pF43oBgnrD 3p2cHFbsO0ndRGnk1sPEOVMLeyGmbPYQ1kMmNL/LBQkIO8OlXqntWSN2RZ6Q4r9pysbH3rmOYqB W+YTe9KaEWODBDmm10UnD4qyH95Aylb9uQL7mqZBOcO8IFZjjGnStf25zZh1CyUjkoCNwgy35RQ Grkm988V7++dl0= X-Received: by 2002:a17:906:9fc8:b0:c25:1a5:62a4 with SMTP id a640c23a62f3a-c2557164d51mr1038686166b.17.1788023159688; Sat, 29 Aug 2026 10:05:59 -0700 (PDT) Received: from localhost ([2603:5004:20a0:100c:4701:1ac4:1c21:4a1]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255f1fa6a7sm207780466b.46.2026.08.29.10.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Aug 2026 10:05:59 -0700 (PDT) From: Jerome Tollet To: Jean Delvare , Guenter Roeck Cc: linux-hwmon@vger.kernel.org, Benoit Masson , Jonathan Corbet , Shuah Khan , Randy Dunlap , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Tollet Subject: [PATCH v5 4/4] hwmon: it87: add IT8613E support Date: Sat, 29 Aug 2026 19:05:45 +0200 Message-ID: <20260829170545.33401-5-jerome.tollet@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260829170545.33401-1-jerome.tollet@gmail.com> References: <20260829170545.33401-1-jerome.tollet@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "benoit.masson" Teach the Super I/O probe path to recognize IT8613E and add its complete hardware monitoring configuration. Add feature flags, temperature resource counts, 11 mV ADC scaling, the IT8665-style PWM register map, and GPIO pin-mux checks. Document the chip in the hwmon guide. Signed-off-by: benoit.masson Signed-off-by: Jerome Tollet --- Documentation/hwmon/it87.rst | 8 +++++ drivers/hwmon/it87.c | 64 ++++++++++++++++++++++++++++++++++-- 2 files changed, 70 insertions(+), 2 deletions(-) diff --git a/Documentation/hwmon/it87.rst b/Documentation/hwmon/it87.rst index fc1c90b02..c33ba8a07 100644 --- a/Documentation/hwmon/it87.rst +++ b/Documentation/hwmon/it87.rst @@ -11,6 +11,14 @@ Supported chips: =20 Datasheet: Not publicly available =20 + * IT8613E + + Prefix: 'it8613' + + Addresses scanned: from Super I/O config space (8 I/O ports) + + Datasheet: Not publicly available + * IT8620E =20 Prefix: 'it8620' diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index e44ec65c7..67a94761d 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -36,6 +36,7 @@ * IT8790E Super I/O chip w/LPC interface * IT8792E Super I/O chip w/LPC interface * IT87952E Super I/O chip w/LPC interface + * IT8613E Super I/O chip w/LPC interface * Sis950 A clone of the IT8705F * * Copyright (C) 2001 Chris Gauthron @@ -65,7 +66,7 @@ =20 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, it8771, it8772, it8781, it8782, it8783, it8786, it8790, - it8792, it8603, it8620, it8622, it8628, it8689, it87952 }; + it8792, it8603, it8613, it8620, it8622, it8628, it8689, it87952 }; =20 static struct platform_device *it87_pdev[2]; =20 @@ -159,6 +160,7 @@ static inline void superio_exit(int ioreg, bool noexit) #define IT8786E_DEVID 0x8786 #define IT8790E_DEVID 0x8790 #define IT8603E_DEVID 0x8603 +#define IT8613E_DEVID 0x8613 #define IT8620E_DEVID 0x8620 #define IT8622E_DEVID 0x8622 #define IT8623E_DEVID 0x8623 @@ -333,6 +335,7 @@ struct it87_devices { #define FEAT_FOUR_TEMP BIT(22) #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */ #define FEAT_NEW_TEMPMAP BIT(24) /* PWM uses extended temp map */ +#define FEAT_11MV_ADC BIT(25) =20 static const struct it87_devices it87_devices[] =3D { [it87] =3D { @@ -549,6 +552,19 @@ static const struct it87_devices it87_devices[] =3D { .num_temp_map =3D 4, .peci_mask =3D 0x07, }, + [it8613] =3D { + .name =3D "it8613", + .model =3D "IT8613E", + .features =3D FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS + | FEAT_TEMP_PECI | FEAT_FIVE_FANS + | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP, + .reg_pwm =3D IT87_REG_PWM_8665, + .num_temp_limit =3D 6, + .num_temp_offset =3D 6, + .num_temp_map =3D 6, + .peci_mask =3D 0x07, + }, [it8620] =3D { .name =3D "it8620", .model =3D "IT8620E", @@ -621,6 +637,7 @@ static const struct it87_devices it87_devices[] =3D { #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) +#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC) #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ @@ -650,7 +667,8 @@ static const struct it87_devices it87_devices[] =3D { #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) #define has_noconf(data) ((data)->features & FEAT_NOCONF) #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ - FEAT_10_9MV_ADC)) + FEAT_10_9MV_ADC | \ + FEAT_11MV_ADC)) #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF) #define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP) =20 @@ -757,6 +775,8 @@ static int adc_lsb(const struct it87_data *data, int nr) lsb =3D 120; else if (has_10_9mv_adc(data)) lsb =3D 109; + else if (has_11mv_adc(data)) + lsb =3D 110; else lsb =3D 160; if (data->in_scaled & BIT(nr)) @@ -3006,6 +3026,9 @@ static int __init it87_find(int sioaddr, unsigned sho= rt *address, case IT8623E_DEVID: sio_data->type =3D it8603; break; + case IT8613E_DEVID: + sio_data->type =3D it8613; + break; case IT8620E_DEVID: sio_data->type =3D it8620; break; @@ -3183,6 +3206,43 @@ static int __init it87_find(int sioaddr, unsigned sh= ort *address, sio_data->skip_in |=3D BIT(5); /* No VIN5 */ sio_data->skip_in |=3D BIT(6); /* No VIN6 */ =20 + sio_data->beep_pin =3D superio_inb(sioaddr, + IT87_SIO_BEEP_PIN_REG) & 0x3f; + } else if (sio_data->type =3D=3D it8613) { + int reg27, reg29, reg2a; + + superio_select(sioaddr, GPIO); + + /* Check for pwm3, fan3, pwm5, fan5 */ + reg27 =3D superio_inb(sioaddr, IT87_SIO_GPIO3_REG); + if (!(reg27 & BIT(1))) + sio_data->skip_fan |=3D BIT(4); + if (reg27 & BIT(3)) + sio_data->skip_pwm |=3D BIT(4); + if (reg27 & BIT(6)) + sio_data->skip_pwm |=3D BIT(2); + if (reg27 & BIT(7)) + sio_data->skip_fan |=3D BIT(2); + + /* Check for pwm2, fan2 */ + reg29 =3D superio_inb(sioaddr, IT87_SIO_GPIO5_REG); + if (reg29 & BIT(1)) + sio_data->skip_pwm |=3D BIT(1); + if (reg29 & BIT(2)) + sio_data->skip_fan |=3D BIT(1); + + /* Check for pwm4, fan4 */ + reg2a =3D superio_inb(sioaddr, IT87_SIO_PINX1_REG); + if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) { + sio_data->skip_fan |=3D BIT(3); + sio_data->skip_pwm |=3D BIT(3); + } + + sio_data->skip_pwm |=3D BIT(0); /* No pwm1 */ + sio_data->skip_fan |=3D BIT(0); /* No fan1 */ + sio_data->skip_in |=3D BIT(3); /* No VIN3 */ + sio_data->skip_in |=3D BIT(6); /* No VIN6 */ + sio_data->beep_pin =3D superio_inb(sioaddr, IT87_SIO_BEEP_PIN_REG) & 0x3f; } else if (sio_data->type =3D=3D it8620 || sio_data->type =3D=3D it8628) { --=20 2.55.0