From nobody Sat Sep 26 23:35:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E406E361670; Fri, 28 Aug 2026 15:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931017; cv=none; b=e77EPbChYkfkRbLXt165aWuXTjHx8UWZQVKFVnEyahJuOKkVYb+mKMuCS+9+KbDbqeR/N2dfSd3olwgf/3zDffBgFHaRKQYBq85YHVv3hZgYUeYbLc53a2txeN2t0DboozNs5fl9keBWxG75n161oCWq9E2o3EipFrDOJ9i66rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931017; c=relaxed/simple; bh=nnHlv8oO55P0LwkFNxkXh4+Oe4hBeg+9+D4lDzARXs8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gEynWTWceldo1OaY5vRH0G/x+rY/db+iOJYHO0/7a2o/T1Kjuna/oGZbbBj8cDbEjCKy8IZbVdjPZlOSx3c57g8JtbifTy9ZbFlDqNXkxYWzUBbSE36fb6sNL1DDAtPcT3S8L1cgf0y4jjyf/iuuiwqfZrjgZwI8VKroszyjsRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UQ27kF//; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UQ27kF//" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787931015; x=1819467015; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nnHlv8oO55P0LwkFNxkXh4+Oe4hBeg+9+D4lDzARXs8=; b=UQ27kF//UYWrN6iQA3DIap8YMOnvhQ+k3xVMNlZUBrAC1rabAKfIJVlS dv2tZGpXfLq1TkzRHL2sXJA8tvXjRkVDsAWCHi3clMrt+bWjXXIWlbdif fhOKCsTqaaG8vd5eARnkJIvCX9FZNzA2QLoeQvdE9Q8O/nRYVE8BIEnpA zgCplyx4PU7bcUVtAY33tGEstR38eKm5VtoVt7G4rfZ9hG/3oNxq6p52v bpCMN3OrEcOZIf06pHMDCFejC02EpTMoK89GAL1nOz9rduwlZ0vRhhDLn RoyYvRNNQoy/6mE4UTzG3yL6ZycWY6mdZF158O+du4SahzP2S6t2qrGiM g==; X-CSE-ConnectionGUID: GXBvmcRaRwuA69VLnPsRjA== X-CSE-MsgGUID: feAmIDOCQbOPsxIRUZk8yw== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="99104581" X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="99104581" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 X-CSE-ConnectionGUID: BFdpWAV6Q720PoHIAxKKpg== X-CSE-MsgGUID: BOYpFh9aQQ6KA/dfGVeAhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="291682272" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.223.138]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 From: Tony Luck To: Tony Luck Cc: Borislav Petkov , Qiuxu Zhuo , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Breno Leitao , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 1/7] cacheinfo: Export get_cpu_cacheinfo_id() for loadable modules Date: Fri, 28 Aug 2026 08:29:56 -0700 Message-ID: <20260828153002.10290-2-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828153002.10290-1-tony.luck@intel.com> References: <20260828153002.10290-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Qiuxu Zhuo get_cpu_cacheinfo_id() is a static inline that requires get_cpu_cacheinfo(), which is not exported. Modules that need to identify which cache instance a CPU belongs to therefore cannot use it. Move it out of line and export it. Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- include/linux/cacheinfo.h | 12 +----------- drivers/base/cacheinfo.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index fc879ac4cc4f..56fa646df0d1 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -82,6 +82,7 @@ struct cpu_cacheinfo { }; =20 struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); +int get_cpu_cacheinfo_id(int cpu, int level); int early_cache_level(unsigned int cpu); int init_cache_level(unsigned int cpu); int init_of_cache_level(unsigned int cpu); @@ -137,17 +138,6 @@ static inline struct cacheinfo *get_cpu_cacheinfo_leve= l(int cpu, int level) return NULL; } =20 -/* - * Get the id of the cache associated with @cpu at level @level. - * cpuhp lock must be held. - */ -static inline int get_cpu_cacheinfo_id(int cpu, int level) -{ - struct cacheinfo *ci =3D get_cpu_cacheinfo_level(cpu, level); - - return ci ? ci->id : -1; -} - #if defined(CONFIG_ARM64) || defined(CONFIG_ARM) #define use_arch_cache_info() (true) #else diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 70701d3bc81c..28d193bf6064 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -38,6 +38,23 @@ struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu) return ci_cacheinfo(cpu); } =20 +/** + * get_cpu_cacheinfo_id - Return the cache ID for a CPU and cache level + * @cpu: CPU number + * @level: Cache level + * + * The caller must hold the cpuhp lock. + * + * Return: Cache ID on success, or -1 if no matching cache exists. + */ +int get_cpu_cacheinfo_id(int cpu, int level) +{ + struct cacheinfo *ci =3D get_cpu_cacheinfo_level(cpu, level); + + return ci ? ci->id : -1; +} +EXPORT_SYMBOL_GPL(get_cpu_cacheinfo_id); + static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, struct cacheinfo *sib_leaf) { --=20 2.55.0 From nobody Sat Sep 26 23:35:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05F5210F0; Fri, 28 Aug 2026 15:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931018; cv=none; b=rShbNkTRw4os98tbLh58AjB4HVZe5K3gW4VH9+HQ3OvcQfUEdJWePXOeR6trldHseW28bhbL6D5CDZP5gLKoWxTpXPKDjtJO9Js/tNW0ErpEMJj8u36g6rQBAOZQpkCCM9rkzwPHCiNo3NMlfQYSBc6WSh6uzPj+em8Nfmp3yz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931018; c=relaxed/simple; bh=rE2WTk3WpUZaBZoXXGYa7EFPCgwt3qyRp5FAeJqsQyA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u+0GfEfkVNy1oUs4q9/O3aFTQNrS8FpFSmQ4moPqQwlbjWLD/Vdf3baLnh7pI1zJwwPwims+971NTo67zuuNcekGM6uTIQPPafns7mxswA/IerV6v2KcoWSlVknDe+qpRib61yK4tHlZEFmlamwVg6l3g6shkVc0lsGROAz7FP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iXJHqE/Y; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iXJHqE/Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787931017; x=1819467017; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rE2WTk3WpUZaBZoXXGYa7EFPCgwt3qyRp5FAeJqsQyA=; b=iXJHqE/YY0pzjxgV7Vkj7ilCjDURbgMn+kjDymprjxzeQo8qHx044dfP UZgUDoRbQuCJla02buPEPscfS4aqhwc6NkeTaESUYzCGeHSs8jodlUJyQ gH4MsxIfWjrlBZcMxjWwqEB4pcEBOBTv5YMQbjRYSIHvMH7nzF9U16BxK bB0T3a/BHHf0QKLxplAIFvwnJSlgHyVWlNytbc+f//DSz2R9FEbpzKrMF 1Cli5k9Xa2TCyju9o2gAJLxaQtSAI6uBirZcQp7vmUu1nSvrSZrgASbPj iwNJyj8ataqvnnzoHYwQmpNQOVmil4XHLwZxhtpmsxHvidM0gflurGE7U Q==; X-CSE-ConnectionGUID: 95WdJc/fSfC4GIec3fXXFQ== X-CSE-MsgGUID: 6A7Yj97IR82Ny4XIJo7C2w== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="99104585" X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="99104585" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 X-CSE-ConnectionGUID: P0i8nchNRgeXImeNtxYYKA== X-CSE-MsgGUID: OYXlBstrTHeY0IuAffERkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="291682275" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.223.138]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 From: Tony Luck To: Tony Luck Cc: Borislav Petkov , Qiuxu Zhuo , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Breno Leitao , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 2/7] x86/mce: Add enumeration for Intel bitfix filter reset Date: Fri, 28 Aug 2026 08:29:57 -0700 Message-ID: <20260828153002.10290-3-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828153002.10290-1-tony.luck@intel.com> References: <20260828153002.10290-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" IA32_CORE_CAPABILITIES enumerates the bitfix filter reset feature. Intel specifies two values for the threshold status field in the IA32_MCi_STATUS MSR: 1 =3D GREEN (threshold has not been reached) 2 =3D YELLOW (threshold exceeded, try bitfix filter reset) Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- arch/x86/include/asm/mce.h | 5 +++++ arch/x86/include/asm/msr-index.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index e575b702063d..9995176d6879 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -13,6 +13,7 @@ #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */ #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */ #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */ +#define MCG_TES_P BIT_ULL(11) /* Threshold-based error status supported = */ #define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */ #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ #define MCG_EXT_CNT_SHIFT 16 @@ -41,6 +42,10 @@ #define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */ #define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */ #define MCI_STATUS_AR BIT_ULL(55) /* Action required */ +#define MCI_STATUS_TES_MASK GENMASK_ULL(54, 53) +#define MCI_STATUS_TES(s) FIELD_GET(MCI_STATUS_TES_MASK, s) +#define MCI_STATUS_TES_GREEN 1 /* Threshold-based errors below thres= hold */ +#define MCI_STATUS_TES_YELLOW 2 /* Threshold-based errors above thre= shold */ #define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */ #define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38) #define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_S= HIFT) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 18c4be75e927..cea60d3ccb2b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -114,6 +114,8 @@ #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRI= TY_CAPS_BIT) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLI= T_LOCK_DETECT_BIT) +#define MSR_IA32_CORE_CAPS_BFF_RESET_BIT 9 +#define MSR_IA32_CORE_CAPS_BFF_RESET BIT(MSR_IA32_CORE_CAPS_BFF_RESET_B= IT) =20 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) --=20 2.55.0 From nobody Sat Sep 26 23:35:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77A9C361968; Fri, 28 Aug 2026 15:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931023; cv=none; b=u2PuBDQrWzVVhrGvK3aI7m+LX7e4ptlbeSs16nU4rmZ5SgZwGaLQWEwkvEUkcw1Wrtg3srWfPtVd3LfXiivYGPytKpuy83+rZVOxwItHY6eOGfS4yrL4K0VzDvOnrmuNo4IrJwz4+4HAvpD0YrLeqKlxIPPpBuhu3YpttWroUtI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931023; c=relaxed/simple; bh=YdNVhDNcqcNuZkeks7ysbwhNgbRkfvVgZV/jw4bmStY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UPft1EA27F+yiB5sX5jBqPCrY1jG8sFgyoBKtxqMv4y99wCkdXhsYL1gAPJfwrDiFCftI48928bdiPC518wyLgVjUESsdRE0nq93z/xwiI/XRJNR50DwfzHg4IXjIFzyqC+lLzVXX+1PwP8OLs6bwSFrfraPHM6CZADcjiRvJ38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Hws1ji8g; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Hws1ji8g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787931016; x=1819467016; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YdNVhDNcqcNuZkeks7ysbwhNgbRkfvVgZV/jw4bmStY=; b=Hws1ji8gixT5hmaV20Oc8x3mBogiF5JrWEZuK7leZC934DPHZP7D9HJz KMmXVNWXLN81B2o/wIXN2TPfPIW/JfiGp8X2xWh2p5xwrIj2Tw41Q8hMJ PTV2qei6tcDUPNVHPciEUSJdBruWCEMQJVVUknb6Qj8ObgV3eA6mF2ugG 3w8hyqLFcTpEf3HkfFBULu+axRrMEue488CGK1/mqJLHMq0H0XkUu8Amg uc/ISYjhG06bXWs2O5G1VjQ6VwFi7MM3WY4rWq92H0fYrSgIdlO7gAKzs VEGOymG9K3ZckiewZKv/MG22cxyYSSsIuV7CA5kGdJ9xtKE3mHYB7hTXB g==; X-CSE-ConnectionGUID: Bpvi0UuLQ7Gb/9In9W2tFA== X-CSE-MsgGUID: MLDrUttUT/KQQffQHJOQQw== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="99104589" X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="99104589" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 X-CSE-ConnectionGUID: 3W3gJfl3R1Gkb/Gs7Bxr+Q== X-CSE-MsgGUID: leqq57gOSzK71mjL9+fekg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="291682279" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.223.138]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 From: Tony Luck To: Tony Luck Cc: Borislav Petkov , Qiuxu Zhuo , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Breno Leitao , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 3/7] EDAC/intel-bff: Add stub Intel bitfix filter driver Date: Fri, 28 Aug 2026 08:29:58 -0700 Message-ID: <20260828153002.10290-4-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828153002.10290-1-tony.luck@intel.com> References: <20260828153002.10290-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check if the platform supports threshold based cache error reporting and the bitfix filter reset feature. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/edac/intel-bff.c | 54 ++++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 6 +++++ drivers/edac/Kconfig | 13 ++++++++++ drivers/edac/Makefile | 2 ++ 4 files changed, 75 insertions(+) create mode 100644 drivers/edac/intel-bff.c diff --git a/drivers/edac/intel-bff.c b/drivers/edac/intel-bff.c new file mode 100644 index 000000000000..905cbe58bc53 --- /dev/null +++ b/drivers/edac/intel-bff.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2026 Intel Corporation. */ + +/* + * Intel driver to reset bitfix filters when they overflow. + * + * Each bitfix filter has limited slots to track corrected errors. + * These slots can be filled by transient corrected errors (e.g., + * bit flips from particle strikes) that don't represent permanent + * hardware defects. + * + * When the filter overflows (yellow status), reset it to reclaim + * slots occupied by transient corrected errors. If the overflow + * repeats frequently after reset, it indicates persistent hardware + * defects that need attention: the system should be scheduled for + * servicing. + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static int __init bff_init(void) +{ + u64 core_caps, mcg_cap; + + if (!cpu_feature_enabled(X86_FEATURE_MCA)) + return -ENODEV; + rdmsrq(MSR_IA32_MCG_CAP, mcg_cap); + if (!(mcg_cap & MCG_TES_P)) + return -ENODEV; + + if (!cpu_feature_enabled(X86_FEATURE_CORE_CAPABILITIES)) + return -ENODEV; + rdmsrq(MSR_IA32_CORE_CAPS, core_caps); + if (!(core_caps & MSR_IA32_CORE_CAPS_BFF_RESET)) + return -ENODEV; + + return 0; +} + +module_init(bff_init); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tony Luck"); +MODULE_DESCRIPTION("Intel bitfix filter reset driver"); diff --git a/MAINTAINERS b/MAINTAINERS index 8014b9f8253e..edc50f7cb025 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9405,6 +9405,12 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/edac/igen6_edac.c =20 +EDAC-INTEL-BFF-RESET +M: Tony Luck +L: linux-edac@vger.kernel.org +S: Maintained +F: drivers/edac/intel-bff.c + EDAC-MPC85XX M: Johannes Thumshirn L: linux-edac@vger.kernel.org diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index a44b85c440ca..f7964cd9545e 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -280,6 +280,19 @@ config EDAC_IMH first used on the Diamond Rapids servers but may appear on others in the future. =20 +config EDAC_INTEL_BFF_RESET + tristate "Intel bitfix filter reset driver" + depends on X86_64 && X86_MCE_INTEL + help + Support for Intel systems that implement bitfix filters to + suppress repeated logging and signaling of the same corrected + error. Those filters can become clogged with transient errors + over time. Clearing the filter may make space for additional + hard errors. + + To compile this driver as a module, choose M here: the module + will be called intel_bff. + config EDAC_PND2 tristate "Intel Pondicherry2" depends on PCI && X86_64 && X86_MCE_INTEL diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index a37534300ab9..c2bae03f247b 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -66,6 +66,8 @@ obj-$(CONFIG_EDAC_I10NM) +=3D i10nm_edac.o skx_edac_comm= on.o imh_edac-y :=3D imh_base.o obj-$(CONFIG_EDAC_IMH) +=3D imh_edac.o skx_edac_common.o =20 +obj-$(CONFIG_EDAC_INTEL_BFF_RESET) +=3D intel-bff.o + obj-$(CONFIG_EDAC_HIGHBANK_MC) +=3D highbank_mc_edac.o obj-$(CONFIG_EDAC_HIGHBANK_L2) +=3D highbank_l2_edac.o =20 --=20 2.55.0 From nobody Sat Sep 26 23:35:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B7D1288C96; Fri, 28 Aug 2026 15:30:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931014; cv=none; b=TGrGAiijWoluZJuS8V/CaBvILiIuwlY99ozyIG7ghrwAcYXYyzcrR7+UwjK9QICfzBwHpUJzdpIzqDqOglz81UxTJikADJVRQk+dAEvxeWgSzRooULGHUaRpyLSxx5ogRG2g83cPOheeCsFBFcYgnW6yruA8AAv/ZdKq21XWLJg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931014; c=relaxed/simple; bh=EvYVX1jlXunQVQY2wapQxH15oGSKPDjk3N3QBKE/0U0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KHhtccnFIlMLVO8JT+jHyOw55qh1RWHOpd1IuCau6p16n7ChMv4FGh9fbNQ4WYB3pBd3srL65RQhPJC6SiQYpgYdMTGNr4uNqmyoH6XwKZNAkPJxnKKisEUcZ3dVmYN9SJAHjJ9f7bMvchjBruNUVyi263f5MxyiHQ4u+Zq3xtc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ENILynUc; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ENILynUc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787931010; x=1819467010; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EvYVX1jlXunQVQY2wapQxH15oGSKPDjk3N3QBKE/0U0=; b=ENILynUcNkgodrXUcYb/MWrZ1h1HgW7c65YFQqRgp8Pw2N9VSUfhBeEg vuYBsvXlI57nywPIxCcOj8Q4ZigdXjlXfO53Fi34EucFObILErFneLsKE ZttYqqEjfph1ow6M4E8GMT9jjle3IrqqQrslZfUqaVcg4UPKoqUYK5606 chx2yVbDBoWLxRU/pDM0nCfY+8Xq3bIZaY2jU8pw7+Re1zInzkkGKLhqG SuZWayWnrulvtwSwViXdyP5u2sfKVOU1xx1fk3wtwp5oQ+DVGRimq3dYP TzYNEfnB4iPVBVbj2G6bL/C8DN47MvazpCfrv+69dyykf58WDl6gWEm0s Q==; X-CSE-ConnectionGUID: 91B2Gl48RbiLc2b4Nd7SGg== X-CSE-MsgGUID: dp/Aj5OKTuO7Vbt1p8J7rQ== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="99104593" X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="99104593" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:10 -0700 X-CSE-ConnectionGUID: Y4uBGVy4THG9uoS3wSZ3QA== X-CSE-MsgGUID: OczJIe/qTqOH4FTiKMLqpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="291682282" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.223.138]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 From: Tony Luck To: Tony Luck Cc: Borislav Petkov , Qiuxu Zhuo , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Breno Leitao , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 4/7] EDAC/intel-bff: Add Diamond Rapids support Date: Fri, 28 Aug 2026 08:29:59 -0700 Message-ID: <20260828153002.10290-5-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828153002.10290-1-tony.luck@intel.com> References: <20260828153002.10290-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are potentially bitfix filters associated with each machine check bank. Only some banks may implement them. Machine check banks have varying scope. E.g. there is a separate L2 cache for each module, each instance has its own bitfix filter. Add information that will be used to map a pair to a unique instance number for a bitfix filter. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/edac/intel-bff.c | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/edac/intel-bff.c b/drivers/edac/intel-bff.c index 905cbe58bc53..f70c5e697dae 100644 --- a/drivers/edac/intel-bff.c +++ b/drivers/edac/intel-bff.c @@ -18,18 +18,55 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include +#include #include #include #include +#include #include =20 +#include #include +#include #include #include #include =20 +/* Machine check bank hardware unit types */ +enum bff_bank_type { + BFF_BANK_NONE =3D 0, + BFF_BANK_DCU, + BFF_BANK_DTLB, + BFF_BANK_MLC, + BFF_BANK_CCF, + BFF_BANK_HSF, + BFF_BANK_IOCACHE, +}; + +/* + * Mapping from machine check bank numbers on Diamond Rapids CPU, that are + * supported by a bitfix filter, to hardware unit type. + */ +static const enum bff_bank_type dmr_mcbanks[MAX_NR_BANKS] =3D { + [1] =3D BFF_BANK_DCU, + [2] =3D BFF_BANK_DTLB, + [3] =3D BFF_BANK_MLC, + [6] =3D BFF_BANK_CCF, + [13] =3D BFF_BANK_HSF, + [17] =3D BFF_BANK_IOCACHE +}; + +static const struct x86_cpu_id bff_cpu_ids[] __initconst =3D { + X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, dmr_mcbanks), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); + +static const enum bff_bank_type *bff_bank_types; + static int __init bff_init(void) { + const struct x86_cpu_id *m; u64 core_caps, mcg_cap; =20 if (!cpu_feature_enabled(X86_FEATURE_MCA)) @@ -44,6 +81,14 @@ static int __init bff_init(void) if (!(core_caps & MSR_IA32_CORE_CAPS_BFF_RESET)) return -ENODEV; =20 + m =3D x86_match_cpu(bff_cpu_ids); + if (!m) { + pr_info("CPU model not supported by the bitfix filter reset driver\n"); + return -ENODEV; + } + + bff_bank_types =3D (const enum bff_bank_type *)m->driver_data; + return 0; } =20 --=20 2.55.0 From nobody Sat Sep 26 23:35:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B03C226D18; Fri, 28 Aug 2026 15:30:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931022; cv=none; b=EB5v+ThziBs2Yvo2jc1PHCclXtkkTVdfNluQwcYQXIeHQqlRLHVv8t8fJPCsdOXXGwZXDoyP4Xj7zin+BH+6UL9dV4gJ/YGG0RCXtfhS3llti+n0mEJDgDq5C7BvmRpCnrD4UZJTdbtGOAduFq2QbIZ0VGUIhkUNkh/fsGvaJLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931022; c=relaxed/simple; bh=rfJT+Huyraak1YVrhZhCUl+qeiCLy0e0yZ+GR+xWVqA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZRqHVramfcbTLDAOJwYeve48zzXmps/5ll7nFsbmAe398v1/XcX1LBxW3/tfMta1fD8iGZYjGtl9BsuVJYV6sUAzzB6ZbFSRGNZzpM33HXFw7SGKyRsX2GF0ayb5phvTu41U0umI0uM1AdWiOGChK2UCYcdBdwjS8zZH6cTjB98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UIcdezGN; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UIcdezGN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787931017; x=1819467017; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rfJT+Huyraak1YVrhZhCUl+qeiCLy0e0yZ+GR+xWVqA=; b=UIcdezGNfbtyitybvq1sbD2YFgG52jZSvokKjwZ60JkJeqJx34v0aKVw STnYMCdf+xFnKqVsNja2RiEb1Cz+Bk/wrCQmZmjoR+cb0F2zPHiIMabwL TciTfGmO+Kv/rBX36HxC47CrZLDSgdKxwQAKVy0bwpClnuF9T4FYDFv5H Fg07g/oY9pqksfkCjIWmqW/ewzcLl5rdw0c6wtxjJNaTIbSbQFOFy6Mgw iotM4Rtt5qsnQMDtSotlRaYDzICt5oRiY6aaQHGAmDabmCJTWsd46KBBD rR/15/s95IcH5pvFyNyOsSez1VZtYqteBKx0drXvA+99SgVHmbU+fdmf4 Q==; X-CSE-ConnectionGUID: mTSK/UxUTMyaFRlr34Zy1A== X-CSE-MsgGUID: Gxj+wTkKTk6Cs0E8XRYCEg== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="99104597" X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="99104597" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:10 -0700 X-CSE-ConnectionGUID: 2S/vktQ6RY+JB+6hUzF+yg== X-CSE-MsgGUID: ngP5/F4lTEu1CHwf4LCmvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="291682285" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.223.138]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 From: Tony Luck To: Tony Luck Cc: Borislav Petkov , Qiuxu Zhuo , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Breno Leitao , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 5/7] EDAC/intel-bff: Reset bitfix filter when it overflows Date: Fri, 28 Aug 2026 08:30:00 -0700 Message-ID: <20260828153002.10290-6-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828153002.10290-1-tony.luck@intel.com> References: <20260828153002.10290-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get notifications for all errors logged in machine check banks. Skip any that do not indicate a bitfix filter overflow. Machine check banks are scoped to a hardware unit, so the reset has to be issued from a CPU within that unit. Use the CPU that reported the error. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/edac/intel-bff.c | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/edac/intel-bff.c b/drivers/edac/intel-bff.c index f70c5e697dae..c46d5255f34b 100644 --- a/drivers/edac/intel-bff.c +++ b/drivers/edac/intel-bff.c @@ -17,11 +17,14 @@ */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 +#include +#include #include #include #include #include #include +#include #include #include =20 @@ -32,6 +35,11 @@ #include #include =20 +/* Intel bitfix filter control register defines */ +#define MSR_MC0_BFF_CTL 0x000006c0 +#define MSR_MCx_BFF_CTL(x) (MSR_MC0_BFF_CTL + (x)) +#define MCI_BFF_RESET BIT_ULL(0) + /* Machine check bank hardware unit types */ enum bff_bank_type { BFF_BANK_NONE =3D 0, @@ -64,6 +72,38 @@ MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); =20 static const enum bff_bank_type *bff_bank_types; =20 +static void bff_reset_and_report(struct mce *mce) +{ + /* Reset bitfix filter using the CPU that logged the yellow status */ + if (wrmsrq_on_cpu(mce->extcpu, MSR_MCx_BFF_CTL(mce->bank), MCI_BFF_RESET)) + pr_warn("Failed to reset bitfix filter for CPU %d Bank %d\n", + mce->extcpu, mce->bank); +} + +static int bff_mce_notify(struct notifier_block *nb, unsigned long val, vo= id *data) +{ + struct mce *mce =3D data; + + /* TES is undefined for uncorrected errors. */ + if (mce->status & MCI_STATUS_UC) + return NOTIFY_DONE; + + if (MCI_STATUS_TES(mce->status) !=3D MCI_STATUS_TES_YELLOW) + return NOTIFY_DONE; + + if (mce->bank >=3D MAX_NR_BANKS || bff_bank_types[mce->bank] =3D=3D BFF_B= ANK_NONE) + return NOTIFY_DONE; + + bff_reset_and_report(mce); + + return NOTIFY_DONE; +} + +static struct notifier_block bff_notifier =3D { + .notifier_call =3D bff_mce_notify, + .priority =3D MCE_PRIO_EDAC, +}; + static int __init bff_init(void) { const struct x86_cpu_id *m; @@ -89,10 +129,18 @@ static int __init bff_init(void) =20 bff_bank_types =3D (const enum bff_bank_type *)m->driver_data; =20 + mce_register_decode_chain(&bff_notifier); + return 0; } =20 +static void __exit bff_exit(void) +{ + mce_unregister_decode_chain(&bff_notifier); +} + module_init(bff_init); +module_exit(bff_exit); =20 MODULE_LICENSE("GPL"); MODULE_AUTHOR("Tony Luck"); --=20 2.55.0 From nobody Sat Sep 26 23:35:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C7BA360EE2; Fri, 28 Aug 2026 15:30:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931024; cv=none; b=tFqQWxvjvXxTa8lf/xSgc1DpQrdVrO5jKvxJKn98kGdHDcWgX5uXBFC6BwZQ5XSZH1JByop95bwT1K4VD6tLkjKC5LXAqV6RW/C3BJHXujU8iLAqJ9xYRzWaanPU/lpe+9g208n7yEFRMlDLjQn5ZnjjQFFUS3qYZmblWMjN6Hs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931024; c=relaxed/simple; bh=TZBaltimlxJ09g+m37Hr8LTGXn/rNqzVEM9ivilaUU8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bQOFGKNTTbM7+DB14qwQZHK5Uz5wKAoXoR+jkTlkAWV8vWmKujiIrwRzG5thb/9WVtG7orY4RPVZq45h8/2Q6imRiEX9MUhxXuw/m8v9xChilvB1FYJMuFuctbTzEY9VNFieDurPAmtS6WlUNF0lYqdczVoWkCA9+lf8MzjGSGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hA+fHZXS; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hA+fHZXS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787931022; x=1819467022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TZBaltimlxJ09g+m37Hr8LTGXn/rNqzVEM9ivilaUU8=; b=hA+fHZXS/swdgADUeqLfTyPkRldQJznUSOrsrOOXYdrJGm/w0ZrhvcCq hJsCCxXa6QiYLUxZFVcyVssmLdcfsKkSur64IqOX1fSDLl0uGM0JY8ud9 oGoVwiP5ifecsUM/4ATG0yq1pxw3I3NKqEorgnLsv5Z47zLVXHJCh9chp hFFOHZv7i2YfPBoC+fRatsQfAaS04lkECUwZpqOc9ltf68GkUOnscNp9j NBOMTPMGzeTdf1G2JzsU51+LOmF7lWgBarufahg1GKge36n5zNqhNZGaI sI1i1EWKI2NgmeVhqf7d/nGDiLwpKIcWbuFtyv2vsfFZs4Vv96RPQY1Ve Q==; X-CSE-ConnectionGUID: wk3mNG5iR6SuqlSTOvsInA== X-CSE-MsgGUID: 8ximVwkPRa6iD/3TCjo+gw== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="99104601" X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="99104601" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:10 -0700 X-CSE-ConnectionGUID: kjXiaU0DTkmsq+gk1XJaSg== X-CSE-MsgGUID: lAhY5Xt8S0GqKoyYdq6ZgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="291682288" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.223.138]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:09 -0700 From: Tony Luck To: Tony Luck Cc: Borislav Petkov , Qiuxu Zhuo , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Breno Leitao , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 6/7] EDAC/intel-bff: Compute unique ID for overflowed filter Date: Fri, 28 Aug 2026 08:30:01 -0700 Message-ID: <20260828153002.10290-7-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828153002.10290-1-tony.luck@intel.com> References: <20260828153002.10290-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Each L2 cache instance has its own bitfix filter, but always reports errors in machine check bank 3 (on Diamond Rapids). Compute a unique bitfix filter instance number based on the CPU that logged the error and the machine check bank number. Special-case the banks associated with the Integrated Memory Hub (IMH). Here the "even" numbered CPU modules are associated with IMH0 and the "odd" modules with IMH1. The unique id will be used to store a time stamp of when the bitfix filter overflowed so that frequent overflows can be logged. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/edac/intel-bff.c | 80 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/edac/intel-bff.c b/drivers/edac/intel-bff.c index c46d5255f34b..06a79745c2fb 100644 --- a/drivers/edac/intel-bff.c +++ b/drivers/edac/intel-bff.c @@ -19,13 +19,18 @@ =20 #include #include +#include +#include #include +#include #include #include #include +#include #include #include #include +#include #include =20 #include @@ -72,12 +77,87 @@ MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); =20 static const enum bff_bank_type *bff_bank_types; =20 +/* Diamond Rapids maps APICID[2] to the IMH instance within a socket. */ +#define APICID_IMH_NUM GENMASK(2, 2) +#define IMH_NUM(apicid) FIELD_GET(APICID_IMH_NUM, apicid) +#define NUM_IMH_PER_SOCKET 2 + +static void bff_set_imh_id(struct mce *mce, unsigned long *id) +{ + int imh_num; + + imh_num =3D NUM_IMH_PER_SOCKET * topology_physical_package_id(mce->extcpu= ) + + IMH_NUM(mce->apicid); + + *id |=3D imh_num; +} + +static bool bff_set_cache_id(int cpu, int level, unsigned long *id) +{ + int cacheid; + + guard(cpus_read_lock)(); + + cacheid =3D get_cpu_cacheinfo_id(cpu, level); + if (cacheid =3D=3D -1) { + pr_warn("Could not get L%d cache id for CPU %d\n", level, cpu); + return false; + } + + *id |=3D cacheid; + + return true; +} + +/* + * Cache IDs are only unique within a cache level. + * Include the MCA bank number so each BFF-capable hardware + * resource has a unique tracking ID. + */ +#define BFF_ID_BANK_FIELD GENMASK(63, 32) + +static unsigned long bff_get_id(struct mce *mce) +{ + unsigned long id =3D FIELD_PREP(BFF_ID_BANK_FIELD, mce->bank); + + switch (bff_bank_types[mce->bank]) { + case BFF_BANK_DCU: + case BFF_BANK_DTLB: + if (!bff_set_cache_id(mce->extcpu, 1, &id)) + return ULONG_MAX; + break; + + case BFF_BANK_MLC: + if (!bff_set_cache_id(mce->extcpu, 2, &id)) + return ULONG_MAX; + break; + + case BFF_BANK_CCF: + if (!bff_set_cache_id(mce->extcpu, 3, &id)) + return ULONG_MAX; + break; + + case BFF_BANK_HSF: + case BFF_BANK_IOCACHE: + bff_set_imh_id(mce, &id); + break; + + default: + return ULONG_MAX; + } + + return id; +} + static void bff_reset_and_report(struct mce *mce) { /* Reset bitfix filter using the CPU that logged the yellow status */ if (wrmsrq_on_cpu(mce->extcpu, MSR_MCx_BFF_CTL(mce->bank), MCI_BFF_RESET)) pr_warn("Failed to reset bitfix filter for CPU %d Bank %d\n", mce->extcpu, mce->bank); + + /* Placeholder use of bff_get_id() */ + pr_debug("unique_id =3D 0x%lx\n", bff_get_id(mce)); } =20 static int bff_mce_notify(struct notifier_block *nb, unsigned long val, vo= id *data) --=20 2.55.0 From nobody Sat Sep 26 23:35:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E73913630BF; Fri, 28 Aug 2026 15:30:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931024; cv=none; b=C+14EX8ZTuwrqBJ3R/RAQGdBf8OELZ3A4aJFoTcU8zVtsYJQe/eVNOiPJxVruujTVG5IRHUvGwSYm3IAnC3Vmi9R3wNuVozuqFT9j0CyvFcZI68Ic8eAAZq8ICeOqk7F17mXkiLABTqaYxFmUtafK58aAvHYhtlNW9Hi5znJ22Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787931024; c=relaxed/simple; bh=gxPoFx6SdnptXG3Hw+pks3NJkGqlI1aInjSfIWG4UM4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=raoJlfKGadISD7L0P0sDuHlT/LR7blEa0aGgcMfHZtBKlDHILic/Tnqecuc1MZtjG6pNKzDQaCf7I2gyIN/1r+cch8QDH6WmVgYSRrit+JGVWXMR2qs3CG1XlwS8Dl4AZL9l5tsNQdPSNlZQTjAMKXEaVtq4aMJqsbTMIlKKwSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FX8dQNt7; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FX8dQNt7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787931019; x=1819467019; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gxPoFx6SdnptXG3Hw+pks3NJkGqlI1aInjSfIWG4UM4=; b=FX8dQNt7XeF2CilNOvx98Zqn4EZakKm+eDd+Mx/YWRlLGjNpMuRzprz2 Blh0WLr9gyZvHbWQQjqJWJnQ47fTwALGJwwNz7oMc6uzcm/k+HDYB99fN sUbQSLvFhJV3m6kegKij5q2I7Hkr3T9s7MFEpufzu5ThnDRz0VMZY3Smt 8PGx044/ROFJAsraNUl5g8MUgUqIU8OjZOYHCBCprWgCPMIRhc8A3DOS2 2zo0gv/arzJzn9Bu63q+PysH/OTRiKJB4Ir1Qvucmggw/faUSXZ0TVUqO ogDJNb8XGdoKzw6uJtz1EAB7JHX/Oq9IpZhua3uKCIWjiQll7qzZ0DCAp g==; X-CSE-ConnectionGUID: xFzyr5w1SdudueKGgMvZKQ== X-CSE-MsgGUID: G4oKpc6yQvavy1Om3O2bng== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="99104605" X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="99104605" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:10 -0700 X-CSE-ConnectionGUID: 6aL0J0V6SnGOTVglG3NbKw== X-CSE-MsgGUID: Vh4gdHBASvOJyPNYILowYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,248,1779174000"; d="scan'208";a="291682292" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.223.138]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 08:30:10 -0700 From: Tony Luck To: Tony Luck Cc: Borislav Petkov , Qiuxu Zhuo , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Breno Leitao , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 7/7] EDAC/intel-bff: Report frequent filter overflows Date: Fri, 28 Aug 2026 08:30:02 -0700 Message-ID: <20260828153002.10290-8-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828153002.10290-1-tony.luck@intel.com> References: <20260828153002.10290-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If an instance of a bitfix filter contains some transient errors built up over time, then resetting the filter will free up slots in the filter to store persistent errors. Save a timestamp when "yellow" status is seen and clear the filter. Log at KERN_WARNING level if the overflow occurred quickly after a previous overflow on the same bitfix filter instance. Use KERN_NOTICE for first, or long delayed, overflow. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/edac/intel-bff.c | 72 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/edac/intel-bff.c b/drivers/edac/intel-bff.c index 06a79745c2fb..adf2ec343129 100644 --- a/drivers/edac/intel-bff.c +++ b/drivers/edac/intel-bff.c @@ -25,13 +25,17 @@ #include #include #include +#include #include +#include #include #include #include #include +#include #include #include +#include =20 #include #include @@ -40,6 +44,16 @@ #include #include =20 +/* + * A 10-minute observation period helps distinguish between: + * + * - A long-term accumulation of transient corrected errors + * (filter stays clear after reset). + * + * - Permanent defects (filter overflows again quickly). + */ +#define BFF_OVERFLOW_INTERVAL secs_to_jiffies(10 * 60) + /* Intel bitfix filter control register defines */ #define MSR_MC0_BFF_CTL 0x000006c0 #define MSR_MCx_BFF_CTL(x) (MSR_MC0_BFF_CTL + (x)) @@ -77,6 +91,8 @@ MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); =20 static const enum bff_bank_type *bff_bank_types; =20 +static DEFINE_XARRAY(bff_bank_xa); + /* Diamond Rapids maps APICID[2] to the IMH instance within a socket. */ #define APICID_IMH_NUM GENMASK(2, 2) #define IMH_NUM(apicid) FIELD_GET(APICID_IMH_NUM, apicid) @@ -149,6 +165,41 @@ static unsigned long bff_get_id(struct mce *mce) return id; } =20 +/* + * Save current timestamp for bff_id. Return true if it is within + * BFF_OVERFLOW_INTERVAL of previous timestamp for this bff_id. + */ +static bool bff_overflow_is_frequent(unsigned long bff_id) +{ + unsigned long now =3D jiffies, interval_end; + unsigned long *ts; + + if (bff_id =3D=3D ULONG_MAX) + return false; + + ts =3D xa_load(&bff_bank_xa, bff_id); + if (!ts) { + ts =3D kzalloc_obj(*ts); + if (!ts) { + pr_warn("Failed to allocate timestamp for bitfix filter 0x%lx\n", bff_i= d); + return false; + } + if (xa_is_err(xa_store(&bff_bank_xa, bff_id, ts, GFP_KERNEL))) { + kfree(ts); + pr_warn("Failed to record timestamp for bitfix filter 0x%lx\n", bff_id); + return false; + } + *ts =3D now; + + return false; + } + + interval_end =3D *ts + BFF_OVERFLOW_INTERVAL; + *ts =3D now; + + return time_before(now, interval_end); +} + static void bff_reset_and_report(struct mce *mce) { /* Reset bitfix filter using the CPU that logged the yellow status */ @@ -156,8 +207,18 @@ static void bff_reset_and_report(struct mce *mce) pr_warn("Failed to reset bitfix filter for CPU %d Bank %d\n", mce->extcpu, mce->bank); =20 - /* Placeholder use of bff_get_id() */ - pr_debug("unique_id =3D 0x%lx\n", bff_get_id(mce)); + /* + * Use the unique id for the bitfix filter instance that overflowed and + * check if this is a repeat within the BFF_OVERFLOW_INTERVAL. If it + * is, then report at WARN severity as the user may want to take action. + */ + if (bff_overflow_is_frequent(bff_get_id(mce))) { + pr_warn_ratelimited(HW_ERR "Socket %d CPU %d Bank %d bitfix filter overf= lowed frequently\n", + mce->socketid, mce->extcpu, mce->bank); + } else { + pr_notice_ratelimited(HW_ERR "Socket %d CPU %d Bank %d bitfix filter ove= rflowed\n", + mce->socketid, mce->extcpu, mce->bank); + } } =20 static int bff_mce_notify(struct notifier_block *nb, unsigned long val, vo= id *data) @@ -216,7 +277,14 @@ static int __init bff_init(void) =20 static void __exit bff_exit(void) { + unsigned long bff_id; + unsigned long *ts; + mce_unregister_decode_chain(&bff_notifier); + + xa_for_each(&bff_bank_xa, bff_id, ts) + kfree(ts); + xa_destroy(&bff_bank_xa); } =20 module_init(bff_init); --=20 2.55.0