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The TI K3 mux routers which route the GPIO input events or Time-Sync events b/w peripherals instead of routing to a CPU. Refer Section 10.2 and 10.2.1 of https://www.ti.com/lit/pdf/sprujb4 Signed-off-by: Rahul Sharma --- .../mux/ti,am62l-event-mux-router.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/ti,am62l-event-mu= x-router.yaml diff --git a/Documentation/devicetree/bindings/mux/ti,am62l-event-mux-route= r.yaml b/Documentation/devicetree/bindings/mux/ti,am62l-event-mux-router.ya= ml new file mode 100644 index 000000000000..a5ba7f78a156 --- /dev/null +++ b/Documentation/devicetree/bindings/mux/ti,am62l-event-mux-router.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/ti,am62l-event-mux-router.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Event Multiplexer on K3 SoCs + +maintainers: + - Rahul Sharma + +description: + The TI K3 mux routers routes the GPIO input events or Time + Sync events between peripherals instead of routing to a CPU. + +allOf: + - $ref: mux-controller.yaml# + +properties: + compatible: + const: ti,am62l-event-mux-router + + reg: + description: Register base address and size. + maxItems: 1 + + '#mux-control-cells': + const: 1 + description: + Number of cells in a mux control specifier. This should be 1. + The cell specifies which mux control to use (0-based index). + + ti,reg-mask-val: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: Register offset (relative to reg base) + - description: Bit mask for the mux control bits + - description: Value to write when mux is active (state 1) + minItems: 1 + description: | + Array of triplets specifying register offset, mask, and value for ea= ch + mux control. Each triplet contains: + - register offset (relative to reg base) + - bit mask for the mux control bits + - value to write when mux is active (state 1) + + idle-states: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Idle state for each mux control. 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charset="utf-8" The driver supports event muxing routers like gpio mux router and timesync router. This driver is adaptation of original reg-mux driver, along with changes specific to support TI's mux router. The idle states this driver supports are only 2 which active(represented by 1 in dt-node) and in-active(represented by 0 in dt-node). Signed-off-by: Rahul Sharma --- drivers/mux/Kconfig | 15 +++ drivers/mux/Makefile | 2 + drivers/mux/ti-k3-event-mux.c | 235 ++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+) create mode 100644 drivers/mux/ti-k3-event-mux.c diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig index eb34457beaab..58739a01f0d5 100644 --- a/drivers/mux/Kconfig +++ b/drivers/mux/Kconfig @@ -83,6 +83,21 @@ config MUX_RZV2H_VBENCTL To compile the driver as a module, choose M here: the module will be called mux-rzv2h-vbenctl. =20 +config MUX_TI_K3_EVENT_ROUTER + tristate "TI Event Mux Router using MMIO registers" + depends on OF && (REGMAP_MMIO || COMPILE_TEST) + help + This is extension of MMIO mux for timesync router and gpiomux + routers on TI K3 SoCs. This driver supports the 3-field format for + mux control: . + + The driver allows configuration of hardware mux routers using + memory-mapped registers. It's based on the mmio-mux driver but + supports the extended 3-field format for more precise control. + + To compile the driver as a module, choose M here: the module will + be called mux-ti-k3-event. + endmenu =20 endif # MULTIPLEXER diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile index 0854c04613b9..114abf88b75e 100644 --- a/drivers/mux/Makefile +++ b/drivers/mux/Makefile @@ -9,6 +9,7 @@ mux-adgs1408-objs :=3D adgs1408.o mux-gpio-objs :=3D gpio.o mux-mmio-objs :=3D mmio.o mux-rzv2h-vbenctl-objs :=3D rzv2h-vbenctl.o +mux-ti-k3-event-objs :=3D ti-k3-event-mux.o =20 obj-$(CONFIG_MULTIPLEXER) +=3D mux-core.o obj-$(CONFIG_MUX_ADG792A) +=3D mux-adg792a.o @@ -16,3 +17,4 @@ obj-$(CONFIG_MUX_ADGS1408) +=3D mux-adgs1408.o obj-$(CONFIG_MUX_GPIO) +=3D mux-gpio.o obj-$(CONFIG_MUX_MMIO) +=3D mux-mmio.o obj-$(CONFIG_MUX_RZV2H_VBENCTL) +=3D mux-rzv2h-vbenctl.o +obj-$(CONFIG_MUX_TI_K3_EVENT_ROUTER) +=3D mux-ti-k3-event.o diff --git a/drivers/mux/ti-k3-event-mux.c b/drivers/mux/ti-k3-event-mux.c new file mode 100644 index 000000000000..2469500d1b48 --- /dev/null +++ b/drivers/mux/ti-k3-event-mux.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MMIO register bit-field controlled multiplexer driver + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com + * + * Based on drivers/mux/mmio.c by Philipp Zabel + * Modified to support 3-field format: reg-offset, mask & value + * + * Author: Rahul Sharma + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MUX_ENABLE_INTR BIT(16) + +struct mux_ti_k3_event { + struct regmap *regmap; + u32 reg; + u32 mask; + u32 value; +}; + +struct mux_ti_k3_event_chip { + struct mux_chip *mux_chip; + struct mux_ti_k3_event *fields; + int num_fields; + u32 *saved_states; +}; + +static int mux_ti_k3_event_suspend(struct device *dev) +{ + struct mux_ti_k3_event_chip *chip =3D dev_get_drvdata(dev); + int i, ret; + + if (!chip->saved_states) { + chip->saved_states =3D devm_kcalloc(dev, chip->num_fields, + sizeof(u32), GFP_KERNEL); + if (!chip->saved_states) + return -ENOMEM; + } + + for (i =3D 0; i < chip->num_fields; i++) { + struct mux_ti_k3_event *field =3D &chip->fields[i]; + + ret =3D regmap_read(field->regmap, field->reg, + &chip->saved_states[i]); + if (ret) + return ret; + } + + return 0; +} + +static int mux_ti_k3_event_resume(struct device *dev) +{ + struct mux_ti_k3_event_chip *chip =3D dev_get_drvdata(dev); + int i, ret; + + if (!chip->saved_states) + return 0; + + for (i =3D 0; i < chip->num_fields; i++) { + struct mux_ti_k3_event *field =3D &chip->fields[i]; + + ret =3D regmap_write(field->regmap, field->reg, + chip->saved_states[i]); + if (ret) + return ret; + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(mux_ti_k3_event_pm_ops, + mux_ti_k3_event_suspend, + mux_ti_k3_event_resume); + +/* + * State behavior: + * - state 0: Clears the mask bits in the target register (inactive state) + * - state 1: Sets both the value bits and enable bit (bit 16) in the regi= ster + */ +static int mux_ti_k3_event_set(struct mux_control *mux, int state) +{ + struct mux_ti_k3_event *fields =3D mux_chip_priv(mux->chip); + struct mux_ti_k3_event *field =3D &fields[mux_control_get_index(mux)]; + + if (!state) + return regmap_update_bits(field->regmap, field->reg, field->mask, 0); + + return regmap_update_bits(field->regmap, field->reg, field->mask | MUX_EN= ABLE_INTR, + field->value | MUX_ENABLE_INTR); +} + +static const struct mux_control_ops mux_ti_k3_event_ops =3D { + .set =3D mux_ti_k3_event_set, +}; + +static const struct regmap_config mux_ti_k3_event_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int mux_ti_k3_event_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct mux_ti_k3_event_chip *chip; + struct mux_ti_k3_event *fields; + struct mux_chip *mux_chip; + struct regmap *regmap; + void __iomem *base; + int num_fields; + int ret; + int i; + + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + return dev_err_probe(dev, -ENODEV, + "failed to get base address\n"); + } else { + regmap =3D devm_regmap_init_mmio(dev, base, &mux_ti_k3_event_regmap_cfg); + } + if (IS_ERR(regmap)) { + iounmap(base); + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to get regmap\n"); + } + + ret =3D of_property_count_u32_elems(np, "ti,reg-mask-val"); + if (!ret || ret % 3) { + ret =3D -EINVAL; + dev_err(dev, "ti,reg-mask-val property missing or invalid: %d\n", + ret); + return ret; + } + + num_fields =3D ret / 3; + mux_chip =3D devm_mux_chip_alloc(dev, num_fields, num_fields * + sizeof(*fields)); + if (IS_ERR(mux_chip)) + return PTR_ERR(mux_chip); + + fields =3D mux_chip_priv(mux_chip); + chip->mux_chip =3D mux_chip; + chip->fields =3D fields; + chip->num_fields =3D num_fields; + + platform_set_drvdata(pdev, chip); + + for (i =3D 0; i < num_fields; i++) { + struct mux_control *mux =3D &mux_chip->mux[i]; + s32 idle_state =3D MUX_IDLE_AS_IS; + u32 reg, mask, value; + + ret =3D of_property_read_u32_index(np, "ti,reg-mask-val", + 3 * i, ®); + if (!ret) + ret =3D of_property_read_u32_index(np, "ti,reg-mask-val", + 3 * i + 1, &mask); + if (!ret) + ret =3D of_property_read_u32_index(np, "ti,reg-mask-val", + 3 * i + 2, &value); + if (ret < 0) { + dev_err(dev, "field %d: failed to read ti,reg-mask-val property: %d\n", + i, ret); + return ret; + } + + /* Validate that value bits are within mask */ + if (value & ~mask) { + dev_err(dev, "field %d: value 0x%x has bits outside mask 0x%x\n", + i, value, mask); + return -EINVAL; + } + + fields[i].regmap =3D regmap; + fields[i].reg =3D reg; + fields[i].mask =3D mask; + fields[i].value =3D value; + + /* This driver supports binary mux (2 states: 0 and active) */ + mux->states =3D 2; + + of_property_read_u32_index(np, "idle-states", i, + (u32 *)&idle_state); + if (idle_state !=3D MUX_IDLE_AS_IS) { + if (idle_state < 0 || idle_state >=3D mux->states) { + dev_err(dev, "field: %d: out of range idle state %d\n", + i, idle_state); + return -EINVAL; + } + + mux->idle_state =3D idle_state; + } + } + + mux_chip->ops =3D &mux_ti_k3_event_ops; + + return devm_mux_chip_register(dev, mux_chip); +} + +static const struct of_device_id mux_ti_k3_event_dt_ids[] =3D { + { .compatible =3D "ti,am62l-event-mux-router", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mux_ti_k3_event_dt_ids); + +static struct platform_driver mux_ti_k3_event_driver =3D { + .driver =3D { + .name =3D "ti-k3-event-mux", + .of_match_table =3D mux_ti_k3_event_dt_ids, + .pm =3D &mux_ti_k3_event_pm_ops, + }, + .probe =3D mux_ti_k3_event_probe, +}; +module_platform_driver(mux_ti_k3_event_driver); + +MODULE_DESCRIPTION("TI K3 Bit-field Controlled Event Multiplexer driver"); +MODULE_AUTHOR("Rahul Sharma "); +MODULE_LICENSE("GPL"); --=20 2.34.1