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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4bab2d593; Fri, 28 Aug 2026 14:52:04 +0800 (GMT+08:00) From: Damon Ding To: Andrzej Hajda , Neil Armstrong , Robert Foss , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sandy Huang , Heiko Stuebner , Andy Yan Cc: Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Dmitry Baryshkov , Marek Szyprowski , Sebastian Reichel , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Damon Ding , Conor Dooley Subject: [PATCH v8 1/5] dt-bindings: display: bridge: analogix-dp: Add data-lanes support for endpoint Date: Fri, 28 Aug 2026 14:51:49 +0800 Message-Id: <20260828065153.590802-2-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260828065153.590802-1-damon.ding@rock-chips.com> References: <20260828065153.590802-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0aa04723ce3f03a8kunm9cc188d5188338 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZQ0xKS1YdSEhMTh5LTR hISElWFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSEpKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=Ljed/ziL5cCkMGijIK1KOZtH1Vil1rHKaBmH09fh4U6BYzvb02NYrmVqlDCeuUV/Kf4kiCI8shVBRFYb5aY5yLaWgfI+s3Wd8eptjWi2SSnSj5HGaGRixQ8Nu4RYZHph3Y5swHR+DfaKbZrUc9s5FksIvNB4i7jId7Gi2WaKRNI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=gbO4NOwH9/N0sj4hUDr89N79K9dV9ulbx0CXUgmsDFg=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add data-lanes property support to the port@1 endpoint for physical lane mapping configuration. Lane mapping is mainly used for below scenarios: 1. Correct PCB lane swap and differential line routing crossover without hardware changes; 2. Adapt mismatched lane pin definitions between SoC and eDP panel; 3. Support multiple panel hardware variants on the same board by configuring data-lanes in device tree only. Additionally, add data-lanes setting in Rockchip eDP DT node example to show actual lane mapping usage. Acked-by: Conor Dooley Reviewed-by: Sebastian Reichel Reviewed-by: Luca Ceresoli Signed-off-by: Damon Ding --- Changes in v2: - Add lane mapping application scenarios in commit message. - Remove redundant deprecated property 'data-lanes' for eDP node. - Update port@1 $ref to /schemas/graph.yaml#/$defs/port-base. Changes in v3: - Squash data-lanes adjustment of Rockchip eDP DT example into this commit. - Add unevaluatedProperties: false to both the port@1 and endpoint nodes. Changes in v5 - Add Acked-by and Reviewed-by tags. Changes in v8 - Add Reviewed-by tags. --- .../bindings/display/bridge/analogix,dp.yaml | 19 ++++++++++++++----- .../rockchip/rockchip,analogix-dp.yaml | 1 + 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,dp.y= aml b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml index 62f0521b0924..ecf206871cdd 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml @@ -42,13 +42,22 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/properties/port - description: - Input node to receive pixel data. + description: Input node to receive pixel data. =20 port@1: - $ref: /schemas/graph.yaml#/properties/port - description: - Port node with one endpoint connected to a dp-connector node. + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Port node with one endpoint connected to sink device = node. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + minItems: 1 + maxItems: 4 + items: + enum: [ 0, 1, 2, 3 ] =20 required: - port@0 diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,an= alogix-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchi= p,analogix-dp.yaml index 6548f157fd96..39dafe75a680 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-= dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-= dp.yaml @@ -160,6 +160,7 @@ examples: reg =3D <1>; =20 edp_out_panel: endpoint { + data-lanes =3D <0 1>; remote-endpoint =3D <&panel_in_edp>; }; }; --=20 2.34.1 From nobody Sat Sep 26 23:52:13 2026 Received: from mail-m15574.qiye.163.com (mail-m15574.qiye.163.com [101.71.155.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3C653D668F; Fri, 28 Aug 2026 06:57:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787900249; cv=none; b=mH3fXVLfbXFv1mTfzR4B6edgzaNUXeubzEl5SZ8rkYZsqacp09wJ2rONzOuPY4AjJdF8X61EznZ/V/enAUMQzmp6I0cDcNpAFyB9RLDefOwa+7PlSg6lGCnnPKapn4SIsgtUH1DbtsQgMFWSDckVTx4HM3d4jy8P76nDhoMbpQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787900249; c=relaxed/simple; bh=mowNlomkjWV8WhtYoTKyfiaWwBDsTac8oQVst65R16Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qASareZ+HQq3LAO2KNciJSsw1LwldyZha2wpPjmgJxGmEOY1VjotpyYc+Kh5FOhCivF7PGp1cW8dCoSO23S8Po22b3XTaUe2BClapYPWoID4gOMLmGwErTQYC1EZJX3OtN8sSu/JExSSLNeQuQFT7UFLpQutsPmyaVuHb0lAZc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=J3ln/bxy; arc=none smtp.client-ip=101.71.155.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="J3ln/bxy" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4bab2d5a4; Fri, 28 Aug 2026 14:52:05 +0800 (GMT+08:00) From: Damon Ding To: Andrzej Hajda , Neil Armstrong , Robert Foss , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sandy Huang , Heiko Stuebner , Andy Yan Cc: Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Dmitry Baryshkov , Marek Szyprowski , Sebastian Reichel , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Damon Ding Subject: [PATCH v8 2/5] drm/dp: Add helper to validate DP lane counts Date: Fri, 28 Aug 2026 14:51:50 +0800 Message-Id: <20260828065153.590802-3-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260828065153.590802-1-damon.ding@rock-chips.com> References: <20260828065153.590802-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0aa04723d5e203a8kunm9cc188d518834a X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZGk4aGlYaSEMdSEsZSU IeQ0lWFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSU9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=J3ln/bxybGTsOfkGBbZzKL9bXT2jZ9+ygl5ZAisrNMxtrVWSl2FG5ZFDMbj6iGPWwecOCgPNJFC+PF3O1qIsbsDr/VcpySVQUJRnOxamoNBrZvltJ9/Duo8jBMIzVAjRuvyhGVnF5/X9fvXA1sjPqaTYubqoh+eUn2HVj5d3WX0=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=3D3tCxbxiOqvsJFvLlKoOy9RkGLmHyoV0izPMCA9ZDc=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add a generic helper function drm_dp_lane_count_is_valid() to check if a DisplayPort lane count is valid. According to the DP specification, only 1, 2, or 4 lanes are supported. This helper avoids duplicating DP lane count validation logic across individual DisplayPort drivers. Suggested-by: Luca Ceresoli Reviewed-by: Luca Ceresoli Signed-off-by: Damon Ding --- Changes in v6: - Add Reviewed-by tag. --- include/drm/display/drm_dp_helper.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_= dp_helper.h index ab16c1be3900..5b05a7fbe174 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -139,6 +139,12 @@ bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, c= onst u8 dpcd[DP_RECEIVER_C =20 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); =20 +static inline bool +drm_dp_lane_count_is_valid(int lane_count) +{ + return lane_count =3D=3D 1 || lane_count =3D=3D 2 || lane_count =3D=3D 4; +} + static inline int drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { --=20 2.34.1 From nobody Sat Sep 26 23:52:13 2026 Received: from mail-m1973180.qiye.163.com (mail-m1973180.qiye.163.com [220.197.31.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58CF9420475; Fri, 28 Aug 2026 11:28:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.80 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787916520; cv=none; b=qiGXChnE8DWaeRzfzhyFK4LAtfLyC+/Uxlwe/c2xL7hqphl7PCx64OhisrSyng0DGCB46cL0EiztKJCjC2sSBQ04p7cUQJeBnZWVJcztmPWdKT7IPYN1B4Lp3qpyReN31PCpoJLqT0x2dTfWNBfNLo+5k3L8Xi4zg8T/j3iBO/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787916520; c=relaxed/simple; bh=IHeGAa96lm6icbclR8lQggZd1zZDtCfIdDQ9Mci1siw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kQ39cwS47KCPereX8CIu3QiyhksLahObxb+/1xruFp5F3YBuhs6UMWSItjhZ4H3Owcmw8nPqd5ejONSrnNbb/taR6TGjlATGh0rRqq0igVjRoN3OUgAiILJKf5cbnndNZWLHTblSgIUhgPyNgBBNCzVa6TqPGO5n/AXjGPrk6qA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ByNkXqq/; arc=none smtp.client-ip=220.197.31.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ByNkXqq/" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4bab2d5aa; Fri, 28 Aug 2026 14:52:07 +0800 (GMT+08:00) From: Damon Ding To: Andrzej Hajda , Neil Armstrong , Robert Foss , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sandy Huang , Heiko Stuebner , Andy Yan Cc: Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Dmitry Baryshkov , Marek Szyprowski , Sebastian Reichel , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Damon Ding , stable@vger.kernel.org Subject: [PATCH v8 3/5] drm/bridge: analogix_dp: Restore mandatory samsung DP DT properties Date: Fri, 28 Aug 2026 14:51:51 +0800 Message-Id: <20260828065153.590802-4-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260828065153.590802-1-damon.ding@rock-chips.com> References: <20260828065153.590802-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0aa04723dd4503a8kunm9cc188d5188355 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZGRhLTVYZHkhKHU1PHk 5KQxhWFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSEpKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=ByNkXqq/v1UABNZl10lnleLwzvhNuRZWIBYWszscHeWdufztyE7+W7VSC+dWoNFk87VgQlRbjZ7o39DSth9TxFS26u3zjhK8+2phaobHx+y6QNuYEyMfiPhQAzY7SWZl0N3BZr/vBJnJD6dxvMH9k/VuNoSNTPalwSLyugZbZN4=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=Qt759fseXk6TL4BSquCkp6QINrVvbZDF08qVXgT34mA=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Revert the change that made samsung,link-rate and samsung,lane-count optional for Exynos DP. Add error checking to fail probe early if the required DT properties are missing. If these properties are missing, video_info->max_link_rate and video_info->max_lane_count remain zero, and so do link_train.link_rate and link_train.lane_count used in the subsequent link training flow, resulting in link training failure. There is no way at all a device can work without these properties. Here is the code flow when either max_link_rate or max_lane_count is 0: analogix_dp_commit() -> analogix_dp_full_link_train(dp, max_lanes =3D 0, max_rate =3D 0) analogix_dp_full_link_train(max_lanes, max_rate): // Read sink capabilities via DPCD and sanitize them link_rate =3D read_dpcd(DP_MAX_LINK_RATE); // >=3D 0x06 after fixup lane_count =3D read_dpcd(DP_MAX_LANE_COUNT); // >=3D 1 after fixup // Clamp by the limits from DT if (link_rate > max_rate) // 0x06 > 0, always true link_rate =3D max_rate; // link_rate =3D 0 if (lane_count > max_lanes) // 1 > 0, always true lane_count =3D max_lanes; // lane_count =3D 0 // Configure TX with the zeroed values set_link_bandwidth(link_rate =3D 0) // writel() is only executed for bwtype =3D=3D 0x06/0x0a, // so LINK_BW_SET is never written and stays at // reset value; phy_configure() gets link_rate =3D 0. set_lane_count(lane_count =3D 0) // writel(0, ANALOGIX_DP_LANE_COUNT_SET) enables 0 lanes; // phy_configure() is called with lanes =3D 0. // Program sink for link training drm_dp_dpcd_write(DP_LINK_BW_SET, {link_rate =3D 0/lane_count =3D 0}) // DP spec requires link rate in {0x06, 0x0a, 0x14} and // lane count in {1, 2, 4}. Writing zeros is illegal, so // the sink cannot enter the training state. // Training loop for (lane =3D 0; lane < lane_count /* 0 */; lane++) // loop body never executes; training_lane[] stays // uninitialized and no training register is programmed Since the sanitized sink values are always non-zero (link_rate >=3D 0x06, lane_count >=3D 1), the clamping with a zero maximum unconditionally forces the training parameters to zero. Clock recovery can never be achieved, so link training fails deterministically. Consequently, making these properties mandatory again cannot break any existing device: a DT without them could never have worked in the first place. Failing probe early with a clear error message is more helpful than a silent link training failure at runtime. Fixes: 0d0abd894ead ("drm: bridge: analogix/dp: add max link rate and lane = count limit for RK3288") Cc: stable@vger.kernel.org Reviewed-by: Luca Ceresoli Signed-off-by: Damon Ding --- Changes in v8: - Expand the commit message with the detailed link training failure analysis, - Add Reviewed-by tag. --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/g= pu/drm/bridge/analogix/analogix_dp_core.c index 566f1e5eb8cd..ddb15d6de05f 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1248,6 +1248,7 @@ static int analogix_dp_dt_parse_pdata(struct analogix= _dp_device *dp) { struct device_node *dp_node =3D dp->dev->of_node; struct video_info *video_info =3D &dp->video_info; + u32 val; =20 switch (dp->plat_data->dev_type) { case RK3288_DP: @@ -1269,10 +1270,14 @@ static int analogix_dp_dt_parse_pdata(struct analog= ix_dp_device *dp) * NOTE: those property parseing code is used for * providing backward compatibility for samsung platform. */ - of_property_read_u32(dp_node, "samsung,link-rate", - &video_info->max_link_rate); - of_property_read_u32(dp_node, "samsung,lane-count", - &video_info->max_lane_count); + if (of_property_read_u32(dp_node, "samsung,link-rate", &val)) + return dev_err_probe(dp->dev, -EINVAL, + "Failed to get samsung,link-rate\n"); + video_info->max_link_rate =3D val; + if (of_property_read_u32(dp_node, "samsung,lane-count", &val)) + return dev_err_probe(dp->dev, -EINVAL, + "Failed to get samsung,lane-count\n"); + video_info->max_lane_count =3D val; break; } =20 --=20 2.34.1 From nobody Sat Sep 26 23:52:13 2026 Received: from mail-m12741.qiye.163.com (mail-m12741.qiye.163.com [115.236.127.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0508E3537E5; Fri, 28 Aug 2026 07:07:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787900861; cv=none; b=mZsjAM9LQKaMNAa+vdfLWF5lKyBWHgRx+sPibjNVLRyKK6Qi6mGATGmm3svqsSF6PHb3qAj99zdekbMNj2k/tgaktftplDhNOj1gcrUnq1kMxWiOSv+ZqlKzg7iA/PAgjA+60OI2LgpZhVE2awojQm3vJm9RYqVK58wyRYto5is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787900861; c=relaxed/simple; bh=EGc2jTS3oA/w9O5c/npYY+tNjKBHzGb7vkKuG05Wbbc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cy1nA6qaVx9HTePUjAzJeLjt0pXHDnRSM+3qX28g/KlKs8oM/fcoEE8z3ARAPA8FnzNDRhuS4vrFm0uZRzULwIqq6sVfTa6zNv3vWpW24MOrme744HFS/h6DfG606AiGSfhgqZQes4iD7fzd0vYDykjgx8Q607T+uhUynNdloOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=KVkwSm5d; arc=none smtp.client-ip=115.236.127.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="KVkwSm5d" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4bab2d5be; Fri, 28 Aug 2026 14:52:09 +0800 (GMT+08:00) From: Damon Ding To: Andrzej Hajda , Neil Armstrong , Robert Foss , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sandy Huang , Heiko Stuebner , Andy Yan Cc: Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Dmitry Baryshkov , Marek Szyprowski , Sebastian Reichel , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Damon Ding Subject: [PATCH v8 4/5] drm/bridge: analogix_dp: Add validation for samsung,lane-count property Date: Fri, 28 Aug 2026 14:51:52 +0800 Message-Id: <20260828065153.590802-5-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260828065153.590802-1-damon.ding@rock-chips.com> References: <20260828065153.590802-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0aa04723e4b303a8kunm9cc188d5188370 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZGU1DSVZOHh5MTEpCQk saGUhWFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSU9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=KVkwSm5di3V6qSiThNRmucxAg335yGzJyOAchgHUR/WdaUY42A0nLiI6EVs/yylLilGbMJLmnLKwQ/VTt2u2ENAygyJqa62QdkGGlbBLdzWfOI4oMFC+fEeh+AjTYvhj2Cg30WqlBe3Fw0nW/Fm1ypcYVVZP7AYNtZawTtHSOwQ=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=sufZXYFvhqt99gCkQ0mCK5s0oy3fyCr/7BG8YjyOEgU=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add validity check for samsung,lane-count to ensure DT-provided lane count values are specification-compliant. Suggested-by: Luca Ceresoli Reviewed-by: Luca Ceresoli Signed-off-by: Damon Ding --- Changes in v5: - Apply DRM DP helper API to check the validity of DP lane count. Changes in v6: - Rebase after the new commit for restoring mandatory properties samsung,link-rate and samsung,lane-count. Changes in v7: - Add Reviewed-by tag. --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/g= pu/drm/bridge/analogix/analogix_dp_core.c index ddb15d6de05f..a74c855936b2 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1274,7 +1274,8 @@ static int analogix_dp_dt_parse_pdata(struct analogix= _dp_device *dp) return dev_err_probe(dp->dev, -EINVAL, "Failed to get samsung,link-rate\n"); video_info->max_link_rate =3D val; - if (of_property_read_u32(dp_node, "samsung,lane-count", &val)) + if (of_property_read_u32(dp_node, "samsung,lane-count", &val) || + !drm_dp_lane_count_is_valid(val)) return dev_err_probe(dp->dev, -EINVAL, "Failed to get samsung,lane-count\n"); video_info->max_lane_count =3D val; --=20 2.34.1 From nobody Sat Sep 26 23:52:13 2026 Received: from mail-aws7240.qiye.163.com (mail-aws7240.qiye.163.com [54.251.7.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E6793D75A1; Fri, 28 Aug 2026 07:07:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.251.7.240 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787900861; cv=none; b=kLEf/h7hJ731n1/I9IdEHTIauPp05LwdbVmIWdmICdlQA6VOR/WGfuZziq/qBcvaKMjlHUHkbuPa27OzWdd2C3zr6vkX1/FBsAbL5Dof3wAyjMOf2/jEP1KDoqnwzUKfCpujK2oVBEtNI6xlvzUJPInJx40/CIkiPKRNLTrPTLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787900861; c=relaxed/simple; bh=Ga4M6p9TfDXAW1OnV+1OYL5tOXiy5sI9jdaHdYiqs2w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=l5bpbuWiOfKZaVpTNv1zLbCMG8M3m8jcsrxU6wEWaxVbWpuZZRt8IgEgq9Uou+gSqqBSC/Wkz/8e8JWxt4+N/y8ErE79sQ9LNkvQTPs5dxwwQ0vvkvdoUc580LCCvi71mXi6A3ltsajyOwtEgH1HeTg23dJ1fUT0F+to1kLBG90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=TS7Lq4+c; arc=none smtp.client-ip=54.251.7.240 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="TS7Lq4+c" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4bab2d5c3; Fri, 28 Aug 2026 14:52:11 +0800 (GMT+08:00) From: Damon Ding To: Andrzej Hajda , Neil Armstrong , Robert Foss , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sandy Huang , Heiko Stuebner , Andy Yan Cc: Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Dmitry Baryshkov , Marek Szyprowski , Sebastian Reichel , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Damon Ding Subject: [PATCH v8 5/5] drm/bridge: analogix_dp: Add support for optional data-lanes mapping Date: Fri, 28 Aug 2026 14:51:53 +0800 Message-Id: <20260828065153.590802-6-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260828065153.590802-1-damon.ding@rock-chips.com> References: <20260828065153.590802-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0aa04723ec2803a8kunm9cc188d518837b X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZQhkaH1YaShlISh4aGk JDSk5WFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSEpKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=TS7Lq4+cqjmu4vyz4wHt52ViZazShlZ9Y19qmzmr2Ff5XJKsGeRI/n59CtNw4xPT6sgghdsIeyQP4RPOr0FoMN2RnW3wOYQF1Ry642hK5U7FQTWX4PG+gNfosiqzKf/swRJO4hHiGrucjESc6fvcDZHIfrQSjafh8mlOgOfOBsE=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=07jua1c31UW2L/pF5LvkY8ta4PXpkxHe7lw8I4lCAJA=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Parse the optional 'data-lanes' device tree property to support custom physical lane mapping configuration. If no valid configuration is found, fall back to the default lane map (0, 1, 2, 3) automatically and keep the driver running. Lane mapping is mainly used for below scenarios: 1. Correct PCB lane swap and differential line routing crossover without hardware changes; 2. Adapt mismatched lane pin definitions between SoC and eDP panel; 3. Support multiple panel hardware variants on the same board by configuring data-lanes in device tree only. Reviewed-by: Sebastian Reichel Signed-off-by: Damon Ding Reviewed-by: Luca Ceresoli --- Changes in v2: - Add lane mapping application scenarios in commit message. Changes in v5: - Add Reviewed-by tag. Changes in v8: - Fix reg parameter of of_graph_get_endpoint_by_regs() for parsing "data-lanes" endpoint from -1 to 0. - Fix the 'tmp' name in analogix_dp_dt_parse_lanes_map() to understandable 'lane_idx'. - Add comment to explain the lane map fill loop. --- .../drm/bridge/analogix/analogix_dp_core.c | 70 +++++++++++++++++++ .../drm/bridge/analogix/analogix_dp_core.h | 4 +- .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 15 ++-- .../gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++ 4 files changed, 84 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/g= pu/drm/bridge/analogix/analogix_dp_core.c index a74c855936b2..18e76d1e78e1 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1244,6 +1244,73 @@ static const struct drm_bridge_funcs analogix_dp_bri= dge_funcs =3D { .detect =3D analogix_dp_bridge_detect, }; =20 +static int analogix_dp_dt_parse_lanes_map(struct analogix_dp_device *dp) +{ + struct video_info *video_info =3D &dp->video_info; + struct device_node *endpoint; + u32 lane_idx[LANE_COUNT4]; + u32 map[LANE_COUNT4] =3D {0, 1, 2, 3}; + bool used[LANE_COUNT4] =3D {false}; + int num_lanes; + int ret, i; + + memcpy(video_info->lane_map, map, sizeof(map)); + + num_lanes =3D drm_of_get_data_lanes_count_ep(dp->dev->of_node, 1, 0, 1, + video_info->max_lane_count); + if (num_lanes < 0) + return -EINVAL; + + endpoint =3D of_graph_get_endpoint_by_regs(dp->dev->of_node, 1, 0); + if (!endpoint) + return -EINVAL; + + ret =3D of_property_read_u32_array(endpoint, "data-lanes", lane_idx, num_= lanes); + of_node_put(endpoint); + if (ret) + return -EINVAL; + + for (i =3D 0; i < num_lanes; i++) { + if (lane_idx[i] >=3D LANE_COUNT4) { + dev_dbg(dp->dev, "data-lanes[%d] =3D %u is out of range\n", i, lane_idx= [i]); + return -EINVAL; + } + + if (used[lane_idx[i]]) { + dev_dbg(dp->dev, "data-lanes[%d] =3D %u is duplicate\n", i, lane_idx[i]= ); + return -EINVAL; + } + + used[lane_idx[i]] =3D true; + map[i] =3D lane_idx[i]; + } + + /* + * Fill the map[] entries not described by 'data-lanes' with the + * lane indices not used so far, e.g. for 'data-lanes =3D <3 1>': + * + * used[] =3D {0, 1, 0, 1} // only lanes 1 and 3 are used + * map[] before =3D {3, 1, x, x} // x =3D unassigned + * map[] after =3D {3, 1, 0, 2} + * + * Unused entries have no effect on the current link with fewer + * lanes in use, but filling them with distinct indices keeps the + * LANE_MAP register holding a valid permutation, just like its + * reset value (0xe4), so the mapping remains sane if a sink with + * a different lane count is connected later, e.g. via DP hot-plug. + */ + for (i =3D 0; i < LANE_COUNT4 && num_lanes < LANE_COUNT4; i++) { + if (!used[i]) + map[num_lanes++] =3D i; + } + + dev_dbg(dp->dev, "Using parsed lane map: <%u %u %u %u>\n", map[0], map[1]= , map[2], map[3]); + + memcpy(video_info->lane_map, map, sizeof(map)); + + return 0; +} + static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) { struct device_node *dp_node =3D dp->dev->of_node; @@ -1282,6 +1349,9 @@ static int analogix_dp_dt_parse_pdata(struct analogix= _dp_device *dp) break; } =20 + if (analogix_dp_dt_parse_lanes_map(dp)) + dev_dbg(dp->dev, "No valid data-lanes found, using default lane map\n"); + return 0; } =20 diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/g= pu/drm/bridge/analogix/analogix_dp_core.h index c7997677a286..4560597604ad 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -137,6 +137,8 @@ struct video_info { =20 int max_link_rate; enum link_lane_count_type max_lane_count; + + u32 lane_map[LANE_COUNT4]; }; =20 struct link_train { @@ -177,7 +179,7 @@ struct analogix_dp_device { /* analogix_dp_reg.c */ void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool ena= ble); void analogix_dp_stop_video(struct analogix_dp_device *dp); -void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); +void analogix_dp_lane_mapping(struct analogix_dp_device *dp); void analogix_dp_init_analog_param(struct analogix_dp_device *dp); void analogix_dp_init_interrupt(struct analogix_dp_device *dp); void analogix_dp_reset(struct analogix_dp_device *dp); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gp= u/drm/bridge/analogix/analogix_dp_reg.c index ea8401293a23..c1344a3f013a 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -48,16 +48,15 @@ void analogix_dp_stop_video(struct analogix_dp_device *= dp) writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); } =20 -void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) +void analogix_dp_lane_mapping(struct analogix_dp_device *dp) { + u32 *lane_map =3D dp->video_info.lane_map; u32 reg; =20 - if (enable) - reg =3D LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | - LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; - else - reg =3D LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | - LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + reg =3D lane_map[0] << LANE0_MAP_SHIFT; + reg |=3D lane_map[1] << LANE1_MAP_SHIFT; + reg |=3D lane_map[2] << LANE2_MAP_SHIFT; + reg |=3D lane_map[3] << LANE3_MAP_SHIFT; =20 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); } @@ -140,7 +139,7 @@ void analogix_dp_reset(struct analogix_dp_device *dp) =20 usleep_range(20, 30); =20 - analogix_dp_lane_swap(dp, 0); + analogix_dp_lane_mapping(dp); =20 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gp= u/drm/bridge/analogix/analogix_dp_reg.h index 12735139046c..ac914e37089b 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -209,6 +209,10 @@ #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) +#define LANE3_MAP_SHIFT (6) +#define LANE2_MAP_SHIFT (4) +#define LANE1_MAP_SHIFT (2) +#define LANE0_MAP_SHIFT (0) =20 /* ANALOGIX_DP_ANALOG_CTL_1 */ #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) --=20 2.34.1