From nobody Sat Sep 26 23:52:24 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AD423BBFD3 for ; Fri, 28 Aug 2026 08:44:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906642; cv=none; b=DgmT+o6opXwgcTa8y+ow39Rh/9ZoXeXLMkkks7hdH6W204Ff3y4lJKGfxEzrdLzwTUxHZiAv2jLY0QZqUICGD90hA80Yw6PeSfhm3IJvq6VIUHIbBf3RfFKjyxde8pOs7nk+ixc3FS5VQFCiVKkVGWbPtYrWkFZY4ldu7LrmfNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906642; c=relaxed/simple; bh=Jk+qkV75ilHOAI4p+1pjg2Qm5Ifc+Amub/MY2jnEyp8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iwK3rSmcS1PZeLCJTEC7X20ezJO1fkUlER7mwd9UQWga0xShhBWCmaz0sOVozk76ydOy0u+5yCBBAhrMTPZVG+MyShAzx/9zBAxXNKxhCyabqkMY69xNVGX2eHIGzMDHpXez8z6xgIk47Eiy4PKV0e+91PnLY7UqqdaYJQYLVzg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=afLW/XmG; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Yid97sWb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="afLW/XmG"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Yid97sWb" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67S66iHd3205990 for ; Fri, 28 Aug 2026 08:43:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 71tdgYNgaYiDhqnIbl6jtVyEhIjCStyRj+6OG2MV96g=; b=afLW/XmGv/zOHAZx zmrLfJR/NLosaSNDDeVe1fYksfFjmhEwp++pFVsm8tgtuRJINFSLoBfKYDD7XLmv Aq2BTtToe1kNHWStrbYftwWBSKKWX3ES5X8h9eDufRVFTczDpkvxFKzrYS2zL0vZ I7i9vOkLMtzDOdv9NORoZKjwmOcqgedmae+Ijebta847WyjUD+BGfAuZ2ySvsKIf lVNuMzYHhKEnmKzDwLL6QwRATmBxKsQ8YDaaEzlSlpTv7x1WBy/+doLFTYU5ueyS hiwG4I94xtKLjUdtHj4aREo1NqVL4H/qT8rYrHWAtaB5wkQrMeRGGvsSjqvvM626 oZnZGg== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gatfxk62e-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 28 Aug 2026 08:43:59 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2d63c16fc5bso17222265ad.1 for ; Fri, 28 Aug 2026 01:43:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787906639; x=1788511439; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=71tdgYNgaYiDhqnIbl6jtVyEhIjCStyRj+6OG2MV96g=; b=Yid97sWbyT8kbK9cr5xrFbU+zUS8rVD6CXq2XgklOO96UzgdW+kgmcpfJasujXuTQV +Ge10ibvSb4ffbhxlGSrPhvLRdsEtgeAFBG91mO7NEWPlLqyIoz3PLIYR2IItYIIbNFn Q/6Nlw8Jsld6c8C68YTwfW0ywSrVJPvrCW49JOPbzjKTbdUs1zVhe1Aaev/1vYGJy/gz F2y74n5lEi9uk1Q6J7uu3UFo4by7LjUfi18kB7PiFu5POlXA+74aF6dq4fg1wU50IRpv RLjJ6CPQ1mWC5fa8+eQGYzO4ynI1OispDW1LKKrQw/YNS9mihK05AmZTlhgRNEj6owXx aYfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787906639; x=1788511439; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=71tdgYNgaYiDhqnIbl6jtVyEhIjCStyRj+6OG2MV96g=; b=GwG/yflcXzzaNIwBOHM08AxQMoQgC6/QeSqRp/B6/nx1gAKqWpqq1/ZUlNAo7FS/Lj MZtjIJOSdOf+BWHI18WZvC53Us4HokzWroup9Fb2MQRmSbJYXIO3cFaMoUV6MedUA5CQ Xh3hgWmwOy1ENNOOeHmN6u2ZBSdtzPjMlAcNttFTxLRmtxAMQwIdDpak9KXnrrtDK/xu aYPJ7qyDJsk6pNa0PL88pfswMOdLUE4hr6kRfUlE0/iTuMAnPxQ/6SXn+m4Ao3FMZTnJ TDiNYqx1eua4wabE2FfOuDDLA0/NkRiGdiOL9IF2xwz4hgQKIe+dVVW7IVmhh9Ufp8oT DiVQ== X-Forwarded-Encrypted: i=1; AHgh+RquO0lKDTF6KNJzJB8F1LcIt70+I5MV1c/vk8wUi/mPI7nvS8ADVRrX76UNQA3w22bKVpTPP8pzIds8JFI=@vger.kernel.org X-Gm-Message-State: AFuF++lAldecmZnBhnbp1tRBkslFVafG5NFASL0jEKemf5xNqLE1qQBQ 7+fNH4nMhMe52ACOtodi3YRqjaJCZLYOZUZbHY4N1C+9updUf/ZCNn+41ti0FQ37Ls9ZB6wQeom nUnCxl6XtBfZOq0tpDnjg1FS6OSj9BsyshtYrpge7r8bnd1Nz5ONtaRl5tdyGrc/vc3g= X-Gm-Gg: AR+sD13NIAOnO1qHRvAo3ZqoXQmUqsn4/isnUGJcdAx0qi28vGy/fU8IWyiVET8z6R1 kOduOKjdFmXhfTErHTkyActOkV3nE3k8AfusZUjbNbB0AJOHXfG6A1X5hcacLLHs8c55j02wcKe iNwT5Rqygnt3JWiXA344TH1wtMFwuGNXiErTe54uwCqfTNEX/uJfrw2PBbH0TNTHhxr0OBVkFzY Ee3SL6k0Xa6qf2Trp8hncdW1AzwVYEwNAtaFPexpRaGOQGRQmLHXCmZ09C71slcbF9HjDvBM75+ +/wFUuO0VO0aFBD2IsvRS6cVw38GG6EhWooE+/+dsHkTo3SsJTjyGmIF40Pw/SBlT6agwsjnDbv YoJYmZnJfzO07uhh667lwE/rgWvjGMcbHjy8= X-Received: by 2002:a17:902:d2c7:b0:2d7:7cb:a44a with SMTP id d9443c01a7336-2d74ddc21d7mr98937695ad.11.1787906638766; Fri, 28 Aug 2026 01:43:58 -0700 (PDT) X-Received: by 2002:a17:902:d2c7:b0:2d7:7cb:a44a with SMTP id d9443c01a7336-2d74ddc21d7mr98936885ad.11.1787906638267; Fri, 28 Aug 2026 01:43:58 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f784857sm3673459eec.3.2026.08.28.01.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 01:43:57 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 28 Aug 2026 14:13:35 +0530 Subject: [PATCH v2 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-nord-v2-1-18bf59d19d6f@oss.qualcomm.com> References: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> In-Reply-To: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel Cc: Krishna Chaitanya Chundru , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787906625; l=10074; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=Jk+qkV75ilHOAI4p+1pjg2Qm5Ifc+Amub/MY2jnEyp8=; b=BaocjX3hNwPZDPjC58bWjzi7h3fJ+5pTTjHJLSBB2Y45ZqQg7qGcanky3BIw1plFfd8kSR5wC gHot4zEPHxlBYhoPFel5SpgO5D75je03WXlu8caOAthbhqnb6OPRfOB X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=UKLt2ify c=1 sm=1 tr=0 ts=6a914a4f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=m1JAq1APDOtiVc4_LWMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: zKV8LmLG6AqhehAWy21xcpMpt04Bd1WH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfX1USxOc31zgwy fcGT6Q7zAY/Iu052JCcthP8zx4hZkagb1xrCd/ws5Edfzaan9aoAVcDPdpZXT5GFX7fygiBKD6+ /S9XSAy7YvGzuCnA9tkDpiezHNJ8gagqx0yWneMF5V+6Z9D/JF0zcth3JMX5eokOfp9uXZIFyAT amA3lZWPHmcmF4pmknPIL+qL33EC7jr7WstIwikG4JtM5hQU7WvmvwqKebnF34uWM9bAg0Ls+xr FqTLfvS3XmXX/gx0q31qB0ZVbIIQw0wnlCpz1yuhZlbcTkRSg68MAuRz5lmVFP3TEjWldu55ak8 0EFWwfBVUcQW5hZJD3vBX9gr80i2jiqVtyj6ydpmq6Pj4NdiUHmN+jaeL6UPchbnu3GDTAF12IE 4FUr2ERNH1pwXYCMka/+7ZBkJKjTxfup+ybiapNBCI/M/HtNXOhEn15nGyN3drQieXItuu8YlDS b7XccY0BVa+ZJuE4emw== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfXwcfnLiLlRYPI 1uVhwhRJXEcPOary0Whrm8/gQHd9w8upGcPqGgwOAtrQvqHx0HXe+Hy8/D8RllDnR6wB++tE0Ae h9EGIG9TWaR0V2Ga7Sr39amimyKSuFY= X-Proofpoint-ORIG-GUID: zKV8LmLG6AqhehAWy21xcpMpt04Bd1WH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280074 Document the PCIe PHY found on the Qualcomm Nord platform. Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple lane configurations using four PHY segments (A/B/C/D). The active topology is selected by firmware through a TCSR configuration register and may be configured as x16, x8+x8, x8+x4+x4, or x8+x4+x2+x2. The binding describes the register regions, clocks, resets, power domains, regulators, PHY provider interface, clock provider interface, and the qcom,link-mode property used by the driver to discover the active lane configuration programmed by firmware. Signed-off-by: Krishna Chaitanya Chundru --- .../phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml | 276 +++++++++++++++++= ++++ 1 file changed, 276 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pc= ie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-p= cie-phy.yaml new file mode 100644 index 000000000000..37198f82c611 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.= yaml @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Nord QMP Bifurcated PCIe PHY + +maintainers: + - Krishna Chaitanya Chundru + +description: | + The Qualcomm Nord PCIe PHY is a Gen5-capable QMP PCIe PHY composed + of four PHY ports (A/B/C/D). The ports can be combined to support + multiple lane topologies, including x16, x8+x8, x8+x4+x4 and + x8+x4+x2+x2 configurations. + + The selected topology is determined by the PCIe link configuration mode + programmed in TCSR registers. Depending on the selected mode, PHY ports + may operate independently or be grouped together to form wider PCIe link= s. + + Each port provides dedicated register space, clocks, resets and power + resources required for PHY operation. + +properties: + compatible: + enum: + - qcom,nord-qmp-gen5x16-pcie-phy + + reg: + minItems: 4 + maxItems: 4 + + reg-names: + items: + - const: port_a + - const: port_b + - const: port_c + - const: port_d + + clocks: + minItems: 17 + maxItems: 17 + + clock-names: + items: + - const: aux_a + - const: cfg_ahb_a + - const: rchng_a + - const: pipe_a + - const: aux_b + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: aux_c + - const: cfg_ahb_c + - const: rchng_c + - const: pipe_c + - const: aux_d + - const: cfg_ahb_d + - const: rchng_d + - const: pipe_d + - const: ref + + power-domains: + minItems: 4 + maxItems: 4 + + power-domain-names: + items: + - const: port_a + - const: port_b + - const: port_c + - const: port_d + + resets: + minItems: 8 + maxItems: 8 + + reset-names: + items: + - const: port_a + - const: port_a_nocsr + - const: port_b + - const: port_b_nocsr + - const: port_c + - const: port_c_nocsr + - const: port_d + - const: port_d_nocsr + + vdda-phy-a-supply: true + + vdda-phy-b-supply: true + + vdda-phy-c-supply: true + + vdda-phy-d-supply: true + + vdda-pll-a-supply: true + + vdda-pll-b-supply: true + + vdda-pll-c-supply: true + + vdda-pll-d-supply: true + + qcom,link-mode: + description: | + Reference to the TCSR syscon and the offset of the + TCSR_PCIE_LINK_CONFIG_MODE register. + 0 (QMP_PCIE_NORD_MODE_X16) =E2=80=94 all ports ganged as x16 + 1 (QMP_PCIE_NORD_MODE_X8_X8) =E2=80=94 x8 (port A) + x8 (port= B+C+D) + 2 (QMP_PCIE_NORD_MODE_X8_X4_X4) =E2=80=94 x8 (A) + x4 (B) + x4 (= C+D) + 3 (QMP_PCIE_NORD_MODE_X8_X4_X2_X2)=E2=80=94 x8 (A) + x4 (B) + x2 (= C) + x2 (D) + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle of the TCSR syscon + - description: Offset of TCSR_PCIE_LINK_CONFIG_MODE register + + "#clock-cells": + const: 1 + description: + Selects the pipe clock output by port index (0=3DA, 1=3DB, 2=3DC, 3= =3DD). + GCC pipe-clock mux parents reference this provider. + + clock-output-names: + items: + - description: Name of the PHY A pipe clock output. + - description: Name of the PHY B pipe clock output. + - description: Name of the PHY C pipe clock output. + - description: Name of the PHY D pipe clock output. + + "#phy-cells": + const: 1 + description: | + Selects the PHY instance by index: + 0 =E2=80=94 port A (up to Gen5 x8; anchor in x16 mode) + 1 =E2=80=94 port B (up to Gen5 x4) + 2 =E2=80=94 port C (up to Gen5 x2) + 3 =E2=80=94 port D (up to Gen5 x2) + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - vdda-phy-a-supply + - vdda-phy-b-supply + - vdda-phy-c-supply + - vdda-phy-d-supply + - vdda-pll-a-supply + - vdda-pll-b-supply + - vdda-pll-c-supply + - vdda-pll-d-supply + - qcom,link-mode + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + phy@1b00000 { + compatible =3D "qcom,nord-qmp-gen5x16-pcie-phy"; + + reg =3D <0x0 0x01b00000 0x0 0x10000>, + <0x0 0x01b10000 0x0 0x10000>, + <0x0 0x01b20000 0x0 0x10000>, + <0x0 0x01b30000 0x0 0x10000>; + reg-names =3D "port_a", + "port_b", + "port_c", + "port_d"; + + clocks =3D <&gcc GCC_PCIE_A_PHY_AUX_CLK>, + <&gcc GCC_PCIE_A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_A_PIPE_CLK>, + <&gcc GCC_PCIE_B_PHY_AUX_CLK>, + <&gcc GCC_PCIE_B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_B_PIPE_CLK>, + <&gcc GCC_PCIE_C_PHY_AUX_CLK>, + <&gcc GCC_PCIE_C_CFG_AHB_CLK>, + <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_C_PIPE_CLK>, + <&gcc GCC_PCIE_D_PHY_AUX_CLK>, + <&gcc GCC_PCIE_D_CFG_AHB_CLK>, + <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_D_PIPE_CLK>, + <&tcsrcc TCSR_PCIE_CLKREF_EN>; + clock-names =3D "aux_a", + "cfg_ahb_a", + "rchng_a", + "pipe_a", + "aux_b", + "cfg_ahb_b", + "rchng_b", + "pipe_b", + "aux_c", + "cfg_ahb_c", + "rchng_c", + "pipe_c", + "aux_d", + "cfg_ahb_d", + "rchng_d", + "pipe_d", + "ref"; + + assigned-clocks =3D <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>, <100000000>, + <100000000>, <100000000>; + + power-domains =3D <&gcc GCC_PCIE_A_PHY_GDSC>, + <&gcc GCC_PCIE_B_PHY_GDSC>, + <&gcc GCC_PCIE_C_PHY_GDSC>, + <&gcc GCC_PCIE_D_PHY_GDSC>; + power-domain-names =3D "port_a", + "port_b", + "port_c", + "port_d"; + + resets =3D <&gcc GCC_PCIE_A_PHY_COM_BCR>, + <&gcc GCC_PCIE_A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_B_PHY_COM_BCR>, + <&gcc GCC_PCIE_B_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_C_PHY_COM_BCR>, + <&gcc GCC_PCIE_C_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_D_PHY_COM_BCR>, + <&gcc GCC_PCIE_D_NOCSR_COM_PHY_BCR>; + reset-names =3D "port_a", + "port_a_nocsr", + "port_b", + "port_b_nocsr", + "port_c", + "port_c_nocsr", + "port_d", + "port_d_nocsr"; + + vdda-phy-a-supply =3D <&vreg_l6a_1p2>; + vdda-phy-b-supply =3D <&vreg_l4a_1p2>; + vdda-phy-c-supply =3D <&vreg_l4a_1p2>; + vdda-phy-d-supply =3D <&vreg_l4a_1p2>; + vdda-pll-a-supply =3D <&vreg_l1e_0p9>; + vdda-pll-b-supply =3D <&vreg_l1e_0p9>; + vdda-pll-c-supply =3D <&vreg_l1e_0p9>; + vdda-pll-d-supply =3D <&vreg_l1e_0p9>; + + qcom,link-mode =3D <&tcsr 0x71050>; + + #clock-cells =3D <1>; + clock-output-names =3D "pcie_a_pipe_clk", + "pcie_b_pipe_clk", + "pcie_c_pipe_clk", + "pcie_d_pipe_clk"; + + #phy-cells =3D <1>; + }; + }; --=20 2.34.1 From nobody Sat Sep 26 23:52:24 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CEAF3E8684 for ; Fri, 28 Aug 2026 08:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906647; cv=none; b=K1JlACzXTJjbEq85VkRqENxFJn1G2SSGVlcfTWCyZACi7UzwJRsaINk3ilMJlDTnjHpDBYgcL9nXfdauixdSF1QFuOB4dQuM/Z7tMznTtn2hLPbU8nLnga+Wwwb7zMs600FkR8eUzQ6hjCLAgDPznzJ4T+lmvrw2PLanyUMHRS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906647; c=relaxed/simple; bh=YgWcPqpc0Tw7AwiZ7DA7bpWlNDJxbNEfk70+YLHN3IM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b063texrCE59KsP6+6PzAvJW5GtpPWuN/BuLrPdusUsgJbO6GaewYcdWHTiKR/oXWE3bS2lG/+CMigyifrhgb3G7xadOhLprKVC2Q6CMJ5cTHJ1L/uriHT+8SihynMkO+aClINBDfTJAVgH/FtYJcampt+TX+UwUckNP4USjvs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QD+XAuqq; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=j6xVhdxw; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QD+XAuqq"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="j6xVhdxw" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67S66Y112761952 for ; Fri, 28 Aug 2026 08:44:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UKkMnWvHtEU3AJjdFVpOEvwgEQWljpY1f7+4AWt13UQ=; b=QD+XAuqqIWu0wKc4 vfWTahr9L/A1sy/QyMSZMD5OOtWeRDd0sF2ZIt3cxc4yUh2Ph2BCYZz5bKjaw5Oq FOt8/Ly6sZROSCRWcRDU1fKxeLTumfxbkNDWGNvgA3RQJIDsdpeeMuZv3iIvL2Jc nQ7xdaUcW7ciyI82YponHEp64x30DN8xhGNRKWTywEP4aXmNNZZUAfIUoAzFL9rB i0lQft/mQ+HZ4mEIGtUsXWzllg2SgyccxiPGrva7z9rRj9dbtTJ9HBYOU8Hlxec5 H9gd8e4QOWFQtFWD3aarmgEkWx3WFWYqUuccap6v1hIVnuNFqu2YqYyfZ7b6Qroi tXJIHA== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gb42p8rt2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 28 Aug 2026 08:44:05 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2d6df0a1e18so16933895ad.1 for ; Fri, 28 Aug 2026 01:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787906645; x=1788511445; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=UKkMnWvHtEU3AJjdFVpOEvwgEQWljpY1f7+4AWt13UQ=; b=j6xVhdxwycAdr3JxBIgUjdN+JB75NW2O8hHcDQpUV/k7+ADqyrSEDr30TMG8AIxYCT 65vfWzj26ytIIcDu00AH6/2ZTIDZTCIE1CnaI+WVZMatntgAQOyqYnvpztg9PllrsRRa 5CtTzruqqog52IznbAOlZa5p3/fXCk2GcrpefLbZUuhWgdE2upjx9LeG3jGK2+pFIJM6 qyEE443QLewwxmV3+JOcZRxmliMVLSf3YoEomf+UnIp2U64pRoLoVBMKLKUfioWzENfV Qkv2A/GJTDznn6ZBOjMZE9GzaIv6h2RkjuprsAok5eEcDLJoAJIjpjnRqvpsD0ODeFPp PVkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787906645; x=1788511445; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=UKkMnWvHtEU3AJjdFVpOEvwgEQWljpY1f7+4AWt13UQ=; b=LXf2IE2igyYY1BSZAdkI6KO6UptoWfvjzbkTaVSOybVLQ/U7EMNoIF4/MoUmHrrokT 9snpC65kw9vbMI46fEvAaG6RxzwR2X8WfsPXnStvmS9QDk20apPGSuEr4TViAt5IgVKp DeI1on5tI7YVkIVCxoXYTH8TGCR0a2hpGwDLU6Wwjq/y0GxMBPsUPlSMP7VjTz/nTs+b 8vQaujrlXoaWWJZaYY2DHSxaKeTVoeZ1S+c+dLFoHan7SuhDH3/vvwz2WbuN49LoqHYs C4su5131c04GwJq3w5YJoxUfbW2RzYLog31cOId3d52pO1LK0rGayhyV4DB1I04Ztw3X B6hQ== X-Forwarded-Encrypted: i=1; AHgh+RqeFzbiHiOdpXgYEX2SFv9BPc4YMSSWMcbisX3Fj5PoZmzOAbeGHOSLPwLoWO2d47mcE5oKDJPb7NaOcJo=@vger.kernel.org X-Gm-Message-State: AFuF++msab6yAIsUGNAv1G6O/ibRnyoQL1oYtrcYS0+HG4PXB4gprUYT c5iqKzp9+dwNV1HbmpVv/UAIQcZmBKg9s8kC7VtU0iRtbUyNbyRgVrbLUqkz5LPQwbD0Kf4Ft7T YqEZXS3K2D697oJ7Onl2W2tiFsy07tqHgQgXXgt+yeXhC1SvL/CV+7HIGhdqnDYjLXFI= X-Gm-Gg: AR+sD12Ge5YJQGuLSSRKygfp7Qm7gYIPNDna56ITZ2V1JWT8BBDt2wffg8JqvDcQAWd Li4gZ5gGTSTdSAmGd0ogxhO204NnxNIj2QefHN5tS5XWYfSLGIWwLRjLc+lOSSABFpGbGq3hPIg Imt7JMbqysuymA35BrZ5ap3clJHZGDiQZEwSyw9+PYDRLvaNKV/X0kxNPi1OMEdec8RnXjN6HhW kU66me7q0690lqfTfk+SAcu0g7khLbxpaxwVq3ZuE0+70b6uASOCJ10FsLPk3p2BBwha8mmwDnU u/hUJMVMOva2pHWcp/Jp21+V3K9Xbzy0PnmfkD/pnvCEjGhdlVJpEcoKMWB6zNfq3hHwILsEEnl HmlC7V1Ixp1AYLoaYgNsuADItMsxpYJbTLF0= X-Received: by 2002:a17:903:13c7:b0:2cc:f5aa:9513 with SMTP id d9443c01a7336-2d74dee93acmr24599005ad.10.1787906644754; Fri, 28 Aug 2026 01:44:04 -0700 (PDT) X-Received: by 2002:a17:903:13c7:b0:2cc:f5aa:9513 with SMTP id d9443c01a7336-2d74dee93acmr24597695ad.10.1787906644217; Fri, 28 Aug 2026 01:44:04 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f784857sm3673459eec.3.2026.08.28.01.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 01:44:03 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 28 Aug 2026 14:13:36 +0530 Subject: [PATCH v2 2/4] dt-bindings: pci: qcom: add Nord PCIe controller compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-nord-v2-2-18bf59d19d6f@oss.qualcomm.com> References: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> In-Reply-To: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel Cc: Krishna Chaitanya Chundru , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787906625; l=947; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=YgWcPqpc0Tw7AwiZ7DA7bpWlNDJxbNEfk70+YLHN3IM=; b=6a9qQEeX3hsEP5/9IdXU63jKORwsf3AJ/9gEUD4IpThtQPlKw/iFS6R7s+vzE3mLD9N87U/U/ cd63oTw9EKpD8l/xhrwVitROD1e91pXSmwuo3d7lBTFFNUMqWpYJpbO X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: Ty_wHgmuPJF_1mwMDgL1XIF5kyP8Adxf X-Authority-Analysis: v=2.4 cv=ToDWQjXh c=1 sm=1 tr=0 ts=6a914a55 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=ly1VyIkaSgMpB_u5KqwA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: Ty_wHgmuPJF_1mwMDgL1XIF5kyP8Adxf X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfX0b1Vt+MgGH4R tZlZXkZSK8pbsiEa1Hd89zxWsvVCWgy7HynOnff6dVQ/wBxh+aW/b88MxWzWKtCKXGTL8OSBefx SOyUpe0OP7q8tB+T22h8FfA6fOcS0Xk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfX8V2sCYAEmJqe ZquMo6k/n0F5uKH/yqQZFitmiOA4mXv1KkNUtl/ex3oynWgvhqP2+9liKstafmn14QwvavDfjwv 9Uo/heCEWWPKAILXCryfZpMEX1BRGAuyzde9FCwLiWCEBEhlxG8nY0EbNpydSwW6DrP0AWhSlGg F/yF7a04qfTIS5l0DPrV2NJ20/E1aVHQXjPBSzvVrNOKvX1oQKhjUoTHIpkbLHg6Y4cTog2pW/4 XKI/nQQvQaC1u7ZIR1ds/3eWHClYrUnhFiORCHekWRVOh0h7wAQNF4Ob1jbzDRMcr1GgToSOMed BKyKHIPmbGRx6hlfS/ERxNiHuBlSGXovYN1ZDIGdChej3n8U8JH2jUS1fxFSyIGfTyq+6tfhQ0w KV4b+Ac0kWHbc77dx7Ixk1qqocI/qNyRVjq/akJrCHgiqM2S8pAWp27g/QafeIf/pOcBQnaJxcU ZIKgdt3XPojHUrWAvQQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280074 Add the qcom,nord-pcie compatible string to the Qualcomm PCIe controller binding. The Nord PCIe controller is compatible with the SA8775P PCIe controller implementation and reuses the same binding definition. Signed-off-by: Krishna Chaitanya Chundru Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index 63630a814f28..b8ba2c4449b7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sa8775p - items: - enum: + - qcom,nord-pcie - qcom,pcie-qcs8300 - const: qcom,pcie-sa8775p =20 --=20 2.34.1 From nobody Sat Sep 26 23:52:24 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E60843E9C3A for ; Fri, 28 Aug 2026 08:44:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906654; cv=none; b=sJLDFKUzQQsikags3CT/MVGXaVRUmxSvcKwE1gJHrXQVzJT/HcfDlI2PRVK+c6Q1bll97MUk9B+pS6Aux/NZLpP3ETqL+VYgPStbuqx5Vo0o8fc/NzPSu+VFIbCCJGJgKMIChQwCAQGIBMUIFmRsXXclsayGAoCJWLWho4zwgec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906654; c=relaxed/simple; bh=5x5TirLtHA0c0Rb9PKOOjbyhhs2shQyZ5pqbvgZXqk0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lgmM8+FHSftI6qMM40CytuBInRdhP2SdB9phA+NcfpsMZ4m5kfXMmadCPtmPzj1tzZVBaTe8r2quII9SgAneEiiFxIVcGy7jdCDWAhjhDodmnnTR4uNF91weZyB+YIIX14rdWYJRVY7WVzYmUxTFdHMGG1a/ftiN2NmdzrRm4io= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ep6PIZSQ; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=I+YiNbiG; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ep6PIZSQ"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="I+YiNbiG" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67S66vT12197015 for ; Fri, 28 Aug 2026 08:44:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Oqpp/YqJcmbInDW8NldSo8VxqiOBNOhc5Rb5jj2yQKE=; b=ep6PIZSQAJWh9+CJ DHUfyd9B+GP3xPPswsw1/HCdB4ePEc22XCkhVeh3bYEyEMU9sLWx2opdPWMShUHo Ppzvw1R5P5M5ruThZg5Viv/fNBrJYjPELTIWlmf22y8wsVSKLrjdQn4ysODiYR4B ncGb1D8gKwL65HXKtkDbwQffMNc6b7hDs2hCEFh+Q7lzb5w73D6AV8ALUOXbnTbS 0eLjgorj5up28hi3EkBZY+yZ97EgjSXsgMw+bccSIgLoxmdqEV3ohocqxtqlIPkZ n6UP603TmG4WrhgcyuL8eWoUTUi2qV/dvoDlv5O2lCfMaaJTc5x4rQuaGoXzhxJT 07yAgg== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gb3mxrvy5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 28 Aug 2026 08:44:11 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2d7151120d6so15323065ad.3 for ; Fri, 28 Aug 2026 01:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787906651; x=1788511451; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Oqpp/YqJcmbInDW8NldSo8VxqiOBNOhc5Rb5jj2yQKE=; b=I+YiNbiGB7aF6ctGIz1sBNwyjTGyeeZbqVkjujq6iS2DQGkiRXfaOOndyj5caOjQJP RevEYKX8o2RYc9VFvc1UYUNtTf28ktNN14dA/L0/u/z8bx5bZ1Cry7PE7zJLWu/sAGFh RBzyjHpHEOj6ZNMhnjLysJahqLK2lNqTYU3LWeXaEbDXdrqAQyRcpqq7IRkzeXHehfU8 GQ7OPRCMYUOWwBAMFjE7VYho6t33Gu/kwcO0AOJ5EDvaiPZYUetH0YzpcICuT5n6TE8i Cpo4RABAkSZ4LU1w46ASaqhmqUvf2xMFfAe3qf/JEzcBR6rggu2VaUQC3GTUf2BPXqHu DlFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787906651; x=1788511451; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Oqpp/YqJcmbInDW8NldSo8VxqiOBNOhc5Rb5jj2yQKE=; b=qlpZ92nHg9ujv9o5/R7owHzQZB/UKmHa+KA38veBpzf/PbKxS1c4ne6wz1isu4yGXU QL3dB0HACklZdg/STK9YueL6q92AeFD51NDOnOH8l9KkHIgEzXBP8c9g5DpFpyaPp/2r L9r0XvJ2jPP6kpDTZs2Cd2+XSIWIml5DU5k/IXJk+ri3Afb3lBT4w772eTgDzLvAldfk iWmsM9gthwcerweJxGt+qH8fhb9pUi+iO2pPNKVxJwPSQwICTSm1VO11UYSrGf15noxt mjWEkBdYzHqa5dhgWC6p1S/CLDhvyoaXyU0RdiJGAmRRSjTXCkoXs4jc/dF+ftLB1rZ2 nmdg== X-Forwarded-Encrypted: i=1; AHgh+RqIIHsd/TGiFp4K3bidJEKWfPNSP7b0q4n1ewGME2cCgJJevll6H2qu8aGOUUsndW/2PWGQPlHDpgAZJy8=@vger.kernel.org X-Gm-Message-State: AFuF++lQssrQ9GdZFIJq6IQWb6iT4rPk2HGST9m79QeswXjUswOsVGpP ogh05AEK7zhYIiKhjDxXYrqjwx7CxJdggivoOqT0YXyfDDyCRhce5PaPKUdSQggSQQSJkqNe8He fbwLUPhMDCmRmicwFbYIzUi/eecCJhtur8thyB8PYlM9xdDPLrS6x+EkZdOQLP82gQ9E= X-Gm-Gg: AR+sD12EX0dQWj6uR44Fm5BvP4ajXYfwHAvZQI3dRkmJ45L5uK9FnnVm7p5HQqD/B23 K5qdLTUFg16xdTQ/8TO6PJSokils6dHeZAsAsAw9jrd8MccqipSV2SYOfWKQAAwusGpwNLfszM8 pypuNrKm7ZpVrHiqhsp+UXEjgMjOFjjLE34zHDZwkYGrAPEA8TugUq8TbEFQkndr8FeN6cDR22t psQ/T9QiHKzvNLoaF8wuFcX9Jj+6wOh+H737zAfYqvTze9gSpzOg+2yJfEUXnANTtPoGNF8UrCB sQ33f8+UZA6WXLfM7DBEfLD3ipZ+rrCDFnVw4kWTc0Q7Q6AivELVrJ7V4k69MvILi6dmiY2wBpZ QC5VFZFLjSHdV3kpHq8baVsRLl7vB/YQyxcE= X-Received: by 2002:a17:903:24f:b0:2cf:c543:2c7e with SMTP id d9443c01a7336-2d74df5fa9dmr90023565ad.10.1787906650742; Fri, 28 Aug 2026 01:44:10 -0700 (PDT) X-Received: by 2002:a17:903:24f:b0:2cf:c543:2c7e with SMTP id d9443c01a7336-2d74df5fa9dmr90022845ad.10.1787906650197; Fri, 28 Aug 2026 01:44:10 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f784857sm3673459eec.3.2026.08.28.01.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 01:44:09 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 28 Aug 2026 14:13:37 +0530 Subject: [PATCH v2 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-nord-v2-3-18bf59d19d6f@oss.qualcomm.com> References: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> In-Reply-To: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel Cc: Krishna Chaitanya Chundru , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787906625; l=2355; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=5x5TirLtHA0c0Rb9PKOOjbyhhs2shQyZ5pqbvgZXqk0=; b=IBotV43TcYpZpOfwsLPTB8XIkHg7+NNwBpXZCCtNFvB6kmG8fHVAB6hp3VkFYdr1DodhCbrZZ tHIu15FOJ/MBazQOqF4rdUggYLGaaymlDjGBZ/GECtR7jmRc5KklXoA X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfXyFLPadhkjN5L funSOnf7HawlYYr5MuVTfMbnv3t+PZde7NE6+RZcEd/KQ50hWCl+SP/KUWAmhXdpmFd3hDL4Vtc Pw+MQeX3pEpVcF0hN8QUdggCcsIOSHWsAZV+gbZBwyEr1+Q+JuYltcfVwcJbp3KVem5GjK7IzrA qhD+/9ch+tuoAQbsSjUdzKgUcVkQsen575qnwPiHWIzJmiattDNAg4i1mXtEbY5rvYIghRGm01r NBFDoDJeZp5a0frD8AGC0Bhw3qJlAPD64PUH7V26miSh1wdbEc9lt7KEAxG115EQrsTSrr1DQCk CKw8IDbgJouVGLxUfM2720aWncY+4Ui9x7sroXVUDXadjDnh6sR6c5WjWpNR9F6h45Ltgq46oO1 cBzb+jahP0GNwyPSU1/4nSibV1fivilTpBDTWqE3slQSn+V0puG4AvcJDbHEaYmQ9E1O77Vsv2M dRya8CgZaAgeTieRdlA== X-Authority-Analysis: v=2.4 cv=MONQXsZl c=1 sm=1 tr=0 ts=6a914a5b cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=kXhGf0cxdCgfIYue-YsA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfX6RonXWPokKU3 HUwbjzfdFPBEZ1FyJgEOiD4tkKB0EICXQEfLFIqC3dibC35UAtKP+oBiGwg62B8yvsXHD+xhULY OS8vEJBXPad7q+yX1nDU+6iDywebP/E= X-Proofpoint-ORIG-GUID: DH76hIOe7vaQ8hl7rFM86cxYWyHeUYGD X-Proofpoint-GUID: DH76hIOe7vaQ8hl7rFM86cxYWyHeUYGD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280074 Nord requires a workaround to address a timing convergence issue in the PCIe power domain. To avoid the issue, set the CORE_CLK_CGC_DIS and AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization. The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This change adds the remaining required settings as documented in QCTDD11972446. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio --- drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index b58a607b713f..b97e40fb7ec8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -281,6 +281,7 @@ struct qcom_pcie_cfg { bool override_no_snoop; bool firmware_managed; bool no_l0s; + bool cgc_dis_workaround; }; =20 struct qcom_pcie_perst { @@ -1097,11 +1098,18 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *p= cie) static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) { const struct qcom_pcie_cfg *pcie_cfg =3D pcie->cfg; + u32 val; =20 if (pcie_cfg->override_no_snoop) writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, pcie->parf + PARF_NO_SNOOP_OVERRIDE); =20 + if (pcie_cfg->cgc_dis_workaround) { + val =3D readl(pcie->parf + PARF_SYS_CTRL); + val |=3D CORE_CLK_CGC_DIS | AUX_PWR_DET; + writel(val, pcie->parf + PARF_SYS_CTRL); + } + qcom_pcie_set_slot_cap(pcie->pci); =20 return 0; @@ -1630,6 +1638,13 @@ static const struct qcom_pcie_cfg cfg_2_9_0 =3D { .ops =3D &ops_2_9_0, }; =20 +static const struct qcom_pcie_cfg cfg_nord =3D { + .ops =3D &ops_1_9_0, + .override_no_snoop =3D true, + .no_l0s =3D true, + .cgc_dis_workaround =3D true, +}; + static const struct qcom_pcie_cfg cfg_sc8280xp =3D { .ops =3D &ops_1_21_0, .no_l0s =3D true, @@ -2464,6 +2479,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) =20 static const struct of_device_id qcom_pcie_match[] =3D { { .compatible =3D "qcom,hawi-pcie", .data =3D &cfg_1_9_0 }, + { .compatible =3D "qcom,nord-pcie", .data =3D &cfg_nord }, { .compatible =3D "qcom,pcie-apq8064", .data =3D &cfg_2_1_0 }, { .compatible =3D "qcom,pcie-apq8084", .data =3D &cfg_1_0_0 }, { .compatible =3D "qcom,pcie-ipq4019", .data =3D &cfg_2_4_0 }, --=20 2.34.1 From nobody Sat Sep 26 23:52:24 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 233633E5EC6 for ; Fri, 28 Aug 2026 08:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906666; cv=none; b=LRHCn6AYV6lprW5tpzBFye5eN1Su2IpZvVswRx5DpvXCkUWwAgJGyyUmLQYcepAgriHAbHlKyu2LELuRFfZMjsjBGtOQojlMzjVyMD8D/6B7W8ElUr2VZZ4yI6Z3IY+6Vn4yiU5bm6wGq8D2cH6mcSm1md1z0OgzI7XY8iqKu9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787906666; c=relaxed/simple; bh=lFhcf9BA14D2Qx/Dvdl0Eae09UQouf7uP3wYhkkmdeE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rbmgknfeaIQcDavoS/C/dcuchgt6qDUn415e2E3j9F02zbkvUpbdjANsLGJN7rUBaj1jk+pjTZ3aIGP28ajW2XvZex71qJAsEAHaY00GuzuLmmhgb6JtDC/6YrUtCxrNw6vxlPCFM9Rnry/2nabwNoe8uyxj9Vh4gCy+wYku9zs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=CLm5sxL3; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=d9NRAweP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="CLm5sxL3"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="d9NRAweP" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67S66ibf2196796 for ; Fri, 28 Aug 2026 08:44:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= imnn4+HHWlg1HUaAg2a/DTCP8fI4tiQD7ftxQxduTY0=; b=CLm5sxL3hwf2OsMR /MYnoTwyJdy+17ngEOJGV7YJCniusJ+/R8SzkSxu2wTpOTC3s0inhtlm+mY6SCH6 e7lMk/ReTEqr5LogdpaAdsQnNE8Kol2o4UWCPds5LON44hZzbIbLiJO/uX0fZJKt 8Jlv5hH11f9yAxiyFBZsHdvutnrnI35nig/yqSmNjEcGxqUONOKZvDpfCB0Enuu6 XjiDliGtVZghKv+LI9Y6LNdR5iCBs7q6qPTFr15qoec27oS/FA/dOjAVL6ZZDEVW f0+ozvoGRldzkSkYtwBZHnJCqwrsySoc5EfBN8NL9ZaJ0Wwq2YRcYXGbJDv/WqPA R4BrPQ== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gb3mxrw00-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 28 Aug 2026 08:44:19 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-3965ba1ba3eso1237961a91.2 for ; Fri, 28 Aug 2026 01:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787906659; x=1788511459; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=imnn4+HHWlg1HUaAg2a/DTCP8fI4tiQD7ftxQxduTY0=; b=d9NRAwePYWb8kIpPDJAqvreagebaegcyHgLP0TtuA4rZzvia4ybkpBbdeZlAvYk2B7 tCJj0zHJWLuztBEPR16rFUvTwjvLeADizwPD3aAmLMfENKY+ARYjhuw/4YKFssaGmum6 BL/rTFBaRNQCVIGHMpY53/h6doI2ORR28zaqeIWXXwsLL43b8dLEvnfK5YT1KJEXNHBz tbDmXLV7/5DVEpedB5Kom7v5Czf+sVVtEeDD/Ame3ciaydZbBQ2CstPb7tXhkbiK09f7 xfUG3jvXqHLgQK46u0g59bcltp5HMwLKl4IVI0om2kRa/c9xUomb+Sr6VKGr5wjPyADG NJVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787906659; x=1788511459; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=imnn4+HHWlg1HUaAg2a/DTCP8fI4tiQD7ftxQxduTY0=; b=eeRPaJzwTa6njq7Gtbtldv4PUksolxGo7IqnCwd96WUWcmfEgf2UjtVBzawzzLoktE fBtmJP5q5fKVE9dPXriyhngjJeTuoXzDhEJgNIM+J7OSlBq/x9XhBAoB55aM0kwi8M1Q hYLTfetgpVq+ijHGk/Hc/fi+s+5By0ndE9txLq+xvULrqWM3fVGTsZYJ5CngMJGxX7Nm /H87/PImIK5z/MJGVBljb+0qI1IXahmsIus9COihw4y6W0oayJ9cYLN8lE0bT3KpT1vP +5WcQz2tfEA+rnC40SlXRL97k9EAqv1l/Un7eqonU1GZT0JOvhss7gojW1S5uF1z2chN STrQ== X-Forwarded-Encrypted: i=1; AHgh+Rpq/507t+U7DAw5eu1hZeb1RQE3mzY29LA8DKerPEZCS2/whIAEjnPv67kYmkwPxAWb9gQirFZkPOAf7sU=@vger.kernel.org X-Gm-Message-State: AFuF++nYaLiMlK3nlxZSIVIYCMZoRAQik7HoOjO0I/BoUzEmOiyjgoxH 4BrbL4ipy2Z9HN+s6A1yLMbpUPDTZG826XDMCO11+30n/lR+htZr1AvjveBQt2GbReSEd8CLJyj baZO3U8SrApZ2EjLvp6ao8LZK72YLYTD4xlSGLUEZZGWxkOyOokZ+ixhFjn3fWWPHvuQ= X-Gm-Gg: AR+sD116vCwH6P+F8+YVp+QqALhfHff0N1bm4VW+8vF18qGf0L8acFugH4w8gMuSa9d nT2LeOlpvr5V4ptlvzz0EE1jAXcKMnL+p96RgfjrSrHHuViBD7nfBYGp0kuyQx9Mx07i37kxPGh lWRMU41XhcxciVA+B4TFdY3MDo9rhYbkMZVyXnedAfts9gc4zXg6PD5qwu+Vd9UqtISfN5QJbF9 e8i4jhec5vSvQcsWBRyLOoI5gJLKrQkGyoPuC4BRUVsha7S6bNeRJVH11tR9V+P0ulX2B+CnYEs lqrHFdj8itEN0uMVtAM8++NQsuXrDuLVhPIsnYaVGC1I+YkUJTviKqSGDMC9ETTZgEawFeIbfkD RNcCoUgxtJ9H7px1YU/356Hmmns8pCqloLQs= X-Received: by 2002:a05:6a20:9383:b0:3d2:df:1854 with SMTP id adf61e73a8af0-3d2664672cfmr10607400637.6.1787906657788; Fri, 28 Aug 2026 01:44:17 -0700 (PDT) X-Received: by 2002:a05:6a20:9383:b0:3d2:df:1854 with SMTP id adf61e73a8af0-3d2664672cfmr10607216637.6.1787906656819; Fri, 28 Aug 2026 01:44:16 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f784857sm3673459eec.3.2026.08.28.01.44.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 01:44:16 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 28 Aug 2026 14:13:38 +0530 Subject: [PATCH v2 4/4] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-nord-v2-4-18bf59d19d6f@oss.qualcomm.com> References: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> In-Reply-To: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel Cc: Krishna Chaitanya Chundru , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787906625; l=89693; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=lFhcf9BA14D2Qx/Dvdl0Eae09UQouf7uP3wYhkkmdeE=; b=GZhCXLhUVZZdDhowOoeL1rDpRnwOYajIaBza0qusbZf7n62EiTnO9M3kS5CXFNDT+sBHg7bZT dwvAMuEE9yVA/H9CVu6NmGyrvxeryY9dE97iblTNPpHMGHDSwoS2Z5p X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfX1I5QOgvFBnjR SRpnsbmTpzKYxEm4K2ge6vFMZoeJmrx7/6V+EAFaQKYyGw5Oln7D7B555obxcsLEzwWvMQhC0G1 B+75FLh+qYyy4i+0CZEw3LkODzjbWxYcb4Tq1SiDrJBSzIBXZ52Zbd2PtaAsxhltqhDKU37vpF+ WJJA9yszpeu4olQS0w1kTmwjbIrJ6i755iNAeh7ei935vDxH21C0fHuKwEw9M7dnh+8C+8avr6f xDy6CcVPkNHmLsnCa04+ctEC2Vh1BE+RDB81dTMcNWipc76ve6RwmFFBdvvke+bELtkLvpOv5g7 suSkVtINT9V6eOU7gidACYYvY3zq4pZmiKut/xyXCHEs7DomOglMjZRQDlIzQuPPXvk9TIa88Mw 06G1nzk4XvM0J2yCCLlJWbkgXcWpUiocR2IXRf3c+XboXkXAkAOBZRHixM8CARj+e685lQTQnwu XBouwcD9yulNMCB2VxQ== X-Authority-Analysis: v=2.4 cv=MONQXsZl c=1 sm=1 tr=0 ts=6a914a63 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=WhUnEXWCkJBGCNJu6gAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA3NCBTYWx0ZWRfX6mvK5ULP5/52 OIBrHvAvpZaoiDzaYd4eK8QShf0IX6MJYlthorfDGQJe2S5tOZN1fY+1Jb7TvbS4qmEHpHssObH 31Ld8DYfE3cYXKKNq8Peip3kh0un7Cc= X-Proofpoint-ORIG-GUID: GoVaVGSOOyYuqIXs6S-HORcvINvkkDq2 X-Proofpoint-GUID: GoVaVGSOOyYuqIXs6S-HORcvINvkkDq2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280074 Add support for the Nord Gen5x16 bifurcated QMP PCIe PHY. Nord has a single PCIe PHY block split into four ports which can be used in multiple lane configurations: x16, x8+x8, x8+x4+x4 and x8+x4+x2+x2. The active topology is selected through the link mode configuration register, and the driver exposes the corresponding PHY instances based on that mode. Unlike Glymur, where the PHY is initialized by firmware, Nord requires Linux to program the PHY registers. Add the PLL, TXRXZ, PCS and PCS lane initialization tables, along with the required power-up, power-down and soft-reset sequencing. Add per-port and grouped PHY configurations for all supported Nord lane modes. Also add support for regular PHY resets in addition to the NOCSR resets, and handle the shared PHY power domain by attaching it once at the multi-PHY level and reusing it across segment groups. The GDSC init is now done using the device created for the PHY itself (devm_phy_create()), rather than the parent multi-PHY platform device. Signed-off-by: Krishna Chaitanya Chundru --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 1077 ++++++++++++++++= +++- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h | 56 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h | 14 + .../qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h | 94 ++ .../phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h | 194 ++++ 5 files changed, 1395 insertions(+), 40 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c b/drivers/ph= y/qualcomm/phy-qcom-qmp-pcie-multiphy.c index e93cba4369fb..076b86bf9953 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include #include #include #include @@ -20,8 +21,16 @@ #include #include #include +#include + +#include =20 #include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-common.h" +#include "phy-qcom-qmp-pcs-v6_40.h" +#include "phy-qcom-qmp-pcs-pcie-v6_40.h" +#include "phy-qcom-qmp-qserdes-com-pcie-v6_40.h" +#include "phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h" =20 #define PHY_INIT_COMPLETE_TIMEOUT_US 10000 =20 @@ -30,8 +39,19 @@ enum qmp_pcie_glymur_link_mode { QMP_PCIE_GLYMUR_MODE_X4X4, }; =20 +enum qmp_pcie_nord_link_mode { + QMP_PCIE_NORD_MODE_X16, + QMP_PCIE_NORD_MODE_X8_X8, + QMP_PCIE_NORD_MODE_X8_X4_X4, + QMP_PCIE_NORD_MODE_X8_X4_X2_X2 +}; + enum qphy_reg_layout { QPHY_PCS_STATUS, + QPHY_PCS_START_CONTROL, + QPHY_PCS_SW_RESET, + QPHY_PCS_POWER_DOWN_CONTROL, + QPHY_COM_BIAS_EN_CLKBUFLR_EN, QPHY_LAYOUT_SIZE }; =20 @@ -39,16 +59,42 @@ static const unsigned int pciephy_v8_50_regs_layout[QPH= Y_LAYOUT_SIZE] =3D { [QPHY_PCS_STATUS] =3D QPHY_V8_50_PCS_STATUS1, }; =20 +static const unsigned int nord_pciephy_v6_40_regs_layout[QPHY_LAYOUT_SIZE]= =3D { + [QPHY_PCS_STATUS] =3D QPHY_V6_40_PCS_STATUS1, + [QPHY_PCS_START_CONTROL] =3D QPHY_V6_40_PCS_START_CONTROL, + [QPHY_PCS_SW_RESET] =3D QPHY_V6_40_PCS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V6_40_PCS_POWER_DOWN_CONTROL, + [QPHY_COM_BIAS_EN_CLKBUFLR_EN] =3D QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFL= R_EN, +}; + struct qmp_pcie_offsets { u16 pcs; + u16 pll; + u16 txrxz; + u16 pcs_lanez; +}; + +struct qmp_phy_cfg_tbls { + const struct qmp_phy_init_tbl *txrxz; + int txrxz_num; + const struct qmp_phy_init_tbl *pcs; + int pcs_num; + const struct qmp_phy_init_tbl *pcs_lanez; + int pcs_lanez_num; }; =20 struct qmp_phy_cfg { const struct qmp_pcie_offsets *offsets; + struct qmp_phy_cfg_tbls tbls; + struct qmp_phy_init_tbl **pll_tbls; + int *pll_nums; + bool bifurcated; const char * const *reg_names; int num_regs; const char * const *pd_names; int num_pds; + const char * const *reset_list; + int num_resets; const char * const *nocsr_reset_list; int num_nocsr_resets; const char * const *vreg_list; @@ -67,6 +113,7 @@ struct qmp_pcie { void __iomem **base; struct clk_bulk_data *clks; struct clk_bulk_data *pipe_clks; + struct reset_control_bulk_data *resets; struct reset_control_bulk_data *nocsr_resets; struct regulator_bulk_data *vregs; struct device **pd_devs; @@ -89,6 +136,10 @@ struct qmp_pcie_match_data { u32 num_modes; }; =20 +/* QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN bits */ +#define COM_BIAS_EN BIT(0) +#define COM_BIAS_EN_MUX BIT(1) + static const char * const glymur_pciephy_clk_l[] =3D { "aux", "cfg_ahb", "ref", "rchng", "phy_b_aux", }; @@ -232,6 +283,890 @@ static const struct qmp_pcie_match_data glymur_qmp_ge= n5x8_match_data =3D { .num_modes =3D ARRAY_SIZE(glymur_qmp_gen5x8_mode_cfgs), }; =20 +static const char * const nord_pciephy_port_a_vreg_l[] =3D { + "vdda-phy-a", "vdda-pll-a", +}; + +static const char * const nord_pciephy_port_b_vreg_l[] =3D { + "vdda-phy-b", "vdda-pll-b", +}; + +static const char * const nord_pciephy_port_c_vreg_l[] =3D { + "vdda-phy-c", "vdda-pll-c", +}; + +static const char * const nord_pciephy_port_d_vreg_l[] =3D { + "vdda-phy-d", "vdda-pll-d", +}; + +static const char * const nord_pciephy_port_cd_vreg_l[] =3D { + "vdda-phy-c", "vdda-phy-d", "vdda-pll-c", "vdda-pll-d", +}; + +static const char * const nord_pciephy_port_bcd_vreg_l[] =3D { + "vdda-phy-b", "vdda-phy-c", "vdda-phy-d", + "vdda-pll-b", "vdda-pll-c", "vdda-pll-d", +}; + +static const char * const nord_pciephy_port_abcd_vreg_l[] =3D { + "vdda-phy-a", "vdda-phy-b", "vdda-phy-c", "vdda-phy-d", + "vdda-pll-a", "vdda-pll-b", "vdda-pll-c", "vdda-pll-d", +}; + +static const struct qmp_pcie_offsets nord_pcie_offsets_v6_40 =3D { + .pll =3D 0x8000, + .pcs =3D 0x9000, + .txrxz =3D 0xd000, + .pcs_lanez =3D 0xe800, +}; + +static struct qmp_phy_init_tbl nord_qmp_pcie_pll_a_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x31= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x31= ), +}; + +static struct qmp_phy_init_tbl nord_qmp_pcie_pll_b_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x22= ), +}; + +static struct qmp_phy_init_tbl nord_qmp_pcie_pll_c_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x20= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x31= ), +}; + +static struct qmp_phy_init_tbl nord_qmp_pcie_pll_d_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x22= ), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x22= ), +}; + +static const struct qmp_phy_init_tbl nord_qmp_pcie_txrxz_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_ENABLES, = 0x1c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B0, = 0xcd), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B1, = 0x34), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B2, = 0x55), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B3, = 0x50), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B4, = 0xac), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B5, = 0xdb), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B6, = 0x52), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B7, = 0x3e), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B0, = 0xce), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B1, = 0x55), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B2, = 0x6d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B3, = 0x60), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B4, = 0x8c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B5, = 0x9d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B6, = 0x6d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B7, = 0x26), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B0, = 0xfb), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B1, = 0xea), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B2, = 0xe8), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B3, = 0x70), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B4, = 0x9c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B5, = 0xf4), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B6, = 0x6d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B7, = 0x3b), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_SUMMER_CAL_SPD_MODE_RATE_012= 3, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH1, = 0x02), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH2, = 0x0d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PHPRE_CTRL, = 0x20), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_TX_ADPT_CTRL, = 0x30), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B0, = 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B1, = 0x4a), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B2, = 0x77), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B3, = 0x50), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B4, = 0x9a), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B5, = 0x47), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B6, = 0x52), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B7, = 0x1d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_1, = 0x05), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_2, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_3, = 0x41), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_4, = 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL1, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL2, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL3, = 0x81), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL4, = 0x8d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOCK_CTRL, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP1_DAC_ENABLE, = 0x1c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP2_DAC_ENABLE, = 0x1c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP345_DAC_ENABLE, = 0x18), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP67_DAC_ENABLE, = 0x10), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE0, = 0x07), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE1, = 0x07), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE2, = 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE3, = 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE4, = 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE0, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE1, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE2, = 0x01), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE3, = 0x03), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE4, = 0x03), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_FLL_DIV_RATIO_RATE_0123, = 0x94), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_01, = 0x66), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_23, = 0x77), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE4, = 0x07), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_CTRL, = 0x58), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_MAN_INDEX, = 0x0d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_ANA_CTRL, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_FUNC_CTRL, = 0xd0), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RAT= E0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RAT= E1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RAT= E2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RAT= E3, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RAT= E4, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE= 0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE= 1, 0x15), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE= 2, 0x10), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE= 3, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE= 4, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CODE_OVRD_RATE_2_3, = 0x24), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL2, = 0x83), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL3, = 0x44), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL4, = 0x04), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_0_1, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_2_3, = 0x11), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE4, = 0x02), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_0_1, = 0x33), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_2_3, = 0x33), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE4, = 0x03), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_0_1, = 0x22), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_2_3, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE4, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_DIV2_CTRL_RATE0123, = 0x7f), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE0, = 0x13), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE0, = 0x13), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE1, = 0x26), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE1, = 0x26), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE2, = 0x9c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE2, = 0x3d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE3, = 0x9c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE3, = 0x3d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE4, = 0x09), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE4, = 0x3d), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL3, = 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL4, = 0xaa), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL5, = 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_CNTRL1, = 0xe1), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE0_1, = 0xdd), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE2_3, = 0xdc), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE4, = 0x05), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_OVRD_MUXES, = 0x11), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE_0123, = 0x55), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE4, = 0x01), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE0, = 0x4b), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE0, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE1, = 0x4b), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE1, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE2, = 0x35), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE2, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE3, = 0x28), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE4, = 0x14), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_0_1, = 0x11), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_2_3, = 0x22), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_4, = 0x04), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE0, = 0x04), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE1, = 0x03), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE2, = 0x01), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE0, = 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE1, = 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE2, = 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE3, = 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE4, = 0xff), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_0_1, = 0x43), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_2_3, = 0x44), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_TYPE_CONFIG, = 0x03), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CTLE_POST_CAL_OFFSET_RATE_0_1_2= , 0x67), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_EN_LOWFREQ, = 0x1f), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RES_CODE_LANE_OFFSET_RX, = 0x18), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE0_1, = 0x88), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE2_3, = 0x88), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE4, = 0x09), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VTHRESH_CAL_MAN_VAL_RATE4, = 0x56), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CLKBUF_ENABLE, = 0x40), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE0, = 0x1e), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE1, = 0x1e), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE2, = 0x1e), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE3, = 0x1e), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE4, = 0x1e), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CNTRL, = 0x2f), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_LVL, = 0x84), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CAL_CTRL1, = 0x10), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL15, = 0x00), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL16, = 0x52), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_CAL_CTRL, = 0x08), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_POST_CAL_OFFSET, = 0x10), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_VREF_SEL, = 0x16), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_BLW_CTRL, = 0x3c), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE3, = 0x17), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE4, = 0x17), +}; + +static const struct qmp_phy_init_tbl nord_qmp_pcie_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG2, 0x3d= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG5, 0xe4= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG6, 0x1f= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG7, 0x0d= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_MULTIPHY_CONFIG2, 0x01= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG2, 0xe4= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG3, 0x30= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG5, 0x05= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG6, 0x08= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG7, 0x20= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG8, 0x20= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG10, 0x40= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG2, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG3, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG4, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ENDPOINT_REFCLK_DRIVE, 0xc1= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_RX_SIGDET_LVL, 0x66= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_OSC_DTCT_ACTIONS, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_LOCK_DETECT_CONFIG1, 0xff= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG1, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG2, 0x04= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG3, 0x1f= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG7, 0x35= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG8, 0x3e= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG1, 0x06= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG2, 0x1c= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG1, 0x03= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG3, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG1, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG5, 0x90= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG7, 0x0d= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG1, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG5, 0x90= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG7, 0x0d= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG1, 0x00= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG5, 0x90= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG7, 0x0d= ), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_TEST_CONTROL1, 0x08= ), +}; + +static const struct qmp_phy_init_tbl nord_qmp_pcie_pcs_lanez_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL5, 0x00), +}; + +static const struct qmp_phy_cfg_tbls nord_qmp_pcie_tbls =3D { + .txrxz =3D nord_qmp_pcie_txrxz_tbl, + .txrxz_num =3D ARRAY_SIZE(nord_qmp_pcie_txrxz_tbl), + .pcs =3D nord_qmp_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(nord_qmp_pcie_pcs_tbl), + .pcs_lanez =3D nord_qmp_pcie_pcs_lanez_tbl, + .pcs_lanez_num =3D ARRAY_SIZE(nord_qmp_pcie_pcs_lanez_tbl), +}; + +static const struct qmp_phy_init_tbl nord_qmp_pcie_bifurcated_pre_pwrup_tb= l[] =3D { + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PRE_STALL_LDO_BOOST_EN, 0x80), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LDO_TIMER_CTRL, 0x91), +}; + +static const struct qmp_phy_init_tbl nord_qmp_pcie_bifurcated_post_cfg_tbl= [] =3D { + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LDO_TIMER_CTRL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PRE_STALL_LDO_BOOST_EN, 0x00), +}; + +static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_a[] =3D { + nord_qmp_pcie_pll_a_tbl, +}; + +static int nord_qmp_pcie_pll_a_nums[] =3D { + ARRAY_SIZE(nord_qmp_pcie_pll_a_tbl), +}; + +static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_b[] =3D { + nord_qmp_pcie_pll_b_tbl, +}; + +static int nord_qmp_pcie_pll_b_nums[] =3D { + ARRAY_SIZE(nord_qmp_pcie_pll_b_tbl), +}; + +static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_c[] =3D { + nord_qmp_pcie_pll_c_tbl, +}; + +static int nord_qmp_pcie_pll_c_nums[] =3D { + ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl), +}; + +static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_d[] =3D { + nord_qmp_pcie_pll_d_tbl, +}; + +static int nord_qmp_pcie_pll_d_nums[] =3D { + ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl), +}; + +static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_cd[] =3D { + nord_qmp_pcie_pll_c_tbl, nord_qmp_pcie_pll_d_tbl, +}; + +static int nord_qmp_pcie_pll_cd_nums[] =3D { + ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl), +}; + +static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_bcd[] =3D { + nord_qmp_pcie_pll_b_tbl, nord_qmp_pcie_pll_c_tbl, nord_qmp_pcie_pll_d_tbl, +}; + +static int nord_qmp_pcie_pll_bcd_nums[] =3D { + ARRAY_SIZE(nord_qmp_pcie_pll_b_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl), + ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl), +}; + +static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_abcd[] =3D { + nord_qmp_pcie_pll_a_tbl, nord_qmp_pcie_pll_b_tbl, + nord_qmp_pcie_pll_c_tbl, nord_qmp_pcie_pll_d_tbl, +}; + +static int nord_qmp_pcie_pll_abcd_nums[] =3D { + ARRAY_SIZE(nord_qmp_pcie_pll_a_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_b_tbl), + ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl), +}; + +static const char * const nord_pciephy_port_a_reg_l[] =3D { "port_a" }; +static const char * const nord_pciephy_port_b_reg_l[] =3D { "port_b" }; +static const char * const nord_pciephy_port_c_reg_l[] =3D { "port_c" }; +static const char * const nord_pciephy_port_d_reg_l[] =3D { "port_d" }; +static const char * const nord_pciephy_port_cd_reg_l[] =3D { "port_c", "po= rt_d" }; +static const char * const nord_pciephy_port_bcd_reg_l[] =3D { "port_b", "p= ort_c", "port_d" }; +static const char * const nord_pciephy_port_abcd_reg_l[] =3D { + "port_a", "port_b", "port_c", "port_d" +}; + +static const char * const nord_pciephy_port_a_clk_l[] =3D { "aux_a", "cfg_= ahb_a", "rchng_a", "ref" }; +static const char * const nord_pciephy_port_b_clk_l[] =3D { + "aux_a", "aux_b", "cfg_ahb_b", "rchng_b", "ref", +}; + +static const char * const nord_pciephy_port_c_clk_l[] =3D { + "aux_a", "aux_c", "cfg_ahb_c", "rchng_c", "ref", +}; + +static const char * const nord_pciephy_port_d_clk_l[] =3D { + "aux_a", "aux_d", "cfg_ahb_d", "rchng_d", "ref", +}; + +static const char * const nord_pciephy_port_cd_clk_l[] =3D { + "aux_a", "aux_c", "cfg_ahb_c", "rchng_c", "aux_d", "cfg_ahb_d", "rchng_d"= , "ref", +}; + +static const char * const nord_pciephy_port_bcd_clk_l[] =3D { + "aux_a", "aux_b", "cfg_ahb_b", "rchng_b", + "aux_c", "cfg_ahb_c", "rchng_c", + "aux_d", "cfg_ahb_d", "rchng_d", "ref", +}; + +static const char * const nord_pciephy_port_abcd_clk_l[] =3D { + "aux_a", "cfg_ahb_a", "rchng_a", + "aux_b", "cfg_ahb_b", "rchng_b", + "aux_c", "cfg_ahb_c", "rchng_c", + "aux_d", "cfg_ahb_d", "rchng_d", "ref", +}; + +static const char * const nord_pciephy_port_a_pipeclk_l[] =3D { "pipe_a" }; +static const char * const nord_pciephy_port_b_pipeclk_l[] =3D { "pipe_b" }; +static const char * const nord_pciephy_port_c_pipeclk_l[] =3D { "pipe_c" }; +static const char * const nord_pciephy_port_d_pipeclk_l[] =3D { "pipe_d" }; + +static const char * const nord_pciephy_port_a_reset_l[] =3D { "port_a" }; +static const char * const nord_pciephy_port_b_reset_l[] =3D { "port_b" }; +static const char * const nord_pciephy_port_c_reset_l[] =3D { "port_c" }; +static const char * const nord_pciephy_port_d_reset_l[] =3D { "port_d" }; +static const char * const nord_pciephy_port_cd_reset_l[] =3D { + "port_c", "port_d", +}; + +static const char * const nord_pciephy_port_bcd_reset_l[] =3D { + "port_b", "port_c", "port_d", +}; + +static const char * const nord_pciephy_port_abcd_reset_l[] =3D { + "port_a", "port_b", "port_c", "port_d", +}; + +static const char * const nord_pciephy_port_a_nocsr_reset_l[] =3D { "port_= a_nocsr" }; +static const char * const nord_pciephy_port_b_nocsr_reset_l[] =3D { "port_= b_nocsr" }; +static const char * const nord_pciephy_port_c_nocsr_reset_l[] =3D { "port_= c_nocsr" }; +static const char * const nord_pciephy_port_d_nocsr_reset_l[] =3D { "port_= d_nocsr" }; +static const char * const nord_pciephy_port_cd_nocsr_reset_l[] =3D { "port= _c_nocsr", "port_d_nocsr" }; +static const char * const nord_pciephy_port_bcd_nocsr_reset_l[] =3D { + "port_b_nocsr", "port_c_nocsr", "port_d_nocsr", +}; + +static const char * const nord_pciephy_port_abcd_nocsr_reset_l[] =3D { + "port_a_nocsr", "port_b_nocsr", "port_c_nocsr", "port_d_nocsr", +}; + +static const char * const nord_pciephy_port_a_pd_l[] =3D { "port_a" }; +static const char * const nord_pciephy_port_b_pd_l[] =3D { "port_a", "port= _b" }; +static const char * const nord_pciephy_port_c_pd_l[] =3D { "port_a", "port= _c" }; +static const char * const nord_pciephy_port_d_pd_l[] =3D { "port_a", "port= _d" }; +static const char * const nord_pciephy_port_cd_pd_l[] =3D { + "port_a", "port_c", "port_d", +}; + +static const char * const nord_pciephy_port_bcd_pd_l[] =3D { + "port_a", "port_b", "port_c", "port_d", +}; + +#define nord_pciephy_port_abcd_pd_l nord_pciephy_port_bcd_pd_l + +#define NORD_QMP_PCIE_PORT_CFG(_port, _pipeclk_l, _bifurcated) \ +static const struct qmp_phy_cfg nord_qmp_pcie_port_##_port##_cfg =3D { \ + .offsets =3D &nord_pcie_offsets_v6_40, \ + .tbls =3D nord_qmp_pcie_tbls, \ + .pll_tbls =3D nord_qmp_pcie_pll_##_port, \ + .pll_nums =3D nord_qmp_pcie_pll_##_port##_nums, \ + .bifurcated =3D _bifurcated, \ + .reg_names =3D nord_pciephy_port_##_port##_reg_l, \ + .num_regs =3D ARRAY_SIZE(nord_pciephy_port_##_port##_reg_l), \ + .pd_names =3D nord_pciephy_port_##_port##_pd_l, \ + .num_pds =3D ARRAY_SIZE(nord_pciephy_port_##_port##_pd_l), \ + .reset_list =3D nord_pciephy_port_##_port##_reset_l, \ + .num_resets =3D ARRAY_SIZE(nord_pciephy_port_##_port##_reset_l), \ + .nocsr_reset_list =3D nord_pciephy_port_##_port##_nocsr_reset_l, \ + .num_nocsr_resets =3D ARRAY_SIZE(nord_pciephy_port_##_port##_nocsr_reset_= l), \ + .vreg_list =3D nord_pciephy_port_##_port##_vreg_l, \ + .num_vregs =3D ARRAY_SIZE(nord_pciephy_port_##_port##_vreg_l), \ + .regs =3D nord_pciephy_v6_40_regs_layout, \ + .phy_status =3D PHYSTATUS_4_20, \ + .clk_list =3D nord_pciephy_port_##_port##_clk_l, \ + .num_clks =3D ARRAY_SIZE(nord_pciephy_port_##_port##_clk_l), \ + .pipe_clk_list =3D _pipeclk_l, \ + .num_pipe_clks =3D 1, \ +} + +NORD_QMP_PCIE_PORT_CFG(a, nord_pciephy_port_a_pipeclk_l, true); +NORD_QMP_PCIE_PORT_CFG(b, nord_pciephy_port_b_pipeclk_l, true); +NORD_QMP_PCIE_PORT_CFG(c, nord_pciephy_port_c_pipeclk_l, true); +NORD_QMP_PCIE_PORT_CFG(d, nord_pciephy_port_d_pipeclk_l, true); +NORD_QMP_PCIE_PORT_CFG(cd, nord_pciephy_port_c_pipeclk_l, true); +NORD_QMP_PCIE_PORT_CFG(bcd, nord_pciephy_port_b_pipeclk_l, true); +NORD_QMP_PCIE_PORT_CFG(abcd, nord_pciephy_port_a_pipeclk_l, false); + +#undef NORD_QMP_PCIE_PORT_CFG + +static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x16_cfgs[] = =3D { + &nord_qmp_pcie_port_abcd_cfg, +}; + +static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x8x8_cfgs[] = =3D { + &nord_qmp_pcie_port_a_cfg, + &nord_qmp_pcie_port_bcd_cfg, +}; + +static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x8x4x4_cfgs[= ] =3D { + &nord_qmp_pcie_port_a_cfg, + &nord_qmp_pcie_port_b_cfg, + &nord_qmp_pcie_port_cd_cfg, +}; + +static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x8x4x2x2_cfg= s[] =3D { + &nord_qmp_pcie_port_a_cfg, + &nord_qmp_pcie_port_b_cfg, + &nord_qmp_pcie_port_c_cfg, + &nord_qmp_pcie_port_d_cfg, +}; + +static const struct qmp_pcie_link_mode_cfg nord_qmp_gen5x16_mode_cfgs[] = =3D { + [QMP_PCIE_NORD_MODE_X16] =3D { + .cfgs =3D nord_qmp_gen5x16_mode_x16_cfgs, + .num_phys =3D ARRAY_SIZE(nord_qmp_gen5x16_mode_x16_cfgs), + }, + [QMP_PCIE_NORD_MODE_X8_X8] =3D { + .cfgs =3D nord_qmp_gen5x16_mode_x8x8_cfgs, + .num_phys =3D ARRAY_SIZE(nord_qmp_gen5x16_mode_x8x8_cfgs), + }, + [QMP_PCIE_NORD_MODE_X8_X4_X4] =3D { + .cfgs =3D nord_qmp_gen5x16_mode_x8x4x4_cfgs, + .num_phys =3D ARRAY_SIZE(nord_qmp_gen5x16_mode_x8x4x4_cfgs), + }, + [QMP_PCIE_NORD_MODE_X8_X4_X2_X2] =3D { + .cfgs =3D nord_qmp_gen5x16_mode_x8x4x2x2_cfgs, + .num_phys =3D ARRAY_SIZE(nord_qmp_gen5x16_mode_x8x4x2x2_cfgs), + }, +}; + +static const struct qmp_pcie_match_data nord_qmp_gen5x16_match_data =3D { + .mode_cfgs =3D nord_qmp_gen5x16_mode_cfgs, + .num_modes =3D ARRAY_SIZE(nord_qmp_gen5x16_mode_cfgs), +}; + +static void qmp_pcie_init_port_registers(struct qmp_pcie *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_pcie_offsets *offs =3D cfg->offsets; + const struct qmp_phy_cfg_tbls *tbls =3D &cfg->tbls; + int i; + + for (i =3D 0; i < cfg->num_regs; i++) { + void __iomem *port =3D qmp->base[i]; + u32 val; + + if (cfg->bifurcated) + qmp_configure(qmp->dev, port + offs->txrxz, + nord_qmp_pcie_bifurcated_pre_pwrup_tbl, + ARRAY_SIZE(nord_qmp_pcie_bifurcated_pre_pwrup_tbl)); + + writel(SW_PWRDN | REFCLK_DRV_DSBL, + port + offs->pcs + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]); + + if (cfg->bifurcated) { + void __iomem *bias_en =3D port + offs->pll + + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]; + + val =3D readl(bias_en); + val |=3D COM_BIAS_EN_MUX | COM_BIAS_EN; + writel(val, bias_en); + } + + qmp_configure(qmp->dev, port + offs->pll, + cfg->pll_tbls[i], cfg->pll_nums[i]); + qmp_configure(qmp->dev, port + offs->txrxz, + tbls->txrxz, tbls->txrxz_num); + qmp_configure(qmp->dev, port + offs->pcs, + tbls->pcs, tbls->pcs_num); + qmp_configure(qmp->dev, port + offs->pcs_lanez, + tbls->pcs_lanez, tbls->pcs_lanez_num); + + if (cfg->bifurcated) + qmp_configure(qmp->dev, port + offs->txrxz, + nord_qmp_pcie_bifurcated_post_cfg_tbl, + ARRAY_SIZE(nord_qmp_pcie_bifurcated_post_cfg_tbl)); + } +} + static int qmp_pcie_pd_power_on(struct qmp_pcie *qmp) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -280,20 +1215,37 @@ static int qmp_pcie_init(struct phy *phy) goto err_pd_power_off; } =20 + ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed: %d\n", ret); + goto err_disable_regulators; + } + ret =3D reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_= resets); if (ret) { dev_err(qmp->dev, "no-csr reset assert failed: %d\n", ret); - goto err_disable_regulators; + goto err_assert_reset; } =20 usleep_range(200, 300); =20 + ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed: %d\n", ret); + goto err_assert_reset; + } + ret =3D clk_bulk_prepare_enable(qmp->cfg->num_clks, qmp->clks); if (ret) - goto err_disable_regulators; + goto err_assert_reset; + + if (cfg->pll_tbls) + qmp_pcie_init_port_registers(qmp); =20 return 0; =20 +err_assert_reset: + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_pd_power_off: @@ -306,8 +1258,19 @@ static int qmp_pcie_exit(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_pcie_offsets *offs =3D cfg->offsets; + int i; =20 - reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); + if (cfg->pll_tbls) { + for (i =3D 0; i < cfg->num_regs; i++) + writel(0x00, qmp->base[i] + offs->pcs + + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]); + } + + if (qmp->nocsr_resets) + reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); + if (qmp->resets) + reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 clk_bulk_disable_unprepare(qmp->cfg->num_clks, qmp->clks); regulator_bulk_disable(cfg->num_vregs, qmp->vregs); @@ -335,6 +1298,15 @@ static int qmp_pcie_power_on(struct phy *phy) goto err_disable_pipe_clk; } =20 + if (cfg->pll_tbls) { + for (i =3D 0; i < cfg->num_regs; i++) { + writel(0x00, qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_SW_RESET]); + writel(0x03, qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_START_CONTRO= L]); + } + + usleep_range(2000, 2500); + } + for (i =3D 0; i < cfg->num_regs; i++) { status =3D qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_STATUS]; ret =3D readl_poll_timeout(status, val, !(val & cfg->phy_status), 200, @@ -357,6 +1329,14 @@ static int qmp_pcie_power_on(struct phy *phy) static int qmp_pcie_power_off(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_pcie_offsets *offs =3D cfg->offsets; + int i; + + if (cfg->pll_tbls) { + for (i =3D 0; i < cfg->num_regs; i++) + writel(0x01, qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_SW_RESET]); + } =20 clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks); =20 @@ -398,45 +1378,39 @@ static const struct phy_ops qmp_pcie_phy_ops =3D { static void qmp_pcie_pd_detach(void *data) { struct qmp_pcie *qmp =3D data; - const struct qmp_phy_cfg *cfg =3D qmp->cfg; int i; =20 - for (i =3D 0; i < cfg->num_pds; i++) { + for (i =3D 0; i < qmp->cfg->num_pds; i++) { if (!IS_ERR_OR_NULL(qmp->pd_devs[i])) dev_pm_domain_detach(qmp->pd_devs[i], true); } } =20 -static int qmp_pcie_pd_init(struct qmp_pcie *qmp) +static int qmp_pcie_pd_init(struct qmp_pcie *qmp, struct phy *phy) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; - struct device *dev =3D qmp->dev; + struct device *pd_dev =3D &phy->dev; int i, ret; =20 if (!cfg->num_pds) return 0; =20 - qmp->pd_devs =3D devm_kcalloc(dev, cfg->num_pds, sizeof(*qmp->pd_devs), + qmp->pd_devs =3D devm_kcalloc(pd_dev, cfg->num_pds, sizeof(*qmp->pd_devs), GFP_KERNEL); if (!qmp->pd_devs) return -ENOMEM; =20 + ret =3D devm_add_action_or_reset(pd_dev, qmp_pcie_pd_detach, qmp); + if (ret) + return ret; + for (i =3D 0; i < cfg->num_pds; i++) { - qmp->pd_devs[i] =3D dev_pm_domain_attach_by_name(dev, - cfg->pd_names[i]); - if (IS_ERR_OR_NULL(qmp->pd_devs[i])) { - ret =3D PTR_ERR(qmp->pd_devs[i]) ? : -ENODATA; - goto err_detach; - } + qmp->pd_devs[i] =3D dev_pm_domain_attach_by_name(pd_dev, cfg->pd_names[i= ]); + if (IS_ERR_OR_NULL(qmp->pd_devs[i])) + return PTR_ERR_OR_ZERO(qmp->pd_devs[i]) ? : -ENODATA; } =20 - return devm_add_action_or_reset(dev, qmp_pcie_pd_detach, qmp); - -err_detach: - while (--i >=3D 0) - dev_pm_domain_detach(qmp->pd_devs[i], false); - - return ret; + return 0; } =20 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) @@ -462,20 +1436,37 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) struct device *dev =3D qmp->dev; int i, ret; =20 - qmp->nocsr_resets =3D devm_kcalloc(dev, cfg->num_nocsr_resets, - sizeof(*qmp->nocsr_resets), - GFP_KERNEL); - if (!qmp->nocsr_resets) - return -ENOMEM; + if (cfg->num_resets) { + qmp->resets =3D devm_kcalloc(dev, cfg->num_resets, + sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; =20 - for (i =3D 0; i < cfg->num_nocsr_resets; i++) - qmp->nocsr_resets[i].id =3D cfg->nocsr_reset_list[i]; + for (i =3D 0; i < cfg->num_resets; i++) + qmp->resets[i].id =3D cfg->reset_list[i]; =20 - ret =3D devm_reset_control_bulk_get_exclusive(dev, - cfg->num_nocsr_resets, - qmp->nocsr_resets); - if (ret) - return dev_err_probe(dev, ret, "failed to get no-csr resets\n"); + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, + qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); + } + + if (cfg->num_nocsr_resets) { + qmp->nocsr_resets =3D devm_kcalloc(dev, cfg->num_nocsr_resets, + sizeof(*qmp->nocsr_resets), + GFP_KERNEL); + if (!qmp->nocsr_resets) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_nocsr_resets; i++) + qmp->nocsr_resets[i].id =3D cfg->nocsr_reset_list[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, + cfg->num_nocsr_resets, + qmp->nocsr_resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get no-csr resets\n"); + } =20 return 0; } @@ -630,6 +1621,7 @@ static struct phy *qmp_pcie_multiphy_xlate(struct devi= ce *dev, static int qmp_pcie_probe_phy(struct qmp_pcie *qmp, struct device_node *np, struct phy **out_phy) { + struct phy *phy; int ret; =20 ret =3D qmp_pcie_get_mmio(qmp); @@ -648,15 +1640,16 @@ static int qmp_pcie_probe_phy(struct qmp_pcie *qmp, = struct device_node *np, if (ret) return ret; =20 - ret =3D qmp_pcie_pd_init(qmp); + phy =3D devm_phy_create(qmp->dev, np, &qmp_pcie_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + ret =3D qmp_pcie_pd_init(qmp, phy); if (ret) return ret; =20 - *out_phy =3D devm_phy_create(qmp->dev, np, &qmp_pcie_phy_ops); - if (IS_ERR(*out_phy)) - return PTR_ERR(*out_phy); - - phy_set_drvdata(*out_phy, qmp); + phy_set_drvdata(phy, qmp); + *out_phy =3D phy; =20 return 0; } @@ -725,6 +1718,10 @@ static const struct of_device_id qmp_pcie_multiphy_of= _match_table[] =3D { .compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy", .data =3D &glymur_qmp_gen5x8_match_data, }, + { + .compatible =3D "qcom,nord-qmp-gen5x16-pcie-phy", + .data =3D &nord_qmp_gen5x16_match_data, + }, { } }; MODULE_DEVICE_TABLE(of, qmp_pcie_multiphy_of_match_table); @@ -739,5 +1736,5 @@ static struct platform_driver qmp_pcie_multiphy_driver= =3D { module_platform_driver(qmp_pcie_multiphy_driver); =20 MODULE_AUTHOR("Qiang Yu "); -MODULE_DESCRIPTION("Qualcomm QMP PCIe Multi-PHY driver for Glymur"); +MODULE_DESCRIPTION("Qualcomm QMP PCIe Multi-PHY driver for Glymur and Nord= "); MODULE_LICENSE("GPL"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h new file mode 100644 index 000000000000..4c6859cebd42 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_40_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_40_H_ + +/* PCS COM =E2=80=94 power, start, clocks */ +#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG2 0x06c +#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG5 0x078 +#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG6 0x07c +#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG7 0x080 +#define QPHY_PCIE_V6_40_PCS_COM_MULTIPHY_CONFIG2 0x088 +#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG2 0x0a0 +#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG3 0x0a4 +#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG5 0x0ac +#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG6 0x0b0 +#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG7 0x0b4 +#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG8 0x0b8 +#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG10 0x0c0 +#define QPHY_PCIE_V6_40_PCS_COM_ENDPOINT_REFCLK_DRIVE 0x0c8 +#define QPHY_PCIE_V6_40_PCS_COM_RX_SIGDET_LVL 0x0ec +#define QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG2 0x0f8 +#define QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG3 0x0fc +#define QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG4 0x100 +#define QPHY_PCIE_V6_40_PCS_COM_OSC_DTCT_ACTIONS 0x194 +#define QPHY_PCIE_V6_40_PCS_COM_LOCK_DETECT_CONFIG1 0x1bc +#define QPHY_PCIE_V6_40_PCS_COM_LOCK_DETECT_CONFIG2 0x1c0 +#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG1 0x1dc +#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG2 0x1e0 +#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG3 0x1e4 +#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG7 0x1f4 +#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG8 0x1f8 + +/* PCS COM =E2=80=94 EQ config */ +#define QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG1 0x380 +#define QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG2 0x384 +#define QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG1 0x38c +#define QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG3 0x394 +#define QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG1 0x3a4 +#define QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG5 0x3b4 +#define QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG7 0x3bc +#define QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG1 0x3c8 +#define QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG5 0x3d8 +#define QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG7 0x3e0 +#define QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG1 0x3ec +#define QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG5 0x3fc +#define QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG7 0x404 +#define QPHY_PCIE_V6_40_PCS_COM_TEST_CONTROL1 0x468 + +/* PCS LANEZ =E2=80=94 output signal mux control */ +#define QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL2 0x0e0 +#define QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL5 0x0f8 + +#endif /* QCOM_PHY_QMP_PCS_PCIE_V6_40_H_ */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h b/drivers/phy/qu= alcomm/phy-qcom-qmp-pcs-v6_40.h new file mode 100644 index 000000000000..c7ac7b3bd97e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_40_H_ +#define QCOM_PHY_QMP_PCS_V6_40_H_ + +#define QPHY_V6_40_PCS_STATUS1 0x010 +#define QPHY_V6_40_PCS_START_CONTROL 0x05c +#define QPHY_V6_40_PCS_SW_RESET 0x060 +#define QPHY_V6_40_PCS_POWER_DOWN_CONTROL 0x064 + +#endif /* QCOM_PHY_QMP_PCS_V6_40_H_ */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h b/d= rivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h new file mode 100644 index 000000000000..a7efd3a8718c --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_PCIE_V6_40_NORD_H_ +#define QCOM_PHY_QMP_QSERDES_COM_PCIE_V6_40_NORD_H_ + +#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1 0x000 +#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1 0x004 +#define QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1 0x00c +#define QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1 0x010 +#define QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1 0x014 +#define QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1 0x018 +#define QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1 0x01c +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1 0x020 +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1 0x024 +#define QSERDES_PCIE_V6_40_COM_DEC_START_MODE1 0x028 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1 0x030 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1 0x034 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1 0x038 +#define QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1 0x03c +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050 +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054 +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c +#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0 0x060 +#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0 0x064 +#define QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0 0x06c +#define QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0 0x070 +#define QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0 0x074 +#define QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0 0x078 +#define QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0 0x07c +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0 0x080 +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0 0x084 +#define QSERDES_PCIE_V6_40_COM_DEC_START_MODE0 0x088 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0 0x090 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0 0x094 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0 0x098 +#define QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1 0x09c +#define QSERDES_PCIE_V6_40_COM_BG_TIMER 0x0bc +#define QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER 0x0c0 +#define QSERDES_PCIE_V6_40_COM_SSC_PER1 0x0cc +#define QSERDES_PCIE_V6_40_COM_SSC_PER2 0x0d0 +#define QSERDES_PCIE_V6_40_COM_POST_DIV_MUX 0x0d8 +#define QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN 0x0dc +#define QSERDES_PCIE_V6_40_COM_CLK_ENABLE1 0x0e0 +#define QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL 0x0e4 +#define QSERDES_PCIE_V6_40_COM_PLL_IVCO 0x0f4 +#define QSERDES_PCIE_V6_40_COM_CMN_IETRIM 0x0fc +#define QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN 0x120 +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG 0x124 +#define QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL 0x13c +#define QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_PCIE_V6_40_COM_CLK_SELECT 0x164 +#define QSERDES_PCIE_V6_40_COM_CORE_CLK_EN 0x170 +#define QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1 0x174 +#define QSERDES_PCIE_V6_40_COM_CMN_MISC1 0x188 +#define QSERDES_PCIE_V6_40_COM_CMN_MODE 0x18c +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1 0x1a0 +#define QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL 0x19c +#define QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2 0x21c +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2 0x220 +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2 0x224 +#define QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2 0x228 +#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2 0x230 +#define QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2 0x22c +#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2 0x1cc +#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2 0x1d0 +#define QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2 0x1dc +#define QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2 0x1e0 +#define QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2 0x1e4 +#define QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2 0x1e8 +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2 0x1ec +#define QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2 0x1f0 +#define QSERDES_PCIE_V6_40_COM_DEC_START_MODE2 0x1f4 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2 0x1fc +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2 0x200 +#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2 0x204 +#define QSERDES_PCIE_V6_40_COM_DCC_CAL_1 0x2d8 +#define QSERDES_PCIE_V6_40_COM_DCC_CAL_2 0x2dc +#define QSERDES_PCIE_V6_40_COM_DCC_CAL_3 0x2e0 +#define QSERDES_PCIE_V6_40_COM_PSM_CAL_EN 0x2f0 +#define QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1 0x2f4 +#define QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL 0x2fc +#define QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO 0x2b8 +#define QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1 0x0f8 +#define QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2 0x218 +#define QSERDES_PCIE_V6_40_COM_DCC_CAL_7 0x300 +#define QSERDES_PCIE_V6_40_COM_DCC_CAL_8 0x304 +#define QSERDES_PCIE_V6_40_COM_DCC_CAL_9 0x308 + +#endif /* QCOM_PHY_QMP_QSERDES_COM_PCIE_V6_40_NORD_H_ */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h b= /drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h new file mode 100644 index 000000000000..dba8599be1fb --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRXZ_PCIE_V6_40_NORD_H_ +#define QCOM_PHY_QMP_QSERDES_TXRXZ_PCIE_V6_40_NORD_H_ + +/* Lane mode / LDO */ +#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL1 0x070 +#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL2 0x074 +#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL3 0x078 +#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL4 0x07c +#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_1 0x094 +#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_2 0x098 +#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_3 0x09c +#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_4 0x0a0 +#define QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_VREF_SEL 0x0bc +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B0 0x0f4 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B1 0x0f8 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B2 0x0fc +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B3 0x100 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B4 0x104 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B5 0x108 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B6 0x10c +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B7 0x110 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B0 0x114 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B1 0x118 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B2 0x11c +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B3 0x120 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B4 0x124 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B5 0x128 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B6 0x12c +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B7 0x130 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B0 0x134 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B1 0x138 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B2 0x13c +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B3 0x140 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B4 0x144 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B5 0x148 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B6 0x14c +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B7 0x150 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B0 0x154 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B1 0x158 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B2 0x15c +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B3 0x160 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B4 0x164 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B5 0x168 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B6 0x16c +#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B7 0x170 + +/* VCO / KVCO calibration */ +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE0 0x1b4 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE0 0x1b8 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE1 0x1bc +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE1 0x1c0 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE2 0x1c4 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE2 0x1c8 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE3 0x1cc +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE3 0x1d0 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE4 0x1d4 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE4 0x1d8 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_0_1 0x1dc +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_2_3 0x1e0 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_0_1 0x1e8 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_2_3 0x1ec +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_4 0x1f0 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE0 0x1f4 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE1 0x1f8 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE2 0x1fc +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE0 0x220 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE0 0x224 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE1 0x228 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE1 0x22c +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE2 0x230 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE2 0x234 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE3 0x238 +#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE4 0x240 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CODE_OVRD_RATE_2_3 0x250 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE0 0x258 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1 0x260 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2 0x268 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE3 0x270 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE4 0x278 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE0 0x280 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1 0x284 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2 0x288 +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE3 0x28c +#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE4 0x290 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_SUMMER_CAL_SPD_MODE_RATE_0123 0x2a8 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL2 0x2c8 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL3 0x2cc +#define QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL4 0x2d0 + +/* Signal detect */ +#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_ENABLES 0x31c +#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE0 0x33c +#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE1 0x340 +#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE2 0x344 +#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE3 0x348 +#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE4 0x34c + +/* CDR */ +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOCK_CTRL 0x364 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE0 0x368 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE1 0x36c +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE2 0x370 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE3 0x374 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE4 0x378 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE0 0x37c +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE1 0x380 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE2 0x384 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE3 0x388 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE4 0x38c +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_FLL_DIV_RATIO_RATE_0123 0x390 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_01 0x398 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_23 0x39c +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE4 0x3a0 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_0_1 0x3a4 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_2_3 0x3a8 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE4 0x3ac +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_0_1 0x3b0 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_2_3 0x3b4 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE4 0x3b8 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_0_1 0x3bc +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_2_3 0x3c0 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE4 0x3c4 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE_0123 0x3c8 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_TYPE_CONFIG 0x3d0 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_EN_LOWFREQ 0x3d4 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_FUNC_CTRL 0x3dc + +/* Rescode / residuals */ +#define QSERDES_PCIE_V6_40_TXRXZ_RES_CODE_LANE_OFFSET_RX 0x3f4 + +/* VGA / GM calibration */ +#define QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE0_1 0x404 +#define QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE2_3 0x408 +#define QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE4 0x40c + +/* RX equalizer */ +#define QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL3 0x454 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL4 0x458 +#define QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL5 0x45c +#define QSERDES_PCIE_V6_40_TXRXZ_CTLE_POST_CAL_OFFSET_RATE_0_1_2 0x478 +#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE0_1 0x490 +#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE2_3 0x494 +#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE4 0x498 +#define QSERDES_PCIE_V6_40_TXRXZ_VTHRESH_CAL_MAN_VAL_RATE4 0x4bc + +/* DFE */ +#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP1_DAC_ENABLE 0x50c +#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP2_DAC_ENABLE 0x510 +#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP345_DAC_ENABLE 0x514 +#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP67_DAC_ENABLE 0x518 +#define QSERDES_PCIE_V6_40_TXRXZ_PHPRE_CTRL 0x51c +#define QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH1 0x52c +#define QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH2 0x530 +#define QSERDES_PCIE_V6_40_TXRXZ_TX_ADPT_CTRL 0x53c +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_CTRL 0x548 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_MAN_INDEX 0x550 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_ANA_CTRL 0x584 +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_DIV2_CTRL_RATE0123 0x58c +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_OVRD_MUXES 0x5ac +#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE4 0x3cc + +/* Clock buffer / LDO stall control (used by bifurcated pre/post-pwrup seq= uences) */ +#define QSERDES_PCIE_V6_40_TXRXZ_CLKBUF_ENABLE 0x04c +#define QSERDES_PCIE_V6_40_TXRXZ_PRE_STALL_LDO_BOOST_EN 0x06c +#define QSERDES_PCIE_V6_40_TXRXZ_LDO_TIMER_CTRL 0x0d8 + +/* Restrim / VGA / signal-detect (v2-only) */ +#define QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_CAL_CTRL 0x0b0 +#define QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_POST_CAL_OFFSET 0x0b8 +#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CNTRL 0x320 +#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_LVL 0x324 +#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CAL_CTRL1 0x32c +#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_CNTRL1 0x488 + +/* BLW / VCO coarse-tune bands (v2-only) */ +#define QSERDES_PCIE_V6_40_TXRXZ_BLW_CTRL 0x594 +#define QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE3 0x5a4 +#define QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE4 0x5a8 +#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE0 0x5c4 +#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE1 0x5c8 +#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE2 0x5cc +#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE3 0x5d0 +#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE4 0x5d4 + +/* Analog backup control (v2-only) */ +#define QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL15 0x7e8 +#define QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL16 0x7ec + +#endif /* QCOM_PHY_QMP_QSERDES_TXRXZ_PCIE_V6_40_NORD_H_ */ --=20 2.34.1