From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E6C046AA9E; Fri, 28 Aug 2026 13:48:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924907; cv=none; b=snwLptBECJlFjRuB/2OIIU2K7OyGw5vPCuTf0zoS/tQf1RPpRqk4PQiuPlZi3E/oqxiLRnrhf+XWe6JzlapMlbXAqjZsdFvagxeUOmFn0eDIZ6rJbjVrF/DHnGCOD+wDr0umKL9cW6AV268H66vBjZCMZA9BVVuV+0Yy7ff5xoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924907; c=relaxed/simple; bh=DVeDmDY8+e7it+VhUQ37DTmCegS6j4QcAXKo2PPe2GA=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=LYzZqzbJAItDJhWXa0x9LGoOJANHjhQEUrUoQvfm/obLWv8ZUXYv4p+kvcZuX46CEAFdfO+EnH/TI4TMqVk2Lkwm5hpB0PzizFtJm3iaxe6vKvRHZBE5embSzhXy29a5eDCryrmrfPPK21uQxgQNUoiJPJFOXagLsQe3LyL0/jI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=B/w8SZId; arc=none smtp.client-ip=210.118.77.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="B/w8SZId" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20260828134816euoutp018a0c3e2648795ffd6e03561f443696bd~P-DhYbMaO2677926779euoutp018; Fri, 28 Aug 2026 13:48:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20260828134816euoutp018a0c3e2648795ffd6e03561f443696bd~P-DhYbMaO2677926779euoutp018 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1787924896; bh=uMTpvxWIHTWA5WP2+3K9U8sgXeHo5NdCmMYa7bPSnFI=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=B/w8SZIdtavo0kLqWnRiPR2OA723DIkfCChmZ+OPJqHz5nfOte89SnOIh+yWFQaPv NQJxv8AiBNCaZDDSihO5pm6DSn6G7W4nQ3kb3msDcDh8cXjR79awH+wMAIcZIuFwmd itwk5250Em5HcXDkBo2frc2bh01uxLTdtk0OEa4U= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20260828134815eucas1p2b2aabc17e9cc6346e5a93bde5c650958~P-DhB-03v2418024180eucas1p29; Fri, 28 Aug 2026 13:48:15 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134813eusmtip1ecc4bb650325f36fd9950693c44853ee~P-DfbWOlr2831928319eusmtip1V; Fri, 28 Aug 2026 13:48:13 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:25 +0200 Subject: [PATCH v2 01/15] dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-1-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134815eucas1p2b2aabc17e9cc6346e5a93bde5c650958 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134815eucas1p2b2aabc17e9cc6346e5a93bde5c650958 X-EPHeader: CA X-CMS-RootMailID: 20260828134815eucas1p2b2aabc17e9cc6346e5a93bde5c650958 References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> Add the dt-binding for the StarFive JH7110 Innosilicon HDMI PHY. This device is a child of the starfive,jh7110-hdmi-subsystem node. It functions as both a PHY provider for the controller and as a clock provider for the variable pixel clock (hdmi_pclk), which it generates from its refoclk. Signed-off-by: Michal Wilczynski --- .../phy/starfive,jh7110-inno-hdmi-phy.yaml | 58 ++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdm= i-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdm= i-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b1ab3c555fbf60a971f511af29a= 03a6b2e4ae097 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.y= aml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Innosilicon INNO HDMI PHY + +maintainers: + - Michal Wilczynski + +description: + The PHY portion of the StarFive JH7110 INNO HDMI IP. + +properties: + compatible: + const: starfive,jh7110-inno-hdmi-phy + + clocks: + maxItems: 1 + + clock-names: + const: refoclk + + '#clock-cells': + const: 0 + + clock-output-names: + const: hdmi_pclk + + '#phy-cells': + const: 0 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + - clock-output-names + - '#phy-cells' + +additionalProperties: false + +examples: + # Shown as a child of the HDMI subsystem node; see + # Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.y= aml + # for the full node. + - | + phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + #clock-cells =3D <0>; + clock-output-names =3D "hdmi_pclk"; + clocks =3D <&xin24m>; + clock-names =3D "refoclk"; + #phy-cells =3D <0>; + }; + +... --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C15E9469834; Fri, 28 Aug 2026 13:48:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924909; cv=none; b=QDX+YQl+0mrP/FzqeiIae+zLks3GVrytWybxeJVcaxy56cT2hvI+ITFwfwnr5QHdedo16B4YhxT6iIysW5UgRSPAQSMC5qfx+gP5Xb8sG1qPpdUIsPd5pXnKteHX6DJ3kOc3k5a34xEBOC9XPO3XLauQbRRpdPzyUsFe4LX9Bw8= ARC-Message-Signature: i=1; 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Fri, 28 Aug 2026 13:48:15 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:26 +0200 Subject: [PATCH v2 02/15] dt-bindings: display: bridge: Add starfive,jh7110-inno-hdmi-controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-2-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134817eucas1p2e2756deff8871be4ea8bb5c65f9c179d X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134817eucas1p2e2756deff8871be4ea8bb5c65f9c179d X-EPHeader: CA X-CMS-RootMailID: 20260828134817eucas1p2e2756deff8871be4ea8bb5c65f9c179d References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> Add the dt-binding for the StarFive JH7110 Innosilicon HDMI controller (DRM bridge). This device is the second child of the starfive,jh7110-hdmi-subsystem node. It consumes register access clocks (sys, mclk, bclk) from the voutcrg and both the pixel clock (pclk) and the PHY from its hdmi_phy sibling. Signed-off-by: Michal Wilczynski --- .../starfive,jh7110-inno-hdmi-controller.yaml | 109 +++++++++++++++++= ++++ 1 file changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/starfive,jh71= 10-inno-hdmi-controller.yaml b/Documentation/devicetree/bindings/display/br= idge/starfive,jh7110-inno-hdmi-controller.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0e584e7b756e24e2f99a62daab3= 117bbf4b472b6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno= -hdmi-controller.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/starfive,jh7110-inno-hdm= i-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Innosilicon HDMI Controller + +maintainers: + - Michal Wilczynski + +description: + The controller portion of the StarFive JH7110 INNO HDMI IP. + +properties: + compatible: + const: starfive,jh7110-inno-hdmi-controller + + interrupts: + maxItems: 1 + + clocks: + items: + - description: System clock for register access + - description: Module clock + - description: Bus clock + - description: Pixel clock from PHY + + clock-names: + items: + - const: sys + - const: mclk + - const: bclk + - const: pclk + + resets: + maxItems: 1 + + reset-names: + const: hdmi_tx + + phys: + maxItems: 1 + + phy-names: + const: hdmi-phy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: + A graph node with one input port and one output port. + +required: + - compatible + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +additionalProperties: false + +examples: + # Shown as a child of the HDMI subsystem node; see + # Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.y= aml + # for the full node. + - | + #include + #include + + controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "sys", "mclk", "bclk", "pclk"; + interrupts =3D <99>; + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + port@1 { + reg =3D <1>; + + endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; + }; + +... --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50CDF4483B4; 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Fri, 28 Aug 2026 13:48:19 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134817eusmtip1ad736395c6f4339d7910b9f526dd37bc~P-DizugV62831928319eusmtip1W; Fri, 28 Aug 2026 13:48:17 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:27 +0200 Subject: [PATCH v2 03/15] dt-bindings: mfd: Add starfive,jh7110-hdmi-subsystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-3-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134819eucas1p2c8e2bb95dd957981ec5e60e1da03223c X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134819eucas1p2c8e2bb95dd957981ec5e60e1da03223c X-EPHeader: CA X-CMS-RootMailID: 20260828134819eucas1p2c8e2bb95dd957981ec5e60e1da03223c References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> Add the dt-binding for the StarFive JH7110 HDMI subsystem. The JH7110 HDMI IP is a monolithic block containing both the digital controller and analog PHY in a single register space. This binding defines the parent device, which holds the shared register map and populates its two children: the PHY and the controller. This is necessary to resolve a circular clock dependency between the HDMI block and the VOUT clock generator. Signed-off-by: Michal Wilczynski --- .../mfd/starfive,jh7110-hdmi-subsystem.yaml | 116 +++++++++++++++++= ++++ 1 file changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-sub= system.yaml b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-su= bsystem.yaml new file mode 100644 index 0000000000000000000000000000000000000000..01f079160ab8c13c6fa4ce3abaa= c6607021b3792 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.= yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/starfive,jh7110-hdmi-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 HDMI subsystem + +maintainers: + - Michal Wilczynski + +description: + The StarFive JH7110 HDMI block is a monolithic IP containing both + the digital controller logic and the analog PHY logic in a single + register space. + +properties: + compatible: + const: starfive,jh7110-hdmi-subsystem + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + NoC display bus clock, which gates access to the whole vout + register region. + + resets: + maxItems: 1 + description: + NoC display bus reset, which gates access to the whole vout + register region. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + - power-domains + +patternProperties: + "^phy(@[0-9a-f]+)?$": + $ref: /schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml# + "^controller(@[0-9a-f]+)?$": + $ref: /schemas/display/bridge/starfive,jh7110-inno-hdmi-controller.yam= l# + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-subsystem"; + reg =3D <0x29590000 0x4000>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>; + power-domains =3D <&pwrc JH7110_PD_VOUT>; + resets =3D <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>; + + controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "sys", "mclk", "bclk", "pclk"; + interrupts =3D <99>; + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + port@1 { + reg =3D <1>; + + endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; + }; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; 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Fri, 28 Aug 2026 13:48:19 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:28 +0200 Subject: [PATCH v2 04/15] drm/bridge: inno-hdmi: Split probe out of bind Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-4-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134821eucas1p2a29505e5487f9e773a36b5dde7257df1 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134821eucas1p2a29505e5487f9e773a36b5dde7257df1 X-EPHeader: CA X-CMS-RootMailID: 20260828134821eucas1p2a29505e5487f9e773a36b5dde7257df1 References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> inno_hdmi_bind() both sets up the bridge and attaches it to a DRM encoder. A platform whose HDMI controller is a child of a larger device needs the first half without the second, since it registers as its own platform driver and lets the DRM core bind the bridge later. Move the setup into a new exported inno_hdmi_probe(), with a matching inno_hdmi_remove(), and reduce inno_hdmi_bind() to a wrapper around it. No functional change intended. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 40 +++++++++++++++++++++++++++++++++-= ---- include/drm/bridge/inno_hdmi.h | 4 ++++ 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 9a62bf59a4033ae9150d82a6defdd78d1f1f2fcb..12fd208d5e852cdcbdebef7853c= b4143c5fe1c0f 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -1061,11 +1061,24 @@ static struct i2c_adapter *inno_hdmi_i2c_adapter(st= ruct inno_hdmi *hdmi) return adap; } =20 -struct inno_hdmi *inno_hdmi_bind(struct device *dev, - struct drm_encoder *encoder, - const struct inno_hdmi_plat_data *plat_data) +/** + * inno_hdmi_probe - Internal helper to perform common setup + * @pdev: platform device + * @plat_data: SoC-specific platform data + * + * This function handles all the common hardware setup: allocating the main + * struct, mapping registers, getting clocks, initializing the hardware, + * setting up the IRQ, and initializing the DDC adapter and bridge struct. + * It returns a pointer to the inno_hdmi struct on success, or an ERR_PTR + * on failure. + * + * This function is used by modern, decoupled MFD/glue drivers. It registe= rs + * the bridge but does not attach it. + */ +struct inno_hdmi *inno_hdmi_probe(struct platform_device *pdev, + const struct inno_hdmi_plat_data *plat_data) { - struct platform_device *pdev =3D to_platform_device(dev); + struct device *dev =3D &pdev->dev; struct inno_hdmi *hdmi; int irq; int ret; @@ -1128,7 +1141,24 @@ struct inno_hdmi *inno_hdmi_bind(struct device *dev, if (ret) return ERR_PTR(ret); =20 - ret =3D drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH= _NO_CONNECTOR); + return hdmi; +} +EXPORT_SYMBOL_GPL(inno_hdmi_probe); + +struct inno_hdmi *inno_hdmi_bind(struct device *dev, + struct drm_encoder *encoder, + const struct inno_hdmi_plat_data *plat_data) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct inno_hdmi *hdmi; + int ret; + + hdmi =3D inno_hdmi_probe(pdev, plat_data); + if (IS_ERR(hdmi)) + return hdmi; + + ret =3D drm_bridge_attach(encoder, &hdmi->bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) return ERR_PTR(ret); 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Fri, 28 Aug 2026 13:48:22 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134821eusmtip1125830265f6655cf1c8de06e0caa93e6~P-DmMb-TN2815728157eusmtip1A; Fri, 28 Aug 2026 13:48:21 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:29 +0200 Subject: [PATCH v2 05/15] drm/bridge: inno-hdmi: Allow the register map to come from a parent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-5-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134822eucas1p15d7a98e2e05c51aaacaac5e946337d07 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134822eucas1p15d7a98e2e05c51aaacaac5e946337d07 X-EPHeader: CA X-CMS-RootMailID: 20260828134822eucas1p15d7a98e2e05c51aaacaac5e946337d07 References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> On some SoCs the HDMI controller does not own its register window. The StarFive JH7110 documents one 64 KB block, u0_hdmitx, that holds both the controller and the PHY, so the parent device maps it and owns the regmap while the two children share it. Use a regmap supplied by the parent device when there is one, and keep mapping our own resource when there is not, so platforms that own their register window are unaffected. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 12fd208d5e852cdcbdebef7853cb4143c5fe1c0f..ebc5093f13ac4f263b903fb7276= 29dfb83d051e1 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -397,6 +397,7 @@ struct inno_hdmi { struct clk *pclk; struct clk *refclk; void __iomem *regs; + struct regmap *regmap; struct regmap *grf; =20 struct inno_hdmi_i2c *i2c; @@ -470,11 +471,23 @@ static int inno_hdmi_find_phy_config(struct inno_hdmi= *hdmi, =20 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) { + u32 val; + + if (hdmi->regmap) { + regmap_read(hdmi->regmap, offset * 4, &val); + return val; + } + return readl_relaxed(hdmi->regs + (offset) * 0x04); } =20 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) { + if (hdmi->regmap) { + regmap_write(hdmi->regmap, offset * 4, val); + return; + } + writel_relaxed(val, hdmi->regs + (offset) * 0x04); } =20 @@ -1095,9 +1108,19 @@ struct inno_hdmi *inno_hdmi_probe(struct platform_de= vice *pdev, hdmi->dev =3D dev; hdmi->plat_data =3D plat_data; =20 - hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(hdmi->regs)) - return ERR_CAST(hdmi->regs); + /* + * On platforms where the controller shares a register space with + * other blocks, the parent owns the regmap. Fall back to mapping + * our own resource where it does not. + */ + if (dev->parent) + hdmi->regmap =3D dev_get_regmap(dev->parent, NULL); + + if (!hdmi->regmap) { + hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hdmi->regs)) + return ERR_CAST(hdmi->regs); + } =20 hdmi->pclk =3D devm_clk_get_enabled(hdmi->dev, "pclk"); if (IS_ERR(hdmi->pclk)) { --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0A3046D087; Fri, 28 Aug 2026 13:48:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924910; cv=none; b=UHYfUWu2Q/mCGUjAlZcSEtPXHVXlE/VTn9lR3Cs6AI6UPluHTqbb3HbKJjLbUGTLIHFEJjRrfxbI/Xxj8r8yocfA1klFbUI+f0xqsi4Ae+b5DJA+ZZSXUgFyroWz+361QFem4LXKBA/2n3TPZe9RCkkOIxRCwtiNGPpUAQByARw= ARC-Message-Signature: i=1; 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Fri, 28 Aug 2026 13:48:22 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:30 +0200 Subject: [PATCH v2 06/15] drm/bridge: inno-hdmi: Add .disable platform operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-6-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134824eucas1p12730831aa4d01856e0c0e6b678c82bdb X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134824eucas1p12730831aa4d01856e0c0e6b678c82bdb X-EPHeader: CA X-CMS-RootMailID: 20260828134824eucas1p12730831aa4d01856e0c0e6b678c82bdb References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> The Innosilicon HDMI driver supports platform-specific behavior through the `inno_hdmi_plat_ops`. While it provides an `.enable` hook for platform-specific power up sequences (like enabling PHYs), it lacks a corresponding hook for power down. This patch adds a new `.disable` op to the `inno_hdmi_plat_ops` struct and calls it at the beginning of `inno_hdmi_bridge_atomic_disable()`. This allows platform specific drivers, such as the StarFive JH7110, to implement their own power down sequence (e.g., calling phy_power_off() and clk_disable_unprepare()). Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 4 ++++ include/drm/bridge/inno_hdmi.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index ebc5093f13ac4f263b903fb727629dfb83d051e1..952cc55c10f7dc07de6ebe943aa= e3e54df2edc8d 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -884,6 +884,10 @@ static void inno_hdmi_bridge_atomic_disable(struct drm= _bridge *bridge, struct drm_atomic_commit *state) { struct inno_hdmi *hdmi =3D bridge_to_inno_hdmi(bridge); + const struct inno_hdmi_plat_ops *plat_ops =3D hdmi->plat_data->ops; + + if (plat_ops && plat_ops->disable) + plat_ops->disable(hdmi->dev); =20 inno_hdmi_standby(hdmi); } diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h index 81da9d9bcd79db8fe26c6dff4569371e484df608..5fca651c56b056d814124aa9c7e= 91aa7fd7ed1cd 100644 --- a/include/drm/bridge/inno_hdmi.h +++ b/include/drm/bridge/inno_hdmi.h @@ -16,6 +16,7 @@ struct platform_device; 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Fri, 28 Aug 2026 13:48:24 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:31 +0200 Subject: [PATCH v2 07/15] drm/bridge: inno-hdmi: Add .mode_valid platform operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-7-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134826eucas1p1ed3a0c4a3207dc01d1ccb33e45ae462e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134826eucas1p1ed3a0c4a3207dc01d1ccb33e45ae462e X-EPHeader: CA X-CMS-RootMailID: 20260828134826eucas1p1ed3a0c4a3207dc01d1ccb33e45ae462e References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> inno_hdmi_bridge_mode_valid() validates the pixel clock against hdmi->refclk, but that clock is optional and is only present on platforms that describe a "ref" clock. Platforms where the pixel clock is produced by a separate device - such as the StarFive JH7110, whose PHY is both the clock and the PHY provider - have no "ref" clock, so the check is skipped entirely and every mode is reported as valid. A mode the platform cannot generate is then advertised to userspace. The subsequent modeset appears to succeed, since the atomic enable path cannot fail, and the display silently stays blank. Add a .mode_valid platform operation so platforms can reject modes they are unable to drive. Platforms that do not implement it are unaffected. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 9 +++++++++ include/drm/bridge/inno_hdmi.h | 5 ++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 952cc55c10f7dc07de6ebe943aae3e54df2edc8d..6da1ef923c99676a2133b4c0e3b= a5744195a335c 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -821,6 +821,7 @@ static enum drm_mode_status inno_hdmi_bridge_mode_valid= (struct drm_bridge *bridg const struct drm_display_mode *mode) { struct inno_hdmi *hdmi =3D bridge_to_inno_hdmi(bridge); + const struct inno_hdmi_plat_ops *plat_ops =3D hdmi->plat_data->ops; unsigned long mpixelclk, max_tolerance; long rounded_refclk; =20 @@ -836,6 +837,14 @@ static enum drm_mode_status inno_hdmi_bridge_mode_vali= d(struct drm_bridge *bridg if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) return MODE_CLOCK_HIGH; =20 + if (plat_ops && plat_ops->mode_valid) { + enum drm_mode_status status; + + status =3D plat_ops->mode_valid(hdmi->dev, mode); + if (status !=3D MODE_OK) + return status; + } + if (hdmi->refclk) { rounded_refclk =3D clk_round_rate(hdmi->refclk, mpixelclk); if (rounded_refclk < 0) diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h index 5fca651c56b056d814124aa9c7e91aa7fd7ed1cd..1e9974401c39e3773bb339eaec0= b45ff1dd9c975 100644 --- a/include/drm/bridge/inno_hdmi.h +++ b/include/drm/bridge/inno_hdmi.h @@ -8,15 +8,18 @@ =20 #include =20 +#include + struct device; struct drm_encoder; -struct drm_display_mode; struct inno_hdmi; struct platform_device; =20 struct inno_hdmi_plat_ops { void (*enable)(struct device *pdev, struct drm_display_mode *mode); void (*disable)(struct device *pdev); + enum drm_mode_status (*mode_valid)(struct device *pdev, + const struct drm_display_mode *mode); }; =20 struct inno_hdmi_phy_config { --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A56E46EC67; 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Fri, 28 Aug 2026 13:48:28 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134826eusmtip1137c7674e9e25e437900ae3d3c66b961~P-DrOH9982815728157eusmtip1C; Fri, 28 Aug 2026 13:48:26 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:32 +0200 Subject: [PATCH v2 08/15] soc: starfive: Add jh7110-hdmi-subsystem driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-8-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134828eucas1p1b4061de1538ef0d3322dc32f3db6140e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134828eucas1p1b4061de1538ef0d3322dc32f3db6140e X-EPHeader: CA X-CMS-RootMailID: 20260828134828eucas1p1b4061de1538ef0d3322dc32f3db6140e References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> Add the parent driver for the monolithic JH7110 HDMI IP block. This driver binds to the starfive,jh7110-hdmi-subsystem node. It maps the shared register block, creates a regmap, and calls devm_of_platform_populate() to create its hdmi_phy and hdmi_controller child devices, which retrieve the shared regmap from this parent. The NoC display-bus clock and reset gate access to the whole vout register region, and this subsystem's PHY child is the first device there to touch registers. Enable the bus before populating the children; PD_VOUT is handled by genpd through the power-domains property. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Signed-off-by: Michal Wilczynski --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/starfive/Kconfig | 27 +++++++ drivers/soc/starfive/Makefile | 2 + drivers/soc/starfive/jh7110-hdmi-subsystem.c | 114 +++++++++++++++++++++++= ++++ 5 files changed, 145 insertions(+) diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index a2d65adffb8052c0ac5a6b60bf33fa9c644701bb..b3b01fc38139d98076c14f626a4= 2ae3b7ef7c5d6 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" source "drivers/soc/sophgo/Kconfig" +source "drivers/soc/starfive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index c9e689080ceb759384f690c2b65a82b3cb451c74..009f85ff891a15e0455f92c5d5a= 4059d8b1fcd3f 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -30,6 +30,7 @@ obj-y +=3D renesas/ obj-y +=3D rockchip/ obj-$(CONFIG_SOC_SAMSUNG) +=3D samsung/ obj-y +=3D sophgo/ +obj-y +=3D starfive/ obj-y +=3D sunxi/ obj-$(CONFIG_ARCH_TEGRA) +=3D tegra/ obj-y +=3D ti/ diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..7592d87dea37a7c14560b3eb9b2= 3e49e503c2d71 --- /dev/null +++ b/drivers/soc/starfive/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Starfive SoC drivers +# + +if ARCH_STARFIVE || COMPILE_TEST +menu "Starfive SoC drivers" + +config SOC_STARFIVE_JH7110_HDMI_SUBSYSTEM + tristate "StarFive JH7110 HDMI subsystem driver" + depends on OF + help + This option enables the parent driver + for the monolithic StarFive JH7110 HDMI peripheral. + + The JH7110 HDMI IP block contains both the digital controller + (DRM bridge) and the analog PHY (clock/phy provider) logic within + a single shared register space. + + This driver acts as a wrapper. Its only job is to map the + shared registers and create separate logical child devices + for the "PHY" and the "controller". This is required to + correctly manage resources and break a circular clock dependency + between the PHY and the VOUT clock generator at probe time. + +endmenu +endif diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..be89d8119212b7a7038817c2f0e= 8eac1984ada88 --- /dev/null +++ b/drivers/soc/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SOC_STARFIVE_JH7110_HDMI_SUBSYSTEM) +=3D jh7110-hdmi-subsyste= m.o diff --git a/drivers/soc/starfive/jh7110-hdmi-subsystem.c b/drivers/soc/sta= rfive/jh7110-hdmi-subsystem.c new file mode 100644 index 0000000000000000000000000000000000000000..d893c1c29f98b072b09d261343d= 3317dbf4c75fe --- /dev/null +++ b/drivers/soc/starfive/jh7110-hdmi-subsystem.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the StarFive JH7110 HDMI subsystem + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * This driver binds to the monolithic HDMI block and creates separate + * logical platform devices for the HDMI Controller (bridge) and the + * HDMI PHY (clock/phy provider), allowing them to share a single regmap + * and breaking the probing circular dependency. + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct regmap_config starfive_hdmi_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 8, + .max_register =3D 0x3fff, +}; + +static void starfive_hdmi_subsys_clk_disable(void *data) +{ + clk_disable_unprepare(data); +} + +static void starfive_hdmi_subsys_rst_assert(void *data) +{ + reset_control_assert(data); +} + +static int starfive_hdmi_subsys_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct reset_control *bus_rst; + void __iomem *regs; + struct regmap *regmap; + struct clk *bus_clk; + int ret; + + /* + * The NoC display-bus clock and reset gate access to the whole vout + * register region, and this subsystem's PHY child is the first device in + * that region to touch registers. Bring the bus up here before + * populating the children; PD_VOUT is powered on by genpd through the + * power-domains property. + */ + bus_clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(bus_clk)) + return dev_err_probe(dev, PTR_ERR(bus_clk), + "Failed to get NoC bus clock\n"); + + ret =3D clk_prepare_enable(bus_clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable NoC bus clock\n"); + + ret =3D devm_add_action_or_reset(dev, starfive_hdmi_subsys_clk_disable, b= us_clk); + if (ret) + return ret; + + bus_rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(bus_rst)) + return dev_err_probe(dev, PTR_ERR(bus_rst), + "Failed to get NoC bus reset\n"); + + ret =3D reset_control_deassert(bus_rst); + if (ret) + return dev_err_probe(dev, ret, "Failed to deassert NoC bus reset\n"); + + ret =3D devm_add_action_or_reset(dev, starfive_hdmi_subsys_rst_assert, bu= s_rst); + if (ret) + return ret; + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + regmap =3D devm_regmap_init_mmio(dev, regs, + &starfive_hdmi_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Failed to init shared regmap\n"); + + ret =3D devm_of_platform_populate(dev); + if (ret) + dev_err(dev, "Failed to populate child devices: %d\n", ret); + + return ret; +} + +static const struct of_device_id starfive_hdmi_subsys_of_match[] =3D { + { .compatible =3D "starfive,jh7110-hdmi-subsystem", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_subsys_of_match); + +static struct platform_driver starfive_hdmi_subsys_driver =3D { + .probe =3D starfive_hdmi_subsys_probe, + .driver =3D { + .name =3D "starfive-hdmi-subsystem", + .of_match_table =3D starfive_hdmi_subsys_of_match, + }, +}; +module_platform_driver(starfive_hdmi_subsys_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive JH7110 HDMI subsystem Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84ADB46D2C8; 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Fri, 28 Aug 2026 13:48:30 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134828eusmtip1e10f1777df471d94950c3265ef92b9ac~P-Ds8YdKI2833728337eusmtip16; Fri, 28 Aug 2026 13:48:28 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:33 +0200 Subject: [PATCH v2 09/15] clk: starfive: jh7110-vout: Allow pixel clock rate propagation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-9-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134830eucas1p1188cde4642239a10afedf46b415dfde4 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134830eucas1p1188cde4642239a10afedf46b415dfde4 X-EPHeader: CA X-CMS-RootMailID: 20260828134830eucas1p1188cde4642239a10afedf46b415dfde4 References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller, and the rate they carry is ultimately produced by the HDMI PHY, which registers hdmitx0_pixelclk as a clock provider. Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them reaches that parent, instead of being clamped to whatever rate the parent already happens to run at. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Signed-off-by: Michal Wilczynski --- drivers/clk/starfive/clk-starfive-jh7110-vout.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/= starfive/clk-starfive-jh7110-vout.c index bad20d5d794a72f071b4d547b7304786a8ba9afa..b608fe358031109a15962a623b1= c14d424023c02 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -40,10 +40,10 @@ static const struct jh71x0_clk_data jh7110_voutclk_data= [] =3D { JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VO= UT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_= VOUT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VO= UT_TOP_AHB), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", CLK_SET_RATE_PAREN= T, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", CLK_SET_RATE_PAREN= T, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), /* LCD */ --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 815AF46C85D; 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Fri, 28 Aug 2026 13:48:32 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134830eusmtip130a7a761181585ee77bcbd8fe2c99b21~P-Duo9cUh2825028250eusmtip1a; Fri, 28 Aug 2026 13:48:30 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:34 +0200 Subject: [PATCH v2 10/15] drm/bridge: starfive: Add JH7110 HDMI controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-10-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134832eucas1p28eb7a61379525744cce7edfc0d579d8e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134832eucas1p28eb7a61379525744cce7edfc0d579d8e X-EPHeader: CA X-CMS-RootMailID: 20260828134832eucas1p28eb7a61379525744cce7edfc0d579d8e References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> Add the HDMI controller (bridge) driver for the StarFive JH7110. This driver binds to the starfive,jh7110-inno-hdmi-controller node. It gets its shared regmap from its parent and its clocks (sys, mclk, bclk) from voutcrg. It consumes the pclk (pixel clock) and PHY from its hdmi_phy sibling. The driver calls the generic inno_hdmi_probe function and passes the shared regmap to it, registering as a DRM bridge. The .enable hook is responsible for setting the PHY's pixel clock rate via clk_set_rate() and powering on the PHY via phy_power_on(). The PHY can only generate the discrete set of pixel clocks described by its pre-PLL table, so .mode_valid rejects any mode clk_round_rate() cannot satisfy. Without it such a mode would be advertised to userspace and the modeset would appear to succeed while the display stayed blank. .enable returns early when the rate is unsupported or the PHY fails to power on, so track whether the pixel clock was actually enabled and let .disable tear down only what was brought up, otherwise the clock refcount underflows. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/Kconfig | 11 ++ drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/jh7110-inno-hdmi.c | 224 ++++++++++++++++++++++++++= ++++ 3 files changed, 236 insertions(+) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 4a57d49b4c6d3ab4b965228835b372d191647197..75b1cf6727d5a32310dcf9fe573= 4d95e14eea8fe 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -359,6 +359,17 @@ config DRM_SOLOMON_SSD2825 Say M here if you want to support this hardware as a module. The module will be named "ssd2825". =20 +config DRM_STARFIVE_JH7110_INNO_HDMI + tristate "Starfive JH7110 Innosilicon HDMI bridge" + depends on OF + depends on ARCH_STARFIVE || COMPILE_TEST + select DRM_INNO_HDMI + help + Enable support for the StarFive JH7110 specific implementation + of the Innosilicon HDMI controller. + This driver acts as a glue layer between the JH7110 HDMI subsystem + parent driver and the generic Innosilicon HDMI bridge driver. + config DRM_THINE_THC63LVD1024 tristate "Thine THC63LVD1024 LVDS decoder bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 15cc821d85b7ea6f3cdc313f3e521b028de567d7..5d843f4ad7ed50b28cb75286c5e= 22789d91a0836 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) +=3D sil-sii8620.o obj-$(CONFIG_DRM_SII902X) +=3D sii902x.o obj-$(CONFIG_DRM_SII9234) +=3D sii9234.o obj-$(CONFIG_DRM_SIMPLE_BRIDGE) +=3D simple-bridge.o +obj-$(CONFIG_DRM_STARFIVE_JH7110_INNO_HDMI) +=3D jh7110-inno-hdmi.o obj-$(CONFIG_DRM_SOLOMON_SSD2825) +=3D ssd2825.o obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) +=3D th1520-dw-hdmi.o obj-$(CONFIG_DRM_THINE_THC63LVD1024) +=3D thc63lvd1024.o diff --git a/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c b/drivers/gpu/drm/br= idge/jh7110-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..be865aa39e33f70614fa7cb58a6= 83b9fcf051599 --- /dev/null +++ b/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) StarFive Technology Co., Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * HDMI controller (bridge) driver for the StarFive JH7110 HDMI subsystem. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +enum stf_hdmi_ctrl_clocks { CLK_SYS =3D 0, CLK_M, CLK_B, CLK_PCLK, CLK_CTR= L_NUM }; + +struct stf_inno_hdmi_controller { + struct device *dev; + struct clk_bulk_data clks[CLK_CTRL_NUM]; + struct reset_control *tx_rst; + struct phy *phy; + bool enabled; +}; + +static enum drm_mode_status +inno_hdmi_starfive_mode_valid(struct device *dev, + const struct drm_display_mode *mode) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + unsigned long pixelclk =3D mode->clock * 1000; + long rounded; + + /* + * The PHY can only generate the discrete set of pixel clocks described + * by its pre-PLL table, and clk_round_rate() fails for anything else. + * Reject those modes here: without this the modeset would appear to + * succeed while the PHY never produces a signal. + */ + rounded =3D clk_round_rate(ctrl->clks[CLK_PCLK].clk, pixelclk); + if (rounded < 0 || rounded !=3D pixelclk) + return MODE_NOCLOCK; + + return MODE_OK; +} + +static void inno_hdmi_starfive_enable(struct device *dev, + struct drm_display_mode *mode) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + int ret; + + /* + * 1. Set the pixel clock rate. This calls the PHY driver's .set_rate op. + */ + ret =3D clk_set_rate(ctrl->clks[CLK_PCLK].clk, mode->clock * 1000); + if (ret) { + dev_err(dev, "Failed to set pclk rate %d: %d\n", + mode->clock * 1000, ret); + return; + } + + /* + * 2. Enable the pixel clock. This calls the PHY driver's .prepare op. + */ + ret =3D clk_prepare_enable(ctrl->clks[CLK_PCLK].clk); + if (ret) { + dev_err(dev, "Failed to enable pclk: %d\n", ret); + return; + } + + /* + * 3. Power on the PHY. This calls the PHY driver's .power_on op, + * which configures the Post-PLL and analog blocks. + */ + ret =3D phy_power_on(ctrl->phy); + if (ret) { + dev_err(dev, "Failed to power on PHY: %d\n", ret); + clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk); + return; + } + + ctrl->enabled =3D true; +} + +static void inno_hdmi_starfive_disable(struct device *dev) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + + /* + * .enable bails out early if the pixel clock rate is unsupported or + * the PHY fails to power on, leaving pclk and the PHY untouched. + * Only tear down what was actually brought up, otherwise the clock + * refcount underflows. + */ + if (!ctrl->enabled) + return; + + phy_power_off(ctrl->phy); + clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk); + ctrl->enabled =3D false; +} + +static int starfive_inno_hdmi_controller_probe(struct platform_device *pde= v) +{ + struct device *dev =3D &pdev->dev; + struct device *parent =3D dev->parent; + struct stf_inno_hdmi_controller *ctrl; + const struct inno_hdmi_plat_data *plat_data; + struct regmap *regmap; + struct inno_hdmi *inno; + int ret; + + ctrl =3D devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->dev =3D dev; + platform_set_drvdata(pdev, ctrl); + + /* Get the shared regmap from the parent */ + regmap =3D dev_get_regmap(parent, NULL); + if (!regmap) { + dev_err(dev, "Failed to get parent regmap\n"); + return -ENODEV; + } + + ctrl->phy =3D devm_phy_get(dev, "hdmi-phy"); + if (IS_ERR(ctrl->phy)) + return dev_err_probe(dev, PTR_ERR(ctrl->phy), "Failed to get PHY\n"); + + ctrl->tx_rst =3D devm_reset_control_get_exclusive(dev, "hdmi_tx"); + if (IS_ERR(ctrl->tx_rst)) + return dev_err_probe(dev, PTR_ERR(ctrl->tx_rst), "failed to get tx reset= \n"); + + /* Populate the clock names this controller *consumes* */ + ctrl->clks[CLK_SYS].id =3D "sys"; + ctrl->clks[CLK_M].id =3D "mclk"; + ctrl->clks[CLK_B].id =3D "bclk"; + ctrl->clks[CLK_PCLK].id =3D "pclk"; /* Pixel clock *from* PHY */ + + ret =3D devm_clk_bulk_get(dev, CLK_CTRL_NUM, ctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Unable to get controller clocks\n"); + + /* pclk is enabled on demand during modeset */ + ret =3D clk_bulk_prepare_enable(CLK_CTRL_NUM - 1, ctrl->clks); + if (ret) + return ret; + + ret =3D reset_control_deassert(ctrl->tx_rst); + if (ret) { + clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks); + return ret; + } + + plat_data =3D of_device_get_match_data(dev); + + /* Hand off to the generic library to create the bridge. */ + inno =3D inno_hdmi_probe(pdev, plat_data); + if (IS_ERR(inno)) { + reset_control_assert(ctrl->tx_rst); + clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks); + return PTR_ERR(inno); + } + + return 0; +} + +static void starfive_inno_hdmi_controller_remove(struct platform_device *p= dev) +{ + struct stf_inno_hdmi_controller *ctrl =3D platform_get_drvdata(pdev); + + reset_control_assert(ctrl->tx_rst); + clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks); +} + +/* + * This table is now only used for the generic .mode_valid check. + * The real validation happens in the PHY driver's .round_rate. + */ +static struct inno_hdmi_phy_config stf_hdmi_phy_configs[] =3D { + { 297000000, 0x00, 0x00 }, + { ~0UL, 0x00, 0x00 }, /* Sentinel */ +}; + +static const struct inno_hdmi_plat_ops stf_inno_hdmi_plat_ops =3D { + .enable =3D inno_hdmi_starfive_enable, + .disable =3D inno_hdmi_starfive_disable, + .mode_valid =3D inno_hdmi_starfive_mode_valid, +}; + +static const struct inno_hdmi_plat_data stf_inno_hdmi_plat_data =3D { + .ops =3D &stf_inno_hdmi_plat_ops, + .phy_configs =3D stf_hdmi_phy_configs, + .default_phy_config =3D &stf_hdmi_phy_configs[0], +}; + +static const struct of_device_id starfive_hdmi_controller_dt_ids[] =3D { + { .compatible =3D "starfive,jh7110-inno-hdmi-controller", + .data =3D &stf_inno_hdmi_plat_data }, + {} +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_controller_dt_ids); + +struct platform_driver starfive_inno_hdmi_controller_driver =3D { + .probe =3D starfive_inno_hdmi_controller_probe, + .remove =3D starfive_inno_hdmi_controller_remove, + .driver =3D { + .name =3D "starfive-inno-hdmi-controller", + .of_match_table =3D starfive_hdmi_controller_dt_ids, + }, +}; +module_platform_driver(starfive_inno_hdmi_controller_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive INNO HDMI Controller Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB6E46D54B; Fri, 28 Aug 2026 13:48:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924925; cv=none; b=WZSdZ4tbvVsjtlLT7r+StpGXdW8KUV8BTcGYmSb01v/Zp5SvKpvn9RYAYkWtx+XOjw4A3I+XmdfzT7pFuNS294TWpKJ42crxFtGnACAckyz/Trx/PGRjcoDlha5IHoTmsMrx7koI2s959vzx6c1da3K1XvHos0S7MS2HRSqbyM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924925; c=relaxed/simple; bh=kSyhTKlr46CyUazCxhC4JQnUXR2crmr2/pVYdBbYRmw=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1787924914; bh=izBZNDHydZtZsP3f9EIyugq6OHKRvXuVqz8xHReuyb8=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=JLIHAHbNmKKXs2XXdiYTxPlEvTPB5VDhDPRUWfuv+pW8RUlFlj3pRHG6+FvEANGvn AHPPMrQQUBhU3Ac/8ZPz4h9wLMWdZDvJwZ4IKcnhhzJMfeWbSdWWnqmR1jL+i9hNEQ Lv1ZC5eKHfswZKa1piLv+HRRRmFlSgW/DDUE/M+U= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20260828134833eucas1p2b3a442d07d7d86d0f82379bc4ecbe62a~P-Dx6ZzSF2729427294eucas1p2-; Fri, 28 Aug 2026 13:48:33 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134832eusmtip11c6327673c8c8eaa071d498e05f7e0d7~P-DwU438m2815728157eusmtip1E; Fri, 28 Aug 2026 13:48:32 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:35 +0200 Subject: [PATCH v2 11/15] phy: Add common Innosilicon HDMI PHY helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-11-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134833eucas1p2b3a442d07d7d86d0f82379bc4ecbe62a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134833eucas1p2b3a442d07d7d86d0f82379bc4ecbe62a X-EPHeader: CA X-CMS-RootMailID: 20260828134833eucas1p2b3a442d07d7d86d0f82379bc4ecbe62a References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> The Innosilicon HDMI PHY IP is used by several SoCs. They differ in where the PHY register block sits in the register space and in which pixel clocks they support, but the pre-PLL programming sequence and the layout of its registers are the same. Add a small library holding that shared part: the pre-PLL configuration table format, a lookup, clk_ops determine_rate and recalc_rate helpers, and the pre-PLL register programming. Callers pass a regmap, a register offset for the PHY block, and their own pixel clock table. No driver uses it yet; the users are converted separately. Signed-off-by: Michal Wilczynski --- drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-inno-hdmi.c | 297 ++++++++++++++++++++++++++++++++++= ++++ include/linux/phy/inno-hdmi-phy.h | 85 +++++++++++ 4 files changed, 391 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 19f3b7d12b7d492d16000fa52483dc5002590d7a..0e973b3b02a30704d339db9f15d= 4695bcbec1c75 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -168,6 +168,14 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. =20 +config PHY_INNO_HDMI + tristate + depends on GENERIC_PHY + select REGMAP + help + Common helpers for the Innosilicon HDMI PHY, shared by the SoC + drivers that instantiate it. Selected by those drivers. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/apple/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d7aa516bcc49e7662c9c9db421833fe591dfbc05..e93c473dfc6d837ed6ba540f0b0= 204a0d68d25bf 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_COMMON_PROPS) +=3D phy-common-props.o obj-$(CONFIG_PHY_COMMON_PROPS_TEST) +=3D phy-common-props-test.o obj-$(CONFIG_GENERIC_PHY) +=3D phy-core.o obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) +=3D phy-core-mipi-dphy.o +obj-$(CONFIG_PHY_INNO_HDMI) +=3D phy-inno-hdmi.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_CAN_TRANSCEIVER) +=3D phy-can-transceiver.o obj-$(CONFIG_PHY_ECONET_PCIE) +=3D phy-econet-pcie.o diff --git a/drivers/phy/phy-inno-hdmi.c b/drivers/phy/phy-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..deb2b73a86f5d6be96dedc818c3= 9777904eb37ee --- /dev/null +++ b/drivers/phy/phy-inno-hdmi.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Common helpers for the Innosilicon HDMI PHY. + * + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * + * Author: Zheng Yang + * Author: Michal Wilczynski + * + * Derived from drivers/phy/rockchip/phy-rockchip-inno-hdmi.c. + * + * The same PHY IP is used by several SoCs, which differ in where the PHY + * register block sits and in the pixel clock table they support, but share + * the pre-PLL programming sequence. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define INNO_PRE_PLL_CONTROL 0xa0 +#define INNO_PRE_PLL_POWER_DOWN BIT(0) +#define INNO_PCLK_VCO_DIV_5_MASK BIT(1) +#define INNO_PCLK_VCO_DIV_5(x) FIELD_PREP(BIT(1), x) + +#define INNO_PRE_PLL_DIV_1 0xa1 +#define INNO_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0) +#define INNO_PRE_PLL_PRE_DIV(x) FIELD_PREP(GENMASK(5, 0), x) + +#define INNO_PRE_PLL_DIV_2 0xa2 +#define INNO_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) +#define INNO_PRE_PLL_FRAC_DIV_DISABLE FIELD_PREP(GENMASK(5, 4), 3) +#define INNO_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define INNO_PRE_PLL_FB_DIV_11_8(x) FIELD_PREP(GENMASK(3, 0), (x) >> 8) + +#define INNO_PRE_PLL_DIV_3 0xa3 +#define INNO_PRE_PLL_FB_DIV_7_0(x) FIELD_PREP(GENMASK(7, 0), x) + +#define INNO_PRE_PLL_TMDSCLK_DIV 0xa4 +#define INNO_PRE_PLL_TMDSCLK_DIV_C(x) FIELD_PREP(GENMASK(1, 0), x) +#define INNO_PRE_PLL_TMDSCLK_DIV_B(x) FIELD_PREP(GENMASK(3, 2), x) +#define INNO_PRE_PLL_TMDSCLK_DIV_A(x) FIELD_PREP(GENMASK(5, 4), x) + +#define INNO_PCLK_DIV_AB 0xa5 +#define INNO_PCLK_DIV_B_MASK GENMASK(6, 5) +#define INNO_PCLK_DIV_B(x) FIELD_PREP(GENMASK(6, 5), x) +#define INNO_PCLK_DIV_A_MASK GENMASK(4, 0) +#define INNO_PCLK_DIV_A(x) FIELD_PREP(GENMASK(4, 0), x) + +#define INNO_PCLK_DIV_CD 0xa6 +#define INNO_PCLK_DIV_C(x) FIELD_PREP(GENMASK(6, 5), x) +#define INNO_PCLK_DIV_D_MASK GENMASK(4, 0) +#define INNO_PCLK_DIV_D(x) FIELD_PREP(GENMASK(4, 0), x) + +#define INNO_PRE_PLL_LOCK_STATUS 0xa9 +#define INNO_PRE_PLL_LOCK BIT(0) + +#define INNO_PRE_PLL_FRAC_DIV_23_16 0xd1 +#define INNO_PRE_PLL_FRAC_DIV_15_8 0xd2 +#define INNO_PRE_PLL_FRAC_DIV_7_0 0xd3 +#define INNO_PRE_PLL_FRAC_DIV(x) FIELD_PREP(GENMASK(7, 0), x) + +#define INNO_FRAC_DIV_WIDTH 24 + +static unsigned int inno_reg(const struct inno_hdmi_phy_pre_pll *pll, + unsigned int reg) +{ + return (pll->offset + reg) * 4; +} + +static void inno_write(const struct inno_hdmi_phy_pre_pll *pll, + unsigned int reg, u8 val) +{ + regmap_write(pll->regmap, inno_reg(pll, reg), val); +} + +static u8 inno_read(const struct inno_hdmi_phy_pre_pll *pll, unsigned int = reg) +{ + unsigned int val; + + regmap_read(pll->regmap, inno_reg(pll, reg), &val); + + return val; +} + +static void inno_update_bits(const struct inno_hdmi_phy_pre_pll *pll, + unsigned int reg, u8 mask, u8 val) +{ + regmap_update_bits(pll->regmap, inno_reg(pll, reg), mask, val); +} + +/** + * inno_hdmi_phy_pre_pll_lookup - find the settings for a pixel clock + * @pll: pre-PLL instance + * @pixclock: requested pixel clock, in Hz + * @tmdsclock: requested TMDS clock, in Hz + * + * Return: the matching table entry, or an ERR_PTR if the PHY cannot gener= ate + * the requested combination. + */ +const struct inno_hdmi_phy_pre_pll_config * +inno_hdmi_phy_pre_pll_lookup(const struct inno_hdmi_phy_pre_pll *pll, + unsigned long pixclock, unsigned long tmdsclock) +{ + const struct inno_hdmi_phy_pre_pll_config *cfg; + + for (cfg =3D pll->table; cfg->pixclock !=3D 0; cfg++) + if (cfg->pixclock =3D=3D pixclock && cfg->tmdsclock =3D=3D tmdsclock) + return cfg; + + return ERR_PTR(-EINVAL); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_lookup); + +/** + * inno_hdmi_phy_pre_pll_determine_rate - clk_ops.determine_rate helper + * @pll: pre-PLL instance + * @req: rate request, updated with the rate the PHY would produce + * + * The PHY can only generate the pixel clocks described by its table, so a + * request that does not appear there is rejected rather than rounded. + * + * Return: 0 on success, -EINVAL if the rate is not supported. + */ +int inno_hdmi_phy_pre_pll_determine_rate(const struct inno_hdmi_phy_pre_pl= l *pll, + struct clk_rate_request *req) +{ + const struct inno_hdmi_phy_pre_pll_config *cfg; + unsigned long rate =3D rounddown(req->rate, 1000); + + for (cfg =3D pll->table; cfg->pixclock !=3D 0; cfg++) { + if (cfg->pixclock =3D=3D rate) { + req->rate =3D cfg->pixclock; + return 0; + } + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_determine_rate); + +/** + * inno_hdmi_phy_pre_pll_recalc_rate - clk_ops.recalc_rate helper + * @pll: pre-PLL instance + * @parent_rate: rate of the reference clock, in Hz + * + * Return: the pixel clock the pre-PLL is currently programmed for, in Hz. + */ +unsigned long +inno_hdmi_phy_pre_pll_recalc_rate(const struct inno_hdmi_phy_pre_pll *pll, + unsigned long parent_rate) +{ + u8 nd, no_a, no_b, no_d; + unsigned long frac; + u64 vco; + u16 nf; + + nd =3D inno_read(pll, INNO_PRE_PLL_DIV_1) & INNO_PRE_PLL_PRE_DIV_MASK; + nf =3D (inno_read(pll, INNO_PRE_PLL_DIV_2) & + INNO_PRE_PLL_FB_DIV_11_8_MASK) << 8; + nf |=3D inno_read(pll, INNO_PRE_PLL_DIV_3); + vco =3D parent_rate * nf; + + if (!(inno_read(pll, INNO_PRE_PLL_DIV_2) & + INNO_PRE_PLL_FRAC_DIV_DISABLE)) { + frac =3D inno_read(pll, INNO_PRE_PLL_FRAC_DIV_7_0) | + (inno_read(pll, INNO_PRE_PLL_FRAC_DIV_15_8) << 8) | + (inno_read(pll, INNO_PRE_PLL_FRAC_DIV_23_16) << 16); + vco +=3D DIV_ROUND_CLOSEST(parent_rate * frac, + BIT(INNO_FRAC_DIV_WIDTH)); + } + + if (inno_read(pll, INNO_PRE_PLL_CONTROL) & INNO_PCLK_VCO_DIV_5_MASK) { + do_div(vco, nd * 5); + } else { + no_a =3D inno_read(pll, INNO_PCLK_DIV_AB) & INNO_PCLK_DIV_A_MASK; + no_b =3D FIELD_GET(INNO_PCLK_DIV_B_MASK, + inno_read(pll, INNO_PCLK_DIV_AB)) + 2; + no_d =3D inno_read(pll, INNO_PCLK_DIV_CD) & INNO_PCLK_DIV_D_MASK; + + do_div(vco, nd * (no_a =3D=3D 1 ? no_b : no_a) * no_d * 2); + } + + return DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_recalc_rate); + +/** + * inno_hdmi_phy_pre_pll_configure - program the pre-PLL dividers + * @pll: pre-PLL instance + * @cfg: settings to program + * + * The caller is responsible for powering the pre-PLL down beforehand and = back + * up afterwards, and for waiting for it to lock. + */ +void inno_hdmi_phy_pre_pll_configure(const struct inno_hdmi_phy_pre_pll *p= ll, + const struct inno_hdmi_phy_pre_pll_config *cfg) +{ + u8 val; + + inno_update_bits(pll, INNO_PRE_PLL_CONTROL, INNO_PCLK_VCO_DIV_5_MASK, + INNO_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); + inno_write(pll, INNO_PRE_PLL_DIV_1, INNO_PRE_PLL_PRE_DIV(cfg->prediv)); + + val =3D INNO_SPREAD_SPECTRUM_MOD_DISABLE; + if (!cfg->fracdiv) + val |=3D INNO_PRE_PLL_FRAC_DIV_DISABLE; + + inno_write(pll, INNO_PRE_PLL_DIV_2, + INNO_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); + inno_write(pll, INNO_PRE_PLL_DIV_3, + INNO_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); + + inno_write(pll, INNO_PCLK_DIV_AB, + INNO_PCLK_DIV_A(cfg->pclk_div_a) | + INNO_PCLK_DIV_B(cfg->pclk_div_b)); + inno_write(pll, INNO_PCLK_DIV_CD, + INNO_PCLK_DIV_C(cfg->pclk_div_c) | + INNO_PCLK_DIV_D(cfg->pclk_div_d)); + + inno_write(pll, INNO_PRE_PLL_TMDSCLK_DIV, + INNO_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | + INNO_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b) | + INNO_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c)); + + inno_write(pll, INNO_PRE_PLL_FRAC_DIV_7_0, + INNO_PRE_PLL_FRAC_DIV(cfg->fracdiv)); + inno_write(pll, INNO_PRE_PLL_FRAC_DIV_15_8, + INNO_PRE_PLL_FRAC_DIV(cfg->fracdiv >> 8)); + inno_write(pll, INNO_PRE_PLL_FRAC_DIV_23_16, + INNO_PRE_PLL_FRAC_DIV(cfg->fracdiv >> 16)); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_configure); + +/** + * inno_hdmi_phy_pre_pll_power_down - power the pre-PLL down or up + * @pll: pre-PLL instance + * @power_down: true to power down, false to power up + */ +void inno_hdmi_phy_pre_pll_power_down(const struct inno_hdmi_phy_pre_pll *= pll, + bool power_down) +{ + inno_update_bits(pll, INNO_PRE_PLL_CONTROL, INNO_PRE_PLL_POWER_DOWN, + power_down ? INNO_PRE_PLL_POWER_DOWN : 0); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_power_down); + +/** + * inno_hdmi_phy_pre_pll_is_powered - report whether the pre-PLL is powere= d up + * @pll: pre-PLL instance + */ +bool inno_hdmi_phy_pre_pll_is_powered(const struct inno_hdmi_phy_pre_pll *= pll) +{ + return !(inno_read(pll, INNO_PRE_PLL_CONTROL) & INNO_PRE_PLL_POWER_DOWN); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_is_powered); + +/** + * inno_hdmi_phy_pre_pll_is_locked - report whether the pre-PLL has locked + * @pll: pre-PLL instance + */ +bool inno_hdmi_phy_pre_pll_is_locked(const struct inno_hdmi_phy_pre_pll *p= ll) +{ + return inno_read(pll, INNO_PRE_PLL_LOCK_STATUS) & INNO_PRE_PLL_LOCK; +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_is_locked); + +/** + * inno_hdmi_phy_pre_pll_wait_locked - wait for the pre-PLL to lock + * @pll: pre-PLL instance + * @timeout_us: how long to wait, in microseconds + * + * Return: 0 once locked, -ETIMEDOUT otherwise. + */ +int inno_hdmi_phy_pre_pll_wait_locked(const struct inno_hdmi_phy_pre_pll *= pll, + unsigned int timeout_us) +{ + unsigned int val; + + return regmap_read_poll_timeout(pll->regmap, + inno_reg(pll, INNO_PRE_PLL_LOCK_STATUS), + val, val & INNO_PRE_PLL_LOCK, + 1000, timeout_us); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_wait_locked); + +MODULE_DESCRIPTION("Innosilicon HDMI PHY common helpers"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/phy/inno-hdmi-phy.h b/include/linux/phy/inno-hdm= i-phy.h new file mode 100644 index 0000000000000000000000000000000000000000..e13911e1a18437cf9cefa43dac4= 94caeb2935782 --- /dev/null +++ b/include/linux/phy/inno-hdmi-phy.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Common helpers for the Innosilicon HDMI PHY. + * + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * + * Author: Zheng Yang + * Author: Michal Wilczynski + * + * Derived from drivers/phy/rockchip/phy-rockchip-inno-hdmi.c. + */ + +#ifndef __PHY_INNO_HDMI_H__ +#define __PHY_INNO_HDMI_H__ + +#include + +struct clk_rate_request; +struct regmap; + +/** + * struct inno_hdmi_phy_pre_pll_config - pre-PLL settings for one pixel cl= ock + * @pixclock: pixel clock this entry describes, in Hz + * @tmdsclock: TMDS clock this entry describes, in Hz + * @prediv: pre-PLL reference divider + * @fbdiv: pre-PLL feedback divider + * @tmds_div_a: TMDS clock divider A + * @tmds_div_b: TMDS clock divider B + * @tmds_div_c: TMDS clock divider C + * @pclk_div_a: pixel clock divider A + * @pclk_div_b: pixel clock divider B + * @pclk_div_c: pixel clock divider C + * @pclk_div_d: pixel clock divider D + * @vco_div_5_en: divide the VCO output by five + * @fracdiv: pre-PLL fractional divider, zero to use integer mode + */ +struct inno_hdmi_phy_pre_pll_config { + unsigned long pixclock; + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 tmds_div_a; + u8 tmds_div_b; + u8 tmds_div_c; + u8 pclk_div_a; + u8 pclk_div_b; + u8 pclk_div_c; + u8 pclk_div_d; + u8 vco_div_5_en; + u32 fracdiv; +}; + +/** + * struct inno_hdmi_phy_pre_pll - a pre-PLL instance + * @regmap: register map covering the PHY registers + * @offset: offset of the PHY register block, in units of the register ind= ex. + * Zero where the PHY block starts the register space, 0x100 on the + * StarFive JH7110 where it is preceded by the HDMI controller. + * @table: pixel clock table, terminated by an entry with a zero pixclock + */ +struct inno_hdmi_phy_pre_pll { + struct regmap *regmap; + unsigned int offset; + const struct inno_hdmi_phy_pre_pll_config *table; +}; + +const struct inno_hdmi_phy_pre_pll_config * +inno_hdmi_phy_pre_pll_lookup(const struct inno_hdmi_phy_pre_pll *pll, + unsigned long pixclock, unsigned long tmdsclock); +int inno_hdmi_phy_pre_pll_determine_rate(const struct inno_hdmi_phy_pre_pl= l *pll, + struct clk_rate_request *req); +unsigned long +inno_hdmi_phy_pre_pll_recalc_rate(const struct inno_hdmi_phy_pre_pll *pll, + unsigned long parent_rate); +void inno_hdmi_phy_pre_pll_configure(const struct inno_hdmi_phy_pre_pll *p= ll, + const struct inno_hdmi_phy_pre_pll_config *cfg); +void inno_hdmi_phy_pre_pll_power_down(const struct inno_hdmi_phy_pre_pll *= pll, + bool power_down); +bool inno_hdmi_phy_pre_pll_is_powered(const struct inno_hdmi_phy_pre_pll *= pll); +bool inno_hdmi_phy_pre_pll_is_locked(const struct inno_hdmi_phy_pre_pll *p= ll); +int inno_hdmi_phy_pre_pll_wait_locked(const struct inno_hdmi_phy_pre_pll *= pll, + unsigned int timeout_us); + +#endif /* __PHY_INNO_HDMI_H__ */ --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C63346C855; Fri, 28 Aug 2026 13:48:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 28 Aug 2026 13:48:35 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134833eusmtip1f4405999af46ddd52eeb3669d28a403a~P-Dx_bdLE2832328323eusmtip1P; Fri, 28 Aug 2026 13:48:33 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:36 +0200 Subject: [PATCH v2 12/15] phy: rockchip: inno-hdmi: Use the common Innosilicon PHY helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-12-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134835eucas1p27736632121c17e11f554e295994a7d8d X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134835eucas1p27736632121c17e11f554e295994a7d8d X-EPHeader: CA X-CMS-RootMailID: 20260828134835eucas1p27736632121c17e11f554e295994a7d8d References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> The RK3328 pre-PLL programming, its table lookup and its recalc_rate and determine_rate implementations are the generic Innosilicon ones, so drop the local copies and use the shared helpers instead. The RK3228 pre-PLL sits at different register addresses, so it keeps its own register level code and only shares the table lookup. The register writes, their order and the values written are unchanged. No functional change intended. Signed-off-by: Michal Wilczynski --- drivers/phy/rockchip/Kconfig | 1 + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 127 +++++-----------------= ---- 2 files changed, 25 insertions(+), 103 deletions(-) diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 14698571b607590dc0e7a29f3b39eb9a5d4e3d25..9732c5be87717dc3ddbea1c6008= 0952336a07af9 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -34,6 +34,7 @@ config PHY_ROCKCHIP_INNO_HDMI depends on COMMON_CLK depends on HAS_IOMEM select GENERIC_PHY + select PHY_INNO_HDMI help Enable this to support the Rockchip Innosilicon HDMI PHY. =20 diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-hdmi.c index 1483907413faa5ce1dc8614db05e6e929410404d..fae766607b0ea120b3adb360013= 87062f39a5c00 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include =20 @@ -240,6 +241,8 @@ struct inno_hdmi_phy { const struct inno_hdmi_phy_drv_data *plat_data; int chip_version; =20 + struct inno_hdmi_phy_pre_pll pre_pll; + /* clk provider */ struct clk_hw hw; struct clk *phyclk; @@ -247,21 +250,6 @@ struct inno_hdmi_phy { unsigned long tmdsclock; }; =20 -struct pre_pll_config { - unsigned long pixclock; - unsigned long tmdsclock; - u8 prediv; - u16 fbdiv; - u8 tmds_div_a; - u8 tmds_div_b; - u8 tmds_div_c; - u8 pclk_div_a; - u8 pclk_div_b; - u8 pclk_div_c; - u8 pclk_div_d; - u8 vco_div_5_en; - u32 fracdiv; -}; =20 struct post_pll_config { unsigned long tmdsclock; @@ -290,7 +278,7 @@ struct inno_hdmi_phy_drv_data { const struct phy_config *phy_cfg_table; }; =20 -static const struct pre_pll_config pre_pll_cfg_table[] =3D { +static const struct inno_hdmi_phy_pre_pll_config pre_pll_cfg_table[] =3D { { 25175000, 25175000, 3, 125, 3, 1, 1, 1, 3, 3, 4, 0, 0xe00000}, { 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f}, { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, @@ -673,20 +661,12 @@ static const struct phy_ops inno_hdmi_phy_ops =3D { }; =20 static const -struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy = *inno, - unsigned long rate) +struct inno_hdmi_phy_pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct = inno_hdmi_phy *inno, + unsigned long rate) { - const struct pre_pll_config *cfg =3D pre_pll_cfg_table; unsigned long tmdsclock =3D inno_hdmi_phy_get_tmdsclk(inno, rate); =20 - for (; cfg->pixclock !=3D 0; cfg++) - if (cfg->pixclock =3D=3D rate && cfg->tmdsclock =3D=3D tmdsclock) - break; - - if (cfg->pixclock =3D=3D 0) - return ERR_PTR(-EINVAL); - - return cfg; + return inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, rate, tmdsclock); } =20 static int inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw *hw) @@ -752,7 +732,7 @@ unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(stru= ct clk_hw *hw, static int inno_hdmi_phy_rk3228_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - const struct pre_pll_config *cfg =3D pre_pll_cfg_table; + const struct inno_hdmi_phy_pre_pll_config *cfg =3D pre_pll_cfg_table; =20 req->rate =3D (req->rate / 1000) * 1000; =20 @@ -773,7 +753,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk= _hw *hw, unsigned long parent_rate) { struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); - const struct pre_pll_config *cfg; + const struct inno_hdmi_phy_pre_pll_config *cfg; unsigned long tmdsclock =3D inno_hdmi_phy_get_tmdsclk(inno, rate); u32 v; int ret; @@ -870,39 +850,11 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(st= ruct clk_hw *hw, unsigned long parent_rate) { struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); - unsigned long frac; - u8 nd, no_a, no_b, no_d; - u64 vco; - u16 nf; - - nd =3D inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK; - nf =3D ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8); - nf |=3D inno_read(inno, 0xa3); - vco =3D parent_rate * nf; - - if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) { - frac =3D inno_read(inno, 0xd3) | - (inno_read(inno, 0xd2) << 8) | - (inno_read(inno, 0xd1) << 16); - vco +=3D DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); - } =20 - if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) { - do_div(vco, nd * 5); - } else { - no_a =3D inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK; - no_b =3D inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; - no_b >>=3D RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; - no_b +=3D 2; - no_d =3D inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; - - do_div(vco, (nd * (no_a =3D=3D 1 ? no_b : no_a) * no_d * 2)); - } + inno->pixclock =3D inno_hdmi_phy_pre_pll_recalc_rate(&inno->pre_pll, + parent_rate); =20 - inno->pixclock =3D DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; - - dev_dbg(inno->dev, "%s rate %lu vco %llu\n", - __func__, inno->pixclock, vco); + dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); =20 return inno->pixclock; } @@ -910,20 +862,9 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(str= uct clk_hw *hw, static int inno_hdmi_phy_rk3328_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - const struct pre_pll_config *cfg =3D pre_pll_cfg_table; - - req->rate =3D (req->rate / 1000) * 1000; - - for (; cfg->pixclock !=3D 0; cfg++) - if (cfg->pixclock =3D=3D req->rate) - break; - - if (cfg->pixclock =3D=3D 0) - return -EINVAL; - - req->rate =3D cfg->pixclock; + struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); =20 - return 0; + return inno_hdmi_phy_pre_pll_determine_rate(&inno->pre_pll, req); } =20 static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, @@ -931,9 +872,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk= _hw *hw, unsigned long parent_rate) { struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); - const struct pre_pll_config *cfg; + const struct inno_hdmi_phy_pre_pll_config *cfg; unsigned long tmdsclock =3D inno_hdmi_phy_get_tmdsclk(inno, rate); - u32 val; int ret; =20 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", @@ -946,35 +886,11 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct c= lk_hw *hw, if (IS_ERR(cfg)) return PTR_ERR(cfg); =20 - inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, - RK3328_PRE_PLL_POWER_DOWN); - - /* Configure pre-pll */ - inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK, - RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); - inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); - - val =3D RK3328_SPREAD_SPECTRUM_MOD_DISABLE; - if (!cfg->fracdiv) - val |=3D RK3328_PRE_PLL_FRAC_DIV_DISABLE; - inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); - inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); - inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) | - RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b)); - inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | - RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); - inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | - RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | - RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); - inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv)); - inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv)); - inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv)); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + inno_hdmi_phy_pre_pll_configure(&inno->pre_pll, cfg); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); =20 - inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); - - /* Wait for Pre-PLL lock */ - ret =3D inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, - 1000, 10000); + ret =3D inno_hdmi_phy_pre_pll_wait_locked(&inno->pre_pll, 10000); if (ret) { dev_err(inno->dev, "Pre-PLL locking failed\n"); return ret; @@ -1373,6 +1289,11 @@ static int inno_hdmi_phy_probe(struct platform_devic= e *pdev) if (IS_ERR(inno->regmap)) return PTR_ERR(inno->regmap); =20 + /* The PHY block starts the register space on these SoCs. */ + inno->pre_pll.regmap =3D inno->regmap; + inno->pre_pll.offset =3D 0; + inno->pre_pll.table =3D pre_pll_cfg_table; + /* only the newer rk3328 hdmiphy has an interrupt */ inno->irq =3D platform_get_irq(pdev, 0); if (inno->irq > 0) { --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A312B46DFE4; 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Fri, 28 Aug 2026 13:48:37 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134835eusmtip154a3678560df343ccb353d15f50ac603~P-DzrL3Ud2815728157eusmtip1G; Fri, 28 Aug 2026 13:48:35 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:37 +0200 Subject: [PATCH v2 13/15] phy: starfive: Add jh7110-inno-hdmi-phy driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-13-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134837eucas1p18f352f4ffb04ca5e55386ed3423f5d1a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134837eucas1p18f352f4ffb04ca5e55386ed3423f5d1a X-EPHeader: CA X-CMS-RootMailID: 20260828134837eucas1p18f352f4ffb04ca5e55386ed3423f5d1a References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> Add the HDMI PHY driver for the StarFive JH7110. This driver binds to the starfive,jh7110-inno-hdmi-phy node and gets its regmap from the parent. It has no dependencies on voutcrg, only on its refoclk (xin24m), which breaks the probe-time circular dependency. This driver provides two main functions: - Clock Provider: It registers clk_ops to provide the variable pixel clock (hdmi_pclk). The .set_rate operation configures the Pre-PLL registers (0x1a0+) based on the requested rate. - PHY Provider: It registers phy_ops for the controller. The .power_on op configures and enables the Post-PLL and other analog blocks (BIAS, LDO, Serializer, etc.). The JH7110 instantiates the same Innosilicon IP as the Rockchip RK3328, with the PHY register block shifted by 0x100 because it sits behind the HDMI controller in the shared register space. The pre-PLL programming therefore comes from the common Innosilicon helpers; this driver adds the JH7110 pixel clock table, the post-PLL and the analog configuration. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Signed-off-by: Michal Wilczynski --- drivers/phy/starfive/Kconfig | 20 + drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-inno-hdmi.c | 567 ++++++++++++++++++++++++= ++++ 3 files changed, 588 insertions(+) diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index d0cdd7cb4a13de22ff643c89a79d99cce57284d7..1da417ffbf224c13224e42a3ce3= 22e3d0c272824 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -25,6 +25,26 @@ config PHY_STARFIVE_JH7110_DPHY_TX system. If M is selected, the module will be called phy-jh7110-dphy-tx.ko. =20 +config PHY_STARFIVE_JH7110_INNO_HDMI + tristate "Starfive JH7110 INNO HDMI PHY" + select PHY_INNO_HDMI + depends on COMMON_CLK + select GENERIC_PHY + help + This option enables the driver for the analog HDMI PHY (Physical + Layer) on the StarFive JH7110 SoC. + + This driver binds to a child node of the 'starfive,jh7110-hdmi-subsyste= m' + parent driver and gets its register map from that parent. + + It is responsible for two main functions: + 1. PHY Provider: It provides standard PHY operations (.power_on, + .power_off) for the HDMI controller (bridge) driver. This + involves configuring the Post-PLL and analog TMDS blocks. + 2. Clock Provider: It registers as a clock provider to supply the + variable pixel clock (hdmi_pclk) to the HDMI controller and + the VOUT subsystem, which it generates using the Pre-PLL. + config PHY_STARFIVE_JH7110_PCIE tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support" depends on HAS_IOMEM diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index eedc4a6fec156320c99ac0a0da609083b6a6a695..e7b13f00880b500f933f21b6037= 384d5c6884e3e 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) +=3D phy-jh7110-dphy-rx.o obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX) +=3D phy-jh7110-dphy-tx.o +obj-$(CONFIG_PHY_STARFIVE_JH7110_INNO_HDMI) +=3D phy-jh7110-inno-hdmi.o obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) +=3D phy-jh7110-pcie.o obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) +=3D phy-jh7110-usb.o diff --git a/drivers/phy/starfive/phy-jh7110-inno-hdmi.c b/drivers/phy/star= five/phy-jh7110-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..f4c4d76a38754d5edd4d8089548= 1560c9650f3e7 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-inno-hdmi.c @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * + * Author: Zheng Yang + * Author: Michal Wilczynski + * + * The register layout and programming sequence derive from + * drivers/phy/rockchip/phy-rockchip-inno-hdmi.c; the JH7110 places the + * same Innosilicon PHY block at a 0x100 register offset. + * + * This driver handles the PHY portion of the StarFive Innosilicon HDMI IP, + * which is part of a monolithic HDMI block. It provides the variable pixel + * clock (from the Pre-PLL) and the PHY operations (for the Post-PLL/analo= g). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * StarFive (JH7110) Innosilicon HDMI PHY Register Definitions + */ + +/* REG: 0x1aa */ +#define STF_INNO_POST_PLL_DIV_1 0x1aa +#define STF_INNO_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2) +#define STF_INNO_POST_PLL_REFCLK_SEL_TMDS BIT(1) +#define STF_INNO_POST_PLL_POWER_DOWN BIT(0) + +/* REG: 0x1ab */ +#define STF_INNO_POST_PLL_DIV_2 0x1ab +#define STF_INNO_POST_PLL_PRE_DIV(x) FIELD_PREP(GENMASK(5, 0), x) +#define STF_INNO_POST_PLL_FB_DIV_8(x) FIELD_PREP(BIT(7), (x) >> 8) + +/* REG: 0x1ac */ +#define STF_INNO_POST_PLL_DIV_3 0x1ac +#define STF_INNO_POST_PLL_FB_DIV_7_0(x) FIELD_PREP(GENMASK(7, 0), x) + +/* REG: 0x1ad */ +#define STF_INNO_POST_PLL_DIV_4 0x1ad +#define STF_INNO_POST_PLL_POST_DIV_MASK GENMASK(1, 0) + +/* REG: 0x1af */ +#define STF_INNO_POST_PLL_LOCK_STATUS 0x1af +#define STF_INNO_POST_PLL_LOCK BIT(0) + +/* REG: 0x1b0 */ +#define STF_INNO_BIAS_CONTROL 0x1b0 +#define STF_INNO_BIAS_ENABLE BIT(2) + +/* REG: 0x1b2 */ +#define STF_INNO_TMDS_CONTROL 0x1b2 +#define STF_INNO_TMDS_CLK_DRIVER_EN BIT(3) +#define STF_INNO_TMDS_D2_DRIVER_EN BIT(2) +#define STF_INNO_TMDS_D1_DRIVER_EN BIT(1) +#define STF_INNO_TMDS_D0_DRIVER_EN BIT(0) +#define STF_INNO_TMDS_DRIVER_ENABLE (STF_INNO_TMDS_CLK_DRIVER_EN | \ + STF_INNO_TMDS_D2_DRIVER_EN | \ + STF_INNO_TMDS_D1_DRIVER_EN | \ + STF_INNO_TMDS_D0_DRIVER_EN) + +/* REG: 0x1b4 */ +#define STF_INNO_LDO_CONTROL 0x1b4 +#define STF_INNO_LDO_ENABLE (BIT(2) | BIT(1) | BIT(0)) + +/* REG: 0x1be */ +#define STF_INNO_SERIALIER_CONTROL 0x1be +#define STF_INNO_SERIALIER_ENABLE (BIT(6) | BIT(5) | BIT(4) | BIT(0)) + +/* REG: 0x1cc */ +#define STF_INNO_RX_CONTROL 0x1cc +#define STF_INNO_RX_ENABLE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +/* + * These tables are copied from the monolithic driver. + * They match the Rockchip PHY driver tables. + */ + +struct post_pll_config { + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 postdiv; + u8 post_div_en; +}; + +static const struct inno_hdmi_phy_pre_pll_config pre_pll_cfg_table[] =3D { + { 25175000, 25175000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0xF55555 }, + { 25200000, 25200000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0 }, + { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0 }, + { 27027000, 27027000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0x170A3D }, + { 28320000, 28320000, 1, 28, 2, 1, 1, 3, 0, 3, 4, 0, 0x51EB85 }, + { 30240000, 30240000, 1, 30, 2, 1, 1, 3, 0, 3, 4, 0, 0x3D70A3 }, + { 31500000, 31500000, 1, 31, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 33750000, 33750000, 1, 33, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 36000000, 36000000, 1, 36, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0 }, + { 46970000, 46970000, 1, 46, 2, 1, 1, 3, 0, 3, 4, 0, 0xF851EB }, + { 49500000, 49500000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 49000000, 49000000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 50000000, 50000000, 1, 50, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 54000000, 54000000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 54054000, 54054000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0x0DD2F1 }, + { 57284000, 57284000, 1, 57, 2, 1, 1, 3, 0, 3, 4, 0, 0x48B439 }, + { 58230000, 58230000, 1, 58, 2, 1, 1, 3, 0, 3, 4, 0, 0x3AE147 }, + { 59341000, 59341000, 1, 59, 2, 1, 1, 3, 0, 3, 4, 0, 0x574BC6 }, + { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0 }, + { 65000000, 65000000, 1, 130, 2, 2, 2, 12, 0, 2, 2, 0, 0 }, + { 68250000, 68250000, 1, 68, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF }, + { 71000000, 71000000, 1, 71, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B }, + { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0 }, + { 75000000, 75000000, 1, 75, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 78750000, 78750000, 1, 78, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 79500000, 79500000, 1, 79, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0 }, + { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000 }, + { 85500000, 85500000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 85750000, 85750000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 85800000, 85800000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCCCCCC }, + { 88750000, 88750000, 1, 88, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 89910000, 89910000, 1, 89, 2, 1, 1, 3, 0, 3, 4, 0, 0xE8F5C1 }, + { 90000000, 90000000, 1, 90, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 101000000, 101000000, 1, 101, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 102250000, 102250000, 1, 102, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF }, + { 106500000, 106500000, 1, 106, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 108000000, 108000000, 1, 90, 3, 0, 0, 5, 0, 2, 2, 0, 0 }, + { 119000000, 119000000, 1, 119, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 131481000, 131481000, 1, 131, 2, 1, 1, 3, 0, 3, 4, 0, 0x7B22D1 }, + { 135000000, 135000000, 1, 135, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 136750000, 136750000, 1, 136, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 147180000, 147180000, 1, 147, 2, 1, 1, 3, 0, 3, 4, 0, 0x2E147A }, + { 148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B }, + { 148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0 }, + { 154000000, 154000000, 1, 154, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 156000000, 156000000, 1, 156, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 157000000, 157000000, 1, 157, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 162000000, 162000000, 1, 162, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 174250000, 174250000, 1, 145, 3, 0, 0, 5, 0, 2, 2, 0, 0x355555 }, + { 174500000, 174500000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 174570000, 174570000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x91EB84 }, + { 175500000, 175500000, 1, 175, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 185590000, 185590000, 1, 185, 2, 1, 1, 3, 0, 3, 4, 0, 0x970A3C }, + { 187000000, 187000000, 1, 187, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 241500000, 241500000, 1, 161, 1, 1, 1, 4, 0, 2, 2, 0, 0 }, + { 241700000, 241700000, 1, 241, 2, 1, 1, 3, 0, 3, 4, 0, 0xB33332 }, + { 262750000, 262750000, 1, 262, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 296500000, 296500000, 1, 296, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B }, + { 297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0 }, + { 594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; + +static const struct post_pll_config post_pll_cfg_table[] =3D { + { 25200000, 1, 80, 13, 3 }, + { 27000000, 1, 40, 11, 3 }, + { 27027000, 1, 40, 11, 3 }, + { 33750000, 1, 40, 11, 3 }, + { 49000000, 1, 20, 1, 3 }, + { 65000000, 1, 20, 1, 3 }, + { 74250000, 1, 20, 1, 3 }, + { 88750000, 1, 20, 1, 3 }, + { 108000000, 1, 20, 1, 3 }, + { 148500000, 1, 20, 1, 3 }, + { 162000000, 1, 20, 1, 3 }, + { 174250000, 1, 20, 1, 3 }, + { 187000000, 1, 20, 1, 3 }, + { 241700000, 1, 20, 1, 3 }, + { 297000000, 4, 20, 0, 0 }, + { 594000000, 4, 20, 0, 0 }, /* postpll_postdiv_en =3D 0 */ + { /* sentinel */ } +}; + +struct starfive_hdmi_phy { + struct device *dev; + struct regmap *regmap; + struct phy *phy; + struct clk *refoclk; + + struct inno_hdmi_phy_pre_pll pre_pll; + + struct clk_hw hw; + struct clk *phyclk; + unsigned long pixclock; + unsigned long tmdsclock; +}; + +static inline void inno_write(struct starfive_hdmi_phy *inno, u32 reg, u8 = val) +{ + regmap_write(inno->regmap, reg * 4, val); +} + +static inline u8 inno_read(struct starfive_hdmi_phy *inno, u32 reg) +{ + u32 val; + + regmap_read(inno->regmap, reg * 4, &val); + return val; +} + +static inline void inno_update_bits(struct starfive_hdmi_phy *inno, u16 re= g, + u8 mask, u8 val) +{ + regmap_update_bits(inno->regmap, reg * 4, mask, val); +} + +#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ + regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \ + sleep_us, timeout_us) + +static inline struct starfive_hdmi_phy *to_starfive_hdmi_phy(struct clk_hw= *hw) +{ + return container_of(hw, struct starfive_hdmi_phy, hw); +} + +static int starfive_hdmi_phy_clk_prepare(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + int ret; + + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); + + if (inno_hdmi_phy_pre_pll_is_locked(&inno->pre_pll)) + return 0; + + ret =3D inno_hdmi_phy_pre_pll_wait_locked(&inno->pre_pll, 100000); + if (ret) { + dev_err(inno->dev, "Timeout waiting for pre-PLL lock\n"); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + return ret; + } + + return 0; +} + +static void starfive_hdmi_phy_clk_unprepare(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + inno->pixclock =3D 0; /* Invalidate cached rate */ +} + +static int starfive_hdmi_phy_clk_is_prepared(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + if (!inno_hdmi_phy_pre_pll_is_powered(&inno->pre_pll)) + return 0; + + return inno_hdmi_phy_pre_pll_is_locked(&inno->pre_pll); +} + +static unsigned long starfive_hdmi_phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + if (!starfive_hdmi_phy_clk_is_prepared(hw)) + return inno->pixclock; + + inno->pixclock =3D inno_hdmi_phy_pre_pll_recalc_rate(&inno->pre_pll, + parent_rate); + + return inno->pixclock; +} + +static int starfive_hdmi_phy_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + return inno_hdmi_phy_pre_pll_determine_rate(&inno->pre_pll, req); +} + +static int starfive_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long= rate, + unsigned long parent_rate) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + const struct inno_hdmi_phy_pre_pll_config *cfg; + + /* + * The JH7110 only drives 8bpc, so the TMDS clock always matches the + * pixel clock. + */ + cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, rate, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); + + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", + __func__, rate, cfg->tmdsclock); + + if (inno->pixclock =3D=3D rate && inno->tmdsclock =3D=3D cfg->tmdsclock) + return 0; + + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE); + inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE); + + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + inno_hdmi_phy_pre_pll_configure(&inno->pre_pll, cfg); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); + + inno->pixclock =3D rate; + inno->tmdsclock =3D cfg->tmdsclock; + + return 0; +} + +static const struct clk_ops starfive_hdmi_phy_clk_ops =3D { + .prepare =3D starfive_hdmi_phy_clk_prepare, + .unprepare =3D starfive_hdmi_phy_clk_unprepare, + .is_prepared =3D starfive_hdmi_phy_clk_is_prepared, + .recalc_rate =3D starfive_hdmi_phy_clk_recalc_rate, + .determine_rate =3D starfive_hdmi_phy_clk_determine_rate, + .set_rate =3D starfive_hdmi_phy_clk_set_rate, +}; + +static int starfive_hdmi_phy_power_on(struct phy *phy) +{ + struct starfive_hdmi_phy *inno =3D phy_get_drvdata(phy); + const struct post_pll_config *cfg =3D post_pll_cfg_table; + const struct inno_hdmi_phy_pre_pll_config *pre_cfg; + unsigned long tmdsclock; + u8 reg_1ad_value; + u8 reg_1aa_value; + + u32 v; + int ret; + + tmdsclock =3D clk_get_rate(inno->phyclk); + pre_cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, tmdsclock, + tmdsclock); + if (IS_ERR(pre_cfg)) { + dev_err(inno->dev, "no pre-PLL config for current pixel clock\n"); + return PTR_ERR(pre_cfg); + } + tmdsclock =3D pre_cfg->tmdsclock; + inno->tmdsclock =3D tmdsclock; + + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE); + inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE); + + /* Find Post-PLL config */ + for (; cfg->tmdsclock !=3D 0; cfg++) + if (tmdsclock <=3D cfg->tmdsclock) + break; + + if (cfg->tmdsclock =3D=3D 0) { + dev_err(inno->dev, "Failed to find Post-PLL config\n"); + return -EINVAL; + } + dev_dbg(inno->dev, "Inno HDMI PHY Power On: pixclk %lu, tmdsclk %lu\n", + inno->pixclock, tmdsclock); + + reg_1ad_value =3D cfg->post_div_en ? cfg->postdiv : 0x00; + reg_1aa_value =3D cfg->post_div_en ? 0x0e : 0x02; + + /* + * Pre-PLL is already prepared and running at inno->pixclock + * via the clk_set_rate and prepare calls from the controller/bridge. + * Now, configure and enable the Post-PLL and TMDS outputs. + */ + + inno_write(inno, STF_INNO_POST_PLL_DIV_2, + STF_INNO_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, STF_INNO_POST_PLL_DIV_3, cfg->fbdiv & 0xff); + inno_write(inno, STF_INNO_POST_PLL_DIV_4, reg_1ad_value); + + /* Power up Post-PLL */ + inno_write(inno, STF_INNO_POST_PLL_DIV_1, reg_1aa_value); + + /* Wait for post PLL lock */ + ret =3D inno_poll(inno, STF_INNO_POST_PLL_LOCK_STATUS, v, + v & STF_INNO_POST_PLL_LOCK, 1000, 100000); + if (ret) { + dev_err(inno->dev, "Post-PLL locking failed\n"); + return ret; + } + + inno_write(inno, STF_INNO_LDO_CONTROL, STF_INNO_LDO_ENABLE); + inno_write(inno, STF_INNO_SERIALIER_CONTROL, + STF_INNO_SERIALIER_ENABLE); + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x8f); + + return 0; +} + +static int starfive_hdmi_phy_power_off(struct phy *phy) +{ + struct starfive_hdmi_phy *inno =3D phy_get_drvdata(phy); + + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); + + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x00); + inno_write(inno, STF_INNO_SERIALIER_CONTROL, 0x00); + inno_write(inno, STF_INNO_LDO_CONTROL, 0x00); + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, 0x00); + inno_write(inno, STF_INNO_RX_CONTROL, 0x00); + + /* Power down Post-PLL */ + inno_update_bits(inno, STF_INNO_POST_PLL_DIV_1, + STF_INNO_POST_PLL_POWER_DOWN, + STF_INNO_POST_PLL_POWER_DOWN); + + inno->tmdsclock =3D 0; + inno->pixclock =3D 0; + + return 0; +} + +static const struct phy_ops starfive_hdmi_phy_ops =3D { + .owner =3D THIS_MODULE, + .power_on =3D starfive_hdmi_phy_power_on, + .power_off =3D starfive_hdmi_phy_power_off, +}; + +static int starfive_hdmi_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device *parent =3D dev->parent; + struct starfive_hdmi_phy *inno; + struct phy_provider *phy_provider; + struct regmap *regmap; + struct clk_init_data init =3D {}; + const char *refoclk_name; + int ret; + + inno =3D devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); + if (!inno) + return -ENOMEM; + + inno->dev =3D dev; + + /* Get the regmap from the parent device */ + regmap =3D dev_get_regmap(parent, NULL); + if (!regmap) { + dev_err(dev, "Failed to get parent regmap\n"); + return -ENODEV; + } + inno->regmap =3D regmap; + + /* + * The PHY block sits behind the HDMI controller in the shared register + * space, so the common pre-PLL helpers need a 0x100 register offset. + */ + inno->pre_pll.regmap =3D regmap; + inno->pre_pll.offset =3D 0x100; + inno->pre_pll.table =3D pre_pll_cfg_table; + + /* Get the input reference clock */ + inno->refoclk =3D devm_clk_get(inno->dev, "refoclk"); + if (IS_ERR(inno->refoclk)) { + ret =3D PTR_ERR(inno->refoclk); + dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n", + ret); + return ret; + } + + /* We must prepare/enable refoclk here so .set_rate/.recalc_rate work */ + ret =3D clk_prepare_enable(inno->refoclk); + if (ret) { + dev_err(dev, "Failed to enable refoclk: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, inno); + + /* Initialize and register the clock provider */ + refoclk_name =3D __clk_get_name(inno->refoclk); + init.parent_names =3D &refoclk_name; + init.num_parents =3D 1; + init.flags =3D 0; + init.name =3D "hdmi_pclk"; + init.ops =3D &starfive_hdmi_phy_clk_ops; + + of_property_read_string(dev->of_node, "clock-output-names", &init.name); + + inno->hw.init =3D &init; + inno->phyclk =3D devm_clk_register(dev, &inno->hw); + if (IS_ERR(inno->phyclk)) { + ret =3D PTR_ERR(inno->phyclk); + dev_err(dev, "Failed to register clock provider: %d\n", ret); + goto err_disable_refoclk; + } + + ret =3D of_clk_add_provider(dev->of_node, of_clk_src_simple_get, inno->ph= yclk); + if (ret) { + dev_err(dev, "Failed to add clock provider: %d\n", ret); + goto err_disable_refoclk; + } + + ret =3D clk_set_rate(inno->phyclk, 297000000); + if (ret) { + dev_err(dev, "Failed to set default rate: %d\n", ret); + goto err_disable_refoclk; + } + + /* Create and register the PHY provider */ + inno->phy =3D devm_phy_create(inno->dev, NULL, &starfive_hdmi_phy_ops); + if (IS_ERR(inno->phy)) { + ret =3D PTR_ERR(inno->phy); + dev_err(inno->dev, "failed to create HDMI PHY: %d\n", ret); + goto err_del_clk_provider; + } + + phy_set_drvdata(inno->phy, inno); + + phy_provider =3D devm_of_phy_provider_register(inno->dev, + of_phy_simple_xlate); + ret =3D PTR_ERR_OR_ZERO(phy_provider); + if (ret) + goto err_del_clk_provider; + + return 0; + +err_del_clk_provider: + of_clk_del_provider(dev->of_node); +err_disable_refoclk: + clk_disable_unprepare(inno->refoclk); + return ret; +} + +static void starfive_hdmi_phy_remove(struct platform_device *pdev) +{ + struct starfive_hdmi_phy *inno =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + clk_disable_unprepare(inno->refoclk); +} + +static const struct of_device_id starfive_hdmi_phy_of_match[] =3D { + { .compatible =3D "starfive,jh7110-inno-hdmi-phy", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_phy_of_match); + +static struct platform_driver starfive_hdmi_phy_driver =3D { + .probe =3D starfive_hdmi_phy_probe, + .remove =3D starfive_hdmi_phy_remove, + .driver =3D { + .name =3D "starfive-inno-hdmi-phy", + .of_match_table =3D starfive_hdmi_phy_of_match, + }, +}; +module_platform_driver(starfive_hdmi_phy_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive JH7110 Innosilicon HDMI PHY Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sat Sep 26 22:58:07 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A31CC46DFE7; Fri, 28 Aug 2026 13:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924924; cv=none; b=pUZLhBN8mpJouGcz/0VkfzeOvX1eJ8F35ygwxSocpLp1x1spDQEiTcG5YKmrYDoeFDmgahF9i5GEOakezeEVuKXpBDEyRIKDUgDbI2IaOy8Eglf2W0w2Kl4WkrnN99yS5pQpUPK4ohJGFLEKFIH9fw5p6rd65HjV01yNBfH2DZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787924924; c=relaxed/simple; bh=7W0xWyhfKVVIoWLKnehFojycB/3vxqvNCvz0CxAplc4=; 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Fri, 28 Aug 2026 13:48:37 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:38 +0200 Subject: [PATCH v2 14/15] riscv: dts: starfive: jh7110: Update DT for display subsystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-14-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134839eucas1p2d19363d17d4dbf5a7ae5228444af16fa X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134839eucas1p2d19363d17d4dbf5a7ae5228444af16fa X-EPHeader: CA X-CMS-RootMailID: 20260828134839eucas1p2d19363d17d4dbf5a7ae5228444af16fa References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> Activate the display subsystem by adding the dc8200, hdmi and voutcrg nodes as direct soc children. Each references the PD_VOUT power domain through power-domains, so genpd powers the domain on demand, and the HDMI-PHY -> voutcrg -> HDMI-controller probe order is resolved by deferred probe. The monolithic hdmi node is modelled as a container with hdmi_phy and hdmi_controller children. This lets the PHY (clock provider, depending only on xin24m) and the controller (clock consumer) probe independently, breaking the circular clock dependency with voutcrg. voutcrg consumes the pixel clock from the &hdmi_phy node instead of the old fixed-clock, and dc8200 gets its pixel clocks from voutcrg's MUXes and is marked dma-noncoherent for framebuffer DMA. The old, incorrect hdmitx0-pixel-clock fixed-clock node is removed. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 119 ++++++++++++++++++++= +++- arch/riscv/boot/dts/starfive/jh7110.dtsi | 87 +++++++++++++++-- 2 files changed, 196 insertions(+), 10 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index a7a1c09a2c9075711f3a214a49618911fdc7b421..7aadc35f4a6aa724c86a868ef65= c5c829e666ee2 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -33,6 +33,25 @@ memory@40000000 { bootph-pre-ram; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* vout applies for space from this CMA + * Without this CMA reservation, + * vout may not work properly. + */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x0 0x20000000>; + alignment =3D <0x0 0x1000>; + alloc-ranges =3D <0x0 0x70000000 0x0 0x20000000>; + linux,cma-default; + }; + }; + gpio-restart { compatible =3D "gpio-restart"; gpios =3D <&sysgpio 35 GPIO_ACTIVE_HIGH>; @@ -73,12 +92,47 @@ codec { }; }; }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; }; =20 &cpus { timebase-frequency =3D <4000000>; }; =20 +&dc8200 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_port0: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_out_dpi0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_in>; + }; + }; + + dpu_port1: port@1 { + reg =3D <1>; + }; + }; +}; + &dvp_clk { clock-frequency =3D <74250000>; }; @@ -99,8 +153,31 @@ &gmac1_rmii_refin { clock-frequency =3D <50000000>; }; =20 -&hdmitx0_pixelclk { - clock-frequency =3D <297000000>; +&hdmi_controller { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_pins>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + hdmi_out_port: port@1 { + reg =3D <1>; + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + + }; + }; }; =20 &i2srx_bclk_ext { @@ -351,6 +428,40 @@ &syscrg { }; =20 &sysgpio { + hdmi_pins: hdmi-0 { + hdmi-cec-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-hpd-pins { + pinmux =3D ; + input-enable; + bias-disable; /* external pull-up */ + }; + + hdmi-scl-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-sda-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux =3D ; }; + +&voutcrg { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 9c3e4598747eb5541effe697044484715569a285..024e33b0e97cb13928d69d1d809= 0ed14d22bb022 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -290,12 +290,6 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock { #clock-cells =3D <0>; }; =20 - hdmitx0_pixelclk: hdmitx0-pixel-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "hdmitx0_pixelclk"; - #clock-cells =3D <0>; - }; - i2srx_bclk_ext: i2srx-bclk-ext-clock { compatible =3D "fixed-clock"; clock-output-names =3D "i2srx_bclk_ext"; @@ -352,6 +346,13 @@ tdm_ext: tdm-ext-clock { #clock-cells =3D <0>; }; =20 + xin24m: xin24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "xin24m"; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -1199,22 +1200,92 @@ csi_phy: phy@19820000 { #phy-cells =3D <0>; }; =20 + dc8200: display@29400000 { + compatible =3D "verisilicon,dc"; + reg =3D <0x0 0x29400000 0x0 0x2800>; + interrupts =3D <95>; + dma-noncoherent; + + power-domains =3D <&pwrc JH7110_PD_VOUT>; + + clocks =3D <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + + resets =3D <&voutcrg JH7110_VOUTRST_DC8200_CORE>, + <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>; + reset-names =3D "core", "axi", "ahb"; + }; + + hdmi_subsystem: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-subsystem"; + reg =3D <0x0 0x29590000 0x0 0x4000>; + + /* + * This MFD's PHY child is the first device in the vout + * region to touch registers, so it owns the NoC display + * bus clock + reset that gate access to the region. + * PD_VOUT is powered on by genpd via power-domains. + */ + power-domains =3D <&pwrc JH7110_PD_VOUT>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>; + resets =3D <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + + clocks =3D <&xin24m>; + clock-names =3D "refoclk"; + + /* Output clock: The variable pixel clock */ + #clock-cells =3D <0>; + clock-output-names =3D "hdmi_pclk"; + + /* PHY provider for the controller */ + #phy-cells =3D <0>; + }; + + hdmi_controller: controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + interrupts =3D <99>; + + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "sys", "mclk", "bclk", "pclk"; + + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + }; + }; + voutcrg: clock-controller@295c0000 { compatible =3D "starfive,jh7110-voutcrg"; reg =3D <0x0 0x295c0000 0x0 0x10000>; + + power-domains =3D <&pwrc JH7110_PD_VOUT>; + clocks =3D <&syscrg JH7110_SYSCLK_VOUT_SRC>, <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, - <&hdmitx0_pixelclk>; + <&hdmi_phy>; clock-names =3D "vout_src", "vout_top_ahb", "vout_top_axi", "vout_top_hdmitx0_mclk", "i2stx0_bclk", "hdmitx0_pixelclk"; + resets =3D <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1787924922; bh=iV6Xa1fxoC/OMSyXdhXIR6VxHfrcQ97alBvh+bV7JIA=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=SKjQECG1pmOp9W6W+GXK7UHEbDXcoio5shiwuGjEQKULqGn8tMCHmGfgr7FAZrZwc G/1343/Pq7zzgCRca8YHpd59fN0iEDnotiBy3Im3EwBvX6QzQA022cZc9fK0HKPUEC kbaycBtoAhqh4F88CebAoZ+neGj89sO7M5WDvgHQ= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20260828134841eucas1p100590973cc6808103c41d0b0fc82573a~P-D5Wxv3f0280802808eucas1p1Z; Fri, 28 Aug 2026 13:48:41 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260828134839eusmtip190fc7410941048a10a1933088912b478~P-D3BV4p42825028250eusmtip1d; Fri, 28 Aug 2026 13:48:39 +0000 (GMT) From: Michal Wilczynski Date: Fri, 28 Aug 2026 15:47:39 +0200 Subject: [PATCH v2 15/15] MAINTAINERS: Add StarFive JH7110 display subsystem entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-jh7110-clean-send-v2-15-331680c8b9d1@samsung.com> In-Reply-To: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260828134841eucas1p100590973cc6808103c41d0b0fc82573a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260828134841eucas1p100590973cc6808103c41d0b0fc82573a X-EPHeader: CA X-CMS-RootMailID: 20260828134841eucas1p100590973cc6808103c41d0b0fc82573a References: <20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com> The JH7110 display subsystem spans a PHY driver, a DRM bridge driver, a parent device and their bindings, and has no existing maintainer entry. Add an entry covering them so patches reach someone who can review them. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8014b9f8253edf15231df215d1b14063a54a55ec..84ac5cfe61cdf775167cf903386= 2724c37946a5f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25778,6 +25778,16 @@ S: Maintained F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c =20 +STARFIVE JH7110 DISPLAY SUBSYSTEM +M: Michal Wilczynski +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-h= dmi-controller.yaml +F: Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.ya= ml +F: Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml +F: drivers/gpu/drm/bridge/jh7110-inno-hdmi.c +F: drivers/phy/starfive/phy-jh7110-inno-hdmi.c +F: drivers/soc/starfive/jh7110-hdmi-subsystem.c + STARFIVE JH7110 DPHY RX DRIVER M: Jack Zhu M: Changhuang Liang --=20 2.34.1