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Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Acked-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index c39ced168d03..4d31637f1dce 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -51,6 +51,7 @@ #include "phy-qcom-qmp-dp-phy-v5.h" #include "phy-qcom-qmp-dp-phy-v6.h" #include "phy-qcom-qmp-dp-phy-v8.h" +#include "phy-qcom-qmp-qserdes-dp-com-v8.h" #include "phy-qcom-qmp-dp-phy-v10.h" =20 #include "phy-qcom-qmp-usb43-pcs-v8.h" @@ -318,8 +319,8 @@ static const unsigned int qmp_v8_n3_usb43dpphy_regs_lay= out[QPHY_LAYOUT_SIZE] =3D { [QPHY_DP_AON_TOGGLE_ENABLE] =3D QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE, =20 [QPHY_COM_RESETSM_CNTRL] =3D QSERDES_V8_COM_RESETSM_CNTRL, - [QPHY_COM_C_READY_STATUS] =3D QSERDES_V8_COM_C_READY_STATUS, - [QPHY_COM_CMN_STATUS] =3D QSERDES_V8_COM_CMN_STATUS, + [QPHY_COM_C_READY_STATUS] =3D DP_QSERDES_V8_COM_C_READY_STATUS, + [QPHY_COM_CMN_STATUS] =3D DP_QSERDES_V8_COM_CMN_STATUS, [QPHY_COM_BIAS_EN_CLKBUFLR_EN] =3D QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, =20 [QPHY_DP_PHY_STATUS] =3D QSERDES_V8_DP_PHY_STATUS, --=20 2.34.1 From nobody Sat Sep 26 23:52:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E782E395ADA for ; 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Fri, 28 Aug 2026 02:43:28 -0700 (PDT) Received: from hu-naala-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f995e60sm4166331eec.22.2026.08.28.02.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 02:43:27 -0700 (PDT) From: Nabige Aala Date: Fri, 28 Aug 2026 15:13:14 +0530 Subject: [PATCH v3 2/4] phy: qualcomm: qmp-combo: Update DP PHY common init tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-glymur-phy-v3-v3-2-8e73ce7c4636@oss.qualcomm.com> References: <20260828-glymur-phy-v3-v3-0-8e73ce7c4636@oss.qualcomm.com> In-Reply-To: <20260828-glymur-phy-v3-v3-0-8e73ce7c4636@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P , Nabige Aala X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Acked-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 4d31637f1dce..b2ffc20e8f6a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1494,10 +1494,10 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_s= erdes_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), @@ -1512,12 +1512,13 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x56), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), @@ -1553,26 +1554,26 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_t= x_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x1a), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VMODE_CTRL1, 0x40), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT1, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x18), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x50), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0d), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x87), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRAN_DRVR_EMP_EN, 0x5f), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x2b), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_PRE1_EMPH, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_PRE1_EMPH, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_DRV_LVL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_DRV_LVL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x3f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x50), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x51), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x0c), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), --=20 2.34.1 From nobody Sat Sep 26 23:52:58 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10E42379EC8 for ; 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Fri, 28 Aug 2026 02:43:31 -0700 (PDT) Received: from hu-naala-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f995e60sm4166331eec.22.2026.08.28.02.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 02:43:31 -0700 (PDT) From: Nabige Aala Date: Fri, 28 Aug 2026 15:13:15 +0530 Subject: [PATCH v3 3/4] phy: qualcomm: qmp-combo: Update link rate specific DP PHY tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260828-glymur-phy-v3-v3-3-8e73ce7c4636@oss.qualcomm.com> References: <20260828-glymur-phy-v3-v3-0-8e73ce7c4636@oss.qualcomm.com> In-Reply-To: <20260828-glymur-phy-v3-v3-0-8e73ce7c4636@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P , Nabige Aala X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Acked-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 43 +++++++++++++++++----------= ---- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index b2ffc20e8f6a..16ccabd945f7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1746,11 +1746,12 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_s= erdes_tbl_hbr3[] =3D { =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x7a), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x8d), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x27), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x83), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x37), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x54), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x06), @@ -1758,16 +1759,17 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serd= es_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa4), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa7), }; =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x21), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x08), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), @@ -1784,7 +1786,8 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x10), @@ -1794,9 +1797,9 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x17), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x03), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), @@ -1804,8 +1807,8 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr2[] =3D { =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x63), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x25), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x5b), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), @@ -1813,7 +1816,7 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), =20 - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x18), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x15), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x4f), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), @@ -1832,19 +1835,19 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serd= es_tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), - 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a=VCFKsFhLO8FUdW1wYC8A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: AABBpPZq42VurSf1N3UjN1XL0z_yFI9z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280082 From: Ritesh Kumar Rework the DP PHY runtime configuration by: - Extracting common DP PHY initialization sequence into qmp_combo_configure_dp_phy_common() function that is shared between qmp_v456_configure_dp_phy() and qmp_v8_configure_dp_phy() - Adding dp_aux_cfg2 field to qmp_phy_cfg structure to store the hardware-specific AUX_CFG2 register value - Defining named constants (QSERDES_DP_PHY_AUX_CFG2_V456 and QSERDES_DP_PHY_AUX_CFG2_V8) for better code readability and maintainability - Adding validation check to ensure dp_aux_cfg2 is properly configured for all hardware variants - Updating qmp_v8_dp_aux_init() with corrected power-down control and bias enable settings - Modifying qmp_v8_configure_dp_clocks() to add VCO divider programming and update auxless/LFPS timing parameters - Refining qmp_v8_configure_dp_phy() with updated driver enable values, TSYNC override sequence, and additional status checks for proper PHY lock verification Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Reviewed-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 185 +++++++++++++++++++-------= ---- 1 file changed, 118 insertions(+), 67 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 16ccabd945f7..5630627dc85e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2478,6 +2478,10 @@ static const struct qmp_combo_lane_mapping dp_data_l= anes[] =3D { =20 struct qmp_combo; =20 +/* DP PHY AUX_CFG2 register values for different hardware versions */ +#define QSERDES_DP_PHY_AUX_CFG2_V456 0xa4 +#define QSERDES_DP_PHY_AUX_CFG2_V8 0x06 + struct qmp_combo_offsets { u16 com; u16 txa; @@ -2541,6 +2545,9 @@ struct qmp_phy_cfg { int (*calibrate_dp_phy)(struct qmp_combo *qmp); void (*dp_aux_init)(struct qmp_combo *qmp); =20 + /* DP PHY AUX_CFG2 register value (hardware-specific) */ + unsigned int dp_aux_cfg2; + /* resets to be requested */ const char * const *reset_list; int num_resets; @@ -2780,6 +2787,7 @@ static const struct qmp_phy_cfg sar2130p_usb3dpphy_cf= g =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -2916,6 +2924,7 @@ static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg= =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -2962,6 +2971,7 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_c= fg =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3007,6 +3017,7 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cf= g =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3116,6 +3127,7 @@ static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3164,6 +3176,7 @@ static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3211,6 +3224,7 @@ static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3256,6 +3270,7 @@ static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3301,6 +3316,7 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3346,6 +3362,7 @@ static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, =20 .regs =3D qmp_v8_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3392,6 +3409,8 @@ static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = =3D { .configure_dp_clocks =3D qmp_v8_configure_dp_clocks, .configure_dp_phy =3D qmp_v8_configure_dp_phy, =20 + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V8, + .regs =3D qmp_v8_n3_usb43dpphy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3693,16 +3712,75 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qm= p) qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); } =20 +static int qmp_combo_configure_dp_phy_common(struct qmp_combo *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + u32 status; + int ret; + + if (!cfg->dp_aux_cfg2) { + dev_err(qmp->dev, "DP AUX CFG2 value not configured\n"); + return -EINVAL; + } + + writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); + + qmp_combo_configure_dp_mode(qmp); + + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); + writel(cfg->dp_aux_cfg2, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); + + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); + + ret =3D qmp->cfg->configure_dp_clocks(qmp); + if (ret) + return ret; + + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS= ], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + return 0; +} + static void qmp_v8_dp_aux_init(struct qmp_combo *qmp) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_= PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + writel(0x3f, qmp->dp_serdes + QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); =20 /* Turn on BIAS current for PHY/PLL */ - writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); + writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); =20 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); @@ -3729,8 +3807,8 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *= qmp) writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); =20 - writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); - writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); =20 qmp_combo_configure_dp_swing(qmp); } @@ -3738,48 +3816,41 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo= *qmp) static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp) { const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; - u32 phy_vco_div; unsigned long pixel_freq; - const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 switch (dp_opts->link_rate) { case 1620: - phy_vco_div =3D 0x4; pixel_freq =3D 1620000000UL / 2; break; case 2700: - phy_vco_div =3D 0x2; pixel_freq =3D 2700000000UL / 2; break; case 5400: - phy_vco_div =3D 0x4; pixel_freq =3D 5400000000UL / 4; break; case 8100: - phy_vco_div =3D 0x3; pixel_freq =3D 8100000000UL / 6; break; default: /* Other link rates aren't supported */ return -EINVAL; } - writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); =20 /* disable core reset tsync */ writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); =20 - writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); - writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); + writel(0x09, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); + writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC); - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); + writel(0x33, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); =20 writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL); writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL); writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1); - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); + writel(0x33, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL); - writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); + writel(0x02, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); =20 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); @@ -3793,48 +3864,10 @@ static int qmp_v456_configure_dp_phy(struct qmp_com= bo *qmp) u32 status; int ret; =20 - writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); - - qmp_combo_configure_dp_mode(qmp); - - writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); - writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); - - writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); - writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); - - ret =3D qmp->cfg->configure_dp_clocks(qmp); + ret =3D qmp_combo_configure_dp_phy_common(qmp); if (ret) return ret; =20 - writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - - writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); - - if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS= ], - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], - status, - ((status & BIT(1)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); =20 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], @@ -3926,7 +3959,7 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *= qmp) u32 status; int ret; =20 - ret =3D qmp_v456_configure_dp_phy(qmp); + ret =3D qmp_combo_configure_dp_phy_common(qmp); if (ret < 0) return ret; =20 @@ -3938,13 +3971,13 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo= *qmp) } else if (dp_opts->lanes =3D=3D 2) { bias0_en =3D reverse ? 0x3f : 0x15; bias1_en =3D reverse ? 0x15 : 0x3f; - drvr0_en =3D 0x10; - drvr1_en =3D 0x10; + drvr0_en =3D 0x30; + drvr1_en =3D 0x30; } else { bias0_en =3D 0x3f; bias1_en =3D 0x3f; - drvr0_en =3D 0x34; - drvr1_en =3D 0x34; + drvr0_en =3D 0x30; + drvr1_en =3D 0x30; } =20 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); @@ -3952,6 +3985,15 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo = *qmp) writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); =20 + writel(0x03, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x23, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x22, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + + writel(0x0a, qmp->dp_tx + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); + writel(0x0a, qmp->dp_tx2 + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); + + writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x08, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); udelay(100); writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); @@ -3959,16 +4001,25 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo= *qmp) =20 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], status, - ((status & BIT(1)) > 0), + ((status & BIT(0)) > 0), 500, 10000)) return -ETIMEDOUT; =20 - writel(0x00, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); - writel(0x00, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); =20 - writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); - writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; =20 return 0; } --=20 2.34.1