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Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/h= dmi/hdmi_bridge.c index 157f19bd90b4..a5f891661ea3 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -472,7 +472,7 @@ msm_hdmi_hotplug_work(struct work_struct *work) /* initialize bridge */ int msm_hdmi_bridge_init(struct hdmi *hdmi) { - struct drm_bridge *bridge =3D NULL; + struct drm_bridge *bridge; struct hdmi_bridge *hdmi_bridge; int ret; =20 --=20 2.53.0 From nobody Sat Sep 26 23:03:46 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 218C446E000 for ; Fri, 28 Aug 2026 14:05:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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However error paths still use the name in error message. Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/msm_io_utils.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_io_utils.c b/drivers/gpu/drm/msm/msm_i= o_utils.c index a6efe1eac271..93b94e330cb8 100644 --- a/drivers/gpu/drm/msm/msm_io_utils.c +++ b/drivers/gpu/drm/msm/msm_io_utils.c @@ -77,7 +77,8 @@ static void __iomem *_msm_ioremap(struct platform_device = *pdev, const char *name =20 if (!res) { if (!quiet) - DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name); + DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", + (name ? name : "#0")); return ERR_PTR(-EINVAL); } =20 @@ -86,7 +87,8 @@ static void __iomem *_msm_ioremap(struct platform_device = *pdev, const char *name ptr =3D devm_ioremap(&pdev->dev, res->start, size); if (!ptr) { if (!quiet) - DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); + DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", + (name ? name : "#0")); return ERR_PTR(-ENOMEM); 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Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/ds= i/dsi_manager.c index 959daa88b1d0..531d4ff78f56 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -429,7 +429,7 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(s= truct drm_bridge *bridge, if (dev_pm_opp_get_opp_count(&pdev->dev) !=3D 0) return MODE_CLOCK_RANGE; } else { - return MODE_ERROR; + return MODE_ERROR; } =20 return msm_dsi_host_check_dsc(host, mode); --=20 2.53.0 From nobody Sat Sep 26 23:03:46 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94AA547044B for ; Fri, 28 Aug 2026 14:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/hdmi.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Docu= mentation/devicetree/bindings/display/msm/hdmi.yaml index dfec6c3480f3..02d27ccad024 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -113,7 +113,7 @@ allOf: - const: core - const: master_iface - const: slave_iface - core-vcc-supplies: false + core-vcc-supply: false =20 - if: properties: @@ -136,7 +136,7 @@ allOf: - const: core - const: alt_iface - const: extp - hdmi-mux-supplies: false + hdmi-mux-supply: false =20 - if: properties: --=20 2.53.0 From nobody Sat Sep 26 23:03:46 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6412946EC90 for ; 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There are just a few differences in hardware, mostly about handling clock reparenting, but more notable the old binding looked incomplete, thus devices could not be considered compatible. The QFPROM MMIO space is not really part of HDMI, thus do not include it in the new device support. Document also VDD IO supply, which is providing power to external 5V elements, like HPD pull ups. This is not a suuply for internal HDMI elements, thus it is valid for older variants as well. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/hdmi.yaml | 67 ++++++++++++++- .../bindings/display/msm/qcom,eliza-mdss.yaml | 96 ++++++++++++++++++= +++- 2 files changed, 158 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Docu= mentation/devicetree/bindings/display/msm/hdmi.yaml index 02d27ccad024..6adaa095b747 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -20,6 +20,7 @@ properties: - qcom,hdmi-tx-8994 - qcom,hdmi-tx-8996 - qcom,hdmi-tx-8998 + - qcom,eliza-hdmi-tx =20 clocks: minItems: 1 @@ -35,10 +36,7 @@ properties: =20 reg-names: minItems: 1 - items: - - const: core_physical - - const: qfprom_physical - - const: hdcp_physical + maxItems: 3 =20 interrupts: maxItems: 1 @@ -62,10 +60,21 @@ properties: core-vcc-supply: description: phandle to VCC supply regulator =20 + vddio-supply: + description: IO (e.g. HPD) supply + hpd-gpios: maxItems: 1 description: hpd pin =20 + operating-points-v2: true + + opp-table: + type: object + + power-domains: + maxItems: 1 + '#sound-dai-cells': const: 1 =20 @@ -113,6 +122,12 @@ allOf: - const: core - const: master_iface - const: slave_iface + reg-names: + minItems: 1 + items: + - const: core_physical + - const: qfprom_physical + - const: hdcp_physical core-vcc-supply: false =20 - if: @@ -136,6 +151,12 @@ allOf: - const: core - const: alt_iface - const: extp + reg-names: + minItems: 1 + items: + - const: core_physical + - const: qfprom_physical + - const: hdcp_physical hdmi-mux-supply: false =20 - if: @@ -159,6 +180,44 @@ allOf: - const: bus - const: mnoc - const: iface_mmss + reg-names: + minItems: 1 + items: + - const: core_physical + - const: qfprom_physical + - const: hdcp_physical + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcom,eliza-hdmi-tx + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface + - const: core + - const: extp + - const: phy_iface + - const: pll + - const: pixel_src + reg: + minItems: 2 + maxItems: 2 + reg-names: + items: + - const: core_physical + - const: hdcp_physical + hdmi-mux-supply: false + + required: + - core-vcc-supply + - core-vdda-supply =20 additionalProperties: false =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml index bd4ba91a171f..6f50f7106c8f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml @@ -63,13 +63,22 @@ patternProperties: contains: const: qcom,eliza-dsi-ctrl =20 + "^hdmi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,eliza-hdmi-tx + "^phy@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: contains: - const: qcom,eliza-dsi-phy-4nm + enum: + - qcom,eliza-dsi-phy-4nm + - qcom,eliza-hdmi-phy =20 required: - compatible @@ -79,6 +88,7 @@ unevaluatedProperties: false examples: - | #include + #include #include #include #include @@ -405,6 +415,90 @@ examples: vdds-supply =3D <&vreg_l2b>; }; =20 + hdmi@aea0000 { + compatible =3D "qcom,eliza-hdmi-tx"; + reg =3D <0x0aea0000 0x1000>, + <0x0aee0000 0x1000>; + reg-names =3D "core_physical", + "hdcp_physical"; + + interrupts-extended =3D <&mdss 8>; + + clocks =3D <&disp_cc_mdss_hdmi_ahbm_clk>, + <&disp_cc_mdss_hdmi_app_clk>, + <&disp_cc_mdss_hdmi_pclk_clk>, + <&disp_cc_mdss_hdmi_intf_clk>, + <&mdss_hdmi_phy>, + <&disp_cc_mdss_hdmi_pclk_clk_src>; + clock-names =3D "iface", + "core", + "extp", + "phy_iface", + "pll", + "pixel_src"; + + operating-points-v2 =3D <&mdss_hdmi_opp_table>; + + phys =3D <&mdss_hdmi_phy>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + #sound-dai-cells =3D <1>; + + core-vcc-supply =3D <&vreg_l2b>; + core-vdda-supply =3D <&vreg_l4b>; + vddio-supply =3D <&hdmi_5p0_reg>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_hdmi_in: endpoint { + remote-endpoint =3D <&dpu_intf4_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_hdmi_out: endpoint { + remote-endpoint =3D <&hdmi_0_connector_in>; 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There is no documentation, except register list and register programming sequence, and downstream sources do not point to any supplies. Signed-off-by: Krzysztof Kozlowski --- .../bindings/phy/qcom,eliza-hdmi-phy.yaml | 71 ++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,eliza-hdmi-phy.yaml= b/Documentation/devicetree/bindings/phy/qcom,eliza-hdmi-phy.yaml new file mode 100644 index 000000000000..764fec0ef29b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,eliza-hdmi-phy.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/phy/qcom,eliza-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Eliza SoC HDMI phy (Synopsys) + +maintainers: + - Rob Clark + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - qcom,eliza-hdmi-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: ref + - const: xo + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 0 + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + + hdmi-phy@9a0600 { + compatible =3D "qcom,eliza-hdmi-phy"; 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Similarly to what is happening on Qualcomm MSM DSI blocks since SM8750. Rework and split the HDMI msm_hdmi_power_on() into smaller steps: 1. Leave untouched logic related to runtime PM (power on the domain). This is done only once, guarded by "if (hdmi->power_on) {" condition, 2. During every msm_hdmi_bridge_atomic_pre_enable(), initialize the HDMI PHY with new msm_hdmi_phy_init() as it was previously powered down. Currently no-op for all the PHYs, 3. Similarly, for every enable prepare and set rate of HDMI pixclock (extp_clk). This will also reparent the pixclock to HDMI PHY PLL later and should happen after the HDMI PHY is initialized (point 2 above). Commit should have no practical impact on existing devices. Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/hdmi/hdmi.h | 4 ++++ drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 30 +++++++++++++++++++++++++----- drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 16 ++++++++++++++++ 3 files changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdm= i.h index 436d4f9fe346..306b988bca72 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -151,6 +151,8 @@ enum hdmi_phy_type { =20 struct hdmi_phy_cfg { enum hdmi_phy_type type; + void (*init)(struct hdmi_phy *phy, unsigned long pixclock); + void (*deinit)(struct hdmi_phy *phy); void (*powerup)(struct hdmi_phy *phy, unsigned long pixclock); void (*powerdown)(struct hdmi_phy *phy); const char * const *reg_names; @@ -186,6 +188,8 @@ static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u= 32 reg) =20 int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy); void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy); +void msm_hdmi_phy_init(struct hdmi_phy *phy, unsigned long pixclock); +void msm_hdmi_phy_deinit(struct hdmi_phy *phy); void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long pixclock); void msm_hdmi_phy_powerdown(struct hdmi_phy *phy); void __init msm_hdmi_phy_driver_register(void); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/h= dmi/hdmi_bridge.c index a5f891661ea3..d0e3b27644fe 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -14,14 +14,20 @@ #include "hdmi.h" =20 static void msm_hdmi_power_on(struct drm_bridge *bridge) +{ + struct hdmi_bridge *hdmi_bridge =3D to_hdmi_bridge(bridge); + struct hdmi *hdmi =3D hdmi_bridge->hdmi; + + pm_runtime_resume_and_get(&hdmi->pdev->dev); +} + +static void msm_hdmi_clk_prepare(struct drm_bridge *bridge) { struct drm_device *dev =3D bridge->dev; struct hdmi_bridge *hdmi_bridge =3D to_hdmi_bridge(bridge); struct hdmi *hdmi =3D hdmi_bridge->hdmi; int ret; =20 - pm_runtime_resume_and_get(&hdmi->pdev->dev); - if (hdmi->extp_clk) { DBG("pixclock: %lu", hdmi->pixclock); ret =3D clk_set_rate(hdmi->extp_clk, hdmi->pixclock); @@ -44,10 +50,16 @@ static void power_off(struct drm_bridge *bridge) */ mdelay(16 + 4); =20 + pm_runtime_put(&hdmi->pdev->dev); +} + +static void msm_hdmi_clk_unprepare(struct drm_bridge *bridge) +{ + struct hdmi_bridge *hdmi_bridge =3D to_hdmi_bridge(bridge); + struct hdmi *hdmi =3D hdmi_bridge->hdmi; + if (hdmi->extp_clk) clk_disable_unprepare(hdmi->extp_clk); - - pm_runtime_put(&hdmi->pdev->dev); } =20 #define AVI_IFRAME_LINE_NUMBER 1 @@ -300,8 +312,14 @@ static void msm_hdmi_bridge_atomic_pre_enable(struct d= rm_bridge *bridge, =20 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); =20 + msm_hdmi_phy_init(phy, hdmi->pixclock); + /* + * Re-parent clocks and set rates once phy is properly initialized. + * OTOH, TX DATA on the phy should not be enabled before clocks are + * configured. + */ + msm_hdmi_clk_prepare(bridge); msm_hdmi_phy_powerup(phy, hdmi->pixclock); - msm_hdmi_set_mode(hdmi, true); =20 if (hdmi->hdcp_ctrl) @@ -325,6 +343,8 @@ static void msm_hdmi_bridge_atomic_post_disable(struct = drm_bridge *bridge, msm_hdmi_set_mode(hdmi, hdmi->hpd_enabled); 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This allows proper votes depending on requested HDMI pixel rate. Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/hdmi/hdmi.c | 8 ++++++++ drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 10 +++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdm= i.c index 474006084633..c46f30063f14 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -368,6 +368,14 @@ static int msm_hdmi_dev_probe(struct platform_device *= pdev) goto err_put_bridge; } =20 + ret =3D devm_pm_opp_set_clkname(dev, "extp"); + if (ret) + return ret; + + ret =3D devm_pm_opp_of_add_table(dev); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "invalid OPP table in device tree\n"); + if (!hdmi->hpd_gpiod) DBG("failed to get HPD gpio"); =20 diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/h= dmi/hdmi_bridge.c index d0e3b27644fe..621083a97b37 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -30,9 +31,10 @@ static void msm_hdmi_clk_prepare(struct drm_bridge *brid= ge) =20 if (hdmi->extp_clk) { DBG("pixclock: %lu", hdmi->pixclock); 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The device clocks look different comparing to last variant of HDMI from MSM8998. Signed-off-by: Krzysztof Kozlowski --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h | 8 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 15 +++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + drivers/gpu/drm/msm/hdmi/hdmi.c | 32 +++++++++ drivers/gpu/drm/msm/hdmi/hdmi.h | 4 ++ drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 75 ++++++++++++++++++= +--- drivers/gpu/drm/msm/msm_drv.h | 5 ++ 8 files changed, 136 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h index b93d32888972..c95cf4e38c12 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h @@ -294,6 +294,14 @@ static const struct dpu_intf_cfg eliza_intf[] =3D { .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, { + .name =3D "intf_11", .id =3D INTF_11, + .base =3D 0x3f000, .len =3D 0x4bc, + .type =3D INTF_HDMI, + .controller_id =3D MSM_HDMI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), } }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gp= u/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 5b7cd5241f45..f6d1f944f4ba 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -206,6 +206,21 @@ static const struct dpu_intr_reg dpu_intr_set_7xxx[] = =3D { MDP_INTF_REV_7xxx_INTR_EN(8), MDP_INTF_REV_7xxx_INTR_STATUS(8) }, + [MDP_INTF9_INTR] =3D { + MDP_INTF_REV_7xxx_INTR_CLEAR(9), + MDP_INTF_REV_7xxx_INTR_EN(9), + MDP_INTF_REV_7xxx_INTR_STATUS(9) + }, + [MDP_INTF10_INTR] =3D { + MDP_INTF_REV_7xxx_INTR_CLEAR(10), + MDP_INTF_REV_7xxx_INTR_EN(10), + MDP_INTF_REV_7xxx_INTR_STATUS(10) + }, + [MDP_INTF11_INTR] =3D { + MDP_INTF_REV_7xxx_INTR_CLEAR(11), + MDP_INTF_REV_7xxx_INTR_EN(11), + MDP_INTF_REV_7xxx_INTR_STATUS(11) + }, }; =20 /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gp= u/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 142358a105c5..231809607be1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -27,6 +27,9 @@ enum dpu_hw_intr_reg { MDP_INTF6_INTR, MDP_INTF7_INTR, MDP_INTF8_INTR, + MDP_INTF9_INTR, + MDP_INTF10_INTR, + MDP_INTF11_INTR, MDP_INTF1_TEAR_INTR, MDP_INTF2_TEAR_INTR, MDP_AD4_0_INTR, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 0e65bf5ddc4a..bdcc0caa4e4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -226,6 +226,9 @@ enum dpu_intf { INTF_6, INTF_7, INTF_8, + INTF_9, + INTF_10, + INTF_11, INTF_MAX }; =20 diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdm= i.c index c46f30063f14..b769780cd5dd 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -234,6 +234,16 @@ static const struct hdmi_platform_config hdmi_tx_8974_= config =3D { .pwr_clk_cnt =3D ARRAY_SIZE(pwr_clk_names_8x74), }; =20 +static const char * const pwr_reg_names_eliza[] =3D {"core-vdda", "core-vc= c", "vddio"}; +static const char * const pwr_clk_names_eliza[] =3D {"iface", "core"}; + +static const struct hdmi_platform_config hdmi_tx_eliza_config =3D { + .pwr_reg_names =3D pwr_reg_names_eliza, + .pwr_reg_cnt =3D ARRAY_SIZE(pwr_reg_names_eliza), + .pwr_clk_names =3D pwr_clk_names_eliza, + .pwr_clk_cnt =3D ARRAY_SIZE(pwr_clk_names_eliza), +}; + static int msm_hdmi_bind(struct device *dev, struct device *master, void *= data) { struct msm_drm_private *priv =3D dev_get_drvdata(master); @@ -360,6 +370,27 @@ static int msm_hdmi_dev_probe(struct platform_device *= pdev) goto err_put_bridge; } =20 + hdmi->phy_iface_clk =3D devm_clk_get_optional(dev, "phy_iface"); + if (IS_ERR(hdmi->phy_iface_clk)) { + ret =3D dev_err_probe(dev, PTR_ERR(hdmi->phy_iface_clk), + "failed to get phy iface clock\n"); + goto err_put_bridge; + } + + hdmi->pixel_src_clk =3D devm_clk_get_optional(dev, "pixel_src"); + if (IS_ERR(hdmi->pixel_src_clk)) { + ret =3D dev_err_probe(dev, PTR_ERR(hdmi->pixel_src_clk), + "failed to get pixel src clock\n"); + goto err_put_bridge; + } + + hdmi->pll_clk =3D devm_clk_get_optional(dev, "pll"); + if (IS_ERR(hdmi->pll_clk)) { + ret =3D dev_err_probe(dev, PTR_ERR(hdmi->pll_clk), + "failed to get pll clock\n"); + goto err_put_bridge; + } + hdmi->hpd_gpiod =3D devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); /* This will catch e.g. -EPROBE_DEFER */ if (IS_ERR(hdmi->hpd_gpiod)) { @@ -458,6 +489,7 @@ static int msm_hdmi_runtime_resume(struct device *dev) static DEFINE_RUNTIME_DEV_PM_OPS(msm_hdmi_pm_ops, msm_hdmi_runtime_suspend= , msm_hdmi_runtime_resume, NULL); =20 static const struct of_device_id msm_hdmi_dt_match[] =3D { + { .compatible =3D "qcom,eliza-hdmi-tx", .data =3D &hdmi_tx_eliza_config }, { .compatible =3D "qcom,hdmi-tx-8998", .data =3D &hdmi_tx_8974_config }, { .compatible =3D "qcom,hdmi-tx-8996", .data =3D &hdmi_tx_8974_config }, { .compatible =3D "qcom,hdmi-tx-8994", .data =3D &hdmi_tx_8974_config }, diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdm= i.h index 306b988bca72..2fa9bec455b4 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -52,6 +52,9 @@ struct hdmi { struct regulator_bulk_data *pwr_regs; struct clk_bulk_data *pwr_clks; struct clk *extp_clk; + struct clk *phy_iface_clk; + struct clk *pixel_src_clk; + struct clk *pll_clk; =20 struct gpio_desc *hpd_gpiod; =20 @@ -171,6 +174,7 @@ struct hdmi_phy { struct platform_device *pdev; void __iomem *mmio; struct hdmi_phy_cfg *cfg; + void *pll; const struct hdmi_phy_funcs *funcs; struct regulator_bulk_data *regs; struct clk **clks; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/h= dmi/hdmi_bridge.c index 621083a97b37..c6a75f653915 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -14,6 +14,18 @@ #include "msm_kms.h" #include "hdmi.h" =20 +static void msm_hdmi_clk_reparent(struct hdmi *hdmi) +{ + int ret; + + if (hdmi->pixel_src_clk && hdmi->pll_clk) { + ret =3D clk_set_parent(hdmi->pixel_src_clk, hdmi->pll_clk); + if (ret) + DRM_DEV_ERROR(hdmi->dev->dev, "failed to set reparent pixel src clock r= ate: %d\n", + ret); + } +} + static void msm_hdmi_power_on(struct drm_bridge *bridge) { struct hdmi_bridge *hdmi_bridge =3D to_hdmi_bridge(bridge); @@ -29,16 +41,34 @@ static void msm_hdmi_clk_prepare(struct drm_bridge *bri= dge) struct hdmi *hdmi =3D hdmi_bridge->hdmi; int ret; =20 + msm_hdmi_clk_reparent(hdmi); if (hdmi->extp_clk) { + /* + * Set rate to hdmi->pixclock: PCLK_CLK_SRC and PCLK_CLK + * Set rate to hdmi->pixclock/2: INTF_CLK and PCLK_DIV_CLK_SRC + * Set rate to hdmi->pixclock: HDMI PHY PLL + */ DBG("pixclock: %lu", hdmi->pixclock); =20 ret =3D dev_pm_opp_set_rate(&hdmi->pdev->dev, hdmi->pixclock); if (ret) DRM_DEV_ERROR(dev->dev, "failed to set OPP rate: %d\n", ret); =20 + ret =3D clk_set_rate(hdmi->pixel_src_clk, hdmi->pixclock); + if (ret) + DRM_DEV_ERROR(dev->dev, "failed to set pixel src clk rate: %d\n", ret); + + ret =3D clk_set_rate(hdmi->phy_iface_clk, hdmi->pixclock / 2); + if (ret) + DRM_DEV_ERROR(dev->dev, "failed to set pixel iface clk rate: %d\n", ret= ); + ret =3D clk_prepare_enable(hdmi->extp_clk); if (ret) DRM_DEV_ERROR(dev->dev, "failed to enable extp clk: %d\n", ret); + + ret =3D clk_prepare_enable(hdmi->phy_iface_clk); + if (ret) + DRM_DEV_ERROR(dev->dev, "failed to enable phy iface clk: %d\n", ret); } } =20 @@ -61,6 +91,7 @@ static void msm_hdmi_clk_unprepare(struct drm_bridge *bri= dge) struct hdmi *hdmi =3D hdmi_bridge->hdmi; =20 if (hdmi->extp_clk) { + clk_disable_unprepare(hdmi->phy_iface_clk); clk_disable_unprepare(hdmi->extp_clk); dev_pm_opp_set_rate(&hdmi->pdev->dev, 0); } @@ -443,21 +474,47 @@ static enum drm_mode_status msm_hdmi_bridge_tmds_char= _rate_valid(const struct dr * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder * instead): */ - if (kms->funcs->round_pixclk) + if (kms->funcs->round_pixclk) { actual =3D kms->funcs->round_pixclk(kms, tmds_rate, hdmi_bridge->hdmi->encoder); - else if (hdmi->extp_clk) - actual =3D clk_round_rate(hdmi->extp_clk, tmds_rate); - else - actual =3D tmds_rate; + DBG("requested=3D%lld, actual=3D%ld", tmds_rate, actual); =20 - DBG("requested=3D%lld, actual=3D%ld", tmds_rate, actual); + if (actual !=3D tmds_rate) + return MODE_CLOCK_RANGE; + return MODE_OK; + } else if (!dev_pm_opp_get_opp_count(&hdmi->pdev->dev)) { + if (hdmi->extp_clk) + actual =3D clk_round_rate(hdmi->extp_clk, tmds_rate); + else + actual =3D tmds_rate; =20 - if (actual !=3D tmds_rate) - return MODE_CLOCK_RANGE; + if (actual !=3D tmds_rate) + return MODE_CLOCK_RANGE; + return MODE_OK; + } else { + struct dev_pm_opp *opp; + unsigned long pclk_rate =3D tmds_rate; =20 - return 0; + if (mode->clock > 600000) + return MODE_CLOCK_HIGH; + + opp =3D dev_pm_opp_find_freq_ceil(&hdmi->pdev->dev, &pclk_rate); + if (!IS_ERR(opp)) { + dev_pm_opp_put(opp); + } else if (PTR_ERR(opp) =3D=3D -ERANGE) { + /* + * An empty table is created by devm_pm_opp_set_clkname() even + * if there is none. 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There is no similarity regarding older HDMI phys. Core parts for handling HDMI phy needs some adjustments as well, because according to programming sequence: 1. The HDMI PHY should be initialized before preparing its PLL. 2. Final power up - enabling the TX lanes - should be performed after PLL is prepared. Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/hdmi/hdmi.h | 18 + drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 12 +- drivers/gpu/drm/msm/hdmi/hdmi_phy_eliza.c | 723 +++++++++++++++++++++= ++++ drivers/gpu/drm/msm/registers/display/hdmi.xml | 140 +++++ 5 files changed, 892 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index d0c3a4c6703b..ae343a250bb0 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -43,6 +43,7 @@ msm-display-$(CONFIG_DRM_MSM_HDMI) +=3D \ hdmi/hdmi_phy_8998.o \ hdmi/hdmi_phy_8x60.o \ hdmi/hdmi_phy_8x74.o \ + hdmi/hdmi_phy_eliza.o \ hdmi/hdmi_pll_8960.o \ =20 msm-display-$(CONFIG_DRM_MSM_MDP4) +=3D \ diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdm= i.h index 2fa9bec455b4..945fbb4d9888 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -149,6 +149,7 @@ enum hdmi_phy_type { MSM_HDMI_PHY_8x74, MSM_HDMI_PHY_8996, MSM_HDMI_PHY_8998, + MSM_HDMI_PHY_ELIZA, MSM_HDMI_PHY_MAX, }; =20 @@ -169,6 +170,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg; extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg; extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg; extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg; +extern const struct hdmi_phy_cfg msm_hdmi_phy_eliza_cfg; =20 struct hdmi_phy { struct platform_device *pdev; @@ -190,6 +192,16 @@ static inline u32 hdmi_phy_read(struct hdmi_phy *phy, = u32 reg) return readl(phy->mmio + reg); } =20 +static inline void hdmi_phy_update_bits(struct hdmi_phy *phy, u32 reg, u32= mask, u32 data) +{ + u32 val; + + val =3D hdmi_phy_read(phy, reg); + val &=3D ~mask; + val |=3D data & mask; + hdmi_phy_write(phy, reg, val); +} + int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy); void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy); void msm_hdmi_phy_init(struct hdmi_phy *phy, unsigned long pixclock); @@ -203,6 +215,7 @@ void __exit msm_hdmi_phy_driver_unregister(void); int msm_hdmi_pll_8960_init(struct platform_device *pdev); int msm_hdmi_pll_8996_init(struct platform_device *pdev); int msm_hdmi_pll_8998_init(struct platform_device *pdev); +int msm_hdmi_pll_eliza_init(struct platform_device *pdev); #else static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev) { @@ -218,6 +231,11 @@ static inline int msm_hdmi_pll_8998_init(struct platfo= rm_device *pdev) { return -ENODEV; } + +static inline int msm_hdmi_pll_eliza_init(struct platform_device *pdev) +{ + return -ENODEV; +} #endif =20 /* diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c b/drivers/gpu/drm/msm/hdmi= /hdmi_phy.c index 8ce87d9adf74..94dc0e5c5c3e 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c @@ -141,6 +141,9 @@ static int msm_hdmi_phy_pll_init(struct platform_device= *pdev, case MSM_HDMI_PHY_8998: ret =3D msm_hdmi_pll_8998_init(pdev); break; + case MSM_HDMI_PHY_ELIZA: + ret =3D msm_hdmi_pll_eliza_init(pdev); + break; /* * we don't have PLL support for these, don't report an error for now */ @@ -168,13 +171,17 @@ static int msm_hdmi_phy_probe(struct platform_device = *pdev) if (!phy->cfg) return -ENODEV; =20 - phy->mmio =3D msm_ioremap(pdev, "hdmi_phy"); + if (phy->cfg->num_regs) + phy->mmio =3D msm_ioremap(pdev, "hdmi_phy"); + else + phy->mmio =3D msm_ioremap(pdev, NULL); if (IS_ERR(phy->mmio)) { DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__); return -ENOMEM; } =20 phy->pdev =3D pdev; + platform_set_drvdata(pdev, phy); =20 ret =3D msm_hdmi_phy_resource_init(phy); if (ret) @@ -195,7 +202,6 @@ static int msm_hdmi_phy_probe(struct platform_device *p= dev) =20 msm_hdmi_phy_resource_disable(phy); =20 - platform_set_drvdata(pdev, phy); =20 return 0; } @@ -218,6 +224,8 @@ static const struct of_device_id msm_hdmi_phy_dt_match[= ] =3D { .data =3D &msm_hdmi_phy_8996_cfg }, { .compatible =3D "qcom,hdmi-phy-8998", .data =3D &msm_hdmi_phy_8998_cfg }, + { .compatible =3D "qcom,eliza-hdmi-phy", + .data =3D &msm_hdmi_phy_eliza_cfg }, {} }; MODULE_DEVICE_TABLE(of, msm_hdmi_phy_dt_match); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_eliza.c b/drivers/gpu/drm/ms= m/hdmi/hdmi_phy_eliza.c new file mode 100644 index 000000000000..fad4e828154e --- /dev/null +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_eliza.c @@ -0,0 +1,723 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hdmi.h" + +#define REF_CLK_HZ 38400000 /* 38.4 MHz */ +#define HDMI_PLL_MAX_FREQ 600000000 /* 600 MHz */ +/* Unscrambled clock freq threshold */ +#define HDMI_PLL_HIGH_FREQ 340000000 /* 340 Mhz */ +#define HDMI_PLL_MIN_FREQ 25000000 + +#define HDMI_PHY_MAX_BIT_RATE 2500000000 /* 2.5 Gbps */ + +/* Number of TX lanes */ +#define HDMI_PHY_TXN_CONTROL 4 + +#define MPLL(mul, qut, rem, den, clkd, vcof, pat, rxv, in, prop) \ + .multiplier =3D (mul), \ + .quotient =3D (qut), \ + .remainder =3D (rem), \ + .denominator =3D (den), \ + .tx_clk_div =3D (clkd), \ + .vco_freq =3D (vcof), \ + .clk_pat =3D (pat), \ + .rxvcosel =3D (rxv), \ + .cp_int_holder =3D (in), \ + .cp_prop_holder =3D (prop) + +struct hdmi_eliza_phy_pll_reg_cfg { + u32 vco_freq; + u32 rxvcosel; + u32 tx_clk_div; + u32 cp_int_holder; + u32 cp_prop_holder; + u32 quotient; + u32 remainder; + u32 multiplier; + u32 denominator; + u32 clk_pat; +}; + +struct hdmi_pll_eliza { + struct device *dev; + struct clk_hw clk_hw; + unsigned long rate; + struct hdmi_eliza_phy_pll_reg_cfg cfg; +}; + + +struct hdmi_pll_eliza_mpll { + unsigned long rate; + struct hdmi_eliza_phy_pll_reg_cfg cfg; +}; + +static const struct hdmi_pll_eliza_mpll mpll_lut[] =3D { + { 25200000, { MPLL(0xb0, 0xe525, 0, 1, 5, 2, 0, 3, 0xc, 0x11) }, }, + { 27000000, { MPLL(0xc0, 0x8000, 0, 1, 5, 2, 0, 3, 0xc, 0x11) }, }, + { 27027000, { MPLL(0xc0, 0x9ccc, 4, 1, 5, 2, 0, 3, 0xb, 0x12) }, }, + { 54000000, { MPLL(0xc0, 0x8000, 0, 1, 4, 2, 0, 3, 0xb, 0x11) }, }, + { 59400000, { MPLL(0xd6, 0xc000, 0, 1, 4, 2, 0, 3, 0xb, 0x12) }, }, + { 72000000, { MPLL(0x76, 0x0000, 0, 1, 3, 3, 0, 4, 0xc, 0x10) }, }, + { 74250000, { MPLL(0x7a, 0x5800, 0, 1, 3, 3, 0, 4, 0xb, 0x12) }, }, + { 82500000, { MPLL(0x8a, 0xf000, 0, 1, 3, 3, 0, 4, 0xb, 0x11) }, }, + { 90000000, { MPLL(0x9a, 0xc000, 0, 1, 3, 2, 0, 4, 0xd, 0x11) }, }, + { 99000000, { MPLL(0xae, 0x2000, 0, 1, 3, 2, 0, 4, 0xc, 0x11) }, }, + { 108000000, { MPLL(0xc0, 0x8000, 0, 1, 3, 2, 0, 3, 0xb, 0x11) }, }, + { 118800000, { MPLL(0xd6, 0xc000, 0, 1, 3, 2, 0, 3, 0xb, 0x12) }, }, + { 148500000, { MPLL(0x7a, 0x5800, 0, 1, 2, 3, 0, 4, 0xc, 0x11) }, }, + { 165000000, { MPLL(0x8a, 0xf000, 0, 1, 2, 3, 0, 4, 0xb, 0x11) }, }, + { 185625000, { MPLL(0xa0, 0xae00, 0, 1, 2, 2, 0, 4, 0xc, 0x11) }, }, + { 198000000, { MPLL(0xae, 0x2000, 0, 1, 2, 2, 0, 4, 0xc, 0x11) }, }, + { 297000000, { MPLL(0x7a, 0x5800, 0, 1, 1, 3, 0, 4, 0xc, 0x11) }, }, + { 371250000, { MPLL(0xa0, 0xae00, 0, 1, 1, 2, 1, 4, 0xc, 0x11) }, }, + { 396000000, { MPLL(0xae, 0x2000, 0, 1, 1, 2, 1, 4, 0xc, 0x11) }, }, + { 495000000, { MPLL(0xe0, 0xe800, 0, 1, 1, 2, 1, 3, 0xb, 0x12) }, }, + { 594000000, { MPLL(0x7a, 0x5800, 0, 1, 0, 3, 1, 4, 0xc, 0x11) }, }, +}; + +#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_eliza, clk_hw) + +static struct hdmi_phy *pll_get_phy(struct hdmi_pll_eliza *pll) +{ + return dev_get_drvdata(pll->dev); +} + +static const struct hdmi_eliza_phy_pll_reg_cfg * +hdmi_pll_eliza_mpll_lut_decoder(unsigned long rate) +{ + const struct hdmi_eliza_phy_pll_reg_cfg *cfg =3D NULL; + int i; + + for (i =3D 0; i < ARRAY_SIZE(mpll_lut); i++) { + if (rate =3D=3D mpll_lut[i].rate) { + cfg =3D &mpll_lut[i].cfg; + break; + } + } + + return cfg; +} + +static int hdmi_eliza_pll_calculator(struct hdmi_pll_eliza *pll, + unsigned long rate, + unsigned long parent_rate, + struct hdmi_eliza_phy_pll_reg_cfg *cfg) +{ + const s64 bit_rate_multiplier =3D 1000; + const s64 bit_rate_divider =3D 1000; + const s64 cp_int_param[3] =3D {4524, -679588, 30860643}; + const s64 cp_prop_param[3] =3D {8023, -1160252, 51717042}; + const u64 gmult =3D 1e4; + s64 expon, base_rate, bit_rate; + s64 ref_clk_int, ref_clk_div; + u64 aux0, aux1, aux2, vco_freq; + u64 utemp, utemp2, multiplier, f_rx_vco; + s64 stemp, stemp2, stemp3; + s32 choice1, ref_ana_mpll_div; + s64 precision3 =3D 1e3; + s64 precision6 =3D 1e6; + + if (rate > HDMI_PLL_HIGH_FREQ) + cfg->clk_pat =3D 1; + else + cfg->clk_pat =3D 0; + + /* + * base_rate =3D clock_khz * bit_rate_multiplier / 1000 + * Division by 1000, nullifies the conversion from KHz to Hz. + */ + base_rate =3D rate / 1000 * gmult; + + /* bit_rate =3D clock_khz * bit_rate_multiplier/bit_rate_divider. */ + utemp =3D DIV_ROUND_UP(bit_rate_multiplier, bit_rate_divider); + + bit_rate =3D base_rate * utemp; + + /* + * REF_CLK_HZ: 38.4 MHz + * min_ref_clk: 50 + * choice1 =3D floor(log2(REF_CLK_HZ/min_ref_clk)) + * choice1 =3D floor(-0.38) + */ + choice1 =3D -1; + ref_ana_mpll_div =3D max_t(s32, choice1, 0); + + /* ref_clk_div =3D 2**ref_ana_mpll_div; */ + ref_clk_div =3D 1UL << ref_ana_mpll_div; + ref_clk_int =3D DIV_ROUND_UP(REF_CLK_HZ, ref_clk_div); + + /* expon =3D floor(log2(4.999999e9/base_rate)) */ + utemp =3D 4.999999e9; + + expon =3D fls64(utemp / base_rate) - 1; + if (expon >=3D 0) + vco_freq =3D base_rate * (1UL << expon); + else + vco_freq =3D base_rate >> 1; + + /* multiplier =3D 2*(floor(bit_rate) * 2**expon / ref_clk_int) -16) */ + multiplier =3D DIV_ROUND_UP(vco_freq, ref_clk_int); + multiplier =3D 2 * (multiplier - 16 - 1); + cfg->multiplier =3D multiplier; + + /* f_rx_vco =3D bit_rate * 2**floor(log2(6e9/bit_rate)); */ + utemp =3D 6e9; + f_rx_vco =3D DIV_ROUND_UP(utemp, bit_rate); + f_rx_vco =3D ilog2(f_rx_vco); + f_rx_vco =3D bit_rate * (1UL << f_rx_vco); + + utemp =3D 4e9; + if (f_rx_vco < utemp) + f_rx_vco *=3D 2; + + utemp =3D 5e9; + if (f_rx_vco > utemp) + cfg->rxvcosel =3D 4; + else + cfg->rxvcosel =3D 3; + + /* + * aux0 =3D (bit_rate * 2**expon / ref_clk_int - (multiplier/2 + 16); + * aux0 =3D aux0 * 2** 16; + */ + if (expon >=3D 0) + utemp =3D bit_rate * (1UL << expon); + else + utemp =3D bit_rate >> 1; + + /* + * Need to store the floating-point values as they are + * essential for precise computations; thus, increasing + * the precision by 10^6. + */ + + utemp *=3D precision6; + utemp =3D DIV_ROUND_UP(utemp, ref_clk_int); + aux0 =3D utemp - (((multiplier >> 1) + 16)) * precision6; + cfg->quotient =3D (aux0 * (1UL << 16)) / precision6; + + /* aux1 =3D ref_clk_int * bit_rate_divider */ + aux1 =3D ref_clk_int * bit_rate_divider; + + /* + * aux2 =3D bit_rate * bit_rate_divider * 2**expon; + * aux2 =3D aux2 - ((multiplier/2 + 16) * aux1 * 2**16); + * aux2 =3D aux2 - aux1 *aux0; + */ + + if (expon >=3D 0) + aux2 =3D bit_rate * (1UL << expon); + else + aux2 =3D bit_rate >> 1; + + aux2 *=3D bit_rate_divider; + utemp =3D ((multiplier >> 1) + 16) * aux1; + aux2 =3D ((aux2 - utemp) * (1UL << 16)) - (cfg->quotient * aux1); + + if (aux2 =3D=3D 0) { + cfg->remainder =3D 0; + cfg->denominator =3D 1; + } else { + cfg->remainder =3D DIV_ROUND_UP(aux2, gcd(aux1, aux2)); + cfg->denominator =3D DIV_ROUND_UP(aux1, gcd(aux1, aux2)); + } + + /* tx_clk_div =3D log2(round(vco_freq/base_rate) * 2) */ + utemp =3D DIV_ROUND_UP(vco_freq, base_rate); + cfg->tx_clk_div =3D ilog2(utemp * 2); + + /* + * FIXME: For rate 198000000, LUT has vco_freq 2 but calculator gives 3 + * FIXME: For rate 198000000 and many others, LUT has cp_prop_holder 11, + * but calculator gives 12 + */ + utemp =3D 3.389e9; + utemp2 =3D 5e9; + if (vco_freq <=3D utemp) { + cfg->vco_freq =3D 2; + } else if (vco_freq < utemp2) { + cfg->vco_freq =3D 3; + } else { + DRM_DEV_ERROR(pll->dev, "bit_rate and vco_freq combination not supported= : %llu", + vco_freq); + return -EINVAL; + } + + /* stemp =3D (REF_CLK_MHZ/2**ref_ana_mpll_div) */ + stemp =3D (REF_CLK_HZ / 1000000) * precision3; + stemp =3D DIV_ROUND_CLOSEST(stemp, 1UL << ref_ana_mpll_div); + + /* stemp2 =3D cp_int_param[0] * stemp**2; */ + stemp2 =3D stemp * stemp * cp_int_param[0]; + stemp2 =3D DIV_ROUND_CLOSEST(stemp2, precision6); + + /* stemp3 =3D cp_int_param[1] * stemp; */ + stemp3 =3D stemp * cp_int_param[1]; + stemp3 /=3D precision3; + + /* + * cp_int_holder =3D floor(cp_int_param[0]*(stemp)**2 + * + cp_int_param[1] * stemp + * + cp_int_param[2]) + */ + stemp3 +=3D cp_int_param[2]; + stemp3 +=3D stemp2; + + cfg->cp_int_holder =3D DIV_ROUND_CLOSEST(stemp3, precision6); + + /* stemp2 =3D cp_prop_param[0] * stemp**2; */ + stemp2 =3D stemp * stemp * cp_prop_param[0]; + stemp2 =3D DIV_ROUND_CLOSEST(stemp2, precision6); + + /* stemp3 =3D cp_prop_param[1] * stemp; */ + stemp3 =3D (stemp * cp_prop_param[1]) / precision3; + + /* + * cp_int_holder =3D floor(cp_prop_param[0]*(stemp)**2 + * + cp_prop_param[1] * stemp + * + cp_prop_param[2]) + */ + stemp3 +=3D stemp2 + cp_prop_param[2]; + + cfg->cp_prop_holder =3D DIV_ROUND_CLOSEST(stemp3, precision6) - 1; + + return 0; +} + +static int hdmi_eliza_pll_configure_pll(struct hdmi_pll_eliza *pll, + unsigned long rate, + unsigned long parent_rate) +{ + struct hdmi_phy *phy =3D pll_get_phy(pll); + const struct hdmi_eliza_phy_pll_reg_cfg *cfg; + struct hdmi_eliza_phy_pll_reg_cfg cfg_calc =3D {}; + int ret; + u32 val; + + cfg =3D hdmi_pll_eliza_mpll_lut_decoder(rate); + if (!cfg) { + DRM_INFO("no valid mpll entry fall back to calculator"); + + ret =3D hdmi_eliza_pll_calculator(pll, rate, parent_rate, &cfg_calc); + if (ret) { + DRM_ERROR("PLL calculation failed for rate %lu\n", rate); + return ret; + } + cfg =3D &cfg_calc; + } + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_CLOCK_PATTERN_CONFIG_0, BIT(= 0), cfg->clk_pat); + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_2, GENMASK(6, 4= ), cfg->rxvcosel << 4); + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_1, GENMASK(7, 2= ), 0x11 << 2); + + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_0, 0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_10, + cfg->cp_int_holder & 0xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_12, + cfg->cp_prop_holder & 0xff); + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_0, BIT(0), BIT= (0)); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_2, + cfg->multiplier & 0xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_3, + (cfg->multiplier >> 8) & 0xff); + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_0, BIT(2), BIT= (2)); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_6, cfg->quotient & 0= xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_7, + (cfg->quotient >> 8) & 0xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_8, cfg->remainder & = 0xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_9, + (cfg->remainder >> 8) & 0xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_4, cfg->denominator = & 0xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_5, + (cfg->denominator >> 8) & 0xff); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_1, + cfg->tx_clk_div & 0x7); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_14, 0x82); + + val =3D hdmi_phy_read(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_0); + val &=3D ~BIT(6); + val &=3D ~(0x3 << 3); + val |=3D (cfg->vco_freq & 0x3) << 3; + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_0, val); + + /* + * Ensure that vco configuration gets flushed to hardware before + * enabling the PLL + */ + wmb(); + + pll->rate =3D rate; + pll->cfg =3D *cfg; + + return 0; +} + +static int hdmi_eliza_pll_set_clk_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) +{ + struct hdmi_pll_eliza *pll =3D hw_clk_to_pll(hw); + + return hdmi_eliza_pll_configure_pll(pll, rate, parent_rate); +}; + +static int hdmi_eliza_pll_prepare(struct clk_hw *hw) +{ + struct hdmi_pll_eliza *pll =3D hw_clk_to_pll(hw); + struct hdmi_phy *phy =3D pll_get_phy(pll); + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_CLOCK_PATTERN_CONFIG_0, BIT(= 1), BIT(1)); + + /* + * This Synopsys PLL does not have a PLL lock-like register, thus there + * is no way to tell when the PLL actually locked. + * Returning now, would lead to stuck pclk or iface RCG clocks at off + * (disp_cc_mdss_hdmi_pclk_clk status stuck at 'off'), + * thus obviously the professional solution is to delay. + * 8 ms was figured out during tests, not based on any datasheet. + */ + mdelay(8); + + return 0; +} + +static int hdmi_eliza_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + req->rate =3D clamp_t(unsigned long, req->rate, HDMI_PLL_MIN_FREQ, HDMI_P= LL_MAX_FREQ); + + return 0; +} + +static u64 hdmi_eliza_pll_vco_freq(u64 ref_clk_hz, u32 multiplier, u32 fra= c_quot, + u32 frac_rem, u32 frac_den) +{ + u64 num; + u64 den; + + num =3D 32ULL * 65536ULL * frac_den + + (u64)multiplier * 65536ULL * frac_den + + 2ULL * ((u64)frac_quot * frac_den + frac_rem); + + den =3D 2ULL * 65536ULL * frac_den; + + return mul_u64_u64_div_u64(ref_clk_hz, num, den); +} + +static unsigned long hdmi_eliza_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct hdmi_pll_eliza *pll =3D hw_clk_to_pll(hw); + u64 rate; + + rate =3D hdmi_eliza_pll_vco_freq(REF_CLK_HZ, pll->cfg.multiplier, + pll->cfg.quotient, pll->cfg.remainder, + pll->cfg.denominator); + + /* rate =3D vco_freq * 2 / (10 * 2^tx_clk_div) */ + rate *=3D 2; + do_div(rate, 10); + rate >>=3D pll->cfg.tx_clk_div; + + return rate; +} + + +static void hdmi_eliza_pll_unprepare(struct clk_hw *hw) +{ + struct hdmi_pll_eliza *pll =3D hw_clk_to_pll(hw); + struct hdmi_phy *phy =3D pll_get_phy(pll); + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_CLOCK_PATTERN_CONFIG_0, BIT(= 1), 0); +} + +static const struct clk_ops hdmi_eliza_pll_ops =3D { + .set_rate =3D hdmi_eliza_pll_set_clk_rate, + .determine_rate =3D hdmi_eliza_pll_determine_rate, + .recalc_rate =3D hdmi_eliza_pll_recalc_rate, + .prepare =3D hdmi_eliza_pll_prepare, + .unprepare =3D hdmi_eliza_pll_unprepare, +}; + +static const struct clk_init_data pll_init =3D { + .name =3D "hdmipll", + .ops =3D &hdmi_eliza_pll_ops, + .parent_data =3D (const struct clk_parent_data[]) { + { .fw_name =3D "xo", .name =3D "xo_board" }, + }, + .num_parents =3D 1, +}; + +int msm_hdmi_pll_eliza_init(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct hdmi_pll_eliza *pll; + struct hdmi_phy *phy; + int ret; + + pll =3D devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + pll->dev =3D dev; + pll->clk_hw.init =3D &pll_init; + + ret =3D devm_clk_hw_register(dev, &pll->clk_hw); + if (ret) { + DRM_DEV_ERROR(dev, "failed to register pll clock\n"); + return ret; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_= hw); + if (ret) { + DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); + return ret; + } + + phy =3D dev_get_drvdata(dev); + phy->pll =3D pll; + + return 0; +} + +static const char * const hdmi_phy_eliza_clk_names[] =3D { + "iface", + "ref", + "xo", +}; + +static void hdmi_eliza_phy_txn_write(struct hdmi_phy *phy, u32 reg, u32 va= lue) +{ + const int phy_txn_offset =3D REG_HDMI_ELIZA_PHY_TX1_CONTROL_0 - REG_HDMI_= ELIZA_PHY_TX0_CONTROL_0; + int i; + + for (i =3D 0; i < HDMI_PHY_TXN_CONTROL; i++) + hdmi_phy_write(phy, reg + i * phy_txn_offset, value); +} + +static void hdmi_eliza_phy_txn_update(struct hdmi_phy *phy, u32 reg, u32 m= ask, u32 value) +{ + const int phy_txn_offset =3D REG_HDMI_ELIZA_PHY_TX1_CONTROL_0 - REG_HDMI_= ELIZA_PHY_TX0_CONTROL_0; + int i; + + for (i =3D 0; i < HDMI_PHY_TXN_CONTROL; i++) + hdmi_phy_update_bits(phy, reg + i * phy_txn_offset, mask, value); +} + +static void hdmi_eliza_phy_configure(struct hdmi_phy *phy) +{ + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_8, BIT(2), = BIT(2)); + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_TX_COMMON_CONTROL_0, BIT(0),= BIT(0)); + + usleep_range(5, 5000); + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_REFCLK_CONTROL_0, BIT(0), BI= T(0)); + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_REFCLK_CONTROL_1, GENMASK(2,= 0), 0x1); + /* Select MPLLB */ + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_3, BIT(0), 0); + + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_11, 0x18); + /* + * MPLLB_CONTROL_12: missing in programming sequence, but present in + * downstream + */ + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_12, 0x12); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_13, 0x18); + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MPLLB_CONTROL_16, BIT(1), BI= T(1)); + /* + * MISC_CONTROL_2: missing in programming sequence, but present in + * downstream + */ + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_2, 0x4d); +} + +static void hdmi_eliza_phy_tx_lane_config(struct hdmi_phy *phy, + unsigned long pixclock) +{ + const unsigned int bpp =3D 24; + + /* Set BIT(3) for MPLLB and clear BIT(0) */ + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_8, BIT(0) |= BIT(3), BIT(3)); + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_9, BIT(0) |= BIT(1) | BIT(2), 0); + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_10, BIT(4) = | BIT(5), BIT(4) | BIT(5)); + + hdmi_eliza_phy_txn_write(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_7, 0); + hdmi_eliza_phy_txn_write(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_6, 0); + hdmi_eliza_phy_txn_write(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_5, 0x3e); + + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_10, BIT(3),= 0); + + if (pixclock * bpp >=3D HDMI_PHY_MAX_BIT_RATE) + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_TX_COMMON_CONTROL_0, BIT(2)= , 0); + else + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_TX_COMMON_CONTROL_0, BIT(2)= , BIT(2)); + + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_9, BIT(3) |= BIT(4), BIT(3) | BIT(4)); +} + +static void hdmi_eliza_phy_disable_hstx_reset(struct hdmi_phy *phy) +{ + hdmi_eliza_phy_txn_write(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_0, 0); + + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_RX1_CONFIG_15, 0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_RX2_CONFIG_15, 0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_REXT_CONTROL_2, 0); +} + +static int hdmi_eliza_phy_ready_poll(struct hdmi_phy *phy, u32 reg, u32 ma= sk, u32 val) +{ + u32 state; + const u32 sleep_us =3D 2000; + const u32 timeout_us =3D 3000000; + + if (readl_poll_timeout_atomic((phy->mmio + reg), state, + ((state & mask) =3D=3D val), + sleep_us, timeout_us)) { + DRM_ERROR("poll timeout, reg: 0x%x status=3D0x%x", reg, state); + + return -ETIMEDOUT; + } + + return 0; +} + +static int hdmi_eliza_phy_tx_ready_poll(struct hdmi_phy *phy) +{ + const int phy_txn_offset =3D REG_HDMI_ELIZA_PHY_TX1_CONTROL_0 - REG_HDMI_= ELIZA_PHY_TX0_CONTROL_0; + int ret =3D 0; + + /* Poll until TXn_ACK=3D=3D0, downstream is wrong here */ + for (int i =3D 0; i < HDMI_PHY_TXN_CONTROL; i++) { + ret |=3D hdmi_eliza_phy_ready_poll(phy, + REG_HDMI_ELIZA_PHY_TX0_CONTROL_2 + i * phy_txn_offset, + BIT(0), 0x0); + if (ret) + break; + } + + return ret; +} + +static int hdmi_eliza_phy_sram_init(struct hdmi_phy *phy) +{ + int ret; + + ret =3D hdmi_eliza_phy_ready_poll(phy, REG_HDMI_ELIZA_PHY_SRAM_CONTROL_1,= BIT(0), BIT(0)); + if (ret) + return ret; + + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ADDRESS_LSB, 0x3); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ADDRESS_MSB, 0xe0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_WRDATA_LSB, 0x18); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_WRDATA_MSB, 0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ACCESS_CMD, 0x3); + ndelay(400); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ACCESS_CMD, 0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ADDRESS_LSB, 0x5); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ADDRESS_MSB, 0x90); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_WRDATA_LSB, 0xc); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_WRDATA_MSB, 0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ACCESS_CMD, 0x3); + ndelay(400); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ACCESS_CMD, 0x0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_0, 0x7); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ADDRESS_LSB, 0x1a); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ADDRESS_MSB, 0xe0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_WRDATA_LSB, 0xa0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_WRDATA_MSB, 0); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ACCESS_CMD, 0x3); + ndelay(400); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_CR_ACCESS_CMD, 0); + + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_SRAM_CONTROL_0, + BIT(1), BIT(1)); + + return 0; +} + +static void hdmi_eliza_phy_init(struct hdmi_phy *phy, + unsigned long pixclock) +{ + + /* pa_iso_disable() */ + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_3, + BIT(1) | BIT(2) | BIT(3), 0); + + /* sw_reset() */ + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_RESET_CONTROL_0, 0x1); + + /* assert_tx_lane_reset() */ + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_9, BIT(5), = BIT(5)); + + /* phy_init_config() */ + hdmi_eliza_phy_configure(phy); + + hdmi_eliza_phy_tx_lane_config(phy, pixclock); + + hdmi_eliza_pll_configure_pll(phy->pll, 396000000, 19200000); + + /* sram_mode() (with SRAM init) */ + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_SRAM_CONTROL_0, + BIT(0) | BIT(1), 0); + /* qcsram_init() */ + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_QCSRAM_CONFIG_3, BIT(0)); + usleep_range(5, 5000); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_QCSRAM_CONFIG_3, 0); + + /* deassert_tx_lane_reset() */ + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_9, BIT(5), = 0); + + hdmi_eliza_phy_disable_hstx_reset(phy); + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_RESET_CONTROL_0, 0); + + if (hdmi_eliza_phy_sram_init(phy)) + return; + + if (hdmi_eliza_phy_tx_ready_poll(phy)) + return; +}; + +static void hdmi_eliza_phy_powerup(struct hdmi_phy *phy, + unsigned long pixclock) +{ + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_TX_COMMON_CONTROL_0, BIT(1),= BIT(1)); +} + +static void hdmi_eliza_phy_deinit(struct hdmi_phy *phy) +{ + /* sw_reset() */ + hdmi_phy_write(phy, REG_HDMI_ELIZA_PHY_RESET_CONTROL_0, 1); + hdmi_eliza_phy_txn_write(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_0, 1); + /* assert_tx_lane_reset() */ + hdmi_eliza_phy_txn_update(phy, REG_HDMI_ELIZA_PHY_TX0_CONTROL_9, BIT(5), = BIT(5)); + /* pa_iso_enable() */ + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_MISC_CONTROL_3, + BIT(1) | BIT(2) | BIT(3), BIT(1) | BIT(2) | BIT(3)); +} + +static void hdmi_eliza_phy_powerdown(struct hdmi_phy *phy) +{ + hdmi_phy_update_bits(phy, REG_HDMI_ELIZA_PHY_TX_COMMON_CONTROL_0, BIT(1),= 0); +} + +const struct hdmi_phy_cfg msm_hdmi_phy_eliza_cfg =3D { + .type =3D MSM_HDMI_PHY_ELIZA, + .init =3D hdmi_eliza_phy_init, + .deinit =3D hdmi_eliza_phy_deinit, + .powerup =3D hdmi_eliza_phy_powerup, + .powerdown =3D hdmi_eliza_phy_powerdown, + .clk_names =3D hdmi_phy_eliza_clk_names, + .num_clks =3D ARRAY_SIZE(hdmi_phy_eliza_clk_names), +}; diff --git a/drivers/gpu/drm/msm/registers/display/hdmi.xml b/drivers/gpu/d= rm/msm/registers/display/hdmi.xml index 0ebb96297dae..4afc36fef172 100644 --- a/drivers/gpu/drm/msm/registers/display/hdmi.xml +++ b/drivers/gpu/drm/msm/registers/display/hdmi.xml @@ -1101,4 +1101,144 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.or= g/freedreno/ rules-fd.xsd"> =20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.53.0 From nobody Sat Sep 26 23:03:46 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 045BD47045C for ; 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Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/eliza.dtsi | 94 +++++++++++++++++++++++++++++++++= +++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom= /eliza.dtsi index 66ea4aaafd73..27dd15766f51 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -2570,7 +2570,14 @@ dpu_intf0_out: endpoint { remote-endpoint =3D <&mdss_dp0_in>; }; }; - /* TODO: HDMI */ + + port@3 { + reg =3D <3>; + + dpu_intf4_out: endpoint { + remote-endpoint =3D <&mdss_hdmi_in>; + }; + }; }; =20 mdp_opp_table: opp-table { @@ -2805,6 +2812,89 @@ mdss_dsi1_phy: phy@ae97000 { status =3D "disabled"; }; =20 + mdss_hdmi: hdmi@aea0000 { + compatible =3D "qcom,eliza-hdmi-tx"; + reg =3D <0x0 0x0aea0000 0x0 0x1000>, + <0x0 0x0aee0000 0x0 0x1000>; + reg-names =3D "core_physical", + "hdcp_physical"; + + interrupts-extended =3D <&mdss 8>; + + clocks =3D <&dispcc DISP_CC_MDSS_HDMI_AHBM_CLK>, + <&dispcc DISP_CC_MDSS_HDMI_APP_CLK>, + <&dispcc DISP_CC_MDSS_HDMI_PCLK_CLK>, + <&dispcc DISP_CC_MDSS_HDMI_INTF_CLK>, + <&mdss_hdmi_phy>, + <&dispcc DISP_CC_MDSS_HDMI_PCLK_CLK_SRC>; + clock-names =3D "iface", + "core", + "extp", + "phy_iface", + "pll", + "pixel_src"; + + operating-points-v2 =3D <&mdss_hdmi_opp_table>; + + phys =3D <&mdss_hdmi_phy>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + #sound-dai-cells =3D <1>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_hdmi_in: endpoint { + remote-endpoint =3D <&dpu_intf4_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_hdmi_out: endpoint { + }; + }; + }; + + mdss_hdmi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-150000000 { + opp-hz =3D /bits/ 64 <150000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + }; + + mdss_hdmi_phy: phy@aea1000 { + compatible =3D "qcom,eliza-hdmi-phy"; + reg =3D <0x0 0x0aea1000 0x0 0x1000>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_HDMI_CLKREF_EN>, + <&bi_tcxo_div2>; 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Add the first one, with the 5V power supply. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 103 ++++++++++++++++++++++++++++= ++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/= qcom/eliza-evk.dtsi index 2fc945658300..533d52ecaacb 100644 --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi @@ -12,6 +12,29 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + hdmi_5p0_reg: regulator-hdmi-5v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "hdmi_5p0"; + + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&tlmm 184 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 =3D <&hdmi_5p0_state>; + pinctrl-names =3D "default"; + }; + + hdmi-0-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_0_connector_in: endpoint { + remote-endpoint =3D <&mdss_hdmi_out>; + }; + }; + }; + pmic-glink { compatible =3D "qcom,eliza-pmic-glink", "qcom,sm8550-pmic-glink", @@ -51,6 +74,34 @@ pmic_glink_ss_in: endpoint { }; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_hdmi { + pinctrl-0 =3D <&hdmi_ddc_default>, + <&hdmi_cec_active>, + <&hdmi_hpd_active>; + pinctrl-1 =3D <&hdmi_ddc_default>, + <&hdmi_cec_sleep>, + <&hdmi_hpd_sleep>; + pinctrl-names =3D "default", "sleep"; + + core-vcc-supply =3D <&vreg_l2b>; + core-vdda-supply =3D <&vreg_l4b>; + vddio-supply =3D <&hdmi_5p0_reg>; + + status =3D "okay"; +}; + +&mdss_hdmi_out { + remote-endpoint =3D <&hdmi_0_connector_in>; +}; + +&mdss_hdmi_phy { + status =3D "okay"; +}; + &pm7550ba_eusb2_repeater { vdd18-supply =3D <&vreg_l7b>; vdd3-supply =3D <&vreg_l17b>; @@ -70,11 +121,63 @@ &sdhc_2 { }; =20 &tlmm { + hdmi_ddc_default: hdmi-ddc-state { + hdmi-ddc-scl-pins { + pins =3D "gpio6"; + function =3D "hdmi_ddc_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hdmi-ddc-sda-pins { + pins =3D "gpio7"; + function =3D "hdmi_ddc_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + hdmi_cec_active: hdmi-cec-active-state { + pins =3D "gpio46"; + function =3D "hdmi_tx_cec"; + drive-strength =3D <16>; + bias-pull-up; + }; + + hdmi_cec_sleep: hdmi-cec-sleep-state { + pins =3D "gpio46"; + function =3D "hdmi_tx_cec"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hdmi_hpd_active: hdmi-hpd-active-state { + pins =3D "gpio47"; + function =3D "hdmi_hot_plug"; + drive-strength =3D <16>; + bias-pull-down; + }; + + hdmi_hpd_sleep: hdmi-hpd-sleep-state { + pins =3D "gpio47"; + function =3D "hdmi_hot_plug"; + drive-strength =3D <2>; + bias-pull-down; + }; + sd_cd: sd-cd-state { pins =3D "gpio58"; function =3D "gpio"; bias-pull-up; }; + + hdmi_5p0_state: hdmi-5p0-state { + pins =3D "gpio184"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + output-low; + }; }; =20 &uart13 { --=20 2.53.0