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Thu, 27 Aug 2026 03:57:44 -0700 (PDT) Received: from wenst-7875.tpe.corp.google.com ([2a00:79e0:201d:8:b7d8:fa42:587e:234d]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b186807bsm2434123a91.12.2026.08.27.03.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 03:57:43 -0700 (PDT) From: Chen-Yu Tsai To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , linux-pwm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jitao Shi Subject: [PATCH] pwm: mtk-disp: Fix period readback Date: Thu, 27 Aug 2026 18:57:36 +0800 Message-ID: <20260827105738.8570-1-wenst@chromium.org> X-Mailer: git-send-email 2.55.0.887.g758fc8c411-goog Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The period value stored in the register is the number of clock cycles - 1. Account for the offset when calculating the period in nanoseconds. This fixes the discrepancy reported by the pwm core when CONFIG_PWM_DEBUG=3D1: mediatek-disp-pwm 1100e000.pwm: .apply is not idempotent (ena=3D1 pol=3D0 281500/499875) -> (ena=3D1 pol=3D0 281500/499750) Calculation discrepancy in the driver was found by AI run by a colleague while debugging another PWM related issue. Check against SoC datasheet and fix done by the author. Fixes: 3f2b16734914 ("pwm: mtk-disp: Implement atomic API .get_state()") Cc: Jitao Shi Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao --- drivers/pwm/pwm-mtk-disp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index b5409e15dac8..68a4512e821a 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -212,7 +212,7 @@ static int mtk_disp_pwm_get_state(struct pwm_chip *chip, * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30, * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow. */ - state->period =3D DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SE= C, rate); + state->period =3D DIV64_U64_ROUND_UP((period + 1) * (clk_div + 1) * NSEC_= PER_SEC, rate); high_width =3D FIELD_GET(PWM_HIGH_WIDTH_MASK, con1); state->duty_cycle =3D DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSE= C_PER_SEC, rate); --=20 2.55.0.887.g758fc8c411-goog