From nobody Mon Sep 28 03:43:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F24C3EB7F4; Thu, 27 Aug 2026 08:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787820047; cv=none; b=Kh+mbUluyvn/NVIHxJp1hEKLl8I7ofiWdooFvf2+9V9lCV0wfLEERQk8IRybFN8drNEwHldBZKyysaoMJEfGjLYw5MYww4iR+Y6uIqZy6G8KKwb0tEGXfKrQNI4c4CnfL1OB/CGldEWg20LwD/s/qBTtiyqGdaR9jPTKVmE93+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787820047; c=relaxed/simple; bh=3+Z6/DMs03PTFoO3aAzzf6hsDxqMJ+xrrf+GTzL+F/M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n+fFNtwxkACRxQl/pWidP6Hz8g9sFR1Ig1yHuf8tRE41PT8uJFhdk8EaaonwVFsvRIYuVRgE9SbARUnyFUCizk9ZALDevxjkizxrrdwigkBPT3joEBhsBa+2YuIcJY5kE2c98wO3Bi+WzKGhiKIBarqNgJM2J2e+Rs9Ddvu/5JA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eNX2cryq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eNX2cryq" Received: by smtp.kernel.org (Postfix) with ESMTPS id AF800C19425; Thu, 27 Aug 2026 08:40:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787820046; bh=3+Z6/DMs03PTFoO3aAzzf6hsDxqMJ+xrrf+GTzL+F/M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eNX2cryq9egT0r/z9CNx+UtpSTSXKuJxP3Rheq008FHOwKdYt2/AexBvvSY78HSZa o+iY6hjRubabChPCcqgeKi82cifpUYB6AWK8ATX+jI+/CxneNptW8Co5MOI1m4Y9vj e/Jz9+caoVl4yVfVt4w15N0QPbJMMcrkOB1M7+B70Hy/cuxo2peZeQ/4D686P4LLsF b5U4kCsoKpHLAjoyjKmD4TCdYAM1CnuZtTsKRUTjyer5cNrFgC4EuSr76mJmnpETC+ A8YDm9lsJ4A+burKQ6BmYn3bUMX0iOfWDmPJQ7Ec7shPjzppjoFG/1BPzclOyJOWbr 2xaShb8CUSqhw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D995C61DC2; Thu, 27 Aug 2026 08:40:46 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 27 Aug 2026 08:40:10 +0000 Subject: [PATCH v4 1/4] dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-s6-s7-pwm-v4-1-d28a2015177d@amlogic.com> References: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> In-Reply-To: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao , Junyi Zhao , Krzysztof Kozlowski , Alexandre Mergnat X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787820043; l=1867; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=EyhN/nBz1aGm3bA756eZeqYpc8GpJGOBSwKy4zTbe6s=; b=B2iCcJhThtx4DRKaVM7MoG+W41W+eDfX3FjdGcR9cCwGar9tjh55GmMWHe8ZWzPnL6BzxpWmW foWDyl/oWeQCnSGdbFKO7oYSFjtbRG7YCWltt6XwL6hhNBZ3dHumImR X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Junyi Zhao Amlogic S7/S7D/S6 different from the previous SoCs, a controller includes one pwm, at the same time, the controller has only one input clock source. Signed-off-by: Junyi Zhao Reviewed-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Reviewed-by: Alexandre Mergnat Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 19 +++++++++++++++= ++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Docum= entation/devicetree/bindings/pwm/pwm-amlogic.yaml index c337d85da40f..93fa97f4011b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -37,6 +37,7 @@ properties: - enum: - amlogic,meson8-pwm-v2 - amlogic,meson-s4-pwm + - amlogic,s7-pwm - items: - enum: - amlogic,a4-pwm @@ -45,6 +46,11 @@ properties: - amlogic,t7-pwm - amlogic,meson-a1-pwm - const: amlogic,meson-s4-pwm + - items: + - enum: + - amlogic,s6-pwm + - amlogic,s7d-pwm + - const: amlogic,s7-pwm - items: - enum: - amlogic,meson8b-pwm-v2 @@ -146,6 +152,19 @@ allOf: clock-names: false required: - clocks + - if: + properties: + compatible: + contains: + enum: + - amlogic,s7-pwm + then: + properties: + clocks: + maxItems: 1 + clock-names: false + required: + - clocks =20 - if: properties: --=20 2.52.0 From nobody Mon Sep 28 03:43:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 411373EC2CD; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-s6-s7-pwm-v4-2-d28a2015177d@amlogic.com> References: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> In-Reply-To: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787820043; l=4621; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=XWBLCai/fzPSLXT+rV6gvMmqDHi7OFZogDsuyVzW6gk=; b=Rh9OjEOD7SNxnECzTQEmrJSTchFP5bhVfta+X6y2sVbP3EbhfJ6CZfSi1WkgC2qIsCwNZv0rq Z1YyvX/Xj/fCH3vrsAFgdZ5vcf9hEZiU/0sVB4IXqNQ7PoIEkRdXils X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add .npwm fill the existing entries, use it in probe, and switch the loop in meson_pwm_init_clocks_meson8b() and meson_pwm_init_channels_s4() to chip->npwm. No functional change. Signed-off-by: Xianwei Zhao Reviewed-by: Alexandre Mergnat --- drivers/pwm/pwm-meson.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 8c6bf3d49753..22cefc6d5dd0 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -113,6 +113,7 @@ struct meson_pwm_data { int (*channels_init)(struct pwm_chip *chip); bool has_constant; bool has_polarity; + u8 npwm; }; =20 struct meson_pwm { @@ -382,7 +383,7 @@ static int meson_pwm_init_clocks_meson8b(struct pwm_chi= p *chip, char name[255]; int err; =20 - for (i =3D 0; i < MESON_NUM_PWMS; i++) { + for (i =3D 0; i < chip->npwm; i++) { struct meson_pwm_channel *channel =3D &meson->channels[i]; struct clk_parent_data div_parent =3D {}, gate_parent =3D {}; struct clk_init_data init =3D {}; @@ -510,7 +511,7 @@ static int meson_pwm_init_channels_s4(struct pwm_chip *= chip) struct meson_pwm *meson =3D to_meson_pwm(chip); int i, ret; =20 - for (i =3D 0; i < MESON_NUM_PWMS; i++) { + for (i =3D 0; i < chip->npwm; i++) { meson->channels[i].clk =3D of_clk_get(np, i); if (IS_ERR(meson->channels[i].clk)) return dev_err_probe(dev, @@ -530,6 +531,7 @@ static int meson_pwm_init_channels_s4(struct pwm_chip *= chip) static const struct meson_pwm_data pwm_meson8b_data =3D { .parent_names =3D { "xtal", NULL, "fclk_div4", "fclk_div3" }, .channels_init =3D meson_pwm_init_channels_meson8b_legacy, + .npwm =3D 2, }; =20 /* @@ -539,6 +541,7 @@ static const struct meson_pwm_data pwm_meson8b_data =3D= { static const struct meson_pwm_data pwm_gxbb_ao_data =3D { .parent_names =3D { "xtal", "clk81", NULL, NULL }, .channels_init =3D meson_pwm_init_channels_meson8b_legacy, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_axg_ee_data =3D { @@ -546,6 +549,7 @@ static const struct meson_pwm_data pwm_axg_ee_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_axg_ao_data =3D { @@ -553,6 +557,7 @@ static const struct meson_pwm_data pwm_axg_ao_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_g12a_ee_data =3D { @@ -560,6 +565,7 @@ static const struct meson_pwm_data pwm_g12a_ee_data =3D= { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { @@ -567,6 +573,7 @@ static const struct meson_pwm_data pwm_g12a_ao_ab_data = =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { @@ -574,22 +581,26 @@ static const struct meson_pwm_data pwm_g12a_ao_cd_dat= a =3D { .channels_init =3D meson_pwm_init_channels_meson8b_legacy, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_meson8_v2_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_v2, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_meson_axg_v2_data =3D { .channels_init =3D meson_pwm_init_channels_meson8b_v2, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D 2, }; =20 static const struct meson_pwm_data pwm_s4_data =3D { .channels_init =3D meson_pwm_init_channels_s4, .has_constant =3D true, .has_polarity =3D true, + .npwm =3D 2, }; =20 static const struct of_device_id meson_pwm_matches[] =3D { @@ -650,9 +661,10 @@ static int meson_pwm_probe(struct platform_device *pde= v) { struct pwm_chip *chip; struct meson_pwm *meson; + const struct meson_pwm_data *pdata =3D of_device_get_match_data(&pdev->de= v); int err; =20 - chip =3D devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson)); + chip =3D devm_pwmchip_alloc(&pdev->dev, pdata->npwm, sizeof(*meson)); if (IS_ERR(chip)) return PTR_ERR(chip); meson =3D to_meson_pwm(chip); @@ -664,7 +676,7 @@ static int meson_pwm_probe(struct platform_device *pdev) spin_lock_init(&meson->lock); chip->ops =3D &meson_pwm_ops; =20 - meson->data =3D of_device_get_match_data(&pdev->dev); + meson->data =3D pdata; =20 err =3D meson->data->channels_init(chip); if (err < 0) --=20 2.52.0 From nobody Mon Sep 28 03:43:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E3A73EC803; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-s6-s7-pwm-v4-3-d28a2015177d@amlogic.com> References: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> In-Reply-To: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787820043; l=2584; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=I6lbpR1bOMmChsZo3uQ/k/8BNNbhwj3qLcmflQoEjK8=; b=j1659NKbIuXJqxgowGvB/TkkqxEEPFicBgqlHDxBXEX9bMCN9fRiQx9seZz5ofywGTUY37R5K 0EH1aPdXWnQBkszh56C7j+op9cREnOXfODis0Hj3utlZ1eD5vzSxP3i X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The S4 PWM driver currently gets each channel clock individually with of_clk_get() and uses a custom cleanup action to release the clocks. Use devm_clk_bulk_get_all() instead to retrieve all per-channel clocks at once. Verify that the number of clocks matches the number of PWM channels and assign each clock to its corresponding channel. This also allows the per-channel clock initialization code to be shared by Meson PWM variants using one clock per channel. Signed-off-by: Xianwei Zhao Reviewed-by: Alexandre Mergnat --- drivers/pwm/pwm-meson.c | 40 ++++++++++++++++------------------------ 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 22cefc6d5dd0..6f151464d7cc 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -497,33 +497,25 @@ static int meson_pwm_init_channels_meson8b_v2(struct = pwm_chip *chip) return meson_pwm_init_clocks_meson8b(chip, mux_parent_data); } =20 -static void meson_pwm_s4_put_clk(void *data) -{ - struct clk *clk =3D data; - - clk_put(clk); -} - -static int meson_pwm_init_channels_s4(struct pwm_chip *chip) +static int meson_pwm_init_channels_per_channel_clk(struct pwm_chip *chip) { struct device *dev =3D pwmchip_parent(chip); - struct device_node *np =3D dev->of_node; struct meson_pwm *meson =3D to_meson_pwm(chip); - int i, ret; + struct clk_bulk_data *clks; + unsigned int i; + int num; =20 - for (i =3D 0; i < chip->npwm; i++) { - meson->channels[i].clk =3D of_clk_get(np, i); - if (IS_ERR(meson->channels[i].clk)) - return dev_err_probe(dev, - PTR_ERR(meson->channels[i].clk), - "Failed to get clk\n"); - - ret =3D devm_add_action_or_reset(dev, meson_pwm_s4_put_clk, - meson->channels[i].clk); - if (ret) - return dev_err_probe(dev, ret, - "Failed to add clk_put action\n"); - } + num =3D devm_clk_bulk_get_all(dev, &clks); + if (num < 0) + return dev_err_probe(dev, num, "Failed to get clocks\n"); + + if (num !=3D chip->npwm) + return dev_err_probe(dev, -EINVAL, + "expected %u clocks, got %d\n", + chip->npwm, num); + + for (i =3D 0; i < chip->npwm; i++) + meson->channels[i].clk =3D clks[i].clk; =20 return 0; } @@ -597,7 +589,7 @@ static const struct meson_pwm_data pwm_meson_axg_v2_dat= a =3D { }; =20 static const struct meson_pwm_data pwm_s4_data =3D { - .channels_init =3D meson_pwm_init_channels_s4, + .channels_init =3D meson_pwm_init_channels_per_channel_clk, .has_constant =3D true, .has_polarity =3D true, .npwm =3D 2, --=20 2.52.0 From nobody Mon Sep 28 03:43:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 540F03EDAB5; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-s6-s7-pwm-v4-4-d28a2015177d@amlogic.com> References: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> In-Reply-To: <20260827-s6-s7-pwm-v4-0-d28a2015177d@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787820043; l=1273; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=bxanl4T1hd21Hw06PnQXj6xGMQbU+zReu1OrHg7McSk=; b=0vaQo/fBgbLRHzWKS3mXgLiyVajPMUz9dbrbZVd3jjmB/2F56tL5Ry9j/ENdIlQL/PLCowQAm P2g2nAg4w+RBIldLTwsxHkfgwYiA7ukj3SBodgsTJ8I/HNKY0pwBTxL X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add support for Amlogic S7 PWM. Amlogic S7 different from the previous SoCs, a controller includes one pwm, at the same time,the controller has only one input clock source. Also use the kernel coding style for the empty of_device_id terminator. Signed-off-by: Xianwei Zhao Reviewed-by: Alexandre Mergnat --- drivers/pwm/pwm-meson.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 6f151464d7cc..2da958231719 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -595,6 +595,13 @@ static const struct meson_pwm_data pwm_s4_data =3D { .npwm =3D 2, }; =20 +static const struct meson_pwm_data pwm_s7_data =3D { + .channels_init =3D meson_pwm_init_channels_per_channel_clk, + .has_constant =3D true, + .has_polarity =3D true, + .npwm =3D 1, +}; + static const struct of_device_id meson_pwm_matches[] =3D { { .compatible =3D "amlogic,meson8-pwm-v2", @@ -645,7 +652,11 @@ static const struct of_device_id meson_pwm_matches[] = =3D { .compatible =3D "amlogic,meson-s4-pwm", .data =3D &pwm_s4_data }, - {}, + { + .compatible =3D "amlogic,s7-pwm", + .data =3D &pwm_s7_data + }, + { } }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); =20 --=20 2.52.0