From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 881AF19CC14 for ; Thu, 27 Aug 2026 17:51:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853090; cv=none; b=kbtu/TiSTikPMoJpJQY0NAJByZfTNJauf3+hp0nF2NZth/xoJ4ckD3jg3lw833dUVPr/svknKpCZVuSKtswzavEeCJNZcC0iwDRXnWERvAFzTbPSW5hsEZ9soYW+yua7iassSS1rQpxvSvfIAu3jsU+19DNNFvT+N0dSgjCcPu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853090; c=relaxed/simple; bh=iY6li1N8aOWymAjX+i7+r5/1IUwgJvmB/19fYvr8jWE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PoYpG/d0/QbfUGTe+qgTrP9QR2/Oz2cfIifdLQs9eZekgirV3pPs5q0M3TVIFuycWvMm4ykWLPq3Tgy5uNd+wKLdtP2/mQ90aUGV/0EuXGYuOOf7Cn4FVRZwO3NDRc6XzlnKlJIq3BGPtofOkR1QcTJojSeXkxg/3RcpHU4Zm20= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Y3AgYA0R; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=hbd8h9zu; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Y3AgYA0R"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="hbd8h9zu" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXjMW000731 for ; Thu, 27 Aug 2026 17:51:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jxfq3sde3/UWkYHQSyS+xk+eWHWNfmqXAOsgq3B6bQk=; b=Y3AgYA0R+YWLTJHV Bq/ckoqpNGdWK2Ttu8lSuK+D7x2nGLU8JKFm/5jeiUrV2rC+YfDU4uJxRmjKaNVJ MbszMVA4hRAaycunghcsMHaLCY4MR+h2p6cVlNGQ03+uqFufDXOQILmU+7IRDpWK khH+YytFiUZEwBZFpniNS3VvPBCGjDDzUkyCZYaXZpuaCUcdUpqHo9oeqMZKZ8ib Rgj9DCHJTe04xo6cwkNxddZgGigGHePjlh9ihRa8ByQJgpTVgM3evALju8FdKczk ONfnXDlbU9fvA+kL99Fbc3873D4cG9dNloO34anG4L1wl02axUFC6xegIX/Agi16 uc9gzw== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ga6etvse5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:51:28 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-cc1d85c012dso233459a12.2 for ; Thu, 27 Aug 2026 10:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853088; x=1788457888; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=jxfq3sde3/UWkYHQSyS+xk+eWHWNfmqXAOsgq3B6bQk=; b=hbd8h9zu3Wasj7FUYAhf6DyQiWm3NAhnmGTM4i4BeR6LmsLbbSMmzvXC/eg0ow4/QO YfHGpbidXgfkVAWyUMamXOD3/ZtzuHKNqZnzycgUPOAFM/9j4X2hhlGPn56s++le49W4 /kT2+zGctoBDrJh4sQ8EA1fhHp0Aqomj66rAKam3WHYRSy0FcSD8exVqHoBFC+oc9GXI 8rMPViY4XGL2TIpn9x1QlJ/yrxF7e/bRxlKeZSAkKqwVal+7eqr+5kXrJsR0ggBNjwA+ BF3CvrRWfOvVn9AwRwd/oGdwTMSjUeRs7Ja83P8lYfUobzy5R8SLEijyM2gmCHbY9osA jrOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853088; x=1788457888; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=jxfq3sde3/UWkYHQSyS+xk+eWHWNfmqXAOsgq3B6bQk=; b=MvShQikVQnu2Qc6q577kbf5e8tGLSXjQWxbmd4Y0MgRPU97vqSl0Gl0ZwSPFNYXabZ to7QLq9sdtat0/v5OYz3IeQZp4FVd/gUNOqdUxUBQWwhVfbi4iqUtfWr6vQPM/EKUU+z 8xvNB8RVtzU6vL0ajyJkX3FzxRZi4fxBJyeTPN7YzavApe4kajZW0iPhoyMN+BwHaoW7 k7UaK1q2AeDZ8FVcEwIxpvHOohkRE8S4K6GVzL7IxzAVpv3Q8U24/+8KH7PmhM1P/1n+ 6iHI13RPjMjX0I+pyhyql0M7qe12iH/rEpkkH3rv3jrtA5gPqOi7ZaLnXDwQelWyq485 xIUg== X-Forwarded-Encrypted: i=1; AHgh+RqaNDvhp3vzh1FZ3cwRUx1fEcL0CKnc/7fd4bCpv7SSfGqaC56ejoOKMkHKKEOt0UAFNKPSNCO2pA9GcQA=@vger.kernel.org X-Gm-Message-State: AFuF++l2P/2FEW+yhPNznsov4VWSTpkZN8hsHqGYiSysPYVzMxOYcUa6 LgSJM3S5TiG/vPZw34ndVFk3eDxwCwFC/chagAzhuBfdo11xNmzLqJTZRLGb13Gu2fM7K4dWZ9F nwvZBIKU19GD0LotSxrELuKsGv4oNEAf5P9XsBkP/DtiqT9N9I7UNIhF/kMNc2tjubxs= X-Gm-Gg: AR+sD10IqnbW1D/VM+fkeads6eSNkpZuO21cKQtTu/oPy1nnEj9Pf0KWfdUdy7xrzhr EGhyyGMP7+AlKNLJdHwwdFts98zWmIgqSU5rWX+0LKf6KzTeCdg0fWyY3VHEwvi6zXtcaH/TJ5c FnhCVuOLqgwEL3YgoUgkn7mHU9sfezyk1dBP6ZJOyJK+0XhBv/9pxUf5Vdn0+Dq2DSzk6Ta2RDX sW/uNxsOi7tNShIYq+WizFD5yXud2tbszUPjnkFh8TuZdzuHBQUoJJplusRPuPEoMDF5KWhXroQ NuyClgVuZoKfL5KYMhQHf8p1bD0vAagyOgszt6t5FoLV1axHUERVH4MbDumTsUQ7q5gRHBRfNPi Cb2VfhgD+5aKh/AOBgiusK4vSIzv5sEm2zHuivczIVqjHAefWjd6hJzZr3IAq9MrEtD+YOZV2K5 JW0tm7jXVVO5tNHkJkHoehsAE= X-Received: by 2002:a05:6300:67c8:b0:3b4:7e2d:a3c2 with SMTP id adf61e73a8af0-3d269519f70mr1365599637.18.1787853087947; Thu, 27 Aug 2026 10:51:27 -0700 (PDT) X-Received: by 2002:a05:6300:67c8:b0:3b4:7e2d:a3c2 with SMTP id adf61e73a8af0-3d269519f70mr1365493637.18.1787853087471; Thu, 27 Aug 2026 10:51:27 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:51:27 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:04 +0530 Subject: [PATCH v5 01/15] soc: qcom: geni-se: allow selection on 32-bit ARM Qualcomm SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-1-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Mukesh Savaliya , Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=1026; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=iY6li1N8aOWymAjX+i7+r5/1IUwgJvmB/19fYvr8jWE=; b=aHAflXlP1yHXGFZJprnZ1WdCMs9h3s8lcsyK93pEvfx6jZpxExN02LtDY/m8J+rWWBNQyfJWV Z6kTXnWAb7XD0B7JqZJqGp21mffzM2wgOR4TI10aG/oBKL4c+4jXQ3D X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Authority-Analysis: v=2.4 cv=NrThtcdJ c=1 sm=1 tr=0 ts=6a907920 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=I-wlBW6BsxmxmlAWD-0A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: s9BoxIOqvGXAjofphCEtZL87PC7NzDZO X-Proofpoint-GUID: s9BoxIOqvGXAjofphCEtZL87PC7NzDZO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MCBTYWx0ZWRfXzSAqQF1WP0iA BFttxGM4puUygktJ5JG7EgMknTMVGUkHSmbxHbznQWZqKh2dkof4DPqi6x23PeDQn12MZvQe9zX o9QiiOmRkWPRVWVQKwLn923rMvROld+BFGpQSQYXcsBN9ZixfxG15xwKXUd6C+TdUZ4t9NgXmij +xGyAK0nsin0XiIPp7wcNAWUgvl74I7BO+L/FqMGnQIIF1Bpurzj+4gC3xn1HEdgVL7dyuQwkIL dC3XZ9bHaCAMraws3MB9DfxIKUgMrJgb2ACG+qKn42G/7hrdQjXF7GEf53+7vdfw/FrCbDudu2F 1/00mCJt19sjdKjOsL3y0z9ofC/a8LCgwwXILw9SnicpnAuwLV/WFUlySphMtADGt1STGharuU2 7Cxnr6XnIn0MK16x8j0WEAaLveW/QNayK1rIHbrjWWmNjWENHrk1TqAXmp8GYbmR/SzzFT706/9 BDy/NAe90Q8pCztn35g== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MCBTYWx0ZWRfX7AHpqOpzDbhT fU59WhtACONQ5v04joAl8pIgKkWX05Vm18DnTxAsG0bYvAwfAPdUnyO9ZGzxylSjuEptD8nLKkh mD4BLljVLIFGePFUZwwokMk2IEkE2Gw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270150 Kuno, a 32-bit ARM Cortex-A7 Qualcomm SoC, uses the GENI-based QUP wrapper for its debug UART. Drop the explicit ARM64 dependency so the driver can be selected on 32-bit ARM as well; QCOM_GENI_SE already sits under the QCOM_SOC menuconfig, which is gated by ARCH_QCOM || COMPILE_TEST, so no replacement dependency is needed. Acked-by: Mukesh Savaliya Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/soc/qcom/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 2b524154d9fb..9f703261d7ac 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -39,7 +39,6 @@ config QCOM_COMMAND_DB =20 config QCOM_GENI_SE tristate "Qualcomm GENI Serial Engine Driver" - depends on ARM64 || COMPILE_TEST default ARCH_QCOM help This driver is used to manage Generic Interface (GENI) firmware based --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B4123E5A35 for ; Thu, 27 Aug 2026 17:51:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853101; cv=none; b=RMnHcI/nBq7LGkZgg66l6XcSUU/Cjm9kS+qA5AZw1R662TdE7CFvggFL/Sxc9uNYo+Zm/fLjLUg0Hdn17h2dy9pGkjGB8fAeJSj9csK1osmslCTg4xFl8fxbpJhxhdNotbR9Mxsx5PDGkyctPdKzmNhfOXSXxH9EvLkjmh7h6q8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853101; c=relaxed/simple; bh=ZHsN8zM/JbhignLDIxWKpOEJ0dJLsvtVmGGylPc0eUU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=leMyj97rAsCLeABrMJo2gpM4Xaq5EHxrd7wJUu5qK63IYC+QGYop1pjgaYNo4vXSfnhL/H7F/lSAXmW2Y3uH0puziKXzqeT8KSNofl4EaTxdgLcYT/2cddwvqUZ9tXWZKccTO4YX3Zt5w6IAV8l9QIDXxuIYq2OWPwifTqQJjXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Zu220O01; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=FGbfvHU6; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Zu220O01"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="FGbfvHU6" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXdQ6313756 for ; Thu, 27 Aug 2026 17:51:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= tKKYzTTyUQNx49FteOTvUbeUFOC22ARPMGkTLmOUYjE=; b=Zu220O01n5yJNHX5 ySNhJyILhSpvi7mx53R3ja2RAMxFAAyh0WET2xjnoMBnNZMZziK09Rnwvvsypy/o DCqfCeKDCb21BWS1Fknfyk6WtYfTaS6YG1+yy9nIBdlxKbnqTPteYujtBBaaAiQu e6x7PwmPYrQVWGuxq6gHdb4tJgrphRNfzjfH4CaPB7pPDMI0pjn3+KyyvTj204bX u+9y805bwL1jRuMLN801CmC7mbeWdD9D9qYbDKadhPvEZ0oXcHPdgU9esRbg4rHX Ovb8ABQX1r6DRL2/sgDS2GOqzLUe3K1rc/mDtIRqoaCud4eCP+UhO2g/i8/Wgl/K PW/qHw== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gak561uc1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:51:37 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-38f97b3f853so301311a91.3 for ; Thu, 27 Aug 2026 10:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853096; x=1788457896; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=tKKYzTTyUQNx49FteOTvUbeUFOC22ARPMGkTLmOUYjE=; b=FGbfvHU6PN2aMlI67zU5m9IPSlPWWH+4MPhu23fWjzpu1zMJU1MnMiaqWrv22YUyo9 Tj3ytE5FR13o+663T4m6AQXBs0B7K1+jOs55tRr6IlGW29yAQ3gDm1Juy5L/UvG86x9Q nCdKXzLq7DjoNeBeY8/JtFzKa7dq/qDZmEiz0MAjmGTgF0EjvqabKx7xPW0IfxqhE5bk duDZM/gn2UvVtS7/7vwbwS63HsweMrA6M/ruySVFvtKRSZgEby/kBW4hs0Horj6puxl9 zQH6WTjRA7JFN6KiVi7eD71lY2FrC8xYsOx2R6UdkjVu+8xKQx5V1+i9gSeNEHELWhS0 LH9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853096; x=1788457896; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=tKKYzTTyUQNx49FteOTvUbeUFOC22ARPMGkTLmOUYjE=; b=mZdsZF+ixhxyXfPIzfhPAYzuWsRh+ZEBmu8VGoLN1AouWAHfWVY/tgc+hNl3fyJ0K9 UXwvPMmLhZEUBSnFTyKgxrl0KTv+keOqpf6d5Spa7YwpLco2RbK7IoYzWsXuOhEgsiZK EfQLiNB9C3jO3jQb07KOmCUtSOd7irk7kl6YuNs4LB/UUNEKYOEXRC2svnf3DAc9XDTx rB1XSA97mhbx9guoIohdi6CuNrDgnY1pB+avDHzspxPAOBHwkjzTbdZ3NbprS63QAGNu fGAzJI8eOuXgnfjXr6HcnZESdT4g2F+6ORVWXD21upyDs6EPrPdAprjmATECneV6W52Q 131g== X-Forwarded-Encrypted: i=1; AHgh+RrzL8DNKXy0aH4NVRcBdqcdu8OrjvCNdWEDhxzKxSqOdEeJWNlJrePdB+zJ53va8YWUsiDfQhARqAIOGK4=@vger.kernel.org X-Gm-Message-State: AFuF++nCsiJCuqUsSfzchqG+GL+/b83vnrblGmV8fant7Z1eRnlfwoCE 65Ysus5ywFVb3vGe9SV1Volks1e0NM0q6/DpdM83o2+Ik9qkWv18EH+fSerwwxlmytNrVPzUVQc zXb/c9vqTovkQVHsmjqm8EpTqjH7gg3S4Nnm7NAcdb8gER5BDGpDl5XK37p8Z7HJ6sBo= X-Gm-Gg: AR+sD13En0U1IhQhhk+l5/ao/FGduvemqg7favmbrqyytOkcLjXUHTJ6+qYY7KhHVD+ 27vf5JcT8P1F2PbHj/A+Kk5npF5oZcnbzlBu4ur+/g7ZOLwUfOY3iIuw3dGhIMg8E5QQIl1wiEk nGY2Z55g8FgSwvE97MOXJqZEvdZCAGBriMWT5u//xTvUe07U96e7QdhusDfaEvz/Na3SRf+9hTJ 3mYrHdRoR4wi7HotoOhNfllsZRm8+nyipI53HbrMktLXBhTOO1TuYSwrMW09ycXFQzB9k3EvaiC 7pWmOJEQu7k929YczvOxMRuG6V81qkN4gl+zUJLBzcpk81ComR8+CmlKr+3py3UkeRo+GgpG/FT 4ov1WtHlv9HEObVDdSoelW0MzqRa3KLsUJ79xnHpXX4Wg/9CGRZKFWVIihvmGSUW8utrOqXg4rc /GiCjP7ZiUfbUSzL9Hoziueqo= X-Received: by 2002:a17:90b:5443:b0:396:4cbf:45bc with SMTP id 98e67ed59e1d1-396d100313fmr1670027a91.16.1787853095968; Thu, 27 Aug 2026 10:51:35 -0700 (PDT) X-Received: by 2002:a17:90b:5443:b0:396:4cbf:45bc with SMTP id 98e67ed59e1d1-396d100313fmr1669920a91.16.1787853095439; Thu, 27 Aug 2026 10:51:35 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:51:35 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:05 +0530 Subject: [PATCH v5 02/15] dt-bindings: power: rpmpd: Document Kuno RPMh power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-2-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=871; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=ZHsN8zM/JbhignLDIxWKpOEJ0dJLsvtVmGGylPc0eUU=; b=vzpCJkMB6+PuXviINwNp3FHtz7nk5WS01Bo1zaRtxjr+lSRFC5WQzJQ1BawfNs62WmAgjGZz3 7ciUxDb3xWuBXJwtYwyZR+4oRn74aMGz3NiBwSWu57vDqmcxYmMWTid X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX0zELGd25ktgN W88LGGyyw6y1Q6LBKV+d4VsT6IFB0r/EEIr1C5gGAVyOJEpB7YBoY0Enbv6uiDQSf9k6TR3aDIe umpHXeEyfdrAu+ta2POHIRusMenDxes= X-Proofpoint-ORIG-GUID: iCjtKFwgeOlvSKZAN3k0Gb7ah9rI4w4d X-Proofpoint-GUID: iCjtKFwgeOlvSKZAN3k0Gb7ah9rI4w4d X-Authority-Analysis: v=2.4 cv=G+Ms1dk5 c=1 sm=1 tr=0 ts=6a907929 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=lHgBgSUrZIjjmBdF2hoA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX7c+pNJvoEo1N czSEegBi2qWeMRo1OEHhVSXEkeHyv4QAP8LOD710IiRPpceyB/sVV1DQBrKm52rfgyyrUCMvWiK NA4/tmf7AfnHFsqNF+FD+um3jTLQFr1WV1bQXp0Zss9r+v7TVaiLU960aEeZfrKJ3Ye0rrA5nIu GZ5x7a4mjV61xyG0ow6rXCRitsF8tqkkH4Yo1L1XUOf1I3yG3BQ8ym0eMkg8pSO64zPRS1S4oIG WdMuzUJLqXVkZZr6pvvrDAEPqZhXLPy5sryLpulSddArvc1SGA0q8UUnbaQ/Di2E5qgyoKPSWHD EPKs4twcDcr9an1c2EiZMAz67sJuSbmU849R+Oqa6gAGAKP53nCX1kwHlIUSer3rpDGoELXp7bJ xu2zf7wRdz8I5bqEUtS0DEPj9AHGbT7IKuPuqLAIqa1oRh3xvr5tD48EFDmw1ksYVWopHaH3G1Y 3FSVh8vPvsBBVmNISag== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Document the RPMh power domains for the Qualcomm Kuno SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Docu= mentation/devicetree/bindings/power/qcom,rpmpd.yaml index 0a45e1f55062..7fc3927efa27 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -21,6 +21,7 @@ properties: - qcom,glymur-rpmhpd - qcom,hawi-rpmhpd - qcom,kaanapali-rpmhpd + - qcom,kuno-rpmhpd - qcom,mdm9607-rpmpd - qcom,milos-rpmhpd - qcom,msm8226-rpmpd --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 435F34A13B0 for ; Thu, 27 Aug 2026 17:51:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853107; cv=none; b=G4EucLTq7IxAJDW9T//c4nMfu8bpFDDIDqhNrBHkkDvO6Det2pV1TTOaQMC7J5l31S5xJ2epR4456azOd3cfDqineq2HEGmTz8tgLEXO1lOl0XVCOUsZrvOJ5GWT88KHVvGJm83o9cRR0WhvglKb+NBtGyCXHxtXVBF0h1NRTHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853107; c=relaxed/simple; bh=k/DT6AgKWqS6ku+QAjOs6ZqZtSg8uMTVP2+zB+uhR9k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C6+RcCYH1wPhq1xqSDXKSxOEa7uNEumjAx4BxQeuE3FkwALnwePZ5cMCxmo4JK7MVmbN09NqDqqxHF1nYUDPV6vS0uC0C7WwjFrW0CyRaBDtwhRWBfqmoIKIW6H6aT5d1PQexLBHcmDhnH40UpgPNKNPTqp6bXGemlPtT1ZSCFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=k1Z6dd2e; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Z6Gdp79q; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="k1Z6dd2e"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Z6Gdp79q" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXibg3613337 for ; Thu, 27 Aug 2026 17:51:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pHKTpe8pp9JpvuVxGFlRJsbq12DvNmufk1YkffXJuU0=; b=k1Z6dd2ejZaZb14h BBiA2j/2MndoDiNZ3U04U6JUwtiVfZKYNpi3GsBPpNAcKgtFfOJ1M5gEyKHYFWGP +dAAXWRbjjpcRAbAWI4+PHVnuevAUUls25FW4l2pSJircAVOx4yUCNXxLkDO/hnB gDoBNNv03WhxxeOh9B9SQnAaYBlY2Yku5Lz8nBHHUlzXUdvLPqq+fP796h630+nS 51n+L6GAXGEMA5qVZr5JxhVgjLHLjvecNKC3q6qOLU35I1WeDc27wOtmG5b9mbyC H1LFfhzsQSd5qAgy8FDp0A7rcZALqTIbUzKMDXsWZGmJI3lWjje5Ubj8RNZDbAEw vgE5ag== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gab7t3wsf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:51:45 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cc132709c76so260022a12.3 for ; Thu, 27 Aug 2026 10:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853105; x=1788457905; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=pHKTpe8pp9JpvuVxGFlRJsbq12DvNmufk1YkffXJuU0=; b=Z6Gdp79qI1O1Re0hmUHhindvoVZy4j+Z+KkuudB91p084yxQcs6j+4GT6y7KbLFpsN QUN85vaRx+cqLNHER0zlFbk6qAg/iOGz2Uv2VN24ie7LuN1Prfl9tZrkiKVswi0Z/3hL qfAdsI3axt9NTS1ndNT4ISIa9W7/EFPVITcm8O+jRysx0XON6nItam6xmXVHu846Zp4Z zKo9ONaPFGc0W2cM5pgNeYp82Rf7378HCF1ReP/8LbDW4oQwoJ6ZiL5XE3sUTboa6RvJ 42Yb2RKfCvMc7VoYMiVQl+i3eqwAsekzn8jtxxMpgaEMBI+XOyYU4z+Z3oFZxiJLiaAn lWKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853105; x=1788457905; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=pHKTpe8pp9JpvuVxGFlRJsbq12DvNmufk1YkffXJuU0=; b=YfhupOuL366R0xzGEzw2ZnOIdkoY/MI7Uh0mq56sRad0GRo+d8s3F30f0nawmEHTlR 4Tp3cA7UxpsxJAEMJXcCTaRpZOWjeJbw0c/qVZ2rdtsK6RI1noAjgJxlagsxq9MQgSe0 JBLMpMOdXApOem3iSUOL5NFXAAGDH8vRZ/bhrNB8T+htOUEPot7BcYzl2oGDvHBp67Xm hnV3IZ0Os2Qqfo9Xt1u7TDOiec4laZkdUkVB7/SsRlC9LGE/BNc6nSoWU8JvBEbwT2pm g2S6TpmqR8OYABOShWFANvn6T/vOrx3E06wkifIMGjzTIOEl5ZBazyDHc2FFQBoPOoYU tntw== X-Forwarded-Encrypted: i=1; AHgh+RoAIF6Qhu2DN/FOIM0RtpefJcbgGgVsBYoQA0psNwl37/vGZo6SsYFcjpBRAH7WTIwu3BFg5LRewLbPvFk=@vger.kernel.org X-Gm-Message-State: AFuF++m6DnqnzZCPXIFzhMRFZ5ge3XUZZD+rBEMblHbhcCdu6UE0U8aA A7pbVXMIMdgGwTZJ2t85DT8MFY0HioPXv8tLIfLHIYZS8ujCtLS+AS7AyToXIsBIGdgqi9DsKZ8 dJMHx14OAb4qIoMJ1YkMkRm74OhN4nTitbnDgpltP0WKPU6vN6VXgCwAvE0LfdURjRC8= X-Gm-Gg: AR+sD10NBI0hmrA7X/JZv6I62/8ykgs4sRM1A/lBf7lXKEm2fxK5UPJHzR2J/D3hSFG qIgAwtoFZPGijuemmMb1UNN4rkWesE3n1r1i6SiwopALdmPj5Z300iR9edaqUhQeBnxOR27ARdr vKxjXgiZl5HzBG9fRn5UYuqhWwzF+Hog/tMpAfQ6qYLIXwYr3lD0K091/xWIrjlgIPbrZA9H+qJ IKApg5CMIGolerf+4d8jEMtk8FUAxlS0mNJklGVFm60GuMvarc2Mh7ljpSBLFHAwfXkgMbx+Yzd z0MVMMT8XR3s29GZQUYfS86qKtXRs3B3VypkRqYFIdSz6f2rx+fCIo3L7ti7N3Q30+pj0llhev9 PQe840DvNDhLXF4InnAfY6WqkH1Ncscl80cfxFkgGg9pgZrcFOixJcNvJSnAY6RWIKsIxPF85bw 1cVzvmX8l42j/HWbLLshNZPDA= X-Received: by 2002:a17:902:f708:b0:2ca:481:de45 with SMTP id d9443c01a7336-2d74dcb5c40mr12274785ad.6.1787853104472; Thu, 27 Aug 2026 10:51:44 -0700 (PDT) X-Received: by 2002:a17:902:f708:b0:2ca:481:de45 with SMTP id d9443c01a7336-2d74dcb5c40mr12273935ad.6.1787853103968; Thu, 27 Aug 2026 10:51:43 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:51:43 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:06 +0530 Subject: [PATCH v5 03/15] pmdomain: qcom: rpmhpd: Add power domains for Kuno Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-3-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=1801; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=k/DT6AgKWqS6ku+QAjOs6ZqZtSg8uMTVP2+zB+uhR9k=; b=i+O8rfJxoGXvxVb8s0xUN5ycmjvQA1VLSZzdlTqgB5ei4txrnc1hXqZx6yMSn+P7/kHrq/WRq +uDDOAajqMPCrT4rDfEz7FVT3k6XSqnAkUgQs9SKUE0OU/9v4bhnuj7 X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Authority-Analysis: v=2.4 cv=X6Bi7mTe c=1 sm=1 tr=0 ts=6a907931 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=1FmER_HI0FvT1hCPThAA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: FG3ECdiDh9H4_SZy-V8x5gnEeXzSumYM X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX1CxhpK+qlIiv supERmq+9m5oifs9lv0CajAJL8neudWpD5KjvO0gl5o0/0O39bsX3Zba/w4+1/5sEnvRto9UusG zBLkZq5vRi3UsFeJxJzcFw2ZJSKZxbM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfXxKLucO/XPrtx iqgsVcdMMF7hsEvEKYromEhMCQfca9SAajC3ofCf02CTojbgdW0OF34tLY4wEI8T7G2fl3x0T8P GqNTqjerqg4hSuigLjAdZcS7oseZFORI+3pXGiCCjvxZQlBr8uN6F41/kO3pn9Q86IzHdMVUChz cvPKCfP7cZLBa8Ohp9/TvuN3KwDYA12QoAAeZhIH6LosAqhnyV8Kas8WYmLu4CFYSit5KsXL6Ny eC9Lv1jZOIUQk752FHFnBrmEQR3a9J3aI3hUYkLyfQ5gGVkUyl+A6ESAO58/PZTuLjD3qKFfbUY 74wj6v/iJQZAWEyG7hKd1EP0wdRKbNEecrDPQ2feOEJXTFDe5EiMlrHfcITB+oZflsLWWTESWjp W0AVVa3sUpXdh2TXPoSU7KmVjr/GLPBUSv1GFW+G7medLVaA8+3Hbkk0CE6SeSPQp7mGlDStaId IAGT0DvlJcgejbmz7cQ== X-Proofpoint-GUID: FG3ECdiDh9H4_SZy-V8x5gnEeXzSumYM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 adultscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Add the RPMh power-domain data for the Qualcomm Kuno SoC to enable the new qcom,kuno-rpmhpd compatible to expose RPMh power domains. Kuno exposes CX, MX and MXC domains (including always-on variants). Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/pmdomain/qcom/rpmhpd.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index 90743275942d..725ce802f683 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -681,6 +681,21 @@ static const struct rpmhpd_desc kaanapali_desc =3D { .num_pds =3D ARRAY_SIZE(kaanapali_rpmhpds), }; =20 +/* Kuno RPMH power domains */ +static struct rpmhpd *kuno_rpmhpds[] =3D { + [RPMHPD_CX] =3D &cx, + [RPMHPD_CX_AO] =3D &cx_ao, + [RPMHPD_MX] =3D &mx, + [RPMHPD_MX_AO] =3D &mx_ao, + [RPMHPD_MXC] =3D &mxc, + [RPMHPD_MXC_AO] =3D &mxc_ao, +}; + +static const struct rpmhpd_desc kuno_desc =3D { + .rpmhpds =3D kuno_rpmhpds, + .num_pds =3D ARRAY_SIZE(kuno_rpmhpds), +}; + /* Hawi RPMH powerdomains */ static struct rpmhpd *hawi_rpmhpds[] =3D { [RPMHPD_CX] =3D &cx, @@ -885,6 +900,7 @@ static const struct of_device_id rpmhpd_match_table[] = =3D { { .compatible =3D "qcom,glymur-rpmhpd", .data =3D &glymur_desc }, { .compatible =3D "qcom,hawi-rpmhpd", .data =3D &hawi_desc }, { .compatible =3D "qcom,kaanapali-rpmhpd", .data =3D &kaanapali_desc }, + { .compatible =3D "qcom,kuno-rpmhpd", .data =3D &kuno_desc }, { .compatible =3D "qcom,milos-rpmhpd", .data =3D &milos_desc }, { .compatible =3D "qcom,nord-rpmhpd", .data =3D &nord_desc }, { .compatible =3D "qcom,qcs615-rpmhpd", .data =3D &qcs615_desc }, --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA3E34B0482 for ; Thu, 27 Aug 2026 17:51:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853115; cv=none; b=ogT65HBqTV4W+GyBnanljtUcLcgGgqz5CQjafjWqwoP5//n59VpPZ5x/S63ba9+zq0c0MR3Glg43p6VcBx8BO7l6D7WKLS5UInk9LxuChqNKsIlQWDLxYFf6EUK27S9oSKBl81lJ+OPNpJgOa87ZG+LQYR2LHKFXFOGPK6pF0Gc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853115; c=relaxed/simple; bh=PwVD29DtUH4dIGkOMbXE9qMjiF+K6OUxLIjMJeof/6o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s2S7XYTYuhF2xl5FdxA7Lq+ASPUbMa3pfy2CBG7uvZZN+goGCWtj/cesIvLxfsIi5WPLGQjH0wXN0CQ+t3bbRfd5/6g3PbY6tFUT1WuflRFG6DlPFyPJdpu4dx2VFPWBV7OW24tcJnph6Fs22g95VIz/I5jNnESUZ92iibTH15Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=OrkbTqbq; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Vqxf4+Q9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="OrkbTqbq"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Vqxf4+Q9" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXnjt1568596 for ; Thu, 27 Aug 2026 17:51:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zPYfTHbFrfi2XEod5q3VXPMVscV9WPdiBhHDyk/uC10=; b=OrkbTqbqWLWzXeag Y6XXLkqEaCKKrZXZSJD6fFjtW+arBtUSejC8LlmqYkZGo1Frz97/GS1qSFnEmtLp YhrS3g+zXKYkgfs1iz7sBl3HodoWvnfSxpf3d3QydT3ID2gs/poLNXfgasgEgg10 t+YK2IuDEzUmvUKW9QjXGbXwuvWLH3IeXv99ppVoX0J2C2ppS54vIS3+q3ZdVudY m0SKc4O5tMYH8nOyLYvthdbfXn9AbPA1yXp2B+SjKwFpFdAi0xOGqA3yl5XOTNYx Ci3O4TFE+r8M9WC7Ms4Byt5ElEsXMDCIoIeBuEyNX788p2kTP1/3bvUN36Zvjosg JgAG6g== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ga8m5m9qn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:51:53 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2d6f75c1219so1667805ad.3 for ; Thu, 27 Aug 2026 10:51:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853112; x=1788457912; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=zPYfTHbFrfi2XEod5q3VXPMVscV9WPdiBhHDyk/uC10=; b=Vqxf4+Q92MctupiPADBLZjeOED9mwvhAgX6482IhIK2+2jpKRSdusIL/uAL65lJWSe WC0E+B1MnRztc7g9iVuFg4AbmybXr7aUX5/kdNuoPidNOqM76MU+uq+ZWd8FCRa9Fh5o k+ItmAGImDDxTHuuuXVmiv4CzYSdHOHrkWeGCNbH9851+fQoVqWMeCaGry32QRDH940Q KzwudAX4Q7b/cSPDsAv1u8jKEd1L+deWyzNtQ9A15Aqlz1E3dGGT/HWdrwAal5tcdQfh iFbAI65bCf7Xe5Rrh2nHtjX4drIQWayWeZ11rrQH48Os4NnwlicgpMsMeIGzNpADIvdO PSIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853113; x=1788457913; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=zPYfTHbFrfi2XEod5q3VXPMVscV9WPdiBhHDyk/uC10=; b=J2Lf+4eplOLrEu6f+tNnjeySU87jGkgq8gy1zfRFfpcBqAKQK2U8tNQhM4j5pESFm1 vKRLx86SOndi2mhqweTfo7yP/QptjumJCZbPTD0xtp+TnWjjVYEbem/zHQr2LhEIvOqZ FBthNMOgbFq6J6/DjP1Y0oY7DLYfdwQYSWiz7NXwVS2val22sF4X53SbpdG1rznMqNJl me3w9HyR7x/opcjxWTmRylpjMwR4CVHnpahRenBXRxy4efZWPm9o2m/xAbbBjIsux6Ij fq+Z+xvVkP/lchBR4OVRTImJ4DOjP8LBlGNfsY7MJokvxj5YhXONezDAS04pDQoLhfzd QT/w== X-Forwarded-Encrypted: i=1; AHgh+RqYh6OSoBFUwtgT9rfHoQpmx4djOxZPAw+f0+8tgYdLoXHZonAqv1gvdnobB0E6iOxy4KaWTQpEQG+K8IY=@vger.kernel.org X-Gm-Message-State: AFuF++kQWfdFHVqEi4o/+94Guzb23Qx+hrXasNuVcHVmAZilQWI6nJXU JFGkJ94EfogXrgKi+7G4+onqgq7Q+1WwbtAWOXYeyf8XsTQvehzAY77mHWZYRilGxIBR6AhRTsg cE3BQESpz8Es+A/tcdxIbaIPaCeuanoFVAj93KstyfTHO/jouJYQ9wgbLYt7c9aPksuw= X-Gm-Gg: AR+sD10auP4XbqnGpMA/RRB+MPBqctv8tmNlaxcFRjyvylUkOPPh4XkII1skvD53k29 +YNJJR1KObAp3bn7X5w28zcUHWLF6IK1FyFYnAjLE3zXRJ7g1nMstdpu6C88dBZQZXM27SFl3Dh fSW3Zyeajmclm8+7phB9PdrWpvmpPy9ITGMtlD7SnLH+5ntY2zZEU3Zp7CFnlXfluAVLm9tRRn1 dlaeqB4EjrC35f05ab5gQXsWJs7csmDx0/mBbPPhDNJBynHVkOytLY7eYU2qQ1l/zu/rGfAzfef +Ts0tqnPpk0lqx3TFirwj9/2ZfEAT2bkYJo8hGBqxnIN/GczZ0j4yegoMDLyMSNyAqy50k34BxM RIUWKx94EOLvWkq5AYrRiPjqChFe1f0FtxpPfpuboi7EHAtZ0BkYrKs5COW0I6auFUI4XBdcjQe uJpNhTOETJQ/ZXZapdsaSuQQ4= X-Received: by 2002:a17:902:d588:b0:2d7:1e07:4859 with SMTP id d9443c01a7336-2d74dbe40e6mr13925165ad.2.1787853112432; Thu, 27 Aug 2026 10:51:52 -0700 (PDT) X-Received: by 2002:a17:902:d588:b0:2d7:1e07:4859 with SMTP id d9443c01a7336-2d74dbe40e6mr13924515ad.2.1787853112019; Thu, 27 Aug 2026 10:51:52 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:51:51 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:07 +0530 Subject: [PATCH v5 04/15] dt-bindings: clock: qcom,rpmhcc: Add Kuno RPMh clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-4-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=902; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=PwVD29DtUH4dIGkOMbXE9qMjiF+K6OUxLIjMJeof/6o=; b=624VoE6RT/CK7yFN44c4vo43lHBpjAc7wHgne3hVVyn8wYeeopVl6LTMwJWZJuoDMQFApxSf7 MCtWLZ/tVAvDZQGkWqsNg8O2BvuWsSs/K3ckjUs5KoziGaqjuojV5us X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-ORIG-GUID: CZ2rb2TiZ9eEaxBpOMm3QCqjDFmCzUWl X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfXzfwUUSyEa18X Gg8gtE2dgG5MEN3IEA+/5dWsU2EXaF6MMczM6FFRKXKH3X60bL1xMZVkQJc157r5J3OUi/rOqqv LsVrgoW1mOPZzVPXD8rqfxIMLyn46Fc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfXz7eZTaZzvRFl tyyWHLe8RHqPSb3d7eoP2T0ZnXT5RrXkYffiHYYj3Gr874PEOTe693QsSwSRaAEyLYTQ/Y4YDQT 8wJo7E2IiygX/R1h1yhUiCfq4dViHqEJBLTgohiKKb4oTDBBof3zIUn+o8g6ZzDq+VBGuqM1g5C S6IxT0B4ueNdUWoyoarHlpwpg5OATxS9uP+OeehqyTo+JGTFMqrlvyLKBUjk3Y2vw0H0bWU7Auw jLOXAdUSsvAkpRBsHzF4sFiw/btKA0aR99CARAH2eAPcvEsWwc7NCbdKtr7V2zWw8JQ03sS/BWA pwcbAuKByb4Q/B1ipB7rza8yC5dQotfV3NpK3tqXUgWyIck9/kHKR7MXIrejPNIW38XQWOYx1dC SaEvKN/0tcHEj/WH1aGciTxIYGWVYX25T6ry2G17fiqyYkTwY7jO1ozrUIlg6D3hhI9TG7dP1eD /pAJ1Nj6tbmKxaxWDEQ== X-Proofpoint-GUID: CZ2rb2TiZ9eEaxBpOMm3QCqjDFmCzUWl X-Authority-Analysis: v=2.4 cv=SomgLvO0 c=1 sm=1 tr=0 ts=6a907939 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=VE4QQHX-7aIn0oL__EwA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Document the RPMh clock controller compatible for the Qualcomm Kuno SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 2b446aca5207..9d521ac9c33f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,glymur-rpmh-clk - qcom,hawi-rpmh-clk - qcom,kaanapali-rpmh-clk + - qcom,kuno-rpmh-clk - qcom,milos-rpmh-clk - qcom,nord-rpmh-clk - qcom,qcs615-rpmh-clk --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EBCC499F01 for ; Thu, 27 Aug 2026 17:52:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853125; cv=none; b=umb2iwskJuYyj/QagxOrgIWis02UtZZ7zOczurKqBFg8l/BPvctjEt558gYfUMvAYtAOGThXJFKcrev9YK/znOU1ylT1jVPZfZTfs2idWeDJsbNOqc3rR6l1DOUjV8oM2noL9OrA5Iu1A+sQhL4+nhIuppedozeMSIxmtGohY9k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853125; c=relaxed/simple; bh=HmmI194gyOrC38jn1kOmQP92tC7eCM4pFbLwZh2jkps=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IlCV5FBw2FQmSwzsQUN2RSWU6ja1fET8QZk3AiuMaixmWen7vBnSoGAszfgawPJvjbhR9mz+2m+ID9v1DcIEsFMLVjoRGDQm4JOXZcRAW9RtiNnXM0srFQB596JKNUcY7Uewf9xPP811/kLM838LWkrYMCZXnpxeIpZc7IAqwu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=dFjphGD1; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=OGKkloIQ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="dFjphGD1"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="OGKkloIQ" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXvBg420129 for ; Thu, 27 Aug 2026 17:52:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= hXdk8G4pm4CrNjX95hM/lx/4VQ+3Uhckavbrp7NZTHs=; b=dFjphGD1N1rclYjX 8PSV+w6jwQkIr9YsWFTgstUfoQy0sQTtmwYkZwWGWf9WrrKhCCKDRV9Sy44n8wgX 9/R6ju+uTmnYRNLj+F+bFhRAFosKeaoHAEdxTGctP4oFWJxbfstvSEJUzPcSqTvQ PNhSNznNXpI7RwaYqH/7/klKwEofU5m8o56E4GcbHF2B02b5CeFb4h1MbghFoCUj 5CVoYfBPrK+W2mzMsTawrpG/17oOGRoBu2cW0Rr+OReb1yrcvZn3KQF8wr4wmVr6 0MwOr0Bz145oMEBJLNBBgoFa5ucHyykmQjLc6lZbG9nt5zqEaGykFAl2Pl/yEXZh n+8o3w== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gagjftkx9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:02 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2d733799ebfso1142395ad.2 for ; Thu, 27 Aug 2026 10:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853121; x=1788457921; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=hXdk8G4pm4CrNjX95hM/lx/4VQ+3Uhckavbrp7NZTHs=; b=OGKkloIQZCYNqRsq4nlpVvITEsr7LRElGFP7JZnhPYItECyap+1/eK33XW54trtgh+ yVG1I/6qoP8QNUhmYp1iuQc+1fjYAkpjV6A0fDSL2uIpIG4MH3i3UqNzVZAl57iHS51V r0O4btIzSIuoZ5bVWoXESoGRlbUwaN+kyhmIiZYoW607zoGX8wxaI3ieMkIJRf/AbWSC dRNW6VJN9f2XCy32mGNqd+d2M3KXYdrBXmb3VhQEMhGnL/fzrkYfV8BtdK9AM6FSO8m7 5Yy7ckN03M0RhN2LZ7HK3c7dp70sTrEYll8QJz2RuFrTb2l5RCnnjRqOzBg01UrcBsXs ky8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853121; x=1788457921; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=hXdk8G4pm4CrNjX95hM/lx/4VQ+3Uhckavbrp7NZTHs=; b=ZUFnvNJBHDXj2AREWT0rMRHpJu7o05HORFBGOEyxki2LJ2z4i5RiOnU8YmksvSuxRc dVwpLDbtkNyqk+wnt5HS/Qj/MsWmuMmBhLKDsIpQCUV7pfXPl0WwicGqwOOmu6+9j29Q /XZQblH/2cRdeeLFycErDTPbwF9aAVzKP10Ou5Hsx6G85r5mbzUT+QWWxMftCFF7frjO FmQ9wvnrt4BQvCWWd5RA4GtS3Cyx7oGZ47zHA0/YTA2b9De7/rec26CWdjHoFEad5gpI 3yGt9LdVtJ3umTrmQzZMRvXUOcV+5IJtDEDxnB/bF4Mj3NsMuez0bqoo/U+NYnlg40w3 CgFg== X-Forwarded-Encrypted: i=1; AHgh+Ror/EwXHEcuvfrejk7beRNkon1e/cI+9y+20IkI5GbEPQxOD+Usg0eJECYYbR4kpE4ydYqM8Ogb7/PI7eA=@vger.kernel.org X-Gm-Message-State: AFuF++mDsK6i1uw9y2QARlCziCApkYbr6EBjL06biiKPz7ujnp60beye SkXggswlQy7bjq2svlanHvOfob7WbI5aSrY32P3qoFHUVQDHWJbGHdRru0crHgmF6yRwAdoMWvW 5k+BDUdfU9OJYAxa90JjVyTjuwMX/oEoyNdrDeHADzbw0r26Fjz5GtZxtzYLw9RFreAQ= X-Gm-Gg: AR+sD12cwe3XBOmDB76B0MuH/0zGk+1CZnz7/GCCHjZ9ylo9rUqcenSktU14qZKeoDu 4z8cd1WLqGFg3Kj+qcAAfX71WPP8lGYSZ4oRzujTuG0V+r9kVgVkLGd6w32PjTQ7Jq61O/peAaC alGtKonn0qVajbq+qGHSEAYykg7zJB+4iUO9YoVQ/MQSNrKf4m9OGADePMMg1Vhx2upeifVN+MO JebGr3kY+LVf4Qb9CQ0NjpSez6aetUDX3/bVsNs55VhBwyt5ZG+bJEyHQXTwMi1AJsIuoPmNEp4 08x+oeq1u0BlCtkq1zMo7Z8CTUZmieUokpqMAzwBAdeWNdeKyGEs9twrTZrFEUBZHI/kSUhYiB3 XOwA7lhtMq+R8iWuDFtMD61upFEH76unZrW+xvMgsXw/KYW79WvGOEbGMarB6DInhuzhXTX8enz AP9sPDUshMoRboZu/p8fwDFJE= X-Received: by 2002:a17:903:144b:b0:2ce:faa6:7cbb with SMTP id d9443c01a7336-2d74dc2fe73mr15355845ad.4.1787853121188; Thu, 27 Aug 2026 10:52:01 -0700 (PDT) X-Received: by 2002:a17:903:144b:b0:2ce:faa6:7cbb with SMTP id d9443c01a7336-2d74dc2fe73mr15355045ad.4.1787853120764; Thu, 27 Aug 2026 10:52:00 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.51.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:00 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:08 +0530 Subject: [PATCH v5 05/15] clk: qcom: clk-rpmh: Add support for Kuno RPMh clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-5-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Dmitry Baryshkov , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=2134; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=HmmI194gyOrC38jn1kOmQP92tC7eCM4pFbLwZh2jkps=; b=DJ/9X+zyxNdrjvjVzxUgzWUEDwu9bnEmv+BH8gG9CMZaVCq54yxqRXbSgGYGyRBaV5davTHKd C5aYGAAFLH0AN+pHU9UyxhEQe4FgERHHN0OYSx4KeaK5c2jJs9Qpcx0 X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-ORIG-GUID: E6bDU2Qg01YTJcpG55598qYanW4VA8-C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfXzf+iwLGjnAMY /O7txDQLoY6yvuZWdsglVYvIPx1kf+lFhQKngpMnxVVTBUXg9o0wTGsr36Vd4upXdHsyDn4k8TR iyi+7h5IA9M4ZIz7imcwHzzsgVsNh1JqfjDAzB45HXkRt7V3lMP8tA3OqxlCTIZE/j1LTWpsHfV VOl0Q8sJMTQAv3fzV6LZg7/xB4eKOwPPUgyKGK4DXcFduO6U7jqTu9Mut+dT2iPIih2etF2ze93 WKhy7hTnowNop1Vr12KpWyclRMkwO/GMC5mGrSfQ+0dqYzZYGMz2aY4JEeb4mn3nm5bvwQXGw37 oZ2TWX8QIPP5Ol0kCh1vVFJMuguVKTRVcx6CjJ6G66bsDwE33Bm/vMTeXQe2+fv+/w80zBiXgP0 ghtFIjG9izClT5AW3boaFFANGT4qcxLOZrDJPrDYG5jw1R4ghPw+QT2brsQsfmmMZSAgwLRMjWB 5gqdJl9QXmve/wpcubw== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX2xxknsEKhzyK u3Pnr6X3GZrDbHLXt1NkYSKhI/Hd9IpYS4UbkQYnUJ4G2VaJXSwvewd4xK/yrSGmbJzkfPjqNqb 0t4fmWv8zkQux63qlsHXQjwVpnKsEOI= X-Proofpoint-GUID: E6bDU2Qg01YTJcpG55598qYanW4VA8-C X-Authority-Analysis: v=2.4 cv=dd+wG3Xe c=1 sm=1 tr=0 ts=6a907942 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=cbMe9IPPLhjBV4UIYdkA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 suspectscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Add the RPMh clock description for the Qualcomm Kuno SoC so the qcom,kuno-rpmh-clk compatible can provide the RPMh-managed clocks to consumers: the CXO div-2 (and always-on variant), RF clock 1 (and always-on variant), the QPIC BCM clock and the IPA clock. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/clk/qcom/clk-rpmh.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index a224a94ae273..ec8700b6186d 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -937,6 +937,20 @@ static const struct clk_rpmh_desc clk_rpmh_kaanapali = =3D { .num_clks =3D ARRAY_SIZE(kaanapali_rpmh_clocks), }; =20 +static struct clk_hw *kuno_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_RF_CLK1] =3D &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] =3D &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_QPIC_CLK] =3D &clk_rpmh_qpic_clk.hw, + [RPMH_IPA_CLK] =3D &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_kuno =3D { + .clks =3D kuno_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(kuno_rpmh_clocks), +}; + static struct clk_hw *eliza_rpmh_clocks[] =3D { [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, @@ -1097,6 +1111,7 @@ static const struct of_device_id clk_rpmh_match_table= [] =3D { { .compatible =3D "qcom,glymur-rpmh-clk", .data =3D &clk_rpmh_glymur}, { .compatible =3D "qcom,hawi-rpmh-clk", .data =3D &clk_rpmh_hawi}, { .compatible =3D "qcom,kaanapali-rpmh-clk", .data =3D &clk_rpmh_kaanapal= i}, + { .compatible =3D "qcom,kuno-rpmh-clk", .data =3D &clk_rpmh_kuno}, { .compatible =3D "qcom,milos-rpmh-clk", .data =3D &clk_rpmh_milos}, { .compatible =3D "qcom,nord-rpmh-clk", .data =3D &clk_rpmh_nord}, { .compatible =3D "qcom,qcs615-rpmh-clk", .data =3D &clk_rpmh_qcs615}, --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37563379EE6 for ; Thu, 27 Aug 2026 17:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853133; cv=none; b=D4xPHueZf30WQmlcKMZQgNPe8tpdsom7LxTKsfx3kzgOKEvP3CFOhpenw1QKfmtDd3Q4xzubI4N2Rg8sLQmbQuwY02j7VTqaDbkRHrSsbDGMtfME/arPtP/fTWS0KQ1bOx2qezQ2mXup1e/pV13TXlgUCFP2utJ8bULlyu3eMiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853133; c=relaxed/simple; bh=ZnkQG+JcPp3GcC7zdZXzSDhHf6/rgK9ZZsLqH/4xBvc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nwh99yOI7LdcTs7RS0/A0tHf1IXhea0jUQaKZ1pwMSFtZXQmgpxhsFIAPuZ5ImgLSTYSCU3PU5GjhXtwGkFQHSyolOfbgdmHjHXbJqMiUGWZpoH5SFZCNpIAIxZfJ/ZuJQXdX5DUH7W0dorsE3zpRU4Te/PfUNsP3E214eUBvlQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cYuJtT6K; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KLPszZNF; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cYuJtT6K"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KLPszZNF" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXcdH4084137 for ; Thu, 27 Aug 2026 17:52:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2sikrRXkwMudaZ+uyQ+IIhj0K3P1q68Uznqjv+0AL44=; b=cYuJtT6K1O7t18pW M52h6b3Cw3Dv967NMKWWUnMKNICuxBk9KmsVV4fCYX1zJ9YMY4Cjjw5FV7/g0HPd Fe7XF/JaLG6gE6ZUhJC4J6av7eEQZuODkbLyqryEeztPEw8fF3xUfC4S+iP7TDZn dPWx+ABDU2+3g50xY6o1DWp8uX7yfhcP/gNHe3w0UrDh/iLhbqiRftLGbgS0yO3K c09AEDS0aW87i/qGgn14x4dpQSP9mFsc6CpFGgmACM5QGRU72DbtZXx9E/5bbu64 wg74LgBGgOFnmpUAQGzhUr5HYPJvxKlZ9aP1zKmCimN8nhIjWon22pLkMZnlMIFp zxmWag== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4game7st9h-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:11 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2d6f75c1219so1674805ad.3 for ; Thu, 27 Aug 2026 10:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853131; x=1788457931; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=2sikrRXkwMudaZ+uyQ+IIhj0K3P1q68Uznqjv+0AL44=; b=KLPszZNFvYFwiZq15jRo9D0iOZxdRT3QavPh/RtOGWcjyhow7k21+/jzyGCQO7Ov5p Qkt2y+pJRUF8lHBpJfbfUQAnUiB/S0DuVd3oK5fAYMcwiLgut0RlphM9DJusQTHrFkjW AUb7TO8lFB7bPdKNfzA6UgVZXnYLpbMDvlMomYRX9Q4mFzXdIdYoGvvKMBdO0/1WVMdu S59MPBGP+elYk0dGT+0vHHk0x+xNPMRywtb/R8LO+Kgcce1zmTuhAS1qMiZmxEdpKJHV x3fmspY3DItDnZOb4plW/aHsipd4wbXMlzwQU0LyAEhMYCpSuV4W7QJQmH6MoqqETx/f ETiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853131; x=1788457931; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=2sikrRXkwMudaZ+uyQ+IIhj0K3P1q68Uznqjv+0AL44=; b=Fd8h5LMEXeuKG383+kws5OzBajsc5TlrGsKKEzAYdECxYD9HoaBBfEQgVc6Aa7ebvQ jaNoUjy1cQmcAtmSXS+LSqiISIwHBnRIgfFc+c5XhNhJ1ij6MfidzHU8glhq10ByT3qW ERWi+wLAbgIXPmuEC6l2Hnnt3pId/PIyEBNPvVRBJ3E4j2oLJlzGOQLL7ckWq8BAk05A dXOnwUYHoGMiaIV8XaYE9MRMW6O/edPDQtdZeeLpGSjN1lKEivF4nI6qOJ/yZcH3+VDP 2W8Pv3oawdxTjUTs/zCMRKvsc9P9h1GE1F18LI/DQZ5bIcHhS3pIaShYRc7TVUJ0WUmQ J51w== X-Forwarded-Encrypted: i=1; AHgh+RpPhvjAfNgT8nwr5tytrIzxlP0yGX3K8JXbdW5L79wm2O1QaiK5C7+zC5IEdSVpTGYVGy9vJLXvkxanPgk=@vger.kernel.org X-Gm-Message-State: AFuF++mpZzg/mA9tm2c//Bpo96WoUk6MRIWj8ouhEjal3KEkVsW66dDH 4gmlx5l7erW63yGMLNNOE8Y8axNYq5WVQqyW9du8Ifcd1rrFPBAKmM5dOhnqzStG9G43icUbx3i nkU18gRa+rbL+nOSLlMnzu96VB6xLHfcx/AFMTZqtJAjrW547kwx5qgklKtyY9aL0+A8= X-Gm-Gg: AR+sD132pWY1D3po1jBYMRknCbo2E+qP87fgAMAYrVdWRYwys0cTEaUU3fEKqOxYf1b X8am08GdXWN3+Umw43pyePG7NANFBkMhgBFtcdbP4K5LVCFdAoi+4VkZIHpgOzom+inSuicJNIP HbIl4D3DiHeSCLgEfuVyDifRfFSbCkVfPXPffsA2IRKHWkawC+PkSwpMLNPCZytktzrF1IucTn0 JweLEcSTDnTeGZJbj0K6sToeKagMtJkUAOZAnx5a205n8rxl+2DQvZHNHNXA+AbtM3FEjhhFy06 pfqkgHTo7C5cUg0Faq/N54k3qMS2MZ9ltfwalAk5AYMBzhpQaXN1614xEyQgmm4WOoMoxz09Mvv lN0jq74T9lsy86uwJHM5o8C+o0P2gHjSTH3NpSQRDg8Evtog+VOK1Z5RhhE2xwLEBvBQx2iCzeX nZxECdssLC0haSzMhsGtOiObo= X-Received: by 2002:a17:902:fd85:b0:2d6:ffa1:429b with SMTP id d9443c01a7336-2d74dc6f7c3mr14002805ad.7.1787853129885; Thu, 27 Aug 2026 10:52:09 -0700 (PDT) X-Received: by 2002:a17:902:fd85:b0:2d6:ffa1:429b with SMTP id d9443c01a7336-2d74dc6f7c3mr14000265ad.7.1787853128867; Thu, 27 Aug 2026 10:52:08 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:08 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:09 +0530 Subject: [PATCH v5 06/15] dt-bindings: interconnect: Add Qualcomm Kuno NoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-6-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=6755; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=ZnkQG+JcPp3GcC7zdZXzSDhHf6/rgK9ZZsLqH/4xBvc=; b=8+4NzS0AYo4ne8nSm4dNJ7oDOmmThnTT5jL5Kafdb+9QqoVMtxp6anYDj+2KgAaRhABwr3lh8 6SPuxFZSr+nAPppB3ss074ZHbRdtWnkcUToNkDAtdD/29vKtJJE3Kcd X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX64vqaaZybvlF 8Lf1Yr5oFdniIHmMnMeMEiMIhgCuH149pVT2m+eDpNH5RC0qZvHMkHthtCpKjXepuqymylg5BGY uu/kakIHdEelwkNTrf6y+4t7I+zHlgn3I6q7qOgaCY514KsNKWzvG9Nz1fg+qtFlkLe/lq+E7ld rD7g0qzgNTDZVHnAbXIyB12aM8wWf4r8qSVKtJrb8g07UGD2GMMgneMHBfTH4gGXyhoFjAN+iGt p1drHioduYq0YzgxW7wNRj5CCGuhH87gmQJtsql/PQSVNihPMPtZwtYncXcuKpZAVBbd+Seos9C 46VhcV+Z4mQiOv+tCg6BtWaYTaFaLoiEa2c8a4e3mhQjTfAmQUYndpQBAbqLvLXFewQzqifShj9 w6WNQ54RZdDKNUD0NJR58fza4YxhtexIRBmy5TvnNMdEUwYeH0lNFFlyi2g3JsC2IcbyxP171wt JHyMBZZsMkcNhEyHFWA== X-Proofpoint-GUID: JKUsrU9zitM7lBoEqtmEQLTmWQmA-q-L X-Authority-Analysis: v=2.4 cv=Yrc/gYYX c=1 sm=1 tr=0 ts=6a90794b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=HzFHdt0s4hRtsg76xsUA:9 a=n-z2q6p6VjFlOU1q:21 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: JKUsrU9zitM7lBoEqtmEQLTmWQmA-q-L X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX67cJYp9UNT02 R+5MYwH7fuYVMzAtjj/OwaBVVEFExvZFiqjUbtxy5BZDLgaWPkt32Ywd249TCSc+dlTkPQj0pr2 mrgpwpf1nOD+yse87JtxijPJfPZdKLs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Document the RPMh-based Network-on-Chip interconnect providers and associated node-ID definitions for the Qualcomm Kuno SoC. Signed-off-by: Hardeep Sharma Reviewed-by: Krzysztof Kozlowski --- .../bindings/interconnect/qcom,kuno-rpmh.yaml | 118 +++++++++++++++++= ++++ include/dt-bindings/interconnect/qcom,kuno.h | 89 ++++++++++++++++ 2 files changed, 207 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.= yaml b/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml new file mode 100644 index 000000000000..20d169b31142 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,kuno-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Kuno SoC + +maintainers: + - Hardeep Sharma + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provide= r is + able to communicate with the BCM through the Resource State Coordinator = (RSC) + associated with each execution environment. Provider nodes must point to= at + least one RPMh device child node pertaining to their RSC and each provid= er + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,kuno.h + +properties: + compatible: + enum: + - qcom,kuno-aggre-noc + - qcom,kuno-clk-virt + - qcom,kuno-cnoc-main + - qcom,kuno-dc-noc + - qcom,kuno-mc-virt + - qcom,kuno-mem-noc + - qcom,kuno-pcie-anoc + - qcom,kuno-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,kuno-clk-virt + - qcom,kuno-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + const: qcom,kuno-aggre-noc + then: + properties: + clocks: + items: + - description: System NoC USB SF AXI clock + - description: IPA clock + + - if: + properties: + compatible: + contains: + const: qcom,kuno-system-noc + then: + properties: + clocks: + items: + - description: IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,kuno-aggre-noc + - qcom,kuno-system-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clk_virt: interconnect-0 { + compatible =3D "qcom,kuno-clk-virt"; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@1640000 { + compatible =3D "qcom,kuno-aggre-noc"; + reg =3D <0x01640000 0x33400>; + clocks =3D <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; +... diff --git a/include/dt-bindings/interconnect/qcom,kuno.h b/include/dt-bind= ings/interconnect/qcom,kuno.h new file mode 100644 index 000000000000..eacbae38f85d --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,kuno.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H + +#define MASTER_SYS_TCU 0 +#define MASTER_LLCC 1 +#define MASTER_AUDIO 2 +#define MASTER_CPUCP 3 +#define MASTER_PCIE_RSCC 4 +#define MASTER_QDSS_BAM 5 +#define MASTER_QPIC 6 +#define MASTER_QUP_0 7 +#define MASTER_ANOC_SNOC 8 +#define MASTER_CNOC_DC_NOC 9 +#define MASTER_CNOC_SNOC 10 +#define MASTER_MSS_PROC 11 +#define MASTER_GEM_NOC_CFG 12 +#define MASTER_GEM_NOC_CNOC 13 +#define MASTER_GEM_NOC_PCIE_SNOC 14 +#define MASTER_ANOC_PCIE_GEM_NOC 15 +#define MASTER_SNOC_SF_MEM_NOC 16 +#define MASTER_QUP_CORE_0 17 +#define MASTER_CRYPTO 18 +#define MASTER_IPA 19 +#define MASTER_MSS_NAV 20 +#define MASTER_TME 21 +#define MASTER_APPSS_PROC 22 +#define MASTER_EMAC 23 +#define MASTER_IPA_PCIE 24 +#define MASTER_PCIE_0 25 +#define MASTER_QDSS_DAP 26 +#define MASTER_QDSS_ETR 27 +#define MASTER_QDSS_ETR_1 28 +#define MASTER_SDCC_4 29 +#define MASTER_USB3_0 30 +#define SLAVE_EBI1 31 +#define SLAVE_AHB2PHY 32 +#define SLAVE_AOSS 33 +#define SLAVE_APPSS 34 +#define SLAVE_AUDIO 35 +#define SLAVE_CLK_CTL 36 +#define SLAVE_RBCPR_CX_CFG 37 +#define SLAVE_RBCPR_MXA_CFG 38 +#define SLAVE_RBCPR_MXC_CFG 39 +#define SLAVE_CRYPTO_0_CFG 40 +#define SLAVE_EMAC_CFG 41 +#define SLAVE_IMEM_CFG 42 +#define SLAVE_IPA_CFG 43 +#define SLAVE_IPC_ROUTER_CFG 44 +#define SLAVE_LAGG_CFG 45 +#define SLAVE_MCCC_MASTER 46 +#define SLAVE_CNOC_MSS 47 +#define SLAVE_PCIE_0_CFG 48 +#define SLAVE_PCIE_RSC_CFG 49 +#define SLAVE_PDM 50 +#define SLAVE_PMU_WRAPPER_CFG 51 +#define SLAVE_PRNG 52 +#define SLAVE_QDSS_CFG 53 +#define SLAVE_QPIC 54 +#define SLAVE_QUP_0 55 +#define SLAVE_SDCC_4 56 +#define SLAVE_SPMI_VGI_COEX 57 +#define SLAVE_TCSR 58 +#define SLAVE_TLMM 59 +#define SLAVE_TME_CFG 60 +#define SLAVE_USB3 61 +#define SLAVE_VSENSE_CTRL_CFG 62 +#define SLAVE_A1NOC_CFG 63 +#define SLAVE_DDRSS_CFG 64 +#define SLAVE_LLCC 65 +#define SLAVE_GEM_NOC_CNOC 66 +#define SLAVE_SNOC_MEM_NOC_SF 67 +#define SLAVE_MEM_NOC_PCIE_SNOC 68 +#define SLAVE_ANOC_PCIE_GEM_NOC 69 +#define SLAVE_SNOC_CNOC 70 +#define SLAVE_ANOC_THROTTLE_CFG 71 +#define SLAVE_QUP_CORE_0 72 +#define SLAVE_BOOT_IMEM 73 +#define SLAVE_IMEM 74 +#define SLAVE_SERVICE_GEM_NOC 75 +#define SLAVE_PCIE_0 76 +#define SLAVE_QDSS_STM 77 +#define SLAVE_TCU 78 + +#endif --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A9DF4A2E1F for ; Thu, 27 Aug 2026 17:52:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853142; cv=none; b=cIVShLu3s92mMYaN9ABTiku7YGlH5WUppUDTGHshUgFs05wBRvEIbRqD3h8bTF3A5fMYdERONaDyLvyl+PINBaaOLf5i1zFYkuwojmqsbgIgdwTgUThG3Ber3bOfLFt04jZawlI1T/+BzWwehFK0yJfNnT9OFcZ0GAUBhAVChq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853142; c=relaxed/simple; bh=YMt01tffizd/QItWpTO+o5zLFgJYC/uKbLx8J6+OhjU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G1ltp8z/R57DuXwOIJVo7ZOf5Ael7FU7NqMy2JzU2V1DaFp53l/klp5lmZST4gzbzcbAC2Bsav90GQEq4jByOhneVHMZfaYaIVL5cDd50yYougdivNfq0et1llbTT031PFgOBhEXzsyyPPM13Hbh7HdR8U77ezls81JIz74Q5sU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=pfSosTIe; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bUimL7/G; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="pfSosTIe"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bUimL7/G" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXein1568365 for ; Thu, 27 Aug 2026 17:52:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jaxPBtFt4fSnEV+87SUaJLo7bEl7ueivESahSDtJv3A=; b=pfSosTIeR3+AJfOT +X+WS0OWGOxFAABznH5fseaD4huEbu2h3sBif7nX/5m4DaENEfY2RIBA4EsN8NGQ 5ZeZs+Aa5Z6GoAZk7HdemcBwsxzkhb6Ijh3YCq+YxZjtH9lUIxTBXJyejkfLs6PN 6ViSLhzpKZtQ4eXxS7c5d6wIWfzd49AsNsX2CvE4FJHTtfMSb9WGT/hDzN6Z+khW +Pb4toV313SJX1C71fuoo+VhUkP+K43CFRZ/j3aPVtG5D3SkvBBT70726oJUL8kR eq+7RC9jSZF8w+On6v/V3XjSDgOJSuUC9W0ovLPDU26hiqTO8mnNu0OY3ZuiXkGT 9896qA== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ga8m5m9tk-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:19 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cb48f41343aso1097072a12.1 for ; Thu, 27 Aug 2026 10:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853138; x=1788457938; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=jaxPBtFt4fSnEV+87SUaJLo7bEl7ueivESahSDtJv3A=; b=bUimL7/GCDdY80HgK91ZcoUer16iR5GGbSwnwvfSCEuavNF1cUieL90Zzaju8PtukP egY+2vPO8ly/OjzEJ6rViIJclQjb1JWfjO74sNN91wXql64dcJGBCVkdFki7wdBxpI8G 0kz+wxEfB7Afp32LnIPZ2q5k7gdq6rlLzqRUHXRLcLyO9CIbo7cyX+2cxAmep+mjI7xD HOBNQ6rd9ldZ+cXO05Mr4j+K2U69OVjU2EidMrYZYtyLAenmzk6+N32WC18iha185UDy q/Nhc4sso6jraviS8HYPnEdO7Ob3nolY1lBzuditPRoDJMOgDKIZZ5abv+SrlaB9hxpK QIZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853138; x=1788457938; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=jaxPBtFt4fSnEV+87SUaJLo7bEl7ueivESahSDtJv3A=; b=k9/yH/cCWzzqAyvArLnB9O6f6EtkylPstdISON9HC8fnRJ63Bg07Nn8KAiG5D/QPZp JG+vJMQiXJ1sQ4GC8okskRD6QIOl/K+FoS8P8fJGACiuM2UzdSEEp6L24VUceXLAEuxF s4kE1JYIjw6NJiHOmQNMinY5uqn4RkKLxD0P4J7smGsUmqOKVvlo7hthpn949WIQkDKQ im6i3mWE49U+n58rmWh5BZvAVS9LMBfBV7A3stXpAclbZqpJpo3ESB+CqqSN9Hdx3rv8 AYOGIQdL+6QXgfRZXtl3yaHzzqPCASFv5iy8+M1Nk8CapFccIq0vnwzP0crzYfg6ttsk g7/A== X-Forwarded-Encrypted: i=1; AHgh+RowmRlUWXfM/zhCzId3n5czL6tB513QEVFsAoGBGeS7upJOChx7HeNaC0fg4+eO4abdwsbZTQZFP9OQ9mA=@vger.kernel.org X-Gm-Message-State: AFuF++mXzaruyM6O/puxWs5sEvHQLJnZWrshUV1DnjqZosnbbLmF7eSR /wXEIdKcjcISMM46iu2QVdQj57soJFHeJJcWO/gUhiD2zkOxP98jwVQhsoki5pzafe0w2pfxwbU Gzwql9K2OcEyK7OJHmd/Ta+r2Lc0XKu7AqGzrKRK7N8D6BHXzuf0HRgSctWvPInbgyFA= X-Gm-Gg: AR+sD118q1fybsd8Dk6PQT2KQyUqYsLDO0kjO28Rc+7RntzGtTHHUN0IQ59O3jSYUw6 LpekvD9P4vere5/OKLx3suhTLrsAAUG+AbqfbwFJVc6mqpqswyUAh40cIl1i8tPNPFW7g7L1ImQ N9wzHF2o+z3j/wy1lu9JqGi3nLXFZeZlbRPz2dOjuTHc2lPHhDR9IGebdaOkpIiwVWR263GDUho RLsY6sN7Krx2c55lvmDrFDiDlSqmbjUwKjOo/nhFmvjENzr6+kw70ecGZR4MD9K6pS1VNlHSwcB Xa6CyT4mTe1zokLFCrpYaxeNmVL2v4S/9gUuFubhqH858F26v+Jo5wP0wpg41SN1rE+5zf2MNIM lKOxHuKEQ0P8GuU2sUwsIUNEpCVBQULiTSE5PjE8nHw9fGAK0/nXhJceGZu60zvW1V2eWDuJwVi Etoj0ic4pUVZoyn4WlhThoKB0= X-Received: by 2002:a17:902:ccd0:b0:2bd:2c3a:2a36 with SMTP id d9443c01a7336-2d725acf14bmr118142065ad.0.1787853137993; Thu, 27 Aug 2026 10:52:17 -0700 (PDT) X-Received: by 2002:a17:902:ccd0:b0:2bd:2c3a:2a36 with SMTP id d9443c01a7336-2d725acf14bmr118141065ad.0.1787853137297; Thu, 27 Aug 2026 10:52:17 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:16 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:10 +0530 Subject: [PATCH v5 07/15] interconnect: qcom: Add Kuno interconnect provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-7-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Konrad Dybcio X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=26248; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=YMt01tffizd/QItWpTO+o5zLFgJYC/uKbLx8J6+OhjU=; b=ed16eX5eoBEmlws7H22FMrtq/dmMIsDQL997wU7pD7bv7gjuqvjgHFI7ORZifjQfqGoXabPjZ cKOsNlWHleuBQC7rBM25eKgHQNb67iQnRRY4s0GHy0om3x+rwxbMA8K X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-ORIG-GUID: kEqEOStctP3RH-7DOMD_qQJnBI6lzr4G X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfXxxKS+DaaJjEM FvP5aSbOJ/rhDKZ8mhPavkSgp7EerrDK0uj3QtZpYbFwMhbNH07sif/4WrOSvoeEYnuLus1kaSF UqyIrU6zUDMDV+3+Ltun2j6dwBEmVWY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX+crXEKfsH6Pb /8cxFqLb0coXB6uK0FVGlOVPsNqnaTRhRZcVumTd8yjFvZDagly9BO7OYa1bvm7xuGiwLEBo0Sj GfG0t4+JOPsX/tW8+DTJuuSbnpl0mP6kaZ1G5KCMAMaItF+WaI04oA1HoC1MqSNH+HSCh5l/MRz rRFBeMIDIbOJlYh0IikvQkXgYtLnxpPafbQE01d9Cm3WvLToEcjPq7lQHpF082ADwZxeeqW82eS kmsz32sYXwwN+NsIU/2EJyVbrBLfZ2M7zcgzG1VxPww54fUAE4UzvGBuJwVbVn0Xbow81O3DFe7 n0slvtQnUT+aMroEPYjUO/CfWuJR14SU1rcB0kC0k7G5TdHH5WJBA3VvnGfYXwD4rbt7pa1T/uZ HhzNHlWuhnh+Bnf+DkwVU8li//Gbl+BeHg3mDL+uhjcsnqOhwVdP8faArviD+reSMn72samqAl6 QhyHZdHMYbJ+vIV8l5Q== X-Proofpoint-GUID: kEqEOStctP3RH-7DOMD_qQJnBI6lzr4G X-Authority-Analysis: v=2.4 cv=SomgLvO0 c=1 sm=1 tr=0 ts=6a907953 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=hP8eNrtOcc-Xm2DFYy4A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Add the interconnect provider driver for the Qualcomm Kuno SoC to enable bus bandwidth voting on the platform. This includes the aggre-noc and cnoc-main NoC instances with their associated BCM nodes. Reviewed-by: Konrad Dybcio Signed-off-by: Hardeep Sharma Reviewed-by: Abel Vesa --- drivers/interconnect/qcom/Kconfig | 13 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/kuno.c | 988 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1003 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index b3187acf90b8..6e6b80f22dbd 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -47,6 +47,19 @@ config INTERCONNECT_QCOM_KAANAPALI This is a driver for the Qualcomm Network-on-Chip on kaanapali-based platforms. =20 +config INTERCONNECT_QCOM_KUNO + tristate "Qualcomm Kuno interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + depends on ARM || COMPILE_TEST + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + default ARCH_QCOM + help + This is a driver for the Qualcomm Network-on-Chip on kuno-based + platforms. The interconnect provider collects and aggregates the + consumer bandwidth requests to satisfy constraints placed on the + Network-on-Chip performance states. + config INTERCONNECT_QCOM_MAILI tristate "Qualcomm MAILI interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 5f139a370bbe..a71478aaf591 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -8,6 +8,7 @@ qnoc-eliza-objs :=3D eliza.o qnoc-glymur-objs :=3D glymur.o qnoc-hawi-objs :=3D hawi.o qnoc-kaanapali-objs :=3D kaanapali.o +qnoc-kuno-objs :=3D kuno.o qnoc-maili-objs :=3D maili.o qnoc-milos-objs :=3D milos.o qnoc-msm8909-objs :=3D msm8909.o @@ -57,6 +58,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) +=3D qnoc-eliza.o obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) +=3D qnoc-glymur.o obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) +=3D qnoc-hawi.o obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) +=3D qnoc-kaanapali.o +obj-$(CONFIG_INTERCONNECT_QCOM_KUNO) +=3D qnoc-kuno.o obj-$(CONFIG_INTERCONNECT_QCOM_MAILI) +=3D qnoc-maili.o obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) +=3D qnoc-milos.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o diff --git a/drivers/interconnect/qcom/kuno.c b/drivers/interconnect/qcom/k= uno.c new file mode 100644 index 000000000000..546622cf8cea --- /dev/null +++ b/drivers/interconnect/qcom/kuno.c @@ -0,0 +1,988 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2_phy =3D { + .name =3D "qhs_ahb2_phy", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_audio =3D { + .name =3D "qhs_audio", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_mxa =3D { + .name =3D "qhs_cpr_mxa", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_mxc =3D { + .name =3D "qhs_cpr_mxc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_crypto_cfg =3D { + .name =3D "qhs_crypto_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_emac0_cfg =3D { + .name =3D "qhs_emac0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie_rscc =3D { + .name =3D "qhs_pcie_rscc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pmu_wrapper_cfg =3D { + .name =3D "qhs_pmu_wrapper_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qpic =3D { + .name =3D "qhs_qpic", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex =3D { + .name =3D "qhs_spmi_vgi_coex", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .name =3D "qhs_usb3", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_anoc_throttle_cfg =3D { + .name =3D "qss_anoc_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qxs_boot_imem =3D { + .name =3D "qxs_boot_imem", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_lagg =3D { + .name =3D "qhs_lagg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_mccc_master =3D { + .name =3D "qhs_mccc_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node srvc_memnoc =3D { + .name =3D "srvc_memnoc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .link_nodes =3D { &qhs_lagg, &qhs_mccc_master }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &ebi }, +}; + +static struct qcom_icc_node qnm_memnoc_cfg =3D { + .name =3D "qnm_memnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &srvc_memnoc }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie =3D { + .name =3D "qnm_memnoc_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &xs_pcie_0 }, +}; + +static struct qcom_icc_node xm_ipa2pcie =3D { + .name =3D "xm_ipa2pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &xs_pcie_0 }, +}; + +static struct qcom_icc_node qns_ddrss_cfg =3D { + .name =3D "qns_ddrss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qnm_cnoc }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_node qhm_pcie_rscc =3D { + .name =3D "qhm_pcie_rscc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 34, + .link_nodes =3D { &qhs_ahb2_phy, &qhs_aoss, + &qhs_apss, &qhs_audio, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto_cfg, &qhs_emac0_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie0_cfg, &qhs_pdm, + &qhs_pmu_wrapper_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_usb3, &qhs_vsense_ctrl_cfg, + &qns_ddrss_cfg, &qss_anoc_throttle_cfg, + &qxs_boot_imem, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_memnoc_cnoc =3D { + .name =3D "qnm_memnoc_cnoc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 35, + .link_nodes =3D { &qhs_ahb2_phy, &qhs_aoss, + &qhs_apss, &qhs_audio, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto_cfg, &qhs_emac0_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie0_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_pmu_wrapper_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3, + &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg, + &qss_anoc_throttle_cfg, &qxs_boot_imem, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qns_memnoc_cnoc =3D { + .name =3D "qns_memnoc_cnoc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_memnoc_cnoc }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc }, +}; + +static struct qcom_icc_node qnm_mdsp =3D { + .name =3D "qnm_mdsp", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc }, +}; + +static struct qcom_icc_node xm_apps0 =3D { + .name =3D "xm_apps0", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc, + &qns_pcie }, +}; + +static struct qcom_icc_node qns_pcie_memnoc =3D { + .name =3D "qns_pcie_memnoc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_memnoc_sf =3D { + .name =3D "qns_memnoc_sf", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_memnoc }, +}; + +static struct qcom_icc_node qhm_cpucp =3D { + .name =3D "qhm_cpucp", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_memnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre_noc =3D { + .name =3D "qnm_aggre_noc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qnm_cnoc_datapath =3D { + .name =3D "qnm_cnoc_datapath", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qxm_mss_nav_ce =3D { + .name =3D "qxm_mss_nav_ce", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qxm_tme =3D { + .name =3D "qxm_tme", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qns_a1noc =3D { + .name =3D "qns_a1noc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre_noc }, +}; + +static struct qcom_icc_node qns_snoc_datapath =3D { + .name =3D "qns_snoc_datapath", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qnm_cnoc_datapath }, +}; + +static struct qcom_icc_node qhm_audio =3D { + .name =3D "qhm_audio", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qhm_qpic =3D { + .name =3D "qhm_qpic", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_emac_0 =3D { + .name =3D "xm_emac_0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_qdss_etr0 =3D { + .name =3D "xm_qdss_etr0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_qdss_etr1 =3D { + .name =3D "xm_qdss_etr1", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_usb3 =3D { + .name =3D "xm_usb3", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 36, + .link_nodes =3D { &qhs_ahb2_phy, &qhs_aoss, + &qhs_apss, &qhs_audio, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto_cfg, &qhs_emac0_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie0_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_pmu_wrapper_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3, + &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg, + &qns_snoc_datapath, &qss_anoc_throttle_cfg, + &qxs_boot_imem, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .enable_mask =3D 0x8, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .enable_mask =3D 0x1, + .num_nodes =3D 39, + .nodes =3D { &qhm_pcie_rscc, &qnm_memnoc_cnoc, + &xm_qdss_dap, &qhs_ahb2_phy, + &qhs_aoss, &qhs_apss, + &qhs_audio, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_crypto_cfg, + &qhs_emac0_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_pcie0_cfg, + &qhs_pcie_rscc, &qhs_pdm, + &qhs_pmu_wrapper_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_usb3, &qhs_vsense_ctrl_cfg, + &qns_ddrss_cfg, &qns_snoc_datapath, + &qss_anoc_throttle_cfg, &qxs_boot_imem, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D 0x1, + .num_nodes =3D 2, + .nodes =3D { &qns_memnoc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .enable_mask =3D 0x1, + .num_nodes =3D 1, + .nodes =3D { &xm_pcie3_0 }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 2, + .nodes =3D { &qns_a1noc, &qnm_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .num_nodes =3D 1, + .nodes =3D { &qxm_mss_nav_ce }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .num_nodes =3D 1, + .nodes =3D { &xs_pcie_0 }, +}; + +static struct qcom_icc_bcm * const aggre_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre_noc_nodes[] =3D { + [MASTER_AUDIO] =3D &qhm_audio, + [MASTER_QDSS_BAM] =3D &qhm_qdss_bam, + [MASTER_QPIC] =3D &qhm_qpic, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_EMAC] =3D &xm_emac_0, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr1, + [MASTER_SDCC_4] =3D &xm_sdc4, + [MASTER_USB3_0] =3D &xm_usb3, + [SLAVE_A1NOC_CFG] =3D &qns_a1noc, +}; + +static const struct qcom_icc_desc kuno_aggre_noc =3D { + .nodes =3D aggre_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre_noc_nodes), + .bcms =3D aggre_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup0, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, +}; + +static const struct qcom_icc_desc kuno_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_PCIE_RSCC] =3D &qhm_pcie_rscc, + [MASTER_GEM_NOC_CNOC] =3D &qnm_memnoc_cnoc, + [MASTER_QDSS_DAP] =3D &xm_qdss_dap, + [SLAVE_AHB2PHY] =3D &qhs_ahb2_phy, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_APPSS] =3D &qhs_apss, + [SLAVE_AUDIO] =3D &qhs_audio, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] =3D &qhs_cpr_cx, + [SLAVE_RBCPR_MXA_CFG] =3D &qhs_cpr_mxa, + [SLAVE_RBCPR_MXC_CFG] =3D &qhs_cpr_mxc, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto_cfg, + [SLAVE_EMAC_CFG] =3D &qhs_emac0_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_CNOC_MSS] =3D &qhs_mss_cfg, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_RSC_CFG] =3D &qhs_pcie_rscc, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PMU_WRAPPER_CFG] =3D &qhs_pmu_wrapper_cfg, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QPIC] =3D &qhs_qpic, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_SDCC_4] =3D &qhs_sdc4, + [SLAVE_SPMI_VGI_COEX] =3D &qhs_spmi_vgi_coex, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_USB3] =3D &qhs_usb3, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_DDRSS_CFG] =3D &qns_ddrss_cfg, + [SLAVE_SNOC_CNOC] =3D &qns_snoc_datapath, + [SLAVE_ANOC_THROTTLE_CFG] =3D &qss_anoc_throttle_cfg, + [SLAVE_BOOT_IMEM] =3D &qxs_boot_imem, + [SLAVE_IMEM] =3D &qxs_imem, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc kuno_cnoc_main =3D { + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_node * const dc_noc_nodes[] =3D { + [MASTER_CNOC_DC_NOC] =3D &qnm_cnoc, + [SLAVE_LAGG_CFG] =3D &qhs_lagg, + [SLAVE_MCCC_MASTER] =3D &qhs_mccc_master, +}; + +static const struct qcom_icc_desc kuno_dc_noc =3D { + .nodes =3D dc_noc_nodes, + .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc kuno_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mem_noc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const mem_noc_nodes[] =3D { + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_MSS_PROC] =3D &qnm_mdsp, + [MASTER_GEM_NOC_CFG] =3D &qnm_memnoc_cfg, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_APPSS_PROC] =3D &xm_apps0, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_GEM_NOC_CNOC] =3D &qns_memnoc_cnoc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, + [SLAVE_SERVICE_GEM_NOC] =3D &srvc_memnoc, +}; + +static const struct qcom_icc_desc kuno_mem_noc =3D { + .nodes =3D mem_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), + .bcms =3D mem_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mem_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { + &bcm_sn1, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] =3D { + [MASTER_PCIE_0] =3D &xm_pcie3_0, + [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_memnoc, +}; + +static const struct qcom_icc_desc kuno_pcie_anoc =3D { + .nodes =3D pcie_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), + .bcms =3D pcie_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn2, + &bcm_sn4, + &bcm_sn7, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_CPUCP] =3D &qhm_cpucp, + [MASTER_ANOC_SNOC] =3D &qnm_aggre_noc, + [MASTER_CNOC_SNOC] =3D &qnm_cnoc_datapath, + [MASTER_GEM_NOC_PCIE_SNOC] =3D &qnm_memnoc_pcie, + [MASTER_MSS_NAV] =3D &qxm_mss_nav_ce, + [MASTER_TME] =3D &qxm_tme, + [MASTER_IPA_PCIE] =3D &xm_ipa2pcie, + [SLAVE_SNOC_MEM_NOC_SF] =3D &qns_memnoc_sf, + [SLAVE_PCIE_0] =3D &xs_pcie_0, +}; + +static const struct qcom_icc_desc kuno_system_noc =3D { + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,kuno-aggre-noc", .data =3D &kuno_aggre_noc }, + { .compatible =3D "qcom,kuno-clk-virt", .data =3D &kuno_clk_virt }, + { .compatible =3D "qcom,kuno-cnoc-main", .data =3D &kuno_cnoc_main }, + { .compatible =3D "qcom,kuno-dc-noc", .data =3D &kuno_dc_noc }, + { .compatible =3D "qcom,kuno-mc-virt", .data =3D &kuno_mc_virt }, + { .compatible =3D "qcom,kuno-mem-noc", .data =3D &kuno_mem_noc }, + { .compatible =3D "qcom,kuno-pcie-anoc", .data =3D &kuno_pcie_anoc }, + { .compatible =3D "qcom,kuno-system-noc", .data =3D &kuno_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-kuno", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Kuno NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CE194B0480 for ; Thu, 27 Aug 2026 17:52:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853150; cv=none; b=g6mlxF+O7elh+MU2omJeBE0NIKR6uSla3MX4e+v7h44YPJ60rvV21qeCRaotzbKfmvEMzkSerSPC/4TPUreOEeZ30atix8p+GmHT/ArfN7O09ed6QIHHo4ckvuL9Ez9QYUYVf6Y6ATGu5Ad6ZRSZEloMx6xVo+wPwVXbRBKgBJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853150; c=relaxed/simple; bh=9Fecwe0sAktGee+deC69QVwT+mIH7oP8T6NEsor/Km4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RmWCiR06sbtJEriU1L6yCUM+ObPkGAl3oYIgQatKmYYArHvE2moZsttAHu1WYVhgrxe4RsjCHnlVTFHhd/2YOOdLfQlsxufM5SJxaHrBDzApy+Tt8vyeFcOS1e9p6g2dhXzunn93AIHqHdO0XeBXrSJDlx9ik40Lln5MPP1ArKs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=bOhbLiwn; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=OnrtjMNM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="bOhbLiwn"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="OnrtjMNM" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXcUJ873673 for ; Thu, 27 Aug 2026 17:52:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= yS6bCkgNl2tfRL+N0AQpU6w6x0P3yKp8A+VMwA4EIUo=; b=bOhbLiwnothWZ6J1 2k3OkBYm24gbYy7eH0y5xykv8V4Hh9DyGa1BsJkCUeMEt0owX11la+1aiTwRrWfV GFm/v6SA6mz7JHHuouJXS5aNYay5xcGk1QWF9g66GmfXxuEQiJGoSeAB/lAywKG7 2VG/4jRJzIB9w5kxqoUjg2Z4ezrJs1+wggnugypTvql4jJz4gTHfP/o/0/lJel2+ IjZxBemVfxU0WSXQdhACi4XZS2E1sk+WvVhF9TQ91GIng0RoX5pCQT+/cK4gtCRC G7Sjswly7Kr3mCkjDokOnW5bwNTIkWzCYakbZ5s261rDCxCUf2h6BcS9E0K93Kbn CDgSpg== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4garn0gfga-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:27 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2d6f75c1219so1681475ad.3 for ; Thu, 27 Aug 2026 10:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853146; x=1788457946; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=yS6bCkgNl2tfRL+N0AQpU6w6x0P3yKp8A+VMwA4EIUo=; b=OnrtjMNMjKgz2ew2uAXjgo6GL1d7ylfvcpTGq0KushF/Rr7fv/SpOLMEjkkRBCHjRd UtdCiQzS0Uv79Fy+nxFiKfuiv1tgDa7+09GuBTf54IdcdRWVkQP5T7DmKfW4CalEy5Ck wWFXRVERkZsU50tH8jioqmR5QD9d4Unx7bHtuC5mr42stuhx5uF0Z0S/SaA3u2qLG+8V 3FzCcaqX9QdBs3ObubzVlvS+cYfi5gI4BagcWT3NLYYXWYV7RO3hJuvRYIfDDMRZeJva Gva5lSKVaKknBcF9MQMwUy9D7sL595NR6XRar3Q/mTxYG+FTHgDsCmVoNYUoi+tWPczg It8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853146; x=1788457946; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=yS6bCkgNl2tfRL+N0AQpU6w6x0P3yKp8A+VMwA4EIUo=; b=rIFebW77WdatReMrmvdUiA5pSWiNc6btTC6eoUlnB0qRVWiGRmdtX+ndu1JGRjkYc6 GNp57vmSef/a7uuq5s5EBKfybOifvzKqqDuUSgQIBd5aUFqxLhXE6l/5BS8Nu7R2TZIL BnoVUv/++RyPXmkQVORHO6zw9gO+dpAjbGUwy30XZRTimCSloJg3w2UcZuDvN5ui1aOh eS9gbzPNGg2wZfk3wGmozLjkq6zyzjDOcqhg9d3NtkYRICo99H+3SfZAggcZGcaLIyCb +yYsyWevmGx63OmbYVJQpK9J2V7DaarjmgqXECc6Ef+Yh27ZDx9OzHNGuPYdhfYlx4jn HZng== X-Forwarded-Encrypted: i=1; AHgh+Rq3kBVNlEmL8Bza6J2moWlbnO6pb+FcWvCewi97Cc7JS1xX+ImvAa4+dFz55by+HiHs4vQ0vjX6KjnV3ZU=@vger.kernel.org X-Gm-Message-State: AFuF++kGdIpEjpYQfuAkvbBnqQs5t7fv0M8AMqakHgOuGTPNhoXD1fRk gFJOQFJ6IgqA+jS5u9uE00sn76FMVdWDpDlpHi4Eo9l9J8osQltckUN8iP1PmvVTuQ9k4mOyhsQ TiJ0vsBtjpD9tNqEhkjaG3RomVXufUj+Nc7abUC9gT4Df7wmr+Y6N26dWmbasy5gqSRc= X-Gm-Gg: AR+sD12UD0iH8f9ctMzNhuszyU2SAwnyKoGo0i/lWIFOHmO52VMxWHbYm7wnkO9+KoA LXyYsAnGLgllPS5nweEU5osqCFh4AY+K2CcVC0DnUZPT24Jn8xNzcU1ukX1hyAp6bG3HoyIhHzU RRK+DlsCF7QhzrbNz0k/D0Kl4XNoj/lGOWgDaeXwCgTuUY0UcCRjSRGnOuawirRVM/omQBEiA6r 1cm++wg7Nd3smKBPgoj0sHKASzbGRZlJ0FvDZ8AgN49K/F1cWihnlkTdoCsBkXV8mom639cxkFP aIlHQ08VDcmJs5LfnjhclXhLMOEQOI/Yv3i4R7Z5LT4ezyOvhg2WY2culxGbHM3OJfycVZS0Wh7 DQXG/N0V/g2jOXVUAqOO9HjmmB3FRG3QTbX5K678lHzLiW7JrLqQVkggz7jPEmo+FFjJZ3gYO8D XWz+QejX+PhVYkQ0XFa2S3Z/A= X-Received: by 2002:a17:902:da8e:b0:2d6:f961:994f with SMTP id d9443c01a7336-2d74dc6f7b8mr9361645ad.8.1787853145925; Thu, 27 Aug 2026 10:52:25 -0700 (PDT) X-Received: by 2002:a17:902:da8e:b0:2d6:f961:994f with SMTP id d9443c01a7336-2d74dc6f7b8mr9360425ad.8.1787853145503; Thu, 27 Aug 2026 10:52:25 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:25 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:11 +0530 Subject: [PATCH v5 08/15] dt-bindings: pinctrl: qcom: Add Kuno TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-8-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=3999; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=9Fecwe0sAktGee+deC69QVwT+mIH7oP8T6NEsor/Km4=; b=40gNZMEgMelOIHYYXNXXlGFmvf9ZjPxiwH11wpQwtzUVtCDU7L4DEV22kqGX1adVRYLwKrdbm yEh8szJeuE5Am01zVrVRVneXZ/Gek/x8b4hBqCNRza3I9Bty24eGWU/ X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX7atKhAyELt4a 914CqVS94q/5FLWrU9IYTgHgASBb0+/LeeuKXaYl7VoEj1QQV/VhLdrbXQ8nZDh+Dezn3COHFVg mlVe+nfsiXRR+2sa1aVcct/VgUU7XBNulz0OJCmuxTBcKfMJFOGZ8dN6di8AJV99UGhiX3OSpJZ BMHO+wQCU4DcnrWeabRmgyz3tGWWUptBqRyBN7EBkuaAHkRZYkbi+11FtbJWRs8tkBuRF6yLU78 RhdvFhn6WShsobRBEwV3CWXUnlOH1gYls5rmxqLYM6edIbfICU8rpjTGTDaPR463CMuROZoRQ1V L4565h9iP3hKjqYPkwvf+rUufdSFcGCQ1sYEKF96HPDcBQq8T7amXdHXJKfV8aGcMsobqblzVVi LkZRFif+vsPFtNroj2Zu6tym8kLKPc29M7qs+seJBfEquQ+ls5W77mIMaDqcdnqkyu1/O8v8noW GEf6B1WFmjUK81KQHfg== X-Proofpoint-GUID: gZBJ6inFPUFzfDeyLRseQAQ7n1mI_hBR X-Authority-Analysis: v=2.4 cv=C+3ZDwP+ c=1 sm=1 tr=0 ts=6a90795b cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=CaveSyEksWnKhASb3GUA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: gZBJ6inFPUFzfDeyLRseQAQ7n1mI_hBR X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX4BchSPv/FB8C +WXGR1LujQ7F8v8xA25yNfPK3t+R0A2wX9LKWsOQOy+71oW9VsvpZRakEUzYTTFQZJjFWyV2g/z yXL7tvbLm3qyBIeQTlQ1/BEfaZ3qq3w= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Add device tree bindings for the Top Level Mode Multiplexer (TLMM) pin controller block found on the Qualcomm Kuno platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- .../bindings/pinctrl/qcom,kuno-tlmm.yaml | 110 +++++++++++++++++= ++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml = b/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml new file mode 100644 index 000000000000..2250526dfae2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kuno-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kuno TLMM block + +maintainers: + - Hardeep Sharma + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Kuno SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kuno-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 55 + + gpio-line-names: + maxItems: 110 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-kuno-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kuno-tlmm-state" + additionalProperties: false + +$defs: + qcom-kuno-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ gpio, audio_ref_clk, coex_uart, ebi2_lcd_a, + ebi2_lcd_cs, ebi2_lcd_reset, ebi2_lcd_te, emac_mdc, emac_m= dio, + emac_pps_in, emac_ptp_aux, emac_ptp_pps, gcc_gp1_clk, + gcc_gp2_clk, gcc_gp3_clk, mi2s0_data0, mi2s0_data1, mi2s0_= sck, + mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s_mclk, nav_gpio, pci_e_rst, + pcie_clkreq_n, pll_bist_sync, pll_clk_aux, qdss_cti_trig0, + qdss_cti_trig1, qdss_cti_trig1_mire, qdss_gpio_traceclk, + qdss_gpio_tracectl, + qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se3_mirb, + qup0_se4, sdc4_clk, sdc4_cmd, + sdc4_data, sdc4_tb_trig, sgmii_phy_intr, spmi_coex_clk, + spmi_coex_data, spmi_vgi_hwevent, uim1_clk, uim1_data, + uim1_present, uim1_reset, usb2phy_ac_en ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,kuno-tlmm"; + reg =3D <0x0f000000 0x400000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 110>; + interrupt-controller; + #interrupt-cells =3D <2>; + + spmi-state { + pins =3D "gpio78", "gpio79"; + function =3D "spmi_vgi_hwevent"; + }; + }; +... --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3C6D4A33FA for ; Thu, 27 Aug 2026 17:52:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853159; cv=none; b=d0ZMEJv2rZyK+oBniHLVVvNG+XVXoGb7e5imz8qwRW4F13JPEIvCdbpS3IZk8xaJ13RDuvuqV9Gwu2v+d3sns0TgU25W9ZS4nFM26qfFjzBO5qHP9hXi1PJHqmnKRAh8xZNf9fW8r/vukha3vmTYSesgG+WoyMAPQLvbIqObmY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853159; c=relaxed/simple; bh=6QBQCIqM/a1bmD7kAAxbFF82/u8Zimh6gYjhMTz+96k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XkXM6CwJHIAiphgRbM9VypSWJ16T8qttmc7gx8TBT92Z3HLU6s9iJKobqmsXoZSN1y6Flqddg4ExAm81Xx70nt/hej/H+Uyk5WXSiaYb0ko78qQaUQCjHnozkclx6xn64p7mGfdPRseBbBAkO96worsfGpNYu3rOP6yGVmv5+6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=TUOUuv2g; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=TV3e7IBM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="TUOUuv2g"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="TV3e7IBM" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXb5G419729 for ; Thu, 27 Aug 2026 17:52:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= U7EUxaoQIEL81uRqEWUifgLpo5UGdyj5xucqq/xWeeg=; b=TUOUuv2gQ9vk3uTn q6YRwChJg5WCWacBmMfKxvZs9s3Yasm9pKBtAvSSJN5CAZ+OHt1NlLbd2MCroAhp rDgZj5kwX0xnu0vj7NML6PeI/lJ8xbbljK8Z/29F7AeT3cT1kXLqMS4KgX5AJyyd Ca+6qZqEIrhtbxEHx4MVaYbFGN8NakRHtEcX7pNxFFcm2X1MXMToa0N/kyDZnOp0 xgSoIJ6YdJ4OPlt9SNWnirEibpnEBm5rmLAD7CVz94YgeIl9eoIjXZ4WYVUXfafy WFJDYipvLuQ2bVVsReUKMha/GNOtb5MxWVD066lu1DCMx2zzqmorUz3Sgc1EUGus ce7OvQ== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gagjftmb2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:35 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2ccb687f82eso1211175ad.3 for ; Thu, 27 Aug 2026 10:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853155; x=1788457955; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=U7EUxaoQIEL81uRqEWUifgLpo5UGdyj5xucqq/xWeeg=; b=TV3e7IBMUPH1inAHsh1S/EORD1YJov9aKhCzlMqPRL36fC9pL3ShjL/aSn5hQyCVPz PV2Zg3tglggA1TVZD7SOEQ5yEWuNq91E6YjEvwgKmP23rQZJyeZfirERrT8De/K4lNfT ecKxAkHsqqlwUeIUVlcA6oh5nl5Lu+m4kUND/k0UybTjho2p1bOJEmWHNdZdSRHYHZ2g m4MLPv/RiPMoeICcBFywQDVrDxAAAo7Zzu+0WNwlay9YJdRFnjf1FQE+hUUBzS2A9RUI /n2C+9p7rvEkcarjpEbKI5tH0I4SwZqth/5tq6FO65td05fSMj3C6jsWcupKHjUkK8Zp aAbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853155; x=1788457955; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=U7EUxaoQIEL81uRqEWUifgLpo5UGdyj5xucqq/xWeeg=; b=qUMUJedVLDoQ6Ih+MKOXhCE2cFk04LBfDbXi1+tM9NyDzyuP8IQxL/5VF4n6hR2ytj lbQGAW+nVC+D5jy+8RMDwj5LEdXBN16pMoB/C6RD6ebkbZj1ZUvUl+emskDMpJ03Zi/A yupj5zRIYtZCDtVSf81IxZ3I7+jQS4+TZ95y3fIY8ES9d/3saMB9TpyRdZINZYRI4kKT sgdYb6G7V0Qgm5vmBHMfrrW6TkU3ypVHL830DTmQ5TeCD8RAnACmIkvlJ9ZIsTqlKJ60 mOeHeHIHR+eujZ7Lx9INvrn0l3yDzAbrJ0UWvAKDvxgJdBr/AB/ZqLYJC3O5AS+Rchyy 66og== X-Forwarded-Encrypted: i=1; AHgh+RqwiGX+rqygNZLJBrnbi4KIF5sv67WTBkH/4hXFtXDXMGcxNFTARzHCdSbj6VsZYGMYvvpUPqGqtdOofa8=@vger.kernel.org X-Gm-Message-State: AFuF++mulbCLV6tWNm+eKquB5IVB3IBNJbOtYaaJnzlEjl+gJH0chAvl K60GKi4CpZmGvvN5sB85Ni2SXzUOpU6h5Ew3mzlz2YGUrX/G783fbSedtheRvDMvlUs2x7FRzAK TwfjKpHp+sO/UnazOON2kU5nF4Vos5YYFo8v9mN8jVJPIO5Ep2YWrmR9cXn1l9aMnsBs= X-Gm-Gg: AR+sD120nHhfEbjrTGnV8Tr4EuAv6I37Rew3i28PALn1IErt49v+5j4ydloCmxyQT4a Y0/FfiuGMZeZwZ/RC4xuontrt6KGYrFJyDBiPKgylUu0MQ7ygg2O0jvtyd1b2bs50lj6CTrMGA1 w/HTIIctx9NjZMXGHSosM7Yqozl+9FwZg6LTrw0TAymkcAGYsSOQBLkA3wD427lxFVPjKzE9wC3 hiUwTB4Rm1KygctZBx/rTKcuG/ayzXAcPCaK2oOlS6Al4QK7/Orent8hOKBcWbI1aB0vVLBx5KE fi/1lNbyDpaCABoGs9r0waddZ27nWDFO+g+wHqkAH8M4zsZmsQDWBGfwFk8OP3Gw5real/3b+tm oFtqeYH+wOD2V4L/TwF6XjzoBtHHHdccM0pFoVXxxYZC9nRqDdWxQ7LxOpfS6SkKseByP4Nwwkc 48b6TkcAWKmpJXttHiIRwz9M8= X-Received: by 2002:a17:903:196b:b0:2d5:ccb7:12c3 with SMTP id d9443c01a7336-2d74dc2b30amr11993075ad.2.1787853154258; Thu, 27 Aug 2026 10:52:34 -0700 (PDT) X-Received: by 2002:a17:903:196b:b0:2d5:ccb7:12c3 with SMTP id d9443c01a7336-2d74dc2b30amr11991765ad.2.1787853153635; Thu, 27 Aug 2026 10:52:33 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:33 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:12 +0530 Subject: [PATCH v5 09/15] pinctrl: qcom: Add Kuno pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-9-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=28488; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=6QBQCIqM/a1bmD7kAAxbFF82/u8Zimh6gYjhMTz+96k=; b=7ZyUBFl89RcrC7t81xe2a0P74XRiEt6GAdCtIZuYlmgsh3N7/FxEfrpPdY2lWjHKgshZGm9qv GaHgTGhUoXCAENmpxc/tQgUZFlrcan8Ok6a0XAKpU5sBPx5T68OjRP7 X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-ORIG-GUID: Wa8vWKayKop7X6Zl3wf9TcWSBaQN3Lbj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfXyw0sPFvmnaAZ 5xLl/0DO+MS2GplhOfTxeDgpoTT+6rK/FtBZ88h+lfyDWNznJA3CkHKUCgBnQdYoPUVVl95USKM W8Z/FJybhSxr7dUpaQ5fkX5qVzZ+ut4pA7XoHs5BmiU/VgD8rq5XbVczIhrHMUwsbfIeCoprgIJ ECaW/lDtoQpnDH00J4rEzguZo9MD/8sgGhWJv9zlu/gUAaB0yei5ryNVFcM4ziPVpS7yauqZKhG 4CJLZ+VZg2jSNpELz1VV4ntgyMVaY+zEQNL30P3bv9IlpDTdh1Wrbt5cN/0T63AL0AAipVP1p1G Ak0XRcdjI8sNe6+2XarhTnh4yTdTEVhVPc6PC6SDXF6+0r4tolvP8JcNJVH2PW804KiCrBsrTOE nrJZmZQP34Q3Zo35bpGlGG4E3mRUdTPfsP5GaDB1wLQt4PX0NuMlhkpIslm+17B4Fz2s/GxX/Ri 8xjiIpSSjIHbEhen4CQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX/WdGWtKsgMMH p7c9nT+RTLC9ZSClgaTU6fF6dnUV0YxX3qnkpe/BjQsZz+n/SuUDr8MvfjGcN9DLvZPBjQmpJsp CLQXldRIAVtDvkDDlDgjYH7YeFF0Jx8= X-Proofpoint-GUID: Wa8vWKayKop7X6Zl3wf9TcWSBaQN3Lbj X-Authority-Analysis: v=2.4 cv=dd+wG3Xe c=1 sm=1 tr=0 ts=6a907963 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=O6wAMhyR-eLTh1z97CkA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 suspectscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Add the TLMM pinctrl driver for the Qualcomm Kuno platform, supporting 110 GPIOs and their pin multiplexing, pin configuration and gpiolib interface through the common pinctrl-msm driver. Signed-off-by: Hardeep Sharma Reviewed-by: Konrad Dybcio Reviewed-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig.msm | 11 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-kuno.c | 801 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 813 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 42875457b5fc..9b95bf8ecb22 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -153,6 +153,17 @@ config PINCTRL_KAANAPALI Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc Kaanapali platform. =20 +config PINCTRL_KUNO + tristate "Qualcomm Kuno pin controller driver" + depends on ARM || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc Kuno platform. + Say Y here to compile statically, or M here to compile it as a + module. If unsure, say N. + config PINCTRL_MAILI tristate "Qualcomm Technologies Inc Maili pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43ecd246afe8..f003add981ab 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_IPQ6018) +=3D pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) +=3D pinctrl-ipq9574.o obj-$(CONFIG_PINCTRL_IPQ9650) +=3D pinctrl-ipq9650.o obj-$(CONFIG_PINCTRL_KAANAPALI) +=3D pinctrl-kaanapali.o +obj-$(CONFIG_PINCTRL_KUNO) +=3D pinctrl-kuno.o obj-$(CONFIG_PINCTRL_MAILI) +=3D pinctrl-maili.o obj-$(CONFIG_PINCTRL_MSM8226) +=3D pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) +=3D pinctrl-msm8660.o diff --git a/drivers/pinctrl/qcom/pinctrl-kuno.c b/drivers/pinctrl/qcom/pin= ctrl-kuno.c new file mode 100644 index 000000000000..404065df2b9f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-kuno.c @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs =3D (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs =3D 10, \ + .ctl_reg =3D REG_BASE + REG_SIZE * id, \ + .io_reg =3D REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg =3D REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg =3D REG_BASE + 0xc + REG_SIZE * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 3, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + } + +static const struct pinctrl_pin_desc kuno_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); + +enum kuno_functions { + msm_mux_gpio, + msm_mux_audio_ref_clk, + msm_mux_coex_uart, + msm_mux_ebi2_lcd_a, + msm_mux_ebi2_lcd_cs, + msm_mux_ebi2_lcd_reset, + msm_mux_ebi2_lcd_te, + msm_mux_emac_mdc, + msm_mux_emac_mdio, + msm_mux_emac_pps_in, + msm_mux_emac_ptp_aux, + msm_mux_emac_ptp_pps, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s_mclk, + msm_mux_nav_gpio, + msm_mux_pci_e_rst, + msm_mux_pcie_clkreq_n, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_qdss_cti_trig0, + msm_mux_qdss_cti_trig1, + msm_mux_qdss_cti_trig1_mire, + msm_mux_qdss_gpio_traceclk, + msm_mux_qdss_gpio_tracectl, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3_mira, + msm_mux_qup0_se3_mirb, + msm_mux_qup0_se4, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sdc4_tb_trig, + msm_mux_sgmii_phy_intr, + msm_mux_spmi_coex_clk, + msm_mux_spmi_coex_data, + msm_mux_spmi_vgi_hwevent, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac_en, + msm_mux__, +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", +}; + +static const char * const audio_ref_clk_groups[] =3D { + "gpio62", +}; + +static const char * const coex_uart_groups[] =3D { + "gpio44", "gpio45", +}; + +static const char * const ebi2_lcd_a_groups[] =3D { + "gpio93", +}; + +static const char * const ebi2_lcd_cs_groups[] =3D { + "gpio94", +}; + +static const char * const ebi2_lcd_reset_groups[] =3D { + "gpio89", +}; + +static const char * const ebi2_lcd_te_groups[] =3D { + "gpio88", +}; + +static const char * const emac_mdc_groups[] =3D { + "gpio98", +}; + +static const char * const emac_mdio_groups[] =3D { + "gpio99", +}; + +static const char * const emac_pps_in_groups[] =3D { + "gpio88", +}; + +static const char * const emac_ptp_aux_groups[] =3D { + "gpio93", "gpio94", +}; + +static const char * const emac_ptp_pps_groups[] =3D { + "gpio93", "gpio94", +}; + +static const char * const gcc_gp1_clk_groups[] =3D { + "gpio34", +}; + +static const char * const gcc_gp2_clk_groups[] =3D { + "gpio46", +}; + +static const char * const gcc_gp3_clk_groups[] =3D { + "gpio35", +}; + +static const char * const mi2s0_data0_groups[] =3D { + "gpio13", +}; + +static const char * const mi2s0_data1_groups[] =3D { + "gpio14", +}; + +static const char * const mi2s0_sck_groups[] =3D { + "gpio15", +}; + +static const char * const mi2s0_ws_groups[] =3D { + "gpio12", +}; + +static const char * const mi2s1_data0_groups[] =3D { + "gpio17", +}; + +static const char * const mi2s1_data1_groups[] =3D { + "gpio18", +}; + +static const char * const mi2s1_sck_groups[] =3D { + "gpio19", +}; + +static const char * const mi2s1_ws_groups[] =3D { + "gpio16", +}; + +static const char * const mi2s_mclk_groups[] =3D { + "gpio62", +}; + +static const char * const nav_gpio_groups[] =3D { + "gpio31", "gpio32", "gpio33", +}; + +static const char * const pci_e_rst_groups[] =3D { + "gpio57", +}; + +static const char * const pcie_clkreq_n_groups[] =3D { + "gpio56", +}; + +static const char * const pll_bist_sync_groups[] =3D { + "gpio47", +}; + +static const char * const pll_clk_aux_groups[] =3D { + "gpio54", +}; + +static const char * const qdss_cti_trig0_groups[] =3D { + "gpio16", "gpio17", "gpio54", "gpio55", "gpio60", "gpio84", "gpio101", + "gpio102", +}; + +static const char * const qdss_cti_trig1_groups[] =3D { + "gpio16", "gpio17", "gpio54", "gpio55", "gpio65", "gpio66", "gpio101", + "gpio102", +}; +static const char * const qdss_cti_trig1_mire_groups[] =3D { + "gpio65", "gpio66", +}; + +static const char * const qdss_gpio_traceclk_groups[] =3D { + "gpio8", +}; + +static const char * const qdss_gpio_tracectl_groups[] =3D { + "gpio9", +}; + +static const char * const qup0_se0_groups[] =3D { + "gpio14", "gpio18", "gpio19", "gpio48", "gpio49", "gpio92", "gpio101", +}; + +static const char * const qup0_se1_groups[] =3D { + "gpio14", "gpio63", "gpio64", "gpio65", "gpio66", "gpio92", "gpio101", +}; + +static const char * const qup0_se2_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio14", "gpio92", "gpio101", +}; + +static const char * const qup0_se3_mira_groups[] =3D { + "gpio8", "gpio9", "gpio14", "gpio16", "gpio17", "gpio92", "gpio101", +}; + +static const char * const qup0_se3_mirb_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const qup0_se4_groups[] =3D { + "gpio10", "gpio11", "gpio14", "gpio80", "gpio81", "gpio92", "gpio101", +}; + +static const char * const sdc4_clk_groups[] =3D { + "gpio103", +}; + +static const char * const sdc4_cmd_groups[] =3D { + "gpio102", +}; + +static const char * const sdc4_data_groups[] =3D { + "gpio104", "gpio105", "gpio106", "gpio107", +}; + +static const char * const sdc4_tb_trig_groups[] =3D { + "gpio101", +}; + +static const char * const sgmii_phy_intr_groups[] =3D { + "gpio91", +}; + +static const char * const spmi_coex_clk_groups[] =3D { + "gpio76", +}; + +static const char * const spmi_coex_data_groups[] =3D { + "gpio75", +}; + +static const char * const spmi_vgi_hwevent_groups[] =3D { + "gpio78", "gpio79", +}; + +static const char * const uim1_clk_groups[] =3D { + "gpio3", +}; + +static const char * const uim1_data_groups[] =3D { + "gpio0", +}; + +static const char * const uim1_present_groups[] =3D { + "gpio1", +}; + +static const char * const uim1_reset_groups[] =3D { + "gpio2", +}; + +static const char * const usb2phy_ac_en_groups[] =3D { + "gpio90", +}; + +static const struct pinfunction kuno_functions[] =3D { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(ebi2_lcd_a), + MSM_PIN_FUNCTION(ebi2_lcd_cs), + MSM_PIN_FUNCTION(ebi2_lcd_reset), + MSM_PIN_FUNCTION(ebi2_lcd_te), + MSM_PIN_FUNCTION(emac_mdc), + MSM_PIN_FUNCTION(emac_mdio), + MSM_PIN_FUNCTION(emac_pps_in), + MSM_PIN_FUNCTION(emac_ptp_aux), + MSM_PIN_FUNCTION(emac_ptp_pps), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s_mclk), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pci_e_rst), + MSM_PIN_FUNCTION(pcie_clkreq_n), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(qdss_cti_trig0), + MSM_PIN_FUNCTION(qdss_cti_trig1), + MSM_PIN_FUNCTION(qdss_cti_trig1_mire), + MSM_PIN_FUNCTION(qdss_gpio_traceclk), + MSM_PIN_FUNCTION(qdss_gpio_tracectl), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3_mira), + MSM_PIN_FUNCTION(qup0_se3_mirb), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sdc4_tb_trig), + MSM_PIN_FUNCTION(sgmii_phy_intr), + MSM_PIN_FUNCTION(spmi_coex_clk), + MSM_PIN_FUNCTION(spmi_coex_data), + MSM_PIN_FUNCTION(spmi_vgi_hwevent), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb2phy_ac_en), +}; + +/* Every pin is maintained as a single group, and missing or non-existing = pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup kuno_groups[] =3D { + [0] =3D PINGROUP(0, uim1_data, _, _, _, _, _, _, _, _), + [1] =3D PINGROUP(1, uim1_present, _, _, _, _, _, _, _, _), + [2] =3D PINGROUP(2, uim1_reset, _, _, _, _, _, _, _, _), + [3] =3D PINGROUP(3, uim1_clk, _, _, _, _, _, _, _, _), + [4] =3D PINGROUP(4, qup0_se2, _, _, _, _, _, _, _, _), + [5] =3D PINGROUP(5, qup0_se2, _, _, _, _, _, _, _, _), + [6] =3D PINGROUP(6, qup0_se2, _, _, _, _, _, _, _, _), + [7] =3D PINGROUP(7, qup0_se2, _, _, _, _, _, _, _, _), + [8] =3D PINGROUP(8, qup0_se3_mira, _, qdss_gpio_traceclk, _, _, _, _, _, = _), + [9] =3D PINGROUP(9, qup0_se3_mira, _, qdss_gpio_tracectl, _, _, _, _, _, = _), + [10] =3D PINGROUP(10, qup0_se4, _, _, _, _, _, _, _, _), + [11] =3D PINGROUP(11, qup0_se4, _, _, _, _, _, _, _, _), + [12] =3D PINGROUP(12, mi2s0_ws, qup0_se3_mirb, _, _, _, _, _, _, _), + [13] =3D PINGROUP(13, mi2s0_data0, qup0_se3_mirb, _, _, _, _, _, _, _), + [14] =3D PINGROUP(14, mi2s0_data1, qup0_se3_mirb, qup0_se0, qup0_se1, qup= 0_se2, + qup0_se3_mira, qup0_se4, _, _), + [15] =3D PINGROUP(15, mi2s0_sck, qup0_se3_mirb, _, _, _, _, _, _, _), + [16] =3D PINGROUP(16, mi2s1_ws, qup0_se3_mira, qdss_cti_trig1, qdss_cti_t= rig0, + _, _, _, _, _), + [17] =3D PINGROUP(17, mi2s1_data0, qup0_se3_mira, qdss_cti_trig1, qdss_ct= i_trig0, + _, _, _, _, _), + [18] =3D PINGROUP(18, mi2s1_data1, qup0_se0, _, _, _, _, _, _, _), + [19] =3D PINGROUP(19, mi2s1_sck, qup0_se0, _, _, _, _, _, _, _), + [20] =3D PINGROUP(20, _, _, _, _, _, _, _, _, _), + [21] =3D PINGROUP(21, _, _, _, _, _, _, _, _, _), + [22] =3D PINGROUP(22, _, _, _, _, _, _, _, _, _), + [23] =3D PINGROUP(23, _, _, _, _, _, _, _, _, _), + [24] =3D PINGROUP(24, _, _, _, _, _, _, _, _, _), + [25] =3D PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] =3D PINGROUP(26, _, _, _, _, _, _, _, _, _), + [27] =3D PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] =3D PINGROUP(28, _, _, _, _, _, _, _, _, _), + [29] =3D PINGROUP(29, _, _, _, _, _, _, _, _, _), + [30] =3D PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] =3D PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] =3D PINGROUP(32, nav_gpio, _, _, _, _, _, _, _, _), + [33] =3D PINGROUP(33, nav_gpio, _, _, _, _, _, _, _, _), + [34] =3D PINGROUP(34, _, gcc_gp1_clk, _, _, _, _, _, _, _), + [35] =3D PINGROUP(35, _, _, gcc_gp3_clk, _, _, _, _, _, _), + [36] =3D PINGROUP(36, _, _, _, _, _, _, _, _, _), + [37] =3D PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] =3D PINGROUP(38, _, _, _, _, _, _, _, _, _), + [39] =3D PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] =3D PINGROUP(40, _, _, _, _, _, _, _, _, _), + [41] =3D PINGROUP(41, _, _, _, _, _, _, _, _, _), + [42] =3D PINGROUP(42, _, _, _, _, _, _, _, _, _), + [43] =3D PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] =3D PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), + [45] =3D PINGROUP(45, coex_uart, _, _, _, _, _, _, _, _), + [46] =3D PINGROUP(46, _, _, _, gcc_gp2_clk, _, _, _, _, _), + [47] =3D PINGROUP(47, _, pll_bist_sync, _, _, _, _, _, _, _), + [48] =3D PINGROUP(48, qup0_se0, _, _, _, _, _, _, _, _), + [49] =3D PINGROUP(49, qup0_se0, _, _, _, _, _, _, _, _), + [50] =3D PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] =3D PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] =3D PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] =3D PINGROUP(53, _, _, _, _, _, _, _, _, _), + [54] =3D PINGROUP(54, qdss_cti_trig1, qdss_cti_trig0, pll_clk_aux, _, _, = _, _, _, _), + [55] =3D PINGROUP(55, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _, _= ), + [56] =3D PINGROUP(56, pcie_clkreq_n, _, _, _, _, _, _, _, _), + [57] =3D PINGROUP(57, pci_e_rst, _, _, _, _, _, _, _, _), + [58] =3D PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] =3D PINGROUP(59, _, _, _, _, _, _, _, _, _), + [60] =3D PINGROUP(60, qdss_cti_trig0, _, _, _, _, _, _, _, _), + [61] =3D PINGROUP(61, _, _, _, _, _, _, _, _, _), + [62] =3D PINGROUP(62, mi2s_mclk, audio_ref_clk, _, _, _, _, _, _, _), + [63] =3D PINGROUP(63, qup0_se1, _, _, _, _, _, _, _, _), + [64] =3D PINGROUP(64, qup0_se1, _, _, _, _, _, _, _, _), + [65] =3D PINGROUP(65, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _= , _, _, _, _), + [66] =3D PINGROUP(66, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _= , _, _, _, _), + [67] =3D PINGROUP(67, _, _, _, _, _, _, _, _, _), + [68] =3D PINGROUP(68, _, _, _, _, _, _, _, _, _), + [69] =3D PINGROUP(69, _, _, _, _, _, _, _, _, _), + [70] =3D PINGROUP(70, _, _, _, _, _, _, _, _, _), + [71] =3D PINGROUP(71, _, _, _, _, _, _, _, _, _), + [72] =3D PINGROUP(72, _, _, _, _, _, _, _, _, _), + [73] =3D PINGROUP(73, _, _, _, _, _, _, _, _, _), + [74] =3D PINGROUP(74, _, _, _, _, _, _, _, _, _), + [75] =3D PINGROUP(75, spmi_coex_data, _, _, _, _, _, _, _, _), + [76] =3D PINGROUP(76, spmi_coex_clk, _, _, _, _, _, _, _, _), + [77] =3D PINGROUP(77, _, _, _, _, _, _, _, _, _), + [78] =3D PINGROUP(78, spmi_vgi_hwevent, _, _, _, _, _, _, _, _), + [79] =3D PINGROUP(79, spmi_vgi_hwevent, _, _, _, _, _, _, _, _), + [80] =3D PINGROUP(80, qup0_se4, _, _, _, _, _, _, _, _), + [81] =3D PINGROUP(81, qup0_se4, _, _, _, _, _, _, _, _), + [82] =3D PINGROUP(82, _, _, _, _, _, _, _, _, _), + [83] =3D PINGROUP(83, _, _, _, _, _, _, _, _, _), + [84] =3D PINGROUP(84, qdss_cti_trig0, _, _, _, _, _, _, _, _), + [85] =3D PINGROUP(85, _, _, _, _, _, _, _, _, _), + [86] =3D PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] =3D PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] =3D PINGROUP(88, ebi2_lcd_te, emac_pps_in, _, _, _, _, _, _, _), + [89] =3D PINGROUP(89, ebi2_lcd_reset, _, _, _, _, _, _, _, _), + [90] =3D PINGROUP(90, usb2phy_ac_en, _, _, _, _, _, _, _, _), + [91] =3D PINGROUP(91, sgmii_phy_intr, _, _, _, _, _, _, _, _), + [92] =3D PINGROUP(92, qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_s= e4, _, _, _, _), + [93] =3D PINGROUP(93, ebi2_lcd_a, emac_ptp_pps, emac_ptp_aux, _, _, _, _,= _, _), + [94] =3D PINGROUP(94, ebi2_lcd_cs, emac_ptp_pps, emac_ptp_aux, _, _, _, _= , _, _), + [95] =3D PINGROUP(95, _, _, _, _, _, _, _, _, _), + [96] =3D PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] =3D PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] =3D PINGROUP(98, emac_mdc, _, _, _, _, _, _, _, _), + [99] =3D PINGROUP(99, emac_mdio, _, _, _, _, _, _, _, _), + [100] =3D PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] =3D PINGROUP(101, sdc4_tb_trig, qdss_cti_trig1, qdss_cti_trig0, qup= 0_se0, + qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _), + [102] =3D PINGROUP(102, sdc4_cmd, qdss_cti_trig1, qdss_cti_trig0, _, _, _= , _, _, _), + [103] =3D PINGROUP(103, sdc4_clk, _, _, _, _, _, _, _, _), + [104] =3D PINGROUP(104, sdc4_data, _, _, _, _, _, _, _, _), + [105] =3D PINGROUP(105, sdc4_data, _, _, _, _, _, _, _, _), + [106] =3D PINGROUP(106, sdc4_data, _, _, _, _, _, _, _, _), + [107] =3D PINGROUP(107, sdc4_data, _, _, _, _, _, _, _, _), + [108] =3D PINGROUP(108, _, _, _, _, _, _, _, _, _), + [109] =3D PINGROUP(109, _, _, _, _, _, _, _, _, _), +}; + +static const struct msm_gpio_wakeirq_map kuno_pdc_map[] =3D { + { 1, 62 }, { 2, 83 }, { 4, 59 }, { 5, 107 }, { 6, 112 }, { 7, 119 }, + { 8, 123 }, { 10, 52 }, { 11, 73 }, { 12, 74 }, { 13, 75 }, { 14, 76 }, + { 15, 77 }, { 16, 81 }, { 17, 82 }, { 18, 80 }, { 19, 100 }, { 21, 88 }, + { 22, 99 }, { 23, 84 }, { 24, 85 }, { 25, 97 }, { 26, 86 }, { 27, 102 }, + { 28, 87 }, { 35, 103 }, { 43, 90 }, { 44, 60 }, { 45, 61 }, { 46, 104 }, + { 47, 89 }, { 48, 105 }, { 49, 106 }, { 50, 101 }, { 52, 109 }, { 53, 79 = }, + { 54, 110 }, { 55, 111 }, { 56, 78 }, { 57, 71 }, { 60, 113 }, { 61, 114 = }, + { 63, 115 }, { 64, 116 }, { 65, 57 }, { 66, 117 }, { 68, 64 }, { 69, 118 = }, + { 71, 108 }, { 73, 120 }, { 74, 121 }, { 76, 47 }, { 77, 122 }, { 78, 65 = }, + { 79, 66 }, { 80, 124 }, { 81, 125 }, { 82, 126 }, { 83, 127 }, { 84, 93 = }, + { 85, 128 }, { 86, 129 }, { 87, 70 }, { 88, 130 }, { 96, 68 }, { 98, 50 }, + { 99, 67 }, { 100, 51 }, { 101, 53 }, { 102, 54 }, { 103, 98 }, { 104, 91= }, + { 105, 69 }, { 106, 55 }, { 107, 56 }, { 109, 72 }, +}; + +static const struct msm_pinctrl_soc_data kuno_tlmm =3D { + .pins =3D kuno_pins, + .npins =3D ARRAY_SIZE(kuno_pins), + .functions =3D kuno_functions, + .nfunctions =3D ARRAY_SIZE(kuno_functions), + .groups =3D kuno_groups, + .ngroups =3D ARRAY_SIZE(kuno_groups), + .ngpios =3D 110, + .wakeirq_map =3D kuno_pdc_map, + .nwakeirq_map =3D ARRAY_SIZE(kuno_pdc_map), +}; + +static int kuno_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &kuno_tlmm); +} + +static const struct of_device_id kuno_tlmm_of_match[] =3D { + { .compatible =3D "qcom,kuno-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, kuno_tlmm_of_match); + +static struct platform_driver kuno_tlmm_driver =3D { + .driver =3D { + .name =3D "kuno-tlmm", + .of_match_table =3D kuno_tlmm_of_match, + }, + .probe =3D kuno_tlmm_probe, +}; + +static int __init kuno_tlmm_init(void) +{ + return platform_driver_register(&kuno_tlmm_driver); +} +arch_initcall(kuno_tlmm_init); + +static void __exit kuno_tlmm_exit(void) +{ + platform_driver_unregister(&kuno_tlmm_driver); +} +module_exit(kuno_tlmm_exit); + +MODULE_DESCRIPTION("QTI Kuno TLMM driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05A804B048C for ; Thu, 27 Aug 2026 17:52:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853166; cv=none; b=Ihw/jtQ3lKTbCKedUNrkKUWbf9GQpEpJsvP+K8D/taFGBmI1pBVjkDXL9rgL3eLBE0wFktUiVNEiyHs0kvCl9JxqdWQd3fhT8x3xwXmnY+l3pYz/BMYTpiu5u2D4EXvOmkmX/jVD3gJLMedRGTPNxuiZnpUA/yHqt/T7HzeabZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853166; c=relaxed/simple; bh=9FPCV87eitw661yJc7gqbrscj5MlCzlDB1E+PFlfCyc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XobYffzZRbNlsQnHAPFjF0/XYx43m45I1HASxwzBnwSb3oE0rX/6ipKK01CbxRWlrDbsu4mYlVTzcWge9N5Y/Un6TK8wZTp4/OdnBLQDVP0qSVHyffYeC5rlLze92bMXUhgeH0ksomJ4GGhMycPlen3u49wyDnG4duspSEms9FY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=RZBq8IFp; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=feud1py8; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="RZBq8IFp"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="feud1py8" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXebH873746 for ; Thu, 27 Aug 2026 17:52:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XYHgBCRZLEB3XoVwSokcAPnaY99rEFsjH7u+mtUXlls=; b=RZBq8IFpwxbYDmxG 7Sos25G/67+VZyucyv805rbaSQqzgdPQE0d39PcfnmI3z/qArTK5hkVjx/2H6794 1GrbWk88RfDRlW3EthG891c65RFE24x0FiyMLDm0h4ffaCMklQ4DQBV/dlQg9fse YH9KKETwt1l3TMyFaAIOSvq2P4TyfRH9gPqoX1aJH+l/kn0C8N2FJdGBvIWNqL3m B28ppjKOPW/W29h+a5wlddmaQmc7anG8d19YHf9jiiG3AebB7Rnfrz5KsREDPGvm UVppY2oZ8eTWzmZ4FVmHwAU0ka5YFvd1QRr5x5gOECW+6rOBt6aE1xr1P1vpjthB LDAoWQ== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4garn0gfya-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:43 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-38e4758ab46so381609a91.0 for ; Thu, 27 Aug 2026 10:52:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853162; x=1788457962; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=XYHgBCRZLEB3XoVwSokcAPnaY99rEFsjH7u+mtUXlls=; b=feud1py8P77nX7sSRUU6GgAao9uXLOjJeJmfLoyAVlNZUGC4EAKyGFq1IA/pNFNka9 x6+a4frGMmt1uuOp007C+JMF9MsIRprQq15U/9yrL057AM73KyW6fbZaZ/vu0KhmnWuW aWtnkAvJrZfq+EEMfz9HYNC2td42dF7OvOi8JNoafvGQFEAESdwZTU+X08DfZ4YQSFoe FLlo2uzQ3mYo45Ij5VrSC2fPBMRuz+4sgkBLukixhs0Jm/ydYIj4uAnvLAxMqJubmlLO 2auEbKoB9xgTp0atP3n6C+kGI72iAV87j36TWrZktZsYm7T0sXRmFYaU+5P8s1I0r6xL x5ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853162; x=1788457962; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=XYHgBCRZLEB3XoVwSokcAPnaY99rEFsjH7u+mtUXlls=; b=iaQ3uhN18wzIqi0YtaPjclhdleIQqMRPnA29MxolMGrzmEdfn39fSwewNKR+l9LmaQ YBLPpAPOwNDKPQN4u8CXSllOPKIEgcgnmBeqdqflKyNlCf6WTQBD/uwsQe8ROH0LsK3z /yGfb8FBxOI9b0KxAhdZa5DSiiKO/MYXKr0lwVVZN3wj6YBzv7tMosdVmm/4wfOtbQ72 nwtQEE0c5G6kFAGXiDw47V7PGxjJPQGRg6v6Zhn5Pqwzw44g6Haus5ZO32et2YEryzhZ VSbhMAW4eWbaJRCvBWOMkLLROaGbcGtl762/WYdZ5wvULFNAxZy3a1ayZFZ1JT7/DVm8 zrFA== X-Forwarded-Encrypted: i=1; AHgh+RodNLEIr53hwTfe8Yjiz+6UDFf6rF8YguG6/blg3EcbYty2vmdnEyixkqzwhLdCDCRfvZxsa603HrxgH+E=@vger.kernel.org X-Gm-Message-State: AFuF++k8kK/CD48A45N2ezYPxsFxKpOA9O7hsUK3iyIfhJtQ57pnTVG1 FAomjXqtTrmUJzl6grAaOe5jN20CRVYpyz/iKD31lOk8EGEl1gGUiXfsM0GOCWI84Oa6lJ9NuAr HdiPZHsBTmi53u6qocDw2SIhtedwaw9K9SknMnpZ21Milen3F3Upu9nTgEdUuaAmODd8= X-Gm-Gg: AR+sD10MfbIrmuWB8hDezZzTP3NhdSAfDLsYpfhPfMnxOtZ/EiASRwxJguvIVE82p/+ c/UNpC9sh5aBgssEX+MD42pPg5wkb22fKftbtWvvtiEcLPnHgkoL/RwLSmtsk9XwiFP3nY4/xmb 1MzX6QF8LdPpP6vUHOMNQtVhHUlzM95DQujQtroOi5gaPUTtpi7MwobL6aF+ytLld99Jj2DZoW7 lQA5c4UHGB/dE/nrRS2obT4XoyNshjK51aSdPwQb7+hHmcSDHmzrSDieJRrNlBGc3jBv99TsGYC RAD4yh1go0A6f8hURf5FbuXrP6Jh75dgM/jWGscyG67LqN706YXv4XCr6T8kCWn/YG2uVKLPR13 DCoV+5YHpAqbZXcHSwgs1sZ/MJRG+nKzHp1iXh8jarBF7v8grwpGz9xDBkOoZE4i+gjbrSEU8U9 NCEIOeCllCpvBS31G43NCaftk= X-Received: by 2002:a05:6a20:6a29:b0:3d1:be60:281b with SMTP id adf61e73a8af0-3d268ef9eb5mr1275236637.15.1787853162231; Thu, 27 Aug 2026 10:52:42 -0700 (PDT) X-Received: by 2002:a05:6a20:6a29:b0:3d1:be60:281b with SMTP id adf61e73a8af0-3d268ef9eb5mr1275086637.15.1787853161631; Thu, 27 Aug 2026 10:52:41 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:41 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:13 +0530 Subject: [PATCH v5 10/15] dt-bindings: clock: qcom: Add Kuno Global Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-10-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=5749; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=9FPCV87eitw661yJc7gqbrscj5MlCzlDB1E+PFlfCyc=; b=TY+V8SFVuEX+OQTKe4e7vYI961JtP+1FaDJZvDP3eLd8vPdFaIU9/VXdgz/qjVw2ALhuQ2IEm h6Syujh2JvoDrAoaczWfiqajzvI9Uj9OatzbmK3WIOBVqlxUw9NYmGh X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX8dXujIHjNTKJ a//vKg1ZIPE9qtD0AWTouWN3Pi1yemY5NhKRvIlGhjjykLNikDj1I7J5UyDbeLF8KdNfLT/inLo WBPlKYjFOl+oxCcqxgosX7hz079e2Z8IPQH6VmO4JBymhMh/tGwnwDSOV07dBfQLT2UrCo+YA0z y25ayjvW4Qy5/jl7FjgPF535NcBU0M5s0C31MwlbN28NIE+jfNK0F4B+aLB7qxOarZwVeQAXUpi FlrkoR8XC1K++CtOOnWiy++RVGBT4zIEOZNmLxl2hQCIlhaKuHsKfvkA4AGQipOhTpf1YnI5jzi e8y6/uKatEz6FrIz3yRQFifLiedIhCrKm37b52k+0eRbXH//BrDCFTzw1qO4Gb6PXTLir3CN76r ooIoPH2nQvvhHS+dIcE/o1nMH1ihUtYMZ1VRKFcLrp7Hrgre7vbKbRv0NdNQHtVYfW2h8Sv+8T2 bJVpl1NCd3u5jeyypHA== X-Proofpoint-GUID: MHJk8onlvLEHogisiCn6BEFacdt0-9cp X-Authority-Analysis: v=2.4 cv=C+3ZDwP+ c=1 sm=1 tr=0 ts=6a90796b cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=PKuh8qK-LUMqOkA3WUgA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: MHJk8onlvLEHogisiCn6BEFacdt0-9cp X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfXy73n6QDnQd0v QV6QyfWtARmlmzYqAfIF7hbGlTPcNazSB0/ilkhuWgdXiKU3//9BdG3/iZXz0AtfSJhrGggy3CG //Bxy9XcYAhKh0mAroCf63bLcd9MZDg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Document the Global Clock Controller (GCC) binding and associated clock/reset IDs for the Qualcomm Kuno SoC. Signed-off-by: Hardeep Sharma Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,kuno-gcc.yaml | 52 +++++++++++ include/dt-bindings/clock/qcom,kuno-gcc.h | 100 +++++++++++++++++= ++++ 2 files changed, 152 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml b/D= ocumentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml new file mode 100644 index 000000000000..7ae37033a1af --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kuno-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Kuno + +maintainers: + - Hardeep Sharma + +description: | + Qualcomm global clock control module provides the clocks and resets on K= uno. + + See also: include/dt-bindings/clock/qcom,kuno-gcc.h + +properties: + compatible: + const: qcom,kuno-gcc + + clocks: + items: + - description: Board XO source + - description: Board active-only XO source + - description: Sleep clock source + - description: PCIe pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible =3D "qcom,kuno-gcc"; + reg =3D <0x00080000 0x1f4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie_pipe_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,kuno-gcc.h b/include/dt-binding= s/clock/qcom,kuno-gcc.h new file mode 100644 index 000000000000..a237b25a061d --- /dev/null +++ b/include/dt-bindings/clock/qcom,kuno-gcc.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H +#define _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL2 2 +#define GPLL3 3 +#define GPLL4 4 +#define GPLL4_OUT_EVEN 5 +#define GCC_EMAC0_AXI_CLK 7 +#define GCC_EMAC0_PHY_AUX_CLK 8 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 9 +#define GCC_EMAC0_PTP_CLK 10 +#define GCC_EMAC0_PTP_CLK_SRC 11 +#define GCC_EMAC0_RGMII_CLK 12 +#define GCC_EMAC0_RGMII_CLK_SRC 13 +#define GCC_EMAC0_SLV_AHB_CLK 14 +#define GCC_EMAC_0_CLKREF_EN 15 +#define GCC_GP1_CLK 16 +#define GCC_GP1_CLK_SRC 17 +#define GCC_GP2_CLK 18 +#define GCC_GP2_CLK_SRC 19 +#define GCC_GP3_CLK 20 +#define GCC_GP3_CLK_SRC 21 +#define GCC_PCIE_0_CLKREF_EN 22 +#define GCC_PCIE_AUX_CLK 23 +#define GCC_PCIE_AUX_CLK_SRC 24 +#define GCC_PCIE_AUX_PHY_CLK_SRC 25 +#define GCC_PCIE_CFG_AHB_CLK 26 +#define GCC_PCIE_MSTR_AXI_CLK 27 +#define GCC_PCIE_PIPE_CLK 28 +#define GCC_PCIE_PIPE_CLK_SRC 29 +#define GCC_PCIE_RCHNG_PHY_CLK 30 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 31 +#define GCC_PCIE_SLEEP_CLK 32 +#define GCC_PCIE_SLV_AXI_CLK 33 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 34 +#define GCC_PDM2_CLK 35 +#define GCC_PDM2_CLK_SRC 36 +#define GCC_PDM_AHB_CLK 37 +#define GCC_PDM_XO4_CLK 38 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 39 +#define GCC_QUPV3_WRAP0_CORE_CLK 40 +#define GCC_QUPV3_WRAP0_S0_CLK 41 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 42 +#define GCC_QUPV3_WRAP0_S1_CLK 43 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 44 +#define GCC_QUPV3_WRAP0_S2_CLK 45 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 46 +#define GCC_QUPV3_WRAP0_S3_CLK 47 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 48 +#define GCC_QUPV3_WRAP0_S4_CLK 49 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 50 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 51 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 52 +#define GCC_SDCC4_AHB_CLK 53 +#define GCC_SDCC4_APPS_CLK 54 +#define GCC_SDCC4_APPS_CLK_SRC 55 +#define GCC_SNOC_CNOC_USB3_CLK 56 +#define GCC_SYS_NOC_USB_SF_AXI_CLK 57 +#define GCC_USB20_MASTER_CLK 58 +#define GCC_USB20_MASTER_CLK_SRC 59 +#define GCC_USB20_MOCK_UTMI_CLK 60 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 61 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 62 +#define GCC_USB20_SLEEP_CLK 63 +#define GCC_USB2_CLKREF_EN 64 +#define GCC_USB3_PRIM_CLKREF_EN 65 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 66 +#define GCC_BOOT_ROM_AHB_CLK 68 + +/* GCC power domains */ +#define GCC_EMAC0_GDSC 0 +#define GCC_PCIE_GDSC 1 +#define GCC_USB20_GDSC 2 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_PCIE_BCR 1 +#define GCC_PCIE_LINK_DOWN_BCR 2 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 3 +#define GCC_PCIE_PHY_BCR 4 +#define GCC_PCIE_PHY_CFG_AHB_BCR 5 +#define GCC_PCIE_PHY_COM_BCR 6 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PDM_BCR 8 +#define GCC_QUPV3_WRAPPER_0_BCR 9 +#define GCC_QUSB2PHY_BCR 10 +#define GCC_SDCC4_BCR 11 +#define GCC_TCSR_PCIE_BCR 12 +#define GCC_USB20_BCR 13 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 + +#endif --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2455F4B0488 for ; Thu, 27 Aug 2026 17:52:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853177; cv=none; b=Zej063+iGKQMbi3JMZXm5tzTDeFwqQmCRfTJPwnlMy9ZdDBIo5EGr6/xvKhryXpaUMU+smlo7wq0HZfgxXJ5p1PHoFapigVfJaaB/OQTDiYcL/JV1DayZW7SpDs04HoHacYJ9GAeuuznLZKi5Wffkmh74SqtXv0sIIAF7q7m0f4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853177; c=relaxed/simple; bh=4eneYjBTVm+QEs/DxK6sZdWcClFJMkkU9VCnVA/UjpM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eY7JOzG68XIgI3MBNOuaiGdnoYbHX5k9s29UH57qpOwoJpn4SinMtbDZTxi75XKDbva320ZZ2MMe/RV167tjMb1MdmLCvdHsLqDKY1sCF+ykUXa2XSgHoAwSDNMv7EB/eYdWbTNuK9ybFOOK2wyi+hdGwG1AidQI7Op0p0Q+i0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=EFCMsZ2b; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=K+645zkh; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="EFCMsZ2b"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="K+645zkh" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXefc4178386 for ; Thu, 27 Aug 2026 17:52:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 3BO6biX+wO4cDKtamvRB+gzh5ADD+Pa1K96ORZNYTF0=; b=EFCMsZ2bBH+aUwVE jFTrTwsak0XIpJRIElNXhoyEumLeIrhbDtbe3nzEPISCfjzbdXG8SG0mRYUFGoLy D8uwVg7PsK5nGGEQH8r4mCDrPpc+nK2/+I5y/xkt6aM8mQt/DKQLnLfz3ESJv/UX ggnzqHjPDgcVIakR478KbBgSzP0xbZCg0J9FxAIwSVY58Lv3DtSW1k6Cs5MS1kGj AV8Xa5nF65bnE9N9XDQ7MakSjMDtqoqGVruxL/N3JMwmdnCc2hlpex1oVTipUTqZ 5zZBtsfCo5w34ZdehwY/qkBuat+bebpCwLgiBC2YZKvg85b4DHrUOITgx6cRWtSc SVL62A== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gaphw12uk-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:52 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2d02df2bf09so998725ad.0 for ; Thu, 27 Aug 2026 10:52:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853172; x=1788457972; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=3BO6biX+wO4cDKtamvRB+gzh5ADD+Pa1K96ORZNYTF0=; b=K+645zkhk88Gc29Q+WCBzcOG/KzZRjrgk9a5bsPiN7p4C3yS3gsnzCWEn6p4Y6WYFF Ry+gNm+JALr4gfIUY/HIi0J0ONdwYjcLuh8ZoJLkBxgKkItt2KsJEBrzYjlyFHGXRfHw W/zOMdowQwPa1SVWz3hh6rP1eRTMcSSRG7tzMHzxtEYNgvf2GuHlpQXKour6rNKB/Aap DRl7DhaSi7lTKUIppzJ4nEArkn3XKB40sUSm6rGPeP5bSUiPjztWLtNxTV3YYZ1rm1Cw Hds/GM+lH5NZgYJ0/GMDm0oX4+h6CZo/mJ+JX6Eykc+qjT7jnxMN4jJVh34VeKkvPyIm e+hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853172; x=1788457972; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=3BO6biX+wO4cDKtamvRB+gzh5ADD+Pa1K96ORZNYTF0=; b=bXhD8lBHuoCgcCDZf9IUujzCgknIkwdjptI1QBWUVikGRVfQVBHkUuoTxBcSAKX7aj HnBc0jn6PA1sscTVq95ax4NL6nVapJNCwFFsJc78WgGTjIaAIWFE+WH2+DOtPMtimRdx N1W+odKoAuyOutwBjc9oQHu0qVx3XBJFDyro0Cjao6UJMSToHANq+Euv/K4p2TUpVCT1 c51k0U7Xf3Dc5PPI0WG6t9GFJG5K2gc02QFoSjEOjo67wHbAMoQEQqh2H366ToEw0WCa /9Yds+pd95rIE7/HfjEKPDcDNIe2FdUWneh1bUcb2zwCuQo1VDGhqq7s0JpqvHL6pguw DSfw== X-Forwarded-Encrypted: i=1; AHgh+RoLMUWLCaz8qP6O+IIvfinpAcqvaiJQ78sR2bFHIa3etc1qfJHlNTc+FvoWbY+yfXbNYwaAar2ZbwETwio=@vger.kernel.org X-Gm-Message-State: AFuF++mGaAPQEkRgPULQUC/aylR7fm1Kz7+XWe63NtNm7gNtxh4+FIQY D9KT4lLuS93YFdGXaUnjXcSUu/AMT9S5A1UE2RILkn4W5B0DQdxa1T2++AKHxm5l5mIq1tCKyF2 KsrP4vbQnj6alEm04MdofeFIKC0hLoKpkjlCQY+ManCbrV7RuGGStW0JCXwkibfkVfF4= X-Gm-Gg: AR+sD13mA/2FtoC5xt4+DFTLWKeKllrWdz5Cis5yrX5NadRHCPmZDurBxDd51qsRTXl e0NcIxiH+jSR5SHPLVip4sASQ4xOgvVBwA4gGn19tFxEI2TAs9SGaFNCSbO/Ypsui9NEjVF68wb pRweKwHQj0rFJK5qq8JQwJ5xyB0R3sIzIqfwe2JzJbsr4R225yHLkYZcMdM4ikP7n2Bw6zrE6pA ziues5kF6Ga7NJsli+2TeJpQdPx988KXbs7ayNci/N6d39sxE7fWcczSm7kdJRQPgSos8mIgdxe +PHBcY3kzvaSy9xC9OTp28XjS/RJt2/Uh9DHo2HFt4rrHENZ5qCSLR4jaXbfEnzxpxcy2WUIiD/ I6TZsVxA+3McHQn7bhbRJePdHpd9rOeI/C1r8gfoc3qF/+t9XvDzUfh4H+PDIXBezqcOEzSavGQ guo3kFamei7RZln8/jcM1JYQE= X-Received: by 2002:a17:902:e552:b0:2cf:8131:75e8 with SMTP id d9443c01a7336-2d74df5b062mr8048855ad.13.1787853171488; Thu, 27 Aug 2026 10:52:51 -0700 (PDT) X-Received: by 2002:a17:902:e552:b0:2cf:8131:75e8 with SMTP id d9443c01a7336-2d74df5b062mr8047895ad.13.1787853170690; Thu, 27 Aug 2026 10:52:50 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:49 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:14 +0530 Subject: [PATCH v5 11/15] clk: qcom: Add Global Clock Controller driver for Kuno Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-11-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=43539; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=4eneYjBTVm+QEs/DxK6sZdWcClFJMkkU9VCnVA/UjpM=; b=RDJxpS2AB9lnxh2p55tHJ9GMmqrGoOZ5VViOu0PpH/x2/xQSoaGPG8YlpJmw9ZVpyAIMRsZOH VaVKa7dhHUTArzwSvCqwL6npPGjBTEGofRUT0O0GxCEJ74IA9AsARyj X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-GUID: DyHqzxT-MX4Y8WIby0xiwBrqsgIyV3V9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX4RqUUltEgxeY +rvSwHCk5AXvANs61p4zqy65K0NE5/Ce9K3FoQ38hRnWEF4M27uqWR61uD9AMzBZd7C8YVjlGVp F3RL+qBMv107v4k5GnkY676ukyPubac= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX4Ex+I54td9KY u/v3jWmD+iL/FIRiXWVHYwioZV1phD7YsSRLZBPR4aqOzG/Hte8xlpML8PuljEet+KjuLIn0DdC kYant5uGOnGtv5aPogO1U/ZYRnvYcVBdLkAVvkH1r++lkKAHegx5MzqoXWmwWO1VtpgYAak0nWr WOfiJZ7xcod/csGoA+n+xMoe1tjBzS6tXECBFxSTzbZaxsYWScanCfmIxtMZLd3HQsb0tJc2p3z 8x0JxCh6YwAtDwW92Pt2Tq9fJ2me5S/fP4v7eLxPWH5fYK/bjXYApBuF8XqNsFE4UB9nAW54DO4 thogGmo2pm8gNJU30Jnh7RI6GicPCdm0B17gGhC6J1uFcBwfin36KBSo3DBq7SWEJGtZu6LmoQv qCWKXv1HvxQSugnKc1RvKbYOEWrcVp19gr295j/y4SicMHBklIeGJdfBSCXCwwdZtJxlIGfBGOJ AR5MEnfNrz1lCiElQnw== X-Proofpoint-ORIG-GUID: DyHqzxT-MX4Y8WIby0xiwBrqsgIyV3V9 X-Authority-Analysis: v=2.4 cv=E8b9Y6dl c=1 sm=1 tr=0 ts=6a907975 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=er59LzwYcjVnkq2hIHsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Add the global clock controller (GCC) driver for the Qualcomm Kuno SoC, providing the PLLs, root clock generators, gate/branch clocks and resets used by the peripheral devices such as UART, SPI, I2C, USB, SD, PCIe and Ethernet. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-kuno.c | 1483 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1495 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index e609a7819e07..5da0f90a9f4e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -212,6 +212,17 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config CLK_KUNO_GCC + tristate "Kuno Global Clock Controller" + depends on ARM || COMPILE_TEST + select QCOM_GDSC + default ARCH_QCOM + help + Support for the global clock controller (GCC) on Kuno devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, SD, PCIe and Ethernet on the Kuno SoC. This clock + controller supplies the clocks and resets to those peripherals. + config CLK_NORD_DISPCC tristate "Nord Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b8590963736a..67f74898a582 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o +obj-$(CONFIG_CLK_KUNO_GCC) +=3D gcc-kuno.o obj-$(CONFIG_CLK_MAILI_VIDEOCC) +=3D videocc-maili.o obj-$(CONFIG_CLK_NORD_DISPCC) +=3D dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o diff --git a/drivers/clk/qcom/gcc-kuno.c b/drivers/clk/qcom/gcc-kuno.c new file mode 100644 index 000000000000..787111397df9 --- /dev/null +++ b/drivers/clk/qcom/gcc-kuno.c @@ -0,0 +1,1483 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, + DT_PCIE_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL2_OUT_MAIN, + P_GPLL3_OUT_MAIN, + P_GPLL4_OUT_EVEN, + P_GPLL4_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static struct clk_alpha_pll gpll2 =3D { + .offset =3D 0x2000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll3 =3D { + .offset =3D 0x3000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll4_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll4_out_even =3D { + .offset =3D 0x4000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpll4_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll4_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll4.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_out_even.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_out_even.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_GPLL4_OUT_MAIN, 3 }, + { P_GPLL2_OUT_MAIN, 4 }, + { P_GPLL3_OUT_MAIN, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_out_even.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, + { .hw =3D &gpll3.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_BI_TCXO, 2 }, +}; + +static struct clk_regmap_mux gcc_pcie_aux_clk_src =3D { + .reg =3D 0x5308c, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_6, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src =3D { + .reg =3D 0x53070, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x7102c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] =3D { + F(62500000, P_GPLL4_OUT_EVEN, 4, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(125000000, P_GPLL2_OUT_MAIN, 4, 0, 0), + F(230400000, P_GPLL3_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_ptp_clk_src =3D { + .cmd_rcgr =3D 0x71064, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_ptp_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] =3D { + F(41666667, P_GPLL4_OUT_EVEN, 6, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(125000000, P_GPLL2_OUT_MAIN, 4, 0, 0), + F(250000000, P_GPLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_rgmii_clk_src =3D { + .cmd_rcgr =3D 0x7104c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rgmii_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(41666667, P_GPLL4_OUT_EVEN, 6, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x47004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x48004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x49004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_aux_phy_clk_src =3D { + .cmd_rcgr =3D 0x53074, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_phy_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(83333333, P_GPLL4_OUT_EVEN, 3, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src =3D { + .cmd_rcgr =3D 0x53038, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie_rchng_phy_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rchng_phy_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x34010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(62500000, P_GPLL4_OUT_EVEN, 4, 0, 0), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x6c004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x6c13c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x6c274, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x6c3ac, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x6c4e4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 1, 1), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(83333333, P_GPLL4_OUT_EVEN, 3, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src =3D { + .cmd_rcgr =3D 0x6a01c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_apps_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] =3D { + F(50000000, P_GPLL4_OUT_EVEN, 5, 0, 0), + F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb20_master_clk_src =3D { + .cmd_rcgr =3D 0x27048, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb20_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2702c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x27044, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x37004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x37004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_axi_clk =3D { + .halt_reg =3D 0x71018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_phy_aux_clk =3D { + .halt_reg =3D 0x71028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_ptp_clk =3D { + .halt_reg =3D 0x71044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rgmii_clk =3D { + .halt_reg =3D 0x71048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_slv_ahb_clk =3D { + .halt_reg =3D 0x71024, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_slv_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac_0_clkref_en =3D { + .halt_reg =3D 0x94004, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x94004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x47000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x47000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x48000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x48000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x49000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_clkref_en =3D { + .halt_reg =3D 0x94000, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x94000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_aux_clk =3D { + .halt_reg =3D 0x53054, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x53054, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cfg_ahb_clk =3D { + .halt_reg =3D 0x53034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_mstr_axi_clk =3D { + .halt_reg =3D 0x53028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_pipe_clk =3D { + .halt_reg =3D 0x53064, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x53064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rchng_phy_clk =3D { + .halt_reg =3D 0x53050, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53050, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rchng_phy_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_rchng_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_sleep_clk =3D { + .halt_reg =3D 0x53060, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53060, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_axi_clk =3D { + .halt_reg =3D 0x5301c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x53018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3400c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x34004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x34004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x34008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x34008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x2d018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x2d008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x6c130, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x6c268, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x6c3a0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x6c4d8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x6c610, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x2d000, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d000, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x2d004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk =3D { + .halt_reg =3D 0x6a010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6a010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk =3D { + .halt_reg =3D 0x6a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_cnoc_usb3_clk =3D { + .halt_reg =3D 0x27060, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27060, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x27060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_cnoc_usb3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb_sf_axi_clk =3D { + .halt_reg =3D 0x27064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x27064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sys_noc_usb_sf_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk =3D { + .halt_reg =3D 0x27018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x27018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk =3D { + .halt_reg =3D 0x27028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x27028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk =3D { + .halt_reg =3D 0x27024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x27024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_clkref_en =3D { + .halt_reg =3D 0x94008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x94008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb2_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_en =3D { + .halt_reg =3D 0x9400c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x9400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk =3D { + .halt_reg =3D 0x29004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x29004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x29004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb_phy_cfg_ahb2phy_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct gdsc gcc_emac0_gdsc =3D { + .gdscr =3D 0x71004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_emac0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_gdsc =3D { + .gdscr =3D 0x53004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb20_gdsc =3D { + .gdscr =3D 0x27004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb20_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gcc_kuno_clocks[] =3D { + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_EMAC0_AXI_CLK] =3D &gcc_emac0_axi_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK] =3D &gcc_emac0_phy_aux_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK_SRC] =3D &gcc_emac0_phy_aux_clk_src.clkr, + [GCC_EMAC0_PTP_CLK] =3D &gcc_emac0_ptp_clk.clkr, + [GCC_EMAC0_PTP_CLK_SRC] =3D &gcc_emac0_ptp_clk_src.clkr, + [GCC_EMAC0_RGMII_CLK] =3D &gcc_emac0_rgmii_clk.clkr, + [GCC_EMAC0_RGMII_CLK_SRC] =3D &gcc_emac0_rgmii_clk_src.clkr, + [GCC_EMAC0_SLV_AHB_CLK] =3D &gcc_emac0_slv_ahb_clk.clkr, + [GCC_EMAC_0_CLKREF_EN] =3D &gcc_emac_0_clkref_en.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_PCIE_0_CLKREF_EN] =3D &gcc_pcie_0_clkref_en.clkr, + [GCC_PCIE_AUX_CLK] =3D &gcc_pcie_aux_clk.clkr, + [GCC_PCIE_AUX_CLK_SRC] =3D &gcc_pcie_aux_clk_src.clkr, + [GCC_PCIE_AUX_PHY_CLK_SRC] =3D &gcc_pcie_aux_phy_clk_src.clkr, + [GCC_PCIE_CFG_AHB_CLK] =3D &gcc_pcie_cfg_ahb_clk.clkr, + [GCC_PCIE_MSTR_AXI_CLK] =3D &gcc_pcie_mstr_axi_clk.clkr, + [GCC_PCIE_PIPE_CLK] =3D &gcc_pcie_pipe_clk.clkr, + [GCC_PCIE_PIPE_CLK_SRC] =3D &gcc_pcie_pipe_clk_src.clkr, + [GCC_PCIE_RCHNG_PHY_CLK] =3D &gcc_pcie_rchng_phy_clk.clkr, + [GCC_PCIE_RCHNG_PHY_CLK_SRC] =3D &gcc_pcie_rchng_phy_clk_src.clkr, + [GCC_PCIE_SLEEP_CLK] =3D &gcc_pcie_sleep_clk.clkr, + [GCC_PCIE_SLV_AXI_CLK] =3D &gcc_pcie_slv_axi_clk.clkr, + [GCC_PCIE_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_slv_q2a_axi_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_SDCC4_AHB_CLK] =3D &gcc_sdcc4_ahb_clk.clkr, + [GCC_SDCC4_APPS_CLK] =3D &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC4_APPS_CLK_SRC] =3D &gcc_sdcc4_apps_clk_src.clkr, + [GCC_SNOC_CNOC_USB3_CLK] =3D &gcc_snoc_cnoc_usb3_clk.clkr, + [GCC_SYS_NOC_USB_SF_AXI_CLK] =3D &gcc_sys_noc_usb_sf_axi_clk.clkr, + [GCC_USB20_MASTER_CLK] =3D &gcc_usb20_master_clk.clkr, + [GCC_USB20_MASTER_CLK_SRC] =3D &gcc_usb20_master_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_CLK] =3D &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK_SRC] =3D &gcc_usb20_mock_utmi_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb20_mock_utmi_postdiv_cl= k_src.clkr, + [GCC_USB20_SLEEP_CLK] =3D &gcc_usb20_sleep_clk.clkr, + [GCC_USB2_CLKREF_EN] =3D &gcc_usb2_clkref_en.clkr, + [GCC_USB3_PRIM_CLKREF_EN] =3D &gcc_usb3_prim_clkref_en.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] =3D &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL0_OUT_EVEN] =3D &gpll0_out_even.clkr, + [GPLL2] =3D &gpll2.clkr, + [GPLL3] =3D &gpll3.clkr, + [GPLL4] =3D &gpll4.clkr, + [GPLL4_OUT_EVEN] =3D &gpll4_out_even.clkr, +}; + +static const struct qcom_reset_map gcc_kuno_resets[] =3D { + [GCC_EMAC0_BCR] =3D { 0x71000 }, + [GCC_PCIE_BCR] =3D { 0x53000 }, + [GCC_PCIE_LINK_DOWN_BCR] =3D { 0x87000 }, + [GCC_PCIE_NOCSR_COM_PHY_BCR] =3D { 0x88008 }, + [GCC_PCIE_PHY_BCR] =3D { 0x54000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] =3D { 0x88000 }, + [GCC_PCIE_PHY_COM_BCR] =3D { 0x88004 }, + [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] =3D { 0x8800c }, + [GCC_PDM_BCR] =3D { 0x34000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x6c000 }, + [GCC_QUSB2PHY_BCR] =3D { 0x2a000 }, + [GCC_SDCC4_BCR] =3D { 0x6a000 }, + [GCC_TCSR_PCIE_BCR] =3D { 0x84000 }, + [GCC_USB20_BCR] =3D { 0x27000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x29000 }, +}; + +static struct gdsc *gcc_kuno_gdscs[] =3D { + [GCC_EMAC0_GDSC] =3D &gcc_emac0_gdsc, + [GCC_PCIE_GDSC] =3D &gcc_pcie_gdsc, + [GCC_USB20_GDSC] =3D &gcc_usb20_gdsc, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), +}; + +static const struct regmap_config gcc_kuno_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f41f0, + .fast_io =3D true, +}; + +static const u32 gcc_kuno_critical_cbcrs[] =3D { + 0x3e004, /* GCC_AHB_PCIE_LINK_CLK */ + 0x3e008, /* GCC_XO_PCIE_LINK_CLK */ +}; + +static const struct qcom_cc_driver_data gcc_kuno_driver_data =3D { + .dfs_rcgs =3D gcc_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(gcc_dfs_clocks), + .clk_cbcrs =3D gcc_kuno_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gcc_kuno_critical_cbcrs), +}; + +static const struct qcom_cc_desc gcc_kuno_desc =3D { + .config =3D &gcc_kuno_regmap_config, + .clks =3D gcc_kuno_clocks, + .num_clks =3D ARRAY_SIZE(gcc_kuno_clocks), + .resets =3D gcc_kuno_resets, + .num_resets =3D ARRAY_SIZE(gcc_kuno_resets), + .gdscs =3D gcc_kuno_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_kuno_gdscs), + .use_rpm =3D true, + .driver_data =3D &gcc_kuno_driver_data, +}; + +static const struct of_device_id gcc_kuno_match_table[] =3D { + { .compatible =3D "qcom,kuno-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_kuno_match_table); + +static int gcc_kuno_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_kuno_desc); +} + +static struct platform_driver gcc_kuno_driver =3D { + .probe =3D gcc_kuno_probe, + .driver =3D { + .name =3D "gcc-kuno", + .of_match_table =3D gcc_kuno_match_table, + }, +}; + +static int __init gcc_kuno_init(void) +{ + return platform_driver_register(&gcc_kuno_driver); +} +subsys_initcall(gcc_kuno_init); + +static void __exit gcc_kuno_exit(void) +{ + platform_driver_unregister(&gcc_kuno_driver); +} +module_exit(gcc_kuno_exit); + +MODULE_DESCRIPTION("QTI GCC Kuno Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBAD94B049D for ; Thu, 27 Aug 2026 17:53:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853184; cv=none; b=BOe1eEkaP4xhxS7/8O4pHg5lf1Fp387zgsd1tuYf7zZuqIkCZK55EAevJ/B2wFg6o9G21e0KVXGDdfXJ8itfLYr5wjju6IGwfZtCgQta6RBardJh3mFoz8cB3LgdCB4dEsUkQUbWHnOJPnTUZcLhiX5VS49WmIvN7tXVZFHueAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853184; c=relaxed/simple; bh=+/+CnJFkK28UfCOUz91D0FsS6GYOqD6AEiwdg9UDtAE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rn1SU/EHh9GkS/V6FsVFn9lrp3z+sAgLZJ18VaaWaU55f+8rlYZs1izHiXEO4AjUySRTYM7X6JeC88aJll/bHZiQ3uyDR3i8Z0RlDhG6Q/7+74d5+KaWlOdDiqUDQ7tkS4I/9B3AKB+6rz6lQWuK4CZHQpZigET5MgoUM2GfJg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=XveKuayk; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=dRWcldDQ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="XveKuayk"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="dRWcldDQ" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXaZd540921 for ; Thu, 27 Aug 2026 17:53:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= GsdXzVEg/opOUMCjXIMLe0tWNQrrcXZla2NfQwnp4TE=; b=XveKuaykkN0fyFu0 oyzT6oSjYAB1CC8LaAlXMiNGzxKK4bODPslUpyRn/9nO3Kf/QBwXzzRvR7ddSitD UIoK4dEm55z0GU1r1+2qSljuF196tNvAi9zQS7gh4FPvYUppdo0DVyPz4FQ7mmk5 jxIH95dYG1D4Zc1D2sdeIUJs5Wf5ZNMibzEES444Cpib+vFG7MlqyKjtVDLTBwRO yUjBy5BeP6my5z6ISXHM0M0rfOs3yiDQoiddXcObRTvE3WzBNT64Ndb5aUczdYSP 8/h5D76PWHQCn9Q3M3UlYJTnKjox8D1QWQ3NBdethPYFzjgAsudHoqDfmtJuEyxg Drh2Og== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4garee0pan-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:52:59 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2cfca8558d2so997115ad.2 for ; Thu, 27 Aug 2026 10:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853179; x=1788457979; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=GsdXzVEg/opOUMCjXIMLe0tWNQrrcXZla2NfQwnp4TE=; b=dRWcldDQlJI+HqvNLey3KHeQbbt2jP2S/GOyDeLVho8zLcECDhpIvpAtYeI0SfW6C6 kkf2zBYMbqdCICQ2o8+r64+uvgOjM4XIKNRNoqTFrU3UrsW3y6V18WCySQemJ6cpnDnD +hfnOssj1w/vD9LFU2AhirQBQcrKazVxz5HKRXfHzznM2JOfT6sRuxU/wmEXzBmcRkdM 5g+V/lUczGdVplEjSLdVV7tOFP0golZXrvEGAXKLEnB2Btd7DhKdEnH9w/jQ0jOdi8Wv js4e/rVmTX1VAUR5u9SnIiw0klZ8J6Y5hBs6fbFQL3TU4TPPMnmCGPEcG3vnJR8XN/Ud 5nbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853179; x=1788457979; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=GsdXzVEg/opOUMCjXIMLe0tWNQrrcXZla2NfQwnp4TE=; b=L0V8guc+4iNqUM6Ec7Yg2E4h21yXawX6Q+317mzhsHj4GULhTyfr0JKJTePbGo1Bhs a00HDKiNRFvKPe3mP4sKLC0fsvcsjpHqFZRUj7AlLwXRzpBkBYDkavbx8pGwid/MEaZR SOhGqfjZ9JNIHnNC3AYLVATeEf6GCNTvVmbAXHmaSSgS5mEVC97KNWNkYOJw9vZNjV/5 CGVZ3PrUfUjVYTa3BljJ3JteF0/ObZnRdcwe6fjFc2RN+C4VfGn5vlxSDShXOTxMRsr4 oxyh9XLgUXbmGrn/VvK9hwTfIOZS/GNajrAsk2s+TgEJ5ZBo1fesB3gIzKJ5QkEm3ey4 Jogw== X-Forwarded-Encrypted: i=1; AHgh+RpEkAMQ2fnGJ72p9psgJKKW0s4NF6FAxEHqXI6lQpznTtOz9b5koLAGnJn31bX4xnOP+Ah3FdrM8pXQZGk=@vger.kernel.org X-Gm-Message-State: AFuF++m1hua6P0QhVGA8psVjr3sCXdg9W7lTYLhX4RCzpwcGDS0lI7L/ kSyWoW7LM8bZxezFwFXlp6RY9KE+LbxLTSDqy+pb/jaZYvvPQ5EiPpgjEcfmHho8Bb2Mo2+7I4S /Gyj3+4/Fhn70wdRTGD/184iRt8dj0w/lLL+GQGIhL3xmnEOd+c8T9BBdTI/l53pYe9s= X-Gm-Gg: AR+sD10oTQCQPwueU/5JgRVxGoy/J+Zxt88qVQnbSwO0V7oj7vFPmQ6vHyWfehR9fQ6 koERRdGf/OliGPHrZ1k2mL4pf4GgENBRWLmynQ2OCZj5LZt/Wl6nlBx2L44nRPbrxeOsAyVS34C 7IkTNjx0DAongLl2t6Xo/SCxj6O50dygdlnIQnMfrBM97FAz6SLmEXInFUQigq3ea+XB4cfgPIq sjIXVNDQAoGmEzPAdaCXO9T7kcJDa/TnlIhMQinmUHiwbXORY0/lhK6j0Nps7wI5JB2U+IFHEGX l2LvCzOvgBFhSeMMyRcMYeIT5yg2j+DViPgnIgdHsrRRcTVM6u80PWZYJlGVo5L/079ZLoPcUZG bpwS0gmgJKDRKHBtfKlst+jmyXbu6vO1VUi0kxxMPn/cBX+aJ2tQq4+lkAvMlN1XQRC76kRwgU9 UY5WbtQJawokWyF/tV0EgL3rA= X-Received: by 2002:a17:903:15cf:b0:2d7:1aeb:739 with SMTP id d9443c01a7336-2d74e1295c2mr11086795ad.13.1787853179211; Thu, 27 Aug 2026 10:52:59 -0700 (PDT) X-Received: by 2002:a17:903:15cf:b0:2d7:1aeb:739 with SMTP id d9443c01a7336-2d74e1295c2mr11085775ad.13.1787853178763; Thu, 27 Aug 2026 10:52:58 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:52:58 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:15 +0530 Subject: [PATCH v5 12/15] dt-bindings: interrupt-controller: qcom,pdc: Add Kuno compatible string Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-12-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=922; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=+/+CnJFkK28UfCOUz91D0FsS6GYOqD6AEiwdg9UDtAE=; b=5+UqgzWqWAt2y8pw+wO8S1gQhj+ILFb5zZykxqwlJVi4SL1guDDGpMcNI/73AXMXGq7fNAD8n e00Bc2sIs1UCSRq9bFhRuWIPh3sI+xeXRdBycjDqBUkKY4tQG6SPHpa X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX9V1QYlWaS+SP jVpMx4MohIj93l6Sj6dtPbEK5YlwKKpXUOO6zuGc4BRMmLrrQtQztBO4HQpSHdmiR7vHtGH+qgw VoClQ0enCMYFxcQxlKtn5/C8mgkDxmeGIatiUVWq9BbsV+Doki3IuLO9S8NlZjNq1E56Om3uQ/i nLVG129OOAHeajFl7e3vLqH84MFatmSqq8WkuFa7XqOkilAEpUVLBanLln+VOImpYiDH4acxyHu 3u4E0DsgIet8YdvvmPqkXqtpJhlfnTptfXyh+dX8Mpcfi+Vu/Pk79IaTEd78zNKaxhIUiuWnd/M 1Q8QTkqOi2vNVuqjPO56t5vLJHyK8Gnaa9ZzcOjcUcmUJy4gYM5obKw3KBcHQ0U5i8Op4CeS0sb thDGNWk38ecPvLNadk2DFpTotpBKWpavu4ZkGjV97nC2F8d0R/HsGqa9r15O9BTbIJbTr02JQ1t uPF8K9jN67rKDs1EMFg== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX+RD0zUsed7ph Vwx/nXSWNccSDVbCGAbRoljLdGpDVs/PeGuio73bvjhVL1YnT+BohjytFeJPRbOO6cPqMAQMagh 8NvWtC8hsCQly4DjsF+RfhAjM7CFFKE= X-Proofpoint-ORIG-GUID: LDe-hjQcUI09B6FJEI0i9Mm4OE5fAS0f X-Proofpoint-GUID: LDe-hjQcUI09B6FJEI0i9Mm4OE5fAS0f X-Authority-Analysis: v=2.4 cv=e8E2j6p/ c=1 sm=1 tr=0 ts=6a90797b cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=_KRvd0mH2JNXacczCDAA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Document the Power Domain Controller found on the Qualcomm Kuno SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index 8162a49d49a6..518fbf6b2761 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -30,6 +30,7 @@ properties: - qcom,glymur-pdc - qcom,hawi-pdc - qcom,kaanapali-pdc + - qcom,kuno-pdc - qcom,maili-pdc - qcom,milos-pdc - qcom,nord-pdc --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D5F54ADD8C for ; Thu, 27 Aug 2026 17:53:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853191; cv=none; b=odWrCUmASci+u9iP4yl3vJxku0p19MUeyFSU1HOV6cf+unoEYa7tlYz6C4/qeljHo0Jsb0evkRY+fe20eoQ6U2AyP8shI4WOmfse5dg8RqX4HfhR0TdlJthxpjWBh/WFHibW488TDPY9XGb28x7iDO2HOKDDuAM4mGisP2szEDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853191; c=relaxed/simple; bh=9JHmO47xFcHiKwRcWRppqe+FIDEC/EmRY/1PhD8wx0w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E6FvheDbnaKkgzEjKg0M+Y7cplVg2PyrCRjxjtSz3UnxTtkCANCLuFh7lWP34wnvnWyEKoGsxxUUnvLLeO5dPQIt3+GwR2LMSqr5eV8i+8FiKW5cwrmUBEaALgr0KHYPMIMO9rE90YXyc7T7RplkjTSmuZWoLCn6oxrry3gSPk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=mgiw19cL; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=dGcgK52M; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="mgiw19cL"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="dGcgK52M" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHYBie1122266 for ; Thu, 27 Aug 2026 17:53:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wOoRRo1BzWfxcKIRahahL37V6D+SA2lxSIowy+5sCk0=; b=mgiw19cLbzJcHRK7 VwPAevQ/8uyHAndrw/snc2A7t2KInmw2k7/t1GZQLI5Uu0SxFiXzsU1Z8HGkH0ub cycv9V5eCxMoxfC5Cf0jpCUXs8i1uThgt+SCm1U6a3UMKWlnZKGlcgpVoqAfQHW6 li/clZWX+3ik3xxqlm9zJh83itxcg683aGzkaaJ6AlNvlF0x35hQnaDWyd17XwOr GEIkEPvuUUHoq+XhI0nv+XRTtFTHfuk3csTxwuecRqaN9ap+R1tqQ64vMukLNr+l tU36z+SwvLHXS7vW0n7oWXZVS+xh0uggurYrejOaFxgyHdbN5xFCWKiV3sermd9e hirGEg== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gapgv999m-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:53:08 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-cc1c18c775eso1427728a12.0 for ; Thu, 27 Aug 2026 10:53:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853188; x=1788457988; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=wOoRRo1BzWfxcKIRahahL37V6D+SA2lxSIowy+5sCk0=; b=dGcgK52M7ZGVoARJyAYUOxL4BHeX75RTACBSx8YUmK3cSBUjse1FDxTaRdIMy0kW6y 2YTLSuQsicw4nI+5Y5jUgGAd/BJG1shY3YcfMutyzoSKbv3MMOpkULtCUoNM2jwMEEei Z4is5IVAzY8rmXO1D1nJLYHWWtIs2o/yFUTe9TMxgDMorlElu/7y8+pRFKvx5mN5+HFx kQe1GVoswWXaq94VfGljOVtPr4k0sTYwK5vsyUmsOuQW8TzPfJfqkw4Dl83mNsWTM+FB G8A01bEWhABrIR7fXE6h3KEFIr9ANtPpmiIgQybUTr527gPMkwdE2KWT4tFNM82ji/TK n9qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853188; x=1788457988; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=wOoRRo1BzWfxcKIRahahL37V6D+SA2lxSIowy+5sCk0=; b=lLltCr0JxPfedrXSAKhaFAUD9rC6deT7WwNL0cO1qi9l0Tpv1rcG6DCM/4tcUxsi0s m1YAsuhBf0z0q0h94NdZt+CxJXaCPuF0ba7QoDYvJ4yxy37VEQ8D7MNG5WbbEnmb4m30 GaJvG1qWstWBysVt8iUZ0EN30g+5CApS2euR7BAcXlasoFk9xREE/VxIWgqHOz79nTqk p2bXglVCVS7MvRRFcR7GvRQCUyOMCfVOaEIqdqfYx7HxVjMT6vEF7cXOZVgipeXDAHNK eSeprdV0sQBxM9fWhVALHoWE8PSBhQMJ+jDrYJJAQdmkh4aZe3u65qgMWmbuHbjbRSz0 aGSA== X-Forwarded-Encrypted: i=1; AHgh+Rplc2WEOAImLZztv+xUn9IbWWI+20B/tNXsk2uQ2AXz2fohoWD48Ehqn9U25v2FyphlhgjeoTyf0RVfmtg=@vger.kernel.org X-Gm-Message-State: AFuF++lKTgmJ6ePSvhHYEGeH7fXOqon4E33Gdde1umlQ24Dltj6ZanOP mKf0cpcWFev9hQ/obIsCkLZPclzJ6/jIh6vs9ehCWkDT5cDOCgjzBg2GErZxMUrHEQtv+1pQ5/S PF4+obo23eI+CrGG0iXTJoUxu58firZIAckShN0XWilQoFsMV+BsB9e2ibA5W3NNUKEo= X-Gm-Gg: AR+sD10V9hVnUf4Z+Xn6Ahnsxtzz+ShnRRYKN79rBZrDMD1YaCaByzYlSHl7c4HgOAA Ni7qLoPM2g28TGjozdtkMOLy/cxdgdWTXtOgUbihBGi9D77Nk6lby50TcevmgNwXUiCrxGO49DX 2CElyvaz6T+17l33PvLPvY35VH2Pj0iUow2LWJabLCMUH2HbvvQNer9DGh95MeYLfzDQxJ4+Yar t3CLNPc64fTNgBWpIpwG+6NkoSXq3Y0M9UKh37XxFOA8+mCuZkG3hBgbl0Xs28Y2QJjXYcxhdJT 66tNUQUhKIZVsmXHUDS4cEc4JLUpLCQG3qvB1OxJrVf7ZbUuSRlhpBtcjNlsZJYZDXCvx7XbSxt zBUrM6SOVCHNmn8gvRmMOU7fqokR8YlIXNgRrwh6hKRkESM4dbcFhX+7rHOZfrDfE9DKHN8ThnT i0/oRNh5g4NtqiEQpJYWesn9I= X-Received: by 2002:a17:903:22c5:b0:2d7:1f17:41f8 with SMTP id d9443c01a7336-2d726b17867mr108846435ad.15.1787853187613; Thu, 27 Aug 2026 10:53:07 -0700 (PDT) X-Received: by 2002:a17:903:22c5:b0:2d7:1f17:41f8 with SMTP id d9443c01a7336-2d726b17867mr108845825ad.15.1787853187160; Thu, 27 Aug 2026 10:53:07 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:53:06 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:16 +0530 Subject: [PATCH v5 13/15] dt-bindings: firmware: qcom,scm: Document SCM on Kuno SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-13-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Bartosz Golaszewski X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=871; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=9JHmO47xFcHiKwRcWRppqe+FIDEC/EmRY/1PhD8wx0w=; b=w78Pw/hDL8SLhPCEJMXKoxFhO6U0UOpZUF5rYcwLAwMKc44iN6Fghd4LGUQo47mNIYLcxJvJo zAPLDw5OR5UBab9ZlI6me33T5i3eV780/WGOyOnbwyhtJdakaPzl5cE X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-ORIG-GUID: zvwBPOTZtiMY63d7ogcrg50ZGYLi97mx X-Proofpoint-GUID: zvwBPOTZtiMY63d7ogcrg50ZGYLi97mx X-Authority-Analysis: v=2.4 cv=FpU1OWrq c=1 sm=1 tr=0 ts=6a907984 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=M4Tw70yJP9P6qS8g1QAA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX79+dLorq8U7M 7q6w0bmsJX7/M+jnJcgYwePAxGNmemXAbm+Ba1soKar2L3Yf1a9ZRMINozuFP6/6yRwCv26I4yH M7+XxaqLb3N8yKMNm90vPrk/1L/JLjTZVxRQewSbx1gpvPu25iVvTG+CdUw8wmtWNDg7hPfRp+T ToEmf9S08c+4TqWruqMoK3zgPmYbLYgcANMjX/uMaF0opcaha45F2Nw17SDTL33b2Uq0SQlnh9g 2J8dfdUOg15kIVPaORnXBjurpEft63/2ztIBbVn4z8ozUHQiQTrAWzgqMoo9fxnEw8MO0FVeStJ Kk/tNzqLKFchOPmk/jpIp8gF+xVuVrH9YQ+XOKBCI70t5xomqpUrp2kFTEPTr6IlR6lkJyHZoi9 QmdzJHooKORE9faXCimpJGSRwP56h5cye60u3PqwRMCW74//HRxN5c3U3P0mp8xk0bFuThXNBnX Ud2CHR/KP16cxvsKqmQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX9yNeaWUlS0/f DyKH78dCwpGpbtJbS6XpTeiEPiJNvYF8tkCecFLDySHsukis9rhA8h5zCRNDHEnHqxmK6FtoRJo JFLXPcvIX79UUZRiL0s0Qy6tXumnn/c= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Document the SCM firmware interface found on the Qualcomm Kuno SoC. Reviewed-by: Bartosz Golaszewski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index 037d4ad8f718..ecee5aef65a7 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -37,6 +37,7 @@ properties: - qcom,scm-ipq9574 - qcom,scm-ipq9650 - qcom,scm-kaanapali + - qcom,scm-kuno - qcom,scm-maili - qcom,scm-mdm9607 - qcom,scm-milos --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91DEF4C77B8 for ; Thu, 27 Aug 2026 17:53:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853199; cv=none; b=KCVV7YSlqi/VT+D3sfaQ+Ar0aApm1vt6/9pvK1FMffIEFfafQKDpttMiulTdF+RPtSWUsnscUCrLm+sEvy5mj4XueGjvZM7EP8mpEHvJscOUtR5lf2epWOcJJDcgRXjGpWol9Xzu06NqfvA5FZEWS1ovy87qC522BtSZeGoVqJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853199; c=relaxed/simple; bh=ItYoLNnh/itsBdfqIb42AjjkJMdlnXNAkIHidF5zyeE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Yz7c37SrWWLdeqhLkq8OA3a5TyMp19bmY6VF7VxXkNWklg+xFUJbqzGaintareqd3DTYtq6XMi1pzKuIzJSIz1GLF/LMH3hRNSAuUIpq0u+Dwzx9OYO6TQRcdkFpG2J6HOth5U2chvRCHo53WiW99tjbofF8aDWGmJmxZeidnCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=RkHbSgXe; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ID8kaomV; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="RkHbSgXe"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ID8kaomV" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXf1m1568373 for ; Thu, 27 Aug 2026 17:53:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= C6e0CuKO+gMRclt1VJTiG7s7VdbGf2b3bc5vZVAaf7s=; b=RkHbSgXez7KatwTr 4FyAAyx7HlHKvwwXWKclK5ehgzUEX8GPZaG1PwKPW5brqgytQ1+6FlTccR0L167g aO8kSI57OUH8P1JlGgdmDH8bRhwEvnaAPI8mapMy324ajW+igDqlk3VcZSsJLJ5O YUFh55k6n6/NCgKS4QJZ1T0aSO/ffUU2ULuMEQim9tpiBa8/yHufcvUdK0a7KF7r 74K0zSMt3QRQ7BCG5TMljp+ZTy/f8qyoES6OAnBLpDswdsajiGAS5sN1D/7gBqcE jnGsN+HeN7NuCOB6KNqr+OcscHsJlNw9c9wB+oCi4up1j90UXj9ggsMrexuUlVlm 0LpWNA== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ga8m5mabv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:53:16 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-cc18ced1a5aso294319a12.1 for ; Thu, 27 Aug 2026 10:53:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853196; x=1788457996; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=C6e0CuKO+gMRclt1VJTiG7s7VdbGf2b3bc5vZVAaf7s=; b=ID8kaomVzq7hvUeNWx7gd8GZZXDdeepUCel+kNgDnEsyR2EppxujUFaOYD8WE2s6Tw /g9nQPbtkGI1Q+0WLqmYKet/OMl1D/PElMh5j0GfYpDfuSSwAXNBgvAJf2nhEFZZD9OV uQvmlioalWi7Vt8Ku0flC8asWPKzrgodpFwH7Rj/tX1b+Aqfg4DkaARsK50kkmZXTsJU 7xyiZosN8HY6/K0NOPD1xWYHilHPnWpCZFjYDTX/fWX4KJS7WamRCOMlVDsANikGs44b BPPF+/uwmwLquV6Lh5c7xIKU84+36pUMX24hqyW/rtCiNcu7ObnqJB5SEXH/ur2bP0es funA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853196; x=1788457996; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=C6e0CuKO+gMRclt1VJTiG7s7VdbGf2b3bc5vZVAaf7s=; b=TPbjEQVkNsqmX0PFj2CdtUmerqNzvsDxwTCDIrKRFWFKGMEWUYZp4tzACympW+slRJ ZpJhy/vG97xE0BUfoxOdHwQwt7Gu9HFajahepURiS4yLTvJaCEzzjYhSjYQZ9LzTxGUF xJvJ2KuGNtSUhYxyKjWRty58/M0d6eTw3FaUrrKwlrxDl2hpr8ZYMzCXVD6VX2Plaah3 fCPLp03oIFBBuk/yfDgxS/XlvLxlsgLth0Y90XSKcxt75n4YaRlUC6B6XuYbl1Spy6Cu 4FwCK11OEPLiOecrqLVJedh/MOwYyb5pBftaqwfXt5OCsdLs4d5weIxkDAJD1JQj+X4Q N/8Q== X-Forwarded-Encrypted: i=1; AHgh+Rr5J0UGhbnyhvswPRbkt3klNcQ+7ACJRrVV9XitgiawNCox0xw09ErmzgoHqMARQN9iZ7MO0Q7smZowyhw=@vger.kernel.org X-Gm-Message-State: AFuF++nnGbpuqlkSvyvqm5VRez6OgBj8JTZnX66cOfPXuGTV6aa96KrS CEyQqs+E0OSkEQ8vGNHWd8achLULXozIpKMYzcGGn7MhSXoP6XbDjZQ9HO1a/uWBuDxDuYKJTHJ hRweqzpt1v83je3c4wD4nFbvvoTdrmZ+dAVFR3B+HkJ2nkTkWru3ADmC5ChChV1Un6ZI= X-Gm-Gg: AR+sD10H0a2atB8RrY1BbCp+QGMYdIyEsrVu34BBG9F5PcVi+erxv1xAzQvtqNiXDau BykCAX23ezre6CE9IPwKFPU1cBal7ChEiTt2woAS7J7bxdlCuU5sExLysHQ1xnJkj7xWTmE9VXr NEdOm2tFAAl/BenQ+ncElb0VCFgbMrqmRj27Dt2kIIEuNiZxjqhmcNnyHiWnrHg88EOda44LK52 /A5qWaxuvmBCRQjHdqDh7uE9n37G1vIikoS2Qn+Lm9zvPiUNyjLcvJ/EUXOSm8VpEOZ6YET1VlU 9REaN4XvcwZMd5CjVpxuFEqntczVo6EQQRg3MSo0C4a34178ezsGJasBSpAqBiXiL/KZYzuiVDI w4bMERupPz488KPhA7PM/gMO8wVOw5TnAiOhjs60Ppwbuu/lCKZRm8XCtWWwVquWrFsf//LJC+Q YDcd6Itp1P0vNYEHkO5TJZb7I= X-Received: by 2002:a05:6a21:496:b0:3c4:1916:9d40 with SMTP id adf61e73a8af0-3d2672043dfmr1491363637.12.1787853195994; Thu, 27 Aug 2026 10:53:15 -0700 (PDT) X-Received: by 2002:a05:6a21:496:b0:3c4:1916:9d40 with SMTP id adf61e73a8af0-3d2672043dfmr1491257637.12.1787853195497; Thu, 27 Aug 2026 10:53:15 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:53:15 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:17 +0530 Subject: [PATCH v5 14/15] dt-bindings: arm: qcom: Document Kuno IDP board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-14-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Bartosz Golaszewski X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=2321; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=ItYoLNnh/itsBdfqIb42AjjkJMdlnXNAkIHidF5zyeE=; b=C22RJD5sgzvXUOzBpV9SoyCEBIxzbYbYsy92vpBFw5E8Raay6bzCVz+AMEy5zCta5NZdYmEjX +fifQkm05AXCQk5irvSl1ZhVhXNOkL2Zm9HU3RI5mZzga5NYVGEcGxq X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-ORIG-GUID: _Z7hSY2qHpsZoeKCsYJDPAi-s7zsltRA X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX5LYMLwKMrn01 qLcA33B2eU2+Rdtfi1PA4R44Hzv2Znc9+QWzipKVbORFiOVWDXr4EOGfyJnhaiwScZ2TQrSm5C7 5GDvKtjHEIdjYEuiy4/Qr2hx3QUQW1s= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX0g25rezOb5v+ ioUNHJsarbiFPVTtfGVdK0yQJhEee/zB8b9PI22AKyBdepa5Hd7kBi/T8F/TzTm41lrCm+vGjGl oOGXmWDglb9RUXU3Rd2UJ7Cqv4kwSyRBy/sjMNlqmtOA+ho5Xnrjpf7YfSvxCF2pNL+Cjf909qA 03LpwU2PoD78wh/fjAPbRN0kItn/hGvakUQpIDKLJH6s3XTetcYlaFygbls+6/YO6qXXihadmKH 4CRaoxF8rI0V6d6BonArgIVmM+jEGdqHWzR8tVeK15/mjB91WSMki9qz/EtwnHB0cmN377nNc9j 5r+lhgAw1jzkKPY4/isk7cgu0+or8/BW3RAck1XOC8YJ+TU9psKQzP4/W1nl3w7pbtPd6j1I6lF lQzvcHhmtYR3rDZxP0mKdWCEn6pKAcv7+RYUkl3MBzmb6nzM32moT5u1S6UK7TyJXI/3e1eEOey m5hMIG06LE1qXTO8+Pg== X-Proofpoint-GUID: _Z7hSY2qHpsZoeKCsYJDPAi-s7zsltRA X-Authority-Analysis: v=2.4 cv=SomgLvO0 c=1 sm=1 tr=0 ts=6a90798c cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=vXfy1ps2I0IJequeNBIA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Document the Qualcomm Kuno IDP board and register the "kuno" codename in the SoC naming convention schema. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bartosz Golaszewski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 4 ++-- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Document= ation/devicetree/bindings/arm/qcom-soc.yaml index e7160b63d814..179aadc86a9f 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -30,7 +30,7 @@ select: contains: oneOf: - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd= [amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|mil= os|nord|shikra).*$" + - pattern: "^qcom,.*(eliza|kaanapali|kuno|glymur|hawi|mahua|mail= i|milos|nord|shikra).*$" required: - compatible =20 @@ -42,7 +42,7 @@ properties: - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm= |x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" - - pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|n= ord|shikra)-.+$" + - pattern: "^qcom,(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|mi= los|nord|shikra)-.+$" =20 # Legacy namings - variations of existing patterns/compatibles are= OK, # but do not add completely new entries to these: diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index ff8a35df7862..ca02a2f0396f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -175,6 +175,11 @@ properties: - qcom,kaanapali-qrd - const: qcom,kaanapali =20 + - items: + - enum: + - qcom,kuno-idp + - const: qcom,kuno + - items: - enum: - qcom,mahua-crd --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A17014B0485 for ; Thu, 27 Aug 2026 17:53:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853208; cv=none; b=nfgQ36zc1Y1OxXxJivA6T1QG0luZrrFay6im1U4f3Lxo+3ISSyPwjss3oOVKLTr3XItZ51Ej1WTfI1RRfuOK/WM2twp05OdO94/n94vDR7shhR9oG1pioR+u24VpmsqWcPuHLy/ouOip2rBx9tl5f5LTc7vc3WTzMn5SpBwrGzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787853208; c=relaxed/simple; bh=VMPk8iPi43dEtmYkKXt01Gm+7aUp6TmVF3AL6pfOShE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L5QIwR+NrDlFmiQxhqDQ+/VOIelYfiMvmBZWW4PTNjwQdKE8kX5NLkI+Rv3X10SZ8edKWwT9KxRiijh4/NPdh3d/WRHZlFoty7risd6kUfhcwNoDa9+6J63XwmljlDhEzDN4CHPvBbRDP36hylwmrQxoo3lk1FKqrZGxU8r+ugs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=RoUyBHsB; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=PXUP7Y/u; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="RoUyBHsB"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="PXUP7Y/u" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67RHXhmh000691 for ; Thu, 27 Aug 2026 17:53:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 1CyKk8AZ6pREhlf/bx2YZm9z4JF80rBaz1RtOIA/3FU=; b=RoUyBHsBNWngjiyx SC1e6d0HWVnKGmJ8HNlTIUMdtGU3iHaWs3e7KWnZkkgChLn2oGxbhaIsTSniPDux hNieNIaNyYoc39YMW1tmeqjJaeIS8vMSlF6x0e3x4n4llI5TQ7yurd63dB4ZqZP+ HdZ1k44v7jO/akgmufKvUkP0UizoYcw935/eoG03uKPfdrGaM5aoWY421uZgjCvh Fr3ov+9NxOLXdl/4KZNNaIwD3q911gtlKGVcuoiiKlQVAz1IcXnOlo1T5qpdPILQ duXE+Uh/EBTaV5jzrIuZw0UmuQB7ntdmEMJtr0yR9QgOuI2QwnFOZi/802ioRZ2n y7W1Vw== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ga6etvt5v-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 27 Aug 2026 17:53:25 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cc18ced1a5aso294613a12.1 for ; Thu, 27 Aug 2026 10:53:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787853205; x=1788458005; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=1CyKk8AZ6pREhlf/bx2YZm9z4JF80rBaz1RtOIA/3FU=; b=PXUP7Y/uJam+upzx5BCAFoDzmu4en6lR+z42MslLkguZAKwTpH6SCs2XRrGPCTSNF5 9LjdrC4g/cwCPcdbwMPY9+HNzcL1heki35EZ9jlP1D3k+qGJ+1rkBnEo9NWFceWfvj4D +USMcm51trociDdbBEdXjA5lAgHHRcT4kmxs8TKERSlRLsCizAQ1e79xZibNml08ZQiP GySNCmWA2lnTmoLoB9yBs8cER5yq8BzXz/sZZ4Nt3XGhvpCGK4C7fgvZcLic3YbgS/uX w0+1bF5KwI+Aznrg8P7j9iwpiHGZW4xX7o/pqhjm9GKNa6hdtKnYV93z4ghZQADL3ReC Fwvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787853205; x=1788458005; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=1CyKk8AZ6pREhlf/bx2YZm9z4JF80rBaz1RtOIA/3FU=; b=pdFVePyOg/KkqzXmpte+CK4D+ThXVCme+v8SPilvxvafvwoYEZ40gJoM/W9lVqLSDg A9pnKOyX7XlNj/ahufvD6j02I4BLQHCeCLKE87I0DmsZhneoCSEUZedHX/te5qg9SzPc coXro9GJsPgMENnoaxUYPmZ4EN8+Ip/zDk6DTc/9N+RD8Ijsu3RVyqjLZ017FibP8vAo rB5++L1erw2Gk7O8UV4hMzxVaBDxBUnMiT8iA18sYqHYF8HZNZOV8KYB3GXIQ4vl0OO0 sEG67hSzZ3LdfONLhhUJef/rjSxH+AiD5BHzSQGauzxNhdwa3E/dN4oljGVXQHm1uJnm on7A== X-Forwarded-Encrypted: i=1; AHgh+RoXfKmAxuIaIDBJG+7nAEQrAfQGutUe9P0+QLZgRA7xiXRi65h+MkgdHDkOXrMQKCho3AlgL6mx+XWL4Fk=@vger.kernel.org X-Gm-Message-State: AFuF++mhsZ7GqjDRoVGSPINGTBxgqIJTFDzx8o/U51cfbitltMyJxU2c GgiHAqKXXDdJQ6zWnR5EoZR5WGaywhEi3BJpG37Thxt+3EoFRtDyZv4Yx0SYahpP6GlpwKmuWkZ d30OL9HfSyjafMjBPdN/YfqYl45trO56S9v/nCqCQwQ3trRs4ERyPpu3v6GGTZ2/x5tg= X-Gm-Gg: AR+sD12zVMYcCECJ+XC47xNIEhfioM3umOBG0+mKNTgXAKIGa7nHBd3FWrMgzkGBXTE H5bLAszY/xmkeMPPu0qCZsoE90a+xIhPfhNqXqMf1+VPVRTAjbW75J9b0EeftvEEiVofNxnu4cs VOPG/JgtqNjEzaxx0eKBAOmO4nwbfpUXENQXO7peVWgsPXTMfGnc15Yxq3G8ih+DXBiGSUUGM0j /pKl9yYLEtuQ2JTyaFFCGAv1YPt8z3v8O3z86DiSADR3ExZrURfQgCtgQP3r7cFmua5e04VoJdS J0IPGIDrM/2V164iSzPno7juoiviJc7bmXjx6xrjCQpF8jcYy2+mSSMbKblabvt4MS46hPIcyzf 7Z4JXq/Evlji2BCZ2Gjvt3GLIZrA8yCQ3ZoO5r4lfuUObrbkYif9aaL4pixnLDgUvxQJWN5RK7t ibYHAyV1Sf2PanVI3fPmBEnQg= X-Received: by 2002:a05:6a20:4327:b0:3c4:1493:6822 with SMTP id adf61e73a8af0-3d268397a7dmr1297316637.18.1787853204839; Thu, 27 Aug 2026 10:53:24 -0700 (PDT) X-Received: by 2002:a05:6a20:4327:b0:3c4:1493:6822 with SMTP id adf61e73a8af0-3d268397a7dmr1297174637.18.1787853204196; Thu, 27 Aug 2026 10:53:24 -0700 (PDT) Received: from hu-hardshar-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d60d25esm23889316eec.4.2026.08.27.10.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 10:53:23 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 23:21:18 +0530 Subject: [PATCH v5 15/15] ARM: dts: qcom: Add initial device tree for Kuno SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v5-15-6d47636a8f09@oss.qualcomm.com> References: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Dmitry Baryshkov , Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787853069; l=12320; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=VMPk8iPi43dEtmYkKXt01Gm+7aUp6TmVF3AL6pfOShE=; b=JY8a8bNF+NhKBRGw0iQbbCEsNI0isE3kg2wH/V6ufIlGCglawxYxcoumT06soZ38H1K1n15bJ CxF8dJp1b03DQ2QMsSF2K9bANUnsHT1apA29ap2ir+wh8sCWL19llne X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Authority-Analysis: v=2.4 cv=NrThtcdJ c=1 sm=1 tr=0 ts=6a907995 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=lKFnvmfiA1OmcLezn0cA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: tFxSxgvxTF_lPkCraAP1UxuTdUmriC_P X-Proofpoint-GUID: tFxSxgvxTF_lPkCraAP1UxuTdUmriC_P X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX7Z5Vd1YrOrUi p1oOXknAUVNP9a7T6O9MKM/D7Ea6ffsyYPjQUoX8yeMkZ7lTJ4/OPCF6oPRF6nNJA/aDc523IXR 5W0U1/T7cmFFqFndRV+r/14sJm/9ZKPgcq9cVa1wWDFEdpZRVS7JJ6mbXdIyFNvZoTe0UOGG26p diP6ex8PN3dlToGmHRrqtnKznmT6L2j6iuKFnKvkMa13XBKQuaLoisRstTLjKl7pS3RWiEnzr/i ZpY9L7B6C0GxcPyl3gSsEivsMpSMMX66gd5CA+pIAcgeu5jyA0camCvGQvs+NK9Cz70USy9s2vK zyp5nf44DDrzZmTbdapi0GjwABsCBEhcanG2Mff3h0FUGQlq9Ew69t/NQIgrK39CAZdR1OlJh57 VTTUl+z497B2gSnLs8Q3hlgwaglWOhIMniQuZqhL36sCZidOCmLDI0ByJAfr2h17zVCDlFoUjnt geuXTiY5plb8DjbvAUQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE1MSBTYWx0ZWRfX5+GDWUguJ0QF TGJ1sK3aXrgEUB82Nwmmp7S97MEJqVfSkisXpSaX3daUnhbXDVQo+4ll94Lhmo/EesxyIMZKeaA iVwvXwHCOf9o7YOlF9H9+xAB68PoOgk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270151 Add SoC-level DTSI (qcom-kuno.dtsi) and IDP board DTS (qcom-kuno-idp.dts) for the Qualcomm Kuno SoC. Peripherals included in this initial set: - Single Cortex-A7 CPU with PSCI idle states - RPMh RSC with clock controller, power domains, and BCM voter - GCC (Global Clock Controller) - TLMM pin controller (110 GPIOs) - Interconnect (aggre-noc, cnoc-main) - GENI UART console (QUP SE3) - SMEM, hardware spinlocks (TCSR mutex) Reviewed-by: Dmitry Baryshkov Reviewed-by: Linus Walleij Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- arch/arm/boot/dts/qcom/Makefile | 1 + arch/arm/boot/dts/qcom/qcom-kuno-idp.dts | 25 ++ arch/arm/boot/dts/qcom/qcom-kuno.dtsi | 423 +++++++++++++++++++++++++++= ++++ 3 files changed, 449 insertions(+) diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makef= ile index 026d5b682b2b..7327a7b8180e 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D \ qcom-ipq4019-ap.dk07.1-c2.dtb \ qcom-ipq8064-ap148.dtb \ qcom-ipq8064-rb3011.dtb \ + qcom-kuno-idp.dtb \ qcom-msm8226-microsoft-dempsey.dtb \ qcom-msm8226-microsoft-makepeace.dtb \ qcom-msm8226-microsoft-moneypenny.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts b/arch/arm/boot/dts/q= com/qcom-kuno-idp.dts new file mode 100644 index 000000000000..c2f6650d3fe6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "qcom-kuno.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Kuno IDP"; + compatible =3D "qcom,kuno-idp", "qcom,kuno"; + + aliases { + serial0 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart3 { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-kuno.dtsi b/arch/arm/boot/dts/qcom= /qcom-kuno.dtsi new file mode 100644 index 000000000000..d0c6e3f21a14 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&intc>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a7"; + reg =3D <0x0>; + enable-method =3D "psci"; + cpu-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "standalone-pc"; + entry-latency-us =3D <350>; + exit-latency-us =3D <450>; + min-residency-us =3D <1774>; + arm,psci-suspend-param =3D <0x40000003>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "pc"; + entry-latency-us =3D <550>; + exit-latency-us =3D <750>; + min-residency-us =3D <6700>; + arm,psci-suspend-param =3D <0x40000004>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + idle-state-name =3D "cx-min"; + entry-latency-us =3D <750>; + exit-latency-us =3D <2350>; + min-residency-us =3D <9144>; + arm,psci-suspend-param =3D <0x40000008>; + }; + }; + }; + + firmware { + scm { + compatible =3D "qcom,scm-kuno", "qcom,scm"; + }; + }; + + memory { + device_type =3D "memory"; + /* Bootloader will fill base and size */ + reg =3D <0x0 0x0>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0>; + }; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + quickboot@82100000 { + reg =3D <0x82100000 0x100000>; + no-map; + }; + + aop-image@82200000 { + reg =3D <0x82200000 0x20000>; + no-map; + }; + + aop-cmd-db@82220000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x82220000 0x20000>; + no-map; + }; + + aop-config@82240000 { + reg =3D <0x82240000 0x20000>; + no-map; + }; + + uefi-log@82260000 { + reg =3D <0x82260000 0x10000>; + no-map; + }; + + ipa-fw@82270000 { + reg =3D <0x82270000 0x10000>; + no-map; + }; + + smem@82280000 { + compatible =3D "qcom,smem"; + reg =3D <0x82280000 0xc0000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + tme-crashdump@82340000 { + reg =3D <0x82340000 0x40000>; + no-map; + }; + + tme-log@82380000 { + reg =3D <0x82380000 0x4000>; + no-map; + }; + + access-control-db@82384000 { + reg =3D <0x82384000 0x40000>; + no-map; + }; + + secdata@823c4000 { + reg =3D <0x823c4000 0x1000>; + no-map; + }; + + modem-efs@823c5000 { + reg =3D <0x823c5000 0x10000>; + no-map; + }; + + cpucp-fw@82400000 { + reg =3D <0x82400000 0x80000>; + no-map; + }; + + xbl-dt-log@824c0000 { + reg =3D <0x824c0000 0x20000>; + no-map; + }; + + qtee@82500000 { + reg =3D <0x82500000 0x180000>; + no-map; + }; + + trusted-apps@82680000 { + reg =3D <0x82680000 0x600000>; + no-map; + }; + + mpss-audio@82e00000 { + reg =3D <0x82e00000 0x5a00000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0xffffffff>; + + gcc: clock-controller@80000 { + compatible =3D "qcom,kuno-gcc"; + reg =3D <0x00080000 0x1f4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qup0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x009c0000 0x2000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x0 0x1000000>; + + uart3: serial@98c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&uart_console_active>; + pinctrl-1 =3D <&uart_console_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + }; + }; + + cnoc_main: interconnect@1580000 { + compatible =3D "qcom,kuno-cnoc-main"; + reg =3D <0x01580000 0x19200>; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@1640000 { + compatible =3D "qcom,kuno-aggre-noc"; + reg =3D <0x01640000 0x33400>; + clocks =3D <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01f40000 0x40000>; + #hwlock-cells =3D <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,kuno-pdc", "qcom,pdc"; + reg =3D <0x0b220000 0x10000>; + qcom,pdc-ranges =3D <1 148 6>, + <9 156 2>, + <17 164 7>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + restart@c264000 { + compatible =3D "qcom,pshold"; + reg =3D <0x0c264000 0x1000>; + }; + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,kuno-tlmm"; + reg =3D <0x0f000000 0x400000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 110>; + interrupt-controller; + #interrupt-cells =3D <2>; + + uart_console_active: uart-console-active-state { + pins =3D "gpio8", "gpio9"; + function =3D "qup0_se3_mira"; + drive-strength =3D <2>; + bias-disable; + }; + + uart_console_sleep: uart-console-sleep-state { + pins =3D "gpio8", "gpio9"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x17000000 0x1000>, + <0x17002000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + timer@17020000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x17020000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + frame@17021000 { + reg =3D <0x17021000 0x1000>, + <0x17022000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + }; + + apps_rsc: rsc@17040000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x17040000 0x10000>, + <0x17050000 0x10000>, + <0x17060000 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + /* drv-1: placeholder (unused) */ + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + power-domains =3D <&cluster_pd>; + + rpmhcc: clock-controller { + compatible =3D "qcom,kuno-rpmh-clk"; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,kuno-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + }; + }; + + timer { + compatible =3D "arm,armv7-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0