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Drop the explicit ARM64 dependency so the driver can be selected on 32-bit ARM as well; QCOM_GENI_SE already sits under the QCOM_SOC menuconfig, which is gated by ARCH_QCOM || COMPILE_TEST, so no replacement dependency is needed. Acked-by: Mukesh Savaliya Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/soc/qcom/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 2b524154d9fb..9f703261d7ac 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -39,7 +39,6 @@ config QCOM_COMMAND_DB =20 config QCOM_GENI_SE tristate "Qualcomm GENI Serial Engine Driver" - depends on ARM64 || COMPILE_TEST default ARCH_QCOM help This driver is used to manage Generic Interface (GENI) firmware based --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5523348EBEF for ; Thu, 27 Aug 2026 16:38:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Docu= mentation/devicetree/bindings/power/qcom,rpmpd.yaml index 0a45e1f55062..7fc3927efa27 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -21,6 +21,7 @@ properties: - qcom,glymur-rpmhpd - qcom,hawi-rpmhpd - qcom,kaanapali-rpmhpd + - qcom,kuno-rpmhpd - qcom,mdm9607-rpmpd - qcom,milos-rpmhpd - qcom,msm8226-rpmpd --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E0FB3839A8 for ; Thu, 27 Aug 2026 16:38:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Kuno exposes CX, MX and MXC domains (including always-on variants). Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/pmdomain/qcom/rpmhpd.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index 90743275942d..725ce802f683 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -681,6 +681,21 @@ static const struct rpmhpd_desc kaanapali_desc =3D { .num_pds =3D ARRAY_SIZE(kaanapali_rpmhpds), }; =20 +/* Kuno RPMH power domains */ +static struct rpmhpd *kuno_rpmhpds[] =3D { + [RPMHPD_CX] =3D &cx, + [RPMHPD_CX_AO] =3D &cx_ao, + [RPMHPD_MX] =3D &mx, + [RPMHPD_MX_AO] =3D &mx_ao, + [RPMHPD_MXC] =3D &mxc, + [RPMHPD_MXC_AO] =3D &mxc_ao, +}; + +static const struct rpmhpd_desc kuno_desc =3D { + .rpmhpds =3D kuno_rpmhpds, + .num_pds =3D ARRAY_SIZE(kuno_rpmhpds), +}; + /* Hawi RPMH powerdomains */ static struct rpmhpd *hawi_rpmhpds[] =3D { [RPMHPD_CX] =3D &cx, @@ -885,6 +900,7 @@ static const struct of_device_id rpmhpd_match_table[] = =3D { { .compatible =3D "qcom,glymur-rpmhpd", .data =3D &glymur_desc }, { .compatible =3D "qcom,hawi-rpmhpd", .data =3D &hawi_desc }, { .compatible =3D "qcom,kaanapali-rpmhpd", .data =3D &kaanapali_desc }, + { .compatible =3D "qcom,kuno-rpmhpd", .data =3D &kuno_desc }, { .compatible =3D "qcom,milos-rpmhpd", .data =3D &milos_desc }, { .compatible =3D "qcom,nord-rpmhpd", .data =3D &nord_desc }, { .compatible =3D "qcom,qcs615-rpmhpd", .data =3D &qcs615_desc }, --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C237F48D89B for ; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 2b446aca5207..9d521ac9c33f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,glymur-rpmh-clk - qcom,hawi-rpmh-clk - qcom,kaanapali-rpmh-clk + - qcom,kuno-rpmh-clk - qcom,milos-rpmh-clk - qcom,nord-rpmh-clk - qcom,qcs615-rpmh-clk --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6CDB4908C6 for ; Thu, 27 Aug 2026 16:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6b1a24bce78sm4253171eaf.3.2026.08.27.09.38.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:39:04 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 22:08:06 +0530 Subject: [PATCH v4 05/15] clk: qcom: clk-rpmh: Add support for Kuno RPMh clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v4-5-dd34f235fc1a@oss.qualcomm.com> References: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Dmitry Baryshkov , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787848688; l=2134; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=HmmI194gyOrC38jn1kOmQP92tC7eCM4pFbLwZh2jkps=; b=O3qlxz7x08CxfPx7NLFQOLsmocO6gj9/OPvgz5ckr+LYjwS8kVRwv1nhMSuHzk1SITQ2RAlQZ oh0cx0wx1jqDxuqlif9h+RqOAy1CpyG+tAYF0Bac5NKmhO9lTdGgQOA X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-ORIG-GUID: zdwQVGWz1ocGGSdf5_Jw_psGO3xgKfKQ X-Proofpoint-GUID: zdwQVGWz1ocGGSdf5_Jw_psGO3xgKfKQ X-Authority-Analysis: v=2.4 cv=FpU1OWrq c=1 sm=1 tr=0 ts=6a906829 cx=c_pps a=7uPEO8VhqeOX8vTJ3z8K6Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=cbMe9IPPLhjBV4UIYdkA:9 a=QEXdDO2ut3YA:10 a=EXS-LbY8YePsIyqnH6vw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX21HFLhFqb2+i v6cxjgUvB09BBR9WMK7yerQQMPtXux8sLLel9ZtjldMru6VtDqFXUzB4ZrfyjnXZzmJbh9MvQXn NXvGtQwhqa7aNGqhKBK6vdRSMZpO49JKefdBHLK0yEwmsTc/jfrXoMzFPidSm4dNTR38FcEOiZC V3aW/o/S2Rp+2BvKCGuLG2w8Plno9HELNRBD9zf3W1Zdt7qXjDUaqMr4jmvFMR+OmarglAdxVws Wci1152J46U9yrXNr00dcuZbqVPgPfMtkSFHEDYBF+LWQEFU1VK+yYglyFXQm8cnvhGLGOemoS+ IhXcRY9DlDOJKe7Eo8Znnt/OmuDgZ/oF6nhE1X3zwWExZOmz9a42CV2Z83TGq/k6etQKsJUzfjm BQzruMOeCEcQfD7mz8io0xP9Bq1zHji4uLvDK+rvpdsvLA2TdShL8BNqTGIW4pvRgSa/AE+8dkc 38uur+RmiM3SLA6ZkgQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX6AmI9a44kZvw w19zUXr94N/3sSOQWGIHmCSCrY5IttmGk7eS6AVb6Z/6lqmuv/uyRBZ7vHPun3yzb+MNZIoV2X2 1VziyTKC+IXfPepXTJSeVIq8Pt84hU0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270140 Add the RPMh clock description for the Qualcomm Kuno SoC so the qcom,kuno-rpmh-clk compatible can provide the RPMh-managed clocks to consumers: the CXO div-2 (and always-on variant), RF clock 1 (and always-on variant), the QPIC BCM clock and the IPA clock. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/clk/qcom/clk-rpmh.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index a224a94ae273..ec8700b6186d 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -937,6 +937,20 @@ static const struct clk_rpmh_desc clk_rpmh_kaanapali = =3D { .num_clks =3D ARRAY_SIZE(kaanapali_rpmh_clocks), }; =20 +static struct clk_hw *kuno_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_RF_CLK1] =3D &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] =3D &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_QPIC_CLK] =3D &clk_rpmh_qpic_clk.hw, + [RPMH_IPA_CLK] =3D &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_kuno =3D { + .clks =3D kuno_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(kuno_rpmh_clocks), +}; + static struct clk_hw *eliza_rpmh_clocks[] =3D { [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, @@ -1097,6 +1111,7 @@ static const struct of_device_id clk_rpmh_match_table= [] =3D { { .compatible =3D "qcom,glymur-rpmh-clk", .data =3D &clk_rpmh_glymur}, { .compatible =3D "qcom,hawi-rpmh-clk", .data =3D &clk_rpmh_hawi}, { .compatible =3D "qcom,kaanapali-rpmh-clk", .data =3D &clk_rpmh_kaanapal= i}, + { .compatible =3D "qcom,kuno-rpmh-clk", .data =3D &clk_rpmh_kuno}, { .compatible =3D "qcom,milos-rpmh-clk", .data =3D &clk_rpmh_milos}, { .compatible =3D "qcom,nord-rpmh-clk", .data =3D &clk_rpmh_nord}, { .compatible =3D "qcom,qcs615-rpmh-clk", .data =3D &clk_rpmh_qcs615}, --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43ACC4908D1 for ; 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Signed-off-by: Hardeep Sharma --- .../bindings/interconnect/qcom,kuno-rpmh.yaml | 118 +++++++++++++++++= ++++ include/dt-bindings/interconnect/qcom,kuno.h | 89 ++++++++++++++++ 2 files changed, 207 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.= yaml b/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml new file mode 100644 index 000000000000..20d169b31142 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,kuno-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Kuno SoC + +maintainers: + - Hardeep Sharma + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provide= r is + able to communicate with the BCM through the Resource State Coordinator = (RSC) + associated with each execution environment. Provider nodes must point to= at + least one RPMh device child node pertaining to their RSC and each provid= er + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,kuno.h + +properties: + compatible: + enum: + - qcom,kuno-aggre-noc + - qcom,kuno-clk-virt + - qcom,kuno-cnoc-main + - qcom,kuno-dc-noc + - qcom,kuno-mc-virt + - qcom,kuno-mem-noc + - qcom,kuno-pcie-anoc + - qcom,kuno-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,kuno-clk-virt + - qcom,kuno-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + const: qcom,kuno-aggre-noc + then: + properties: + clocks: + items: + - description: System NoC USB SF AXI clock + - description: IPA clock + + - if: + properties: + compatible: + contains: + const: qcom,kuno-system-noc + then: + properties: + clocks: + items: + - description: IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,kuno-aggre-noc + - qcom,kuno-system-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clk_virt: interconnect-0 { + compatible =3D "qcom,kuno-clk-virt"; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@1640000 { + compatible =3D "qcom,kuno-aggre-noc"; + reg =3D <0x01640000 0x33400>; + clocks =3D <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; +... diff --git a/include/dt-bindings/interconnect/qcom,kuno.h b/include/dt-bind= ings/interconnect/qcom,kuno.h new file mode 100644 index 000000000000..eacbae38f85d --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,kuno.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H + +#define MASTER_SYS_TCU 0 +#define MASTER_LLCC 1 +#define MASTER_AUDIO 2 +#define MASTER_CPUCP 3 +#define MASTER_PCIE_RSCC 4 +#define MASTER_QDSS_BAM 5 +#define MASTER_QPIC 6 +#define MASTER_QUP_0 7 +#define MASTER_ANOC_SNOC 8 +#define MASTER_CNOC_DC_NOC 9 +#define MASTER_CNOC_SNOC 10 +#define MASTER_MSS_PROC 11 +#define MASTER_GEM_NOC_CFG 12 +#define MASTER_GEM_NOC_CNOC 13 +#define MASTER_GEM_NOC_PCIE_SNOC 14 +#define MASTER_ANOC_PCIE_GEM_NOC 15 +#define MASTER_SNOC_SF_MEM_NOC 16 +#define MASTER_QUP_CORE_0 17 +#define MASTER_CRYPTO 18 +#define MASTER_IPA 19 +#define MASTER_MSS_NAV 20 +#define MASTER_TME 21 +#define MASTER_APPSS_PROC 22 +#define MASTER_EMAC 23 +#define MASTER_IPA_PCIE 24 +#define MASTER_PCIE_0 25 +#define MASTER_QDSS_DAP 26 +#define MASTER_QDSS_ETR 27 +#define MASTER_QDSS_ETR_1 28 +#define MASTER_SDCC_4 29 +#define MASTER_USB3_0 30 +#define SLAVE_EBI1 31 +#define SLAVE_AHB2PHY 32 +#define SLAVE_AOSS 33 +#define SLAVE_APPSS 34 +#define SLAVE_AUDIO 35 +#define SLAVE_CLK_CTL 36 +#define SLAVE_RBCPR_CX_CFG 37 +#define SLAVE_RBCPR_MXA_CFG 38 +#define SLAVE_RBCPR_MXC_CFG 39 +#define SLAVE_CRYPTO_0_CFG 40 +#define SLAVE_EMAC_CFG 41 +#define SLAVE_IMEM_CFG 42 +#define SLAVE_IPA_CFG 43 +#define SLAVE_IPC_ROUTER_CFG 44 +#define SLAVE_LAGG_CFG 45 +#define SLAVE_MCCC_MASTER 46 +#define SLAVE_CNOC_MSS 47 +#define SLAVE_PCIE_0_CFG 48 +#define SLAVE_PCIE_RSC_CFG 49 +#define SLAVE_PDM 50 +#define SLAVE_PMU_WRAPPER_CFG 51 +#define SLAVE_PRNG 52 +#define SLAVE_QDSS_CFG 53 +#define SLAVE_QPIC 54 +#define SLAVE_QUP_0 55 +#define SLAVE_SDCC_4 56 +#define SLAVE_SPMI_VGI_COEX 57 +#define SLAVE_TCSR 58 +#define SLAVE_TLMM 59 +#define SLAVE_TME_CFG 60 +#define SLAVE_USB3 61 +#define SLAVE_VSENSE_CTRL_CFG 62 +#define SLAVE_A1NOC_CFG 63 +#define SLAVE_DDRSS_CFG 64 +#define SLAVE_LLCC 65 +#define SLAVE_GEM_NOC_CNOC 66 +#define SLAVE_SNOC_MEM_NOC_SF 67 +#define SLAVE_MEM_NOC_PCIE_SNOC 68 +#define SLAVE_ANOC_PCIE_GEM_NOC 69 +#define SLAVE_SNOC_CNOC 70 +#define SLAVE_ANOC_THROTTLE_CFG 71 +#define SLAVE_QUP_CORE_0 72 +#define SLAVE_BOOT_IMEM 73 +#define SLAVE_IMEM 74 +#define SLAVE_SERVICE_GEM_NOC 75 +#define SLAVE_PCIE_0 76 +#define SLAVE_QDSS_STM 77 +#define SLAVE_TCU 78 + +#endif --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DAFD47FB01 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6b1a24bce78sm4253171eaf.3.2026.08.27.09.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:39:22 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 22:08:08 +0530 Subject: [PATCH v4 07/15] interconnect: qcom: Add Kuno interconnect provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v4-7-dd34f235fc1a@oss.qualcomm.com> References: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Konrad Dybcio X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787848688; l=26248; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=YMt01tffizd/QItWpTO+o5zLFgJYC/uKbLx8J6+OhjU=; b=6AAtGYzhrKnwNe7GFXety7pFvGn4l5r9EjrEBpJiCwpfep8TlLthsW74aksQ7bwWvi8WjEc7+ 363vmSP8P6WDIHR7sHSHN0xdlXGkvPz0XEsBwAJd5ryaGytELCOkuwy X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX+Pf1hjId3FN7 3uoaFsXvodEXU+kgrmq34erpZCAd6tRWWGI+DOVofs0N0ueYr/n8MFtmH0bQsQfMwJYZGt8VBSB JUgjxXsw60WJUV4X3IG/MNe2vmCSv2fLjlC5ONfsV0oUPLmEXHAJz9+AkVKtbVVBbUcVkdA7pjy EFuL+mKlMpJ/TPFexisb8YdXhWjvVCoaEPcaPv2W50bEcGcSNAVkNJNYb2hktNLob3d6dDF6r7S pV+0auASYbCMWc6JrTCTLdkgAjcJjFy7Avu7tXF2MT2j+2Z5i013CTESSr1l7y5CFA4RWkwiJ3q UtOjjggJXV+Omle76xZR8QrQKic5NC0aXly4ewyzzfwk9da2iSvxi3hw20aGn6Sk0jDHqWrV226 1VngfqOyRJGLa3MNDaZ7M71V2Iouy9unDA1D1wcucckTQDgVQXYrdhM+6N127Ufi2BloXogIQaf dAPBpPib7YEt+3hXZLg== X-Proofpoint-GUID: v6CFCWvXBgfrGqho8HEWlt8qNwfiNDkl X-Authority-Analysis: v=2.4 cv=C+3ZDwP+ c=1 sm=1 tr=0 ts=6a90683c cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=hP8eNrtOcc-Xm2DFYy4A:9 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-ORIG-GUID: v6CFCWvXBgfrGqho8HEWlt8qNwfiNDkl X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX0JgI/4lD1Wib kDhw0qLu6tYkzGJnipkNX9x0II6rX3K9wsKTUBca8nWfs2vqw2SHFFQkV8DC2GD3Qi9WXAHV56a IO+f1AILSYpGVhFtNlVRwf2VYayKHUI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270140 Add the interconnect provider driver for the Qualcomm Kuno SoC to enable bus bandwidth voting on the platform. This includes the aggre-noc and cnoc-main NoC instances with their associated BCM nodes. Reviewed-by: Konrad Dybcio Signed-off-by: Hardeep Sharma --- drivers/interconnect/qcom/Kconfig | 13 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/kuno.c | 988 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1003 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index b3187acf90b8..6e6b80f22dbd 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -47,6 +47,19 @@ config INTERCONNECT_QCOM_KAANAPALI This is a driver for the Qualcomm Network-on-Chip on kaanapali-based platforms. =20 +config INTERCONNECT_QCOM_KUNO + tristate "Qualcomm Kuno interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + depends on ARM || COMPILE_TEST + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + default ARCH_QCOM + help + This is a driver for the Qualcomm Network-on-Chip on kuno-based + platforms. The interconnect provider collects and aggregates the + consumer bandwidth requests to satisfy constraints placed on the + Network-on-Chip performance states. + config INTERCONNECT_QCOM_MAILI tristate "Qualcomm MAILI interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 5f139a370bbe..a71478aaf591 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -8,6 +8,7 @@ qnoc-eliza-objs :=3D eliza.o qnoc-glymur-objs :=3D glymur.o qnoc-hawi-objs :=3D hawi.o qnoc-kaanapali-objs :=3D kaanapali.o +qnoc-kuno-objs :=3D kuno.o qnoc-maili-objs :=3D maili.o qnoc-milos-objs :=3D milos.o qnoc-msm8909-objs :=3D msm8909.o @@ -57,6 +58,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) +=3D qnoc-eliza.o obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) +=3D qnoc-glymur.o obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) +=3D qnoc-hawi.o obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) +=3D qnoc-kaanapali.o +obj-$(CONFIG_INTERCONNECT_QCOM_KUNO) +=3D qnoc-kuno.o obj-$(CONFIG_INTERCONNECT_QCOM_MAILI) +=3D qnoc-maili.o obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) +=3D qnoc-milos.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o diff --git a/drivers/interconnect/qcom/kuno.c b/drivers/interconnect/qcom/k= uno.c new file mode 100644 index 000000000000..546622cf8cea --- /dev/null +++ b/drivers/interconnect/qcom/kuno.c @@ -0,0 +1,988 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2_phy =3D { + .name =3D "qhs_ahb2_phy", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_audio =3D { + .name =3D "qhs_audio", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_mxa =3D { + .name =3D "qhs_cpr_mxa", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_mxc =3D { + .name =3D "qhs_cpr_mxc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_crypto_cfg =3D { + .name =3D "qhs_crypto_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_emac0_cfg =3D { + .name =3D "qhs_emac0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie_rscc =3D { + .name =3D "qhs_pcie_rscc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pmu_wrapper_cfg =3D { + .name =3D "qhs_pmu_wrapper_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qpic =3D { + .name =3D "qhs_qpic", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex =3D { + .name =3D "qhs_spmi_vgi_coex", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .name =3D "qhs_usb3", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_anoc_throttle_cfg =3D { + .name =3D "qss_anoc_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qxs_boot_imem =3D { + .name =3D "qxs_boot_imem", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_lagg =3D { + .name =3D "qhs_lagg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_mccc_master =3D { + .name =3D "qhs_mccc_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node srvc_memnoc =3D { + .name =3D "srvc_memnoc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .link_nodes =3D { &qhs_lagg, &qhs_mccc_master }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &ebi }, +}; + +static struct qcom_icc_node qnm_memnoc_cfg =3D { + .name =3D "qnm_memnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &srvc_memnoc }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie =3D { + .name =3D "qnm_memnoc_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &xs_pcie_0 }, +}; + +static struct qcom_icc_node xm_ipa2pcie =3D { + .name =3D "xm_ipa2pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &xs_pcie_0 }, +}; + +static struct qcom_icc_node qns_ddrss_cfg =3D { + .name =3D "qns_ddrss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qnm_cnoc }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_node qhm_pcie_rscc =3D { + .name =3D "qhm_pcie_rscc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 34, + .link_nodes =3D { &qhs_ahb2_phy, &qhs_aoss, + &qhs_apss, &qhs_audio, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto_cfg, &qhs_emac0_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie0_cfg, &qhs_pdm, + &qhs_pmu_wrapper_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_usb3, &qhs_vsense_ctrl_cfg, + &qns_ddrss_cfg, &qss_anoc_throttle_cfg, + &qxs_boot_imem, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_memnoc_cnoc =3D { + .name =3D "qnm_memnoc_cnoc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 35, + .link_nodes =3D { &qhs_ahb2_phy, &qhs_aoss, + &qhs_apss, &qhs_audio, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto_cfg, &qhs_emac0_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie0_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_pmu_wrapper_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3, + &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg, + &qss_anoc_throttle_cfg, &qxs_boot_imem, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qns_memnoc_cnoc =3D { + .name =3D "qns_memnoc_cnoc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_memnoc_cnoc }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc }, +}; + +static struct qcom_icc_node qnm_mdsp =3D { + .name =3D "qnm_mdsp", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc }, +}; + +static struct qcom_icc_node xm_apps0 =3D { + .name =3D "xm_apps0", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .link_nodes =3D { &qns_llcc, &qns_memnoc_cnoc, + &qns_pcie }, +}; + +static struct qcom_icc_node qns_pcie_memnoc =3D { + .name =3D "qns_pcie_memnoc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_memnoc_sf =3D { + .name =3D "qns_memnoc_sf", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_memnoc }, +}; + +static struct qcom_icc_node qhm_cpucp =3D { + .name =3D "qhm_cpucp", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_memnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre_noc =3D { + .name =3D "qnm_aggre_noc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qnm_cnoc_datapath =3D { + .name =3D "qnm_cnoc_datapath", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qxm_mss_nav_ce =3D { + .name =3D "qxm_mss_nav_ce", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qxm_tme =3D { + .name =3D "qxm_tme", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &qns_memnoc_sf, &xs_pcie_0 }, +}; + +static struct qcom_icc_node qns_a1noc =3D { + .name =3D "qns_a1noc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre_noc }, +}; + +static struct qcom_icc_node qns_snoc_datapath =3D { + .name =3D "qns_snoc_datapath", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qnm_cnoc_datapath }, +}; + +static struct qcom_icc_node qhm_audio =3D { + .name =3D "qhm_audio", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qhm_qpic =3D { + .name =3D "qhm_qpic", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_emac_0 =3D { + .name =3D "xm_emac_0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_qdss_etr0 =3D { + .name =3D "xm_qdss_etr0", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_qdss_etr1 =3D { + .name =3D "xm_qdss_etr1", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_usb3 =3D { + .name =3D "xm_usb3", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 36, + .link_nodes =3D { &qhs_ahb2_phy, &qhs_aoss, + &qhs_apss, &qhs_audio, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto_cfg, &qhs_emac0_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie0_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_pmu_wrapper_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3, + &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg, + &qns_snoc_datapath, &qss_anoc_throttle_cfg, + &qxs_boot_imem, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .enable_mask =3D 0x8, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .enable_mask =3D 0x1, + .num_nodes =3D 39, + .nodes =3D { &qhm_pcie_rscc, &qnm_memnoc_cnoc, + &xm_qdss_dap, &qhs_ahb2_phy, + &qhs_aoss, &qhs_apss, + &qhs_audio, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_crypto_cfg, + &qhs_emac0_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_pcie0_cfg, + &qhs_pcie_rscc, &qhs_pdm, + &qhs_pmu_wrapper_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_usb3, &qhs_vsense_ctrl_cfg, + &qns_ddrss_cfg, &qns_snoc_datapath, + &qss_anoc_throttle_cfg, &qxs_boot_imem, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D 0x1, + .num_nodes =3D 2, + .nodes =3D { &qns_memnoc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .enable_mask =3D 0x1, + .num_nodes =3D 1, + .nodes =3D { &xm_pcie3_0 }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 2, + .nodes =3D { &qns_a1noc, &qnm_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .num_nodes =3D 1, + .nodes =3D { &qxm_mss_nav_ce }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .num_nodes =3D 1, + .nodes =3D { &xs_pcie_0 }, +}; + +static struct qcom_icc_bcm * const aggre_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre_noc_nodes[] =3D { + [MASTER_AUDIO] =3D &qhm_audio, + [MASTER_QDSS_BAM] =3D &qhm_qdss_bam, + [MASTER_QPIC] =3D &qhm_qpic, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_EMAC] =3D &xm_emac_0, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr1, + [MASTER_SDCC_4] =3D &xm_sdc4, + [MASTER_USB3_0] =3D &xm_usb3, + [SLAVE_A1NOC_CFG] =3D &qns_a1noc, +}; + +static const struct qcom_icc_desc kuno_aggre_noc =3D { + .nodes =3D aggre_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre_noc_nodes), + .bcms =3D aggre_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup0, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, +}; + +static const struct qcom_icc_desc kuno_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_PCIE_RSCC] =3D &qhm_pcie_rscc, + [MASTER_GEM_NOC_CNOC] =3D &qnm_memnoc_cnoc, + [MASTER_QDSS_DAP] =3D &xm_qdss_dap, + [SLAVE_AHB2PHY] =3D &qhs_ahb2_phy, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_APPSS] =3D &qhs_apss, + [SLAVE_AUDIO] =3D &qhs_audio, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] =3D &qhs_cpr_cx, + [SLAVE_RBCPR_MXA_CFG] =3D &qhs_cpr_mxa, + [SLAVE_RBCPR_MXC_CFG] =3D &qhs_cpr_mxc, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto_cfg, + [SLAVE_EMAC_CFG] =3D &qhs_emac0_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_CNOC_MSS] =3D &qhs_mss_cfg, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_RSC_CFG] =3D &qhs_pcie_rscc, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PMU_WRAPPER_CFG] =3D &qhs_pmu_wrapper_cfg, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QPIC] =3D &qhs_qpic, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_SDCC_4] =3D &qhs_sdc4, + [SLAVE_SPMI_VGI_COEX] =3D &qhs_spmi_vgi_coex, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_USB3] =3D &qhs_usb3, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_DDRSS_CFG] =3D &qns_ddrss_cfg, + [SLAVE_SNOC_CNOC] =3D &qns_snoc_datapath, + [SLAVE_ANOC_THROTTLE_CFG] =3D &qss_anoc_throttle_cfg, + [SLAVE_BOOT_IMEM] =3D &qxs_boot_imem, + [SLAVE_IMEM] =3D &qxs_imem, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc kuno_cnoc_main =3D { + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_node * const dc_noc_nodes[] =3D { + [MASTER_CNOC_DC_NOC] =3D &qnm_cnoc, + [SLAVE_LAGG_CFG] =3D &qhs_lagg, + [SLAVE_MCCC_MASTER] =3D &qhs_mccc_master, +}; + +static const struct qcom_icc_desc kuno_dc_noc =3D { + .nodes =3D dc_noc_nodes, + .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc kuno_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mem_noc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const mem_noc_nodes[] =3D { + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_MSS_PROC] =3D &qnm_mdsp, + [MASTER_GEM_NOC_CFG] =3D &qnm_memnoc_cfg, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_APPSS_PROC] =3D &xm_apps0, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_GEM_NOC_CNOC] =3D &qns_memnoc_cnoc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, + [SLAVE_SERVICE_GEM_NOC] =3D &srvc_memnoc, +}; + +static const struct qcom_icc_desc kuno_mem_noc =3D { + .nodes =3D mem_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), + .bcms =3D mem_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mem_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { + &bcm_sn1, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] =3D { + [MASTER_PCIE_0] =3D &xm_pcie3_0, + [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_memnoc, +}; + +static const struct qcom_icc_desc kuno_pcie_anoc =3D { + .nodes =3D pcie_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), + .bcms =3D pcie_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn2, + &bcm_sn4, + &bcm_sn7, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_CPUCP] =3D &qhm_cpucp, + [MASTER_ANOC_SNOC] =3D &qnm_aggre_noc, + [MASTER_CNOC_SNOC] =3D &qnm_cnoc_datapath, + [MASTER_GEM_NOC_PCIE_SNOC] =3D &qnm_memnoc_pcie, + [MASTER_MSS_NAV] =3D &qxm_mss_nav_ce, + [MASTER_TME] =3D &qxm_tme, + [MASTER_IPA_PCIE] =3D &xm_ipa2pcie, + [SLAVE_SNOC_MEM_NOC_SF] =3D &qns_memnoc_sf, + [SLAVE_PCIE_0] =3D &xs_pcie_0, +}; + +static const struct qcom_icc_desc kuno_system_noc =3D { + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,kuno-aggre-noc", .data =3D &kuno_aggre_noc }, + { .compatible =3D "qcom,kuno-clk-virt", .data =3D &kuno_clk_virt }, + { .compatible =3D "qcom,kuno-cnoc-main", .data =3D &kuno_cnoc_main }, + { .compatible =3D "qcom,kuno-dc-noc", .data =3D &kuno_dc_noc }, + { .compatible =3D "qcom,kuno-mc-virt", .data =3D &kuno_mc_virt }, + { .compatible =3D "qcom,kuno-mem-noc", .data =3D &kuno_mem_noc }, + { .compatible =3D "qcom,kuno-pcie-anoc", .data =3D &kuno_pcie_anoc }, + { .compatible =3D "qcom,kuno-system-noc", .data =3D &kuno_system_noc }, + { } +}; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6b1a24bce78sm4253171eaf.3.2026.08.27.09.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:39:31 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 22:08:09 +0530 Subject: [PATCH v4 08/15] dt-bindings: pinctrl: qcom: Add Kuno TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v4-8-dd34f235fc1a@oss.qualcomm.com> References: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787848688; l=3999; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=9Fecwe0sAktGee+deC69QVwT+mIH7oP8T6NEsor/Km4=; b=fwLGC9BZJIM5/cbpxIquX/TnSdBSPeRCEgbOicDICXCkapdsB4ssHBS5BUut2kAvBatwP8yAA assKcfeMqvABvnEGMHmDn+jlO5WBEyhGQF3ncvO0mJgMRD5KdDrNKxg X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX7lpcTtWlEOIr uHkBS1GPIy2xkeSMkkx79pNtGxemEsab3D4xEaOjhrUODp0OuiVj9o4ld6LV3xOwqwDZnGKZZSt hmtns5UzVrtD/J/c54dgiHjSc4NBMpctCXXuQA0HJRD8xkeewFYzNcvbpFhHQLUG/WDlXuK1yCq kYYzgBy68aXayJgbQr8EIgHIJBykt1iKn0z5EmHl7/qIunSxqCTJh5/ChGjpe+bljgYxB3IiHP4 Rzf/j+LuQNCbNmXOAXY0Zcn3sNcp96Y9H3iL0rodRdaCw99YPWgi/xEJox6m9uBp5oyx1P+J+4R fPuubjTyQQizVA9WSO/P45EiGV7smfu/fy2EU4hdYc38oAM25N95YbryAXLKUo52Lx5XYnw4cps HEhqbqYRHjiVAnVq1e9bKczNVNC9UyhXqWXhRTOjBTdgYCOjQ3MaK7zwfnimIQTTMdtf2ITXcxP yRfauDehr4K+vVHGxTA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX4+bikBfrx1LW 0PvPJD2o2dreljPfhJRgHZX7EJr19ioSgX60Tid6Cb9WPe/48IRHiRZc/KrsWyr0WkazYEpGeqJ rlfcCrUl/7n7nHfiJhtzSVevfiyN3sE= X-Proofpoint-ORIG-GUID: 8Nt3_0XKCLsr8nUuVMDCBHcLjKvURf1l X-Proofpoint-GUID: 8Nt3_0XKCLsr8nUuVMDCBHcLjKvURf1l X-Authority-Analysis: v=2.4 cv=e8E2j6p/ c=1 sm=1 tr=0 ts=6a906845 cx=c_pps a=WJcna6AvsNCxL/DJwPP1KA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=CaveSyEksWnKhASb3GUA:9 a=QEXdDO2ut3YA:10 a=_Y9Zt4tPzoBS9L09Snn2:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270140 Add device tree bindings for the Top Level Mode Multiplexer (TLMM) pin controller block found on the Qualcomm Kuno platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- .../bindings/pinctrl/qcom,kuno-tlmm.yaml | 110 +++++++++++++++++= ++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml = b/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml new file mode 100644 index 000000000000..2250526dfae2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kuno-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kuno TLMM block + +maintainers: + - Hardeep Sharma + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Kuno SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kuno-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 55 + + gpio-line-names: + maxItems: 110 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-kuno-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kuno-tlmm-state" + additionalProperties: false + +$defs: + qcom-kuno-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ gpio, audio_ref_clk, coex_uart, ebi2_lcd_a, + ebi2_lcd_cs, ebi2_lcd_reset, ebi2_lcd_te, emac_mdc, emac_m= dio, + emac_pps_in, emac_ptp_aux, emac_ptp_pps, gcc_gp1_clk, + gcc_gp2_clk, gcc_gp3_clk, mi2s0_data0, mi2s0_data1, mi2s0_= sck, + mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s_mclk, nav_gpio, pci_e_rst, + pcie_clkreq_n, pll_bist_sync, pll_clk_aux, qdss_cti_trig0, + qdss_cti_trig1, qdss_cti_trig1_mire, qdss_gpio_traceclk, + qdss_gpio_tracectl, + qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se3_mirb, + qup0_se4, sdc4_clk, sdc4_cmd, + sdc4_data, sdc4_tb_trig, sgmii_phy_intr, spmi_coex_clk, + spmi_coex_data, spmi_vgi_hwevent, uim1_clk, uim1_data, + uim1_present, uim1_reset, usb2phy_ac_en ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,kuno-tlmm"; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6b1a24bce78sm4253171eaf.3.2026.08.27.09.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:39:40 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 22:08:10 +0530 Subject: [PATCH v4 09/15] pinctrl: qcom: Add Kuno pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v4-9-dd34f235fc1a@oss.qualcomm.com> References: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787848688; l=28488; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=6QBQCIqM/a1bmD7kAAxbFF82/u8Zimh6gYjhMTz+96k=; b=0ch43myytjMPsZNo21YwytsqDAJLeBxYTixtKighAj01ZNTJ58Lt4DJ9LWlZFKyP1Q42y6aHV 1ev8TNwTL12BVq6ynF7OhGC6cp9QKnbZxTv1h90dvy2iNfhD/mSKye7 X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX2VZlT4qdKfxL 5vbghb/h/vmQaJg0x0PDwQ8QhGHDD4kyihiTvM+SessBKftgr8FR/czJRgWh3X1ZxHeHb/TtXQd GyUzjHSkoD+Nk6uHVDXuBKbDsoeq+O4= X-Proofpoint-ORIG-GUID: FbBpVTHvhqvbUDrouJcg18ol0OlRcgiY X-Proofpoint-GUID: FbBpVTHvhqvbUDrouJcg18ol0OlRcgiY X-Authority-Analysis: v=2.4 cv=G+Ms1dk5 c=1 sm=1 tr=0 ts=6a90684e cx=c_pps a=zPxD6eHSjdtQ/OcAcrOFGw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=O6wAMhyR-eLTh1z97CkA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=y8BKWJGFn5sdPF1Y92-H:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX9zAE2AXlZs7Q InM0BTm9m1MDOAGa9/gMubBYN813LFICpDJnv21qBBh4bMNZ67qt3W/oJlMndHXxO9XOLvbH2TI Lowh+c928ZXhYfxLOKB/zGaf/pxxx8FeHV4tiUce+D5WvtJ3g954X4sozBq+VPYsEvPWGMfYXoG slFrGAnnWqsJyQlMVDrb28ekkM8/cGHYNY9V7/kIq5IDsUvKCCXbulNidbjGHSHtf/VidPHQRCl nFuthcLhzK8k2Dxp5+rSHu/uDVaA4qwvIXwUikwA/0C9wGKzCtDFPS1E1F/Dyfrs5c+ztGFzb/T bPEsaMekC/zY9UlcFhn1SFoE+TNjDoYOUdex4zbmU1fQZExImYYeMT3SB6ymQy/3818JEdDchvG FmTnD5TogKMkEiUj+E/X5RAf4ZkEvogS/rFQ6ZWRDhgtJRAYKzzV5z/KLFYLMBVXIV0u3KGoDWY IL8gvnYD1No5vK5KOzw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270140 Add the TLMM pinctrl driver for the Qualcomm Kuno platform, supporting 110 GPIOs and their pin multiplexing, pin configuration and gpiolib interface through the common pinctrl-msm driver. Signed-off-by: Hardeep Sharma --- drivers/pinctrl/qcom/Kconfig.msm | 11 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-kuno.c | 801 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 813 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 42875457b5fc..9b95bf8ecb22 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -153,6 +153,17 @@ config PINCTRL_KAANAPALI Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc Kaanapali platform. =20 +config PINCTRL_KUNO + tristate "Qualcomm Kuno pin controller driver" + depends on ARM || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc Kuno platform. + Say Y here to compile statically, or M here to compile it as a + module. If unsure, say N. + config PINCTRL_MAILI tristate "Qualcomm Technologies Inc Maili pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43ecd246afe8..f003add981ab 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_IPQ6018) +=3D pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) +=3D pinctrl-ipq9574.o obj-$(CONFIG_PINCTRL_IPQ9650) +=3D pinctrl-ipq9650.o obj-$(CONFIG_PINCTRL_KAANAPALI) +=3D pinctrl-kaanapali.o +obj-$(CONFIG_PINCTRL_KUNO) +=3D pinctrl-kuno.o obj-$(CONFIG_PINCTRL_MAILI) +=3D pinctrl-maili.o obj-$(CONFIG_PINCTRL_MSM8226) +=3D pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) +=3D pinctrl-msm8660.o diff --git a/drivers/pinctrl/qcom/pinctrl-kuno.c b/drivers/pinctrl/qcom/pin= ctrl-kuno.c new file mode 100644 index 000000000000..404065df2b9f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-kuno.c @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs =3D (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs =3D 10, \ + .ctl_reg =3D REG_BASE + REG_SIZE * id, \ + .io_reg =3D REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg =3D REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg =3D REG_BASE + 0xc + REG_SIZE * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 3, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + } + +static const struct pinctrl_pin_desc kuno_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); + +enum kuno_functions { + msm_mux_gpio, + msm_mux_audio_ref_clk, + msm_mux_coex_uart, + msm_mux_ebi2_lcd_a, + msm_mux_ebi2_lcd_cs, + msm_mux_ebi2_lcd_reset, + msm_mux_ebi2_lcd_te, + msm_mux_emac_mdc, + msm_mux_emac_mdio, + msm_mux_emac_pps_in, + msm_mux_emac_ptp_aux, + msm_mux_emac_ptp_pps, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s_mclk, + msm_mux_nav_gpio, + msm_mux_pci_e_rst, + msm_mux_pcie_clkreq_n, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_qdss_cti_trig0, + msm_mux_qdss_cti_trig1, + msm_mux_qdss_cti_trig1_mire, + msm_mux_qdss_gpio_traceclk, + msm_mux_qdss_gpio_tracectl, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3_mira, + msm_mux_qup0_se3_mirb, + msm_mux_qup0_se4, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sdc4_tb_trig, + msm_mux_sgmii_phy_intr, + msm_mux_spmi_coex_clk, + msm_mux_spmi_coex_data, + msm_mux_spmi_vgi_hwevent, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac_en, + msm_mux__, +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", +}; + +static const char * const audio_ref_clk_groups[] =3D { + "gpio62", +}; + +static const char * const coex_uart_groups[] =3D { + "gpio44", "gpio45", +}; + +static const char * const ebi2_lcd_a_groups[] =3D { + "gpio93", +}; + +static const char * const ebi2_lcd_cs_groups[] =3D { + "gpio94", +}; + +static const char * const ebi2_lcd_reset_groups[] =3D { + "gpio89", +}; + +static const char * const ebi2_lcd_te_groups[] =3D { + "gpio88", +}; + +static const char * const emac_mdc_groups[] =3D { + "gpio98", +}; + +static const char * const emac_mdio_groups[] =3D { + "gpio99", +}; + +static const char * const emac_pps_in_groups[] =3D { + "gpio88", +}; + +static const char * const emac_ptp_aux_groups[] =3D { + "gpio93", "gpio94", +}; + +static const char * const emac_ptp_pps_groups[] =3D { + "gpio93", "gpio94", +}; + +static const char * const gcc_gp1_clk_groups[] =3D { + "gpio34", +}; + +static const char * const gcc_gp2_clk_groups[] =3D { + "gpio46", +}; + +static const char * const gcc_gp3_clk_groups[] =3D { + "gpio35", +}; + +static const char * const mi2s0_data0_groups[] =3D { + "gpio13", +}; + +static const char * const mi2s0_data1_groups[] =3D { + "gpio14", +}; + +static const char * const mi2s0_sck_groups[] =3D { + "gpio15", +}; + +static const char * const mi2s0_ws_groups[] =3D { + "gpio12", +}; + +static const char * const mi2s1_data0_groups[] =3D { + "gpio17", +}; + +static const char * const mi2s1_data1_groups[] =3D { + "gpio18", +}; + +static const char * const mi2s1_sck_groups[] =3D { + "gpio19", +}; + +static const char * const mi2s1_ws_groups[] =3D { + "gpio16", +}; + +static const char * const mi2s_mclk_groups[] =3D { + "gpio62", +}; + +static const char * const nav_gpio_groups[] =3D { + "gpio31", "gpio32", "gpio33", +}; + +static const char * const pci_e_rst_groups[] =3D { + "gpio57", +}; + +static const char * const pcie_clkreq_n_groups[] =3D { + "gpio56", +}; + +static const char * const pll_bist_sync_groups[] =3D { + "gpio47", +}; + +static const char * const pll_clk_aux_groups[] =3D { + "gpio54", +}; + +static const char * const qdss_cti_trig0_groups[] =3D { + "gpio16", "gpio17", "gpio54", "gpio55", "gpio60", "gpio84", "gpio101", + "gpio102", +}; + +static const char * const qdss_cti_trig1_groups[] =3D { + "gpio16", "gpio17", "gpio54", "gpio55", "gpio65", "gpio66", "gpio101", + "gpio102", +}; +static const char * const qdss_cti_trig1_mire_groups[] =3D { + "gpio65", "gpio66", +}; + +static const char * const qdss_gpio_traceclk_groups[] =3D { + "gpio8", +}; + +static const char * const qdss_gpio_tracectl_groups[] =3D { + "gpio9", +}; + +static const char * const qup0_se0_groups[] =3D { + "gpio14", "gpio18", "gpio19", "gpio48", "gpio49", "gpio92", "gpio101", +}; + +static const char * const qup0_se1_groups[] =3D { + "gpio14", "gpio63", "gpio64", "gpio65", "gpio66", "gpio92", "gpio101", +}; + +static const char * const qup0_se2_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio14", "gpio92", "gpio101", +}; + +static const char * const qup0_se3_mira_groups[] =3D { + "gpio8", "gpio9", "gpio14", "gpio16", "gpio17", "gpio92", "gpio101", +}; + +static const char * const qup0_se3_mirb_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const qup0_se4_groups[] =3D { + "gpio10", "gpio11", "gpio14", "gpio80", "gpio81", "gpio92", "gpio101", +}; + +static const char * const sdc4_clk_groups[] =3D { + "gpio103", +}; + +static const char * const sdc4_cmd_groups[] =3D { + "gpio102", +}; + +static const char * const sdc4_data_groups[] =3D { + "gpio104", "gpio105", "gpio106", "gpio107", +}; + +static const char * const sdc4_tb_trig_groups[] =3D { + "gpio101", +}; + +static const char * const sgmii_phy_intr_groups[] =3D { + "gpio91", +}; + +static const char * const spmi_coex_clk_groups[] =3D { + "gpio76", +}; + +static const char * const spmi_coex_data_groups[] =3D { + "gpio75", +}; + +static const char * const spmi_vgi_hwevent_groups[] =3D { + "gpio78", "gpio79", +}; + +static const char * const uim1_clk_groups[] =3D { + "gpio3", +}; + +static const char * const uim1_data_groups[] =3D { + "gpio0", +}; + +static const char * const uim1_present_groups[] =3D { + "gpio1", +}; + +static const char * const uim1_reset_groups[] =3D { + "gpio2", +}; + +static const char * const usb2phy_ac_en_groups[] =3D { + "gpio90", +}; + +static const struct pinfunction kuno_functions[] =3D { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(ebi2_lcd_a), + MSM_PIN_FUNCTION(ebi2_lcd_cs), + MSM_PIN_FUNCTION(ebi2_lcd_reset), + MSM_PIN_FUNCTION(ebi2_lcd_te), + MSM_PIN_FUNCTION(emac_mdc), + MSM_PIN_FUNCTION(emac_mdio), + MSM_PIN_FUNCTION(emac_pps_in), + MSM_PIN_FUNCTION(emac_ptp_aux), + MSM_PIN_FUNCTION(emac_ptp_pps), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s_mclk), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pci_e_rst), + MSM_PIN_FUNCTION(pcie_clkreq_n), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(qdss_cti_trig0), + MSM_PIN_FUNCTION(qdss_cti_trig1), + MSM_PIN_FUNCTION(qdss_cti_trig1_mire), + MSM_PIN_FUNCTION(qdss_gpio_traceclk), + MSM_PIN_FUNCTION(qdss_gpio_tracectl), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3_mira), + MSM_PIN_FUNCTION(qup0_se3_mirb), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sdc4_tb_trig), + MSM_PIN_FUNCTION(sgmii_phy_intr), + MSM_PIN_FUNCTION(spmi_coex_clk), + MSM_PIN_FUNCTION(spmi_coex_data), + MSM_PIN_FUNCTION(spmi_vgi_hwevent), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb2phy_ac_en), +}; + +/* Every pin is maintained as a single group, and missing or non-existing = pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup kuno_groups[] =3D { + [0] =3D PINGROUP(0, uim1_data, _, _, _, _, _, _, _, _), + [1] =3D PINGROUP(1, uim1_present, _, _, _, _, _, _, _, _), + [2] =3D PINGROUP(2, uim1_reset, _, _, _, _, _, _, _, _), + [3] =3D PINGROUP(3, uim1_clk, _, _, _, _, _, _, _, _), + [4] =3D PINGROUP(4, qup0_se2, _, _, _, _, _, _, _, _), + [5] =3D PINGROUP(5, qup0_se2, _, _, _, _, _, _, _, _), + [6] =3D PINGROUP(6, qup0_se2, _, _, _, _, _, _, _, _), + [7] =3D PINGROUP(7, qup0_se2, _, _, _, _, _, _, _, _), + [8] =3D PINGROUP(8, qup0_se3_mira, _, qdss_gpio_traceclk, _, _, _, _, _, = _), + [9] =3D PINGROUP(9, qup0_se3_mira, _, qdss_gpio_tracectl, _, _, _, _, _, = _), + [10] =3D PINGROUP(10, qup0_se4, _, _, _, _, _, _, _, _), + [11] =3D PINGROUP(11, qup0_se4, _, _, _, _, _, _, _, _), + [12] =3D PINGROUP(12, mi2s0_ws, qup0_se3_mirb, _, _, _, _, _, _, _), + [13] =3D PINGROUP(13, mi2s0_data0, qup0_se3_mirb, _, _, _, _, _, _, _), + [14] =3D PINGROUP(14, mi2s0_data1, qup0_se3_mirb, qup0_se0, qup0_se1, qup= 0_se2, + qup0_se3_mira, qup0_se4, _, _), + [15] =3D PINGROUP(15, mi2s0_sck, qup0_se3_mirb, _, _, _, _, _, _, _), + [16] =3D PINGROUP(16, mi2s1_ws, qup0_se3_mira, qdss_cti_trig1, qdss_cti_t= rig0, + _, _, _, _, _), + [17] =3D PINGROUP(17, mi2s1_data0, qup0_se3_mira, qdss_cti_trig1, qdss_ct= i_trig0, + _, _, _, _, _), + [18] =3D PINGROUP(18, mi2s1_data1, qup0_se0, _, _, _, _, _, _, _), + [19] =3D PINGROUP(19, mi2s1_sck, qup0_se0, _, _, _, _, _, _, _), + [20] =3D PINGROUP(20, _, _, _, _, _, _, _, _, _), + [21] =3D PINGROUP(21, _, _, _, _, _, _, _, _, _), + [22] =3D PINGROUP(22, _, _, _, _, _, _, _, _, _), + [23] =3D PINGROUP(23, _, _, _, _, _, _, _, _, _), + [24] =3D PINGROUP(24, _, _, _, _, _, _, _, _, _), + [25] =3D PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] =3D PINGROUP(26, _, _, _, _, _, _, _, _, _), + [27] =3D PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] =3D PINGROUP(28, _, _, _, _, _, _, _, _, _), + [29] =3D PINGROUP(29, _, _, _, _, _, _, _, _, _), + [30] =3D PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] =3D PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] =3D PINGROUP(32, nav_gpio, _, _, _, _, _, _, _, _), + [33] =3D PINGROUP(33, nav_gpio, _, _, _, _, _, _, _, _), + [34] =3D PINGROUP(34, _, gcc_gp1_clk, _, _, _, _, _, _, _), + [35] =3D PINGROUP(35, _, _, gcc_gp3_clk, _, _, _, _, _, _), + [36] =3D PINGROUP(36, _, _, _, _, _, _, _, _, _), + [37] =3D PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] =3D PINGROUP(38, _, _, _, _, _, _, _, _, _), + [39] =3D PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] =3D PINGROUP(40, _, _, _, _, _, _, _, _, _), + [41] =3D PINGROUP(41, _, _, _, _, _, _, _, _, _), + [42] =3D PINGROUP(42, _, _, _, _, _, _, _, _, _), + [43] =3D PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] =3D PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), + [45] =3D PINGROUP(45, coex_uart, _, _, _, _, _, _, _, _), + [46] =3D PINGROUP(46, _, _, _, gcc_gp2_clk, _, _, _, _, _), + [47] =3D PINGROUP(47, _, pll_bist_sync, _, _, _, _, _, _, _), + [48] =3D PINGROUP(48, qup0_se0, _, _, _, _, _, _, _, _), + [49] =3D PINGROUP(49, qup0_se0, _, _, _, _, _, _, _, _), + [50] =3D PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] =3D PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] =3D PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] =3D PINGROUP(53, _, _, _, _, _, _, _, _, _), + [54] =3D PINGROUP(54, qdss_cti_trig1, qdss_cti_trig0, pll_clk_aux, _, _, = _, _, _, _), + [55] =3D PINGROUP(55, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _, _= ), + [56] =3D PINGROUP(56, pcie_clkreq_n, _, _, _, _, _, _, _, _), + [57] =3D PINGROUP(57, pci_e_rst, _, _, _, _, _, _, _, _), + [58] =3D PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] =3D PINGROUP(59, _, _, _, _, _, _, _, _, _), + [60] =3D PINGROUP(60, qdss_cti_trig0, _, _, _, _, _, _, _, _), + [61] =3D PINGROUP(61, _, _, _, _, _, _, _, _, _), + [62] =3D PINGROUP(62, mi2s_mclk, audio_ref_clk, _, _, _, _, _, _, _), + [63] =3D PINGROUP(63, qup0_se1, _, _, _, _, _, _, _, _), + [64] =3D PINGROUP(64, qup0_se1, _, _, _, _, _, _, _, _), + [65] =3D PINGROUP(65, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _= , _, _, _, _), + [66] =3D PINGROUP(66, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _= , _, _, _, _), + [67] =3D PINGROUP(67, _, _, _, _, _, _, _, _, _), + [68] =3D PINGROUP(68, _, _, _, _, _, _, _, _, _), + [69] =3D PINGROUP(69, _, _, _, _, _, _, _, _, _), + [70] =3D PINGROUP(70, _, _, _, _, _, _, _, _, _), + [71] =3D PINGROUP(71, _, _, _, _, _, _, _, _, _), + [72] =3D PINGROUP(72, _, _, _, _, _, _, _, _, _), + [73] =3D PINGROUP(73, _, _, _, _, _, _, _, _, _), + [74] =3D PINGROUP(74, _, _, _, _, _, _, _, _, _), + [75] =3D PINGROUP(75, spmi_coex_data, _, _, _, _, _, _, _, _), + [76] =3D PINGROUP(76, spmi_coex_clk, _, _, _, _, _, _, _, _), + [77] =3D PINGROUP(77, _, _, _, _, _, _, _, _, _), + [78] =3D PINGROUP(78, spmi_vgi_hwevent, _, _, _, _, _, _, _, _), + [79] =3D PINGROUP(79, spmi_vgi_hwevent, _, _, _, _, _, _, _, _), + [80] =3D PINGROUP(80, qup0_se4, _, _, _, _, _, _, _, _), + [81] =3D PINGROUP(81, qup0_se4, _, _, _, _, _, _, _, _), + [82] =3D PINGROUP(82, _, _, _, _, _, _, _, _, _), + [83] =3D PINGROUP(83, _, _, _, _, _, _, _, _, _), + [84] =3D PINGROUP(84, qdss_cti_trig0, _, _, _, _, _, _, _, _), + [85] =3D PINGROUP(85, _, _, _, _, _, _, _, _, _), + [86] =3D PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] =3D PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] =3D PINGROUP(88, ebi2_lcd_te, emac_pps_in, _, _, _, _, _, _, _), + [89] =3D PINGROUP(89, ebi2_lcd_reset, _, _, _, _, _, _, _, _), + [90] =3D PINGROUP(90, usb2phy_ac_en, _, _, _, _, _, _, _, _), + [91] =3D PINGROUP(91, sgmii_phy_intr, _, _, _, _, _, _, _, _), + [92] =3D PINGROUP(92, qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_s= e4, _, _, _, _), + [93] =3D PINGROUP(93, ebi2_lcd_a, emac_ptp_pps, emac_ptp_aux, _, _, _, _,= _, _), + [94] =3D PINGROUP(94, ebi2_lcd_cs, emac_ptp_pps, emac_ptp_aux, _, _, _, _= , _, _), + [95] =3D PINGROUP(95, _, _, _, _, _, _, _, _, _), + [96] =3D PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] =3D PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] =3D PINGROUP(98, emac_mdc, _, _, _, _, _, _, _, _), + [99] =3D PINGROUP(99, emac_mdio, _, _, _, _, _, _, _, _), + [100] =3D PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] =3D PINGROUP(101, sdc4_tb_trig, qdss_cti_trig1, qdss_cti_trig0, qup= 0_se0, + qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _), + [102] =3D PINGROUP(102, sdc4_cmd, qdss_cti_trig1, qdss_cti_trig0, _, _, _= , _, _, _), + [103] =3D PINGROUP(103, sdc4_clk, _, _, _, _, _, _, _, _), + [104] =3D PINGROUP(104, sdc4_data, _, _, _, _, _, _, _, _), + [105] =3D PINGROUP(105, sdc4_data, _, _, _, _, _, _, _, _), + [106] =3D PINGROUP(106, sdc4_data, _, _, _, _, _, _, _, _), + [107] =3D PINGROUP(107, sdc4_data, _, _, _, _, _, _, _, _), + [108] =3D PINGROUP(108, _, _, _, _, _, _, _, _, _), + [109] =3D PINGROUP(109, _, _, _, _, _, _, _, _, _), +}; + +static const struct msm_gpio_wakeirq_map kuno_pdc_map[] =3D { + { 1, 62 }, { 2, 83 }, { 4, 59 }, { 5, 107 }, { 6, 112 }, { 7, 119 }, + { 8, 123 }, { 10, 52 }, { 11, 73 }, { 12, 74 }, { 13, 75 }, { 14, 76 }, + { 15, 77 }, { 16, 81 }, { 17, 82 }, { 18, 80 }, { 19, 100 }, { 21, 88 }, + { 22, 99 }, { 23, 84 }, { 24, 85 }, { 25, 97 }, { 26, 86 }, { 27, 102 }, + { 28, 87 }, { 35, 103 }, { 43, 90 }, { 44, 60 }, { 45, 61 }, { 46, 104 }, + { 47, 89 }, { 48, 105 }, { 49, 106 }, { 50, 101 }, { 52, 109 }, { 53, 79 = }, + { 54, 110 }, { 55, 111 }, { 56, 78 }, { 57, 71 }, { 60, 113 }, { 61, 114 = }, + { 63, 115 }, { 64, 116 }, { 65, 57 }, { 66, 117 }, { 68, 64 }, { 69, 118 = }, + { 71, 108 }, { 73, 120 }, { 74, 121 }, { 76, 47 }, { 77, 122 }, { 78, 65 = }, + { 79, 66 }, { 80, 124 }, { 81, 125 }, { 82, 126 }, { 83, 127 }, { 84, 93 = }, + { 85, 128 }, { 86, 129 }, { 87, 70 }, { 88, 130 }, { 96, 68 }, { 98, 50 }, + { 99, 67 }, { 100, 51 }, { 101, 53 }, { 102, 54 }, { 103, 98 }, { 104, 91= }, + { 105, 69 }, { 106, 55 }, { 107, 56 }, { 109, 72 }, +}; + +static const struct msm_pinctrl_soc_data kuno_tlmm =3D { + .pins =3D kuno_pins, + .npins =3D ARRAY_SIZE(kuno_pins), + .functions =3D kuno_functions, + .nfunctions =3D ARRAY_SIZE(kuno_functions), + .groups =3D kuno_groups, + .ngroups =3D ARRAY_SIZE(kuno_groups), + .ngpios =3D 110, + .wakeirq_map =3D kuno_pdc_map, + .nwakeirq_map =3D ARRAY_SIZE(kuno_pdc_map), +}; + +static int kuno_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &kuno_tlmm); +} + +static const struct of_device_id kuno_tlmm_of_match[] =3D { + { .compatible =3D "qcom,kuno-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, kuno_tlmm_of_match); + +static struct platform_driver kuno_tlmm_driver =3D { + .driver =3D { + .name =3D "kuno-tlmm", + .of_match_table =3D kuno_tlmm_of_match, + }, + .probe =3D kuno_tlmm_probe, +}; + +static int __init kuno_tlmm_init(void) +{ + return platform_driver_register(&kuno_tlmm_driver); +} +arch_initcall(kuno_tlmm_init); + +static void __exit kuno_tlmm_exit(void) +{ + platform_driver_unregister(&kuno_tlmm_driver); +} +module_exit(kuno_tlmm_exit); + +MODULE_DESCRIPTION("QTI Kuno TLMM driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6b1a24bce78sm4253171eaf.3.2026.08.27.09.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:39:49 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 22:08:11 +0530 Subject: [PATCH v4 10/15] dt-bindings: clock: qcom: Add Kuno Global Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v4-10-dd34f235fc1a@oss.qualcomm.com> References: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787848688; l=5749; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=9FPCV87eitw661yJc7gqbrscj5MlCzlDB1E+PFlfCyc=; b=THRecKjInsGkrbimoAUM4rAtwm+vArD8Vaf5lSlwEQ4dUSeGaQmP6dfSzryd5NEjMZ5B77BYC Ss+a1EuK9FRBwpWRMrja3mJJe+XTdiw2wkyp6OErQbQLVEC1HtMtIHG X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Authority-Analysis: v=2.4 cv=NrThtcdJ c=1 sm=1 tr=0 ts=6a906856 cx=c_pps a=AKZTfHrQPB8q3CcvmcIuDA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=PKuh8qK-LUMqOkA3WUgA:9 a=QEXdDO2ut3YA:10 a=pF_qn-MSjDawc0seGVz6:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: KX3KxBgUHcToVfNxG5W9IopL-qEzl0ZH X-Proofpoint-GUID: KX3KxBgUHcToVfNxG5W9IopL-qEzl0ZH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfXwknbnpL1rX29 V9BppUUln0M+hDycP6AcgnOtRM8wQnb64LoerfCouN86R7vURGH2jYkrsKgxBVHbBBqvulsEISP MRUVWtRRhBdp1WVlj1OtKVQbfv9iXECP/8tXc688b3Ot2NqpDGasMNnBKbxCgiJdbZVKJprK0YE VHli9oqtXPZSJUxbqe1LAY32WueoFPli/e1dNoojlJhRj3sN3gdBF13pYd27amS2pcqY1ah5KEL kJKpQV9vQ5LtuwmcvWz4t2iwG216JsaHigmOkwA3jISPDaOSlfYdc8npWzCQo/Dtk1HXisHEHqH D8RQj4DJ+OkPYs6ZvdEYzfRwYht/8tga1iixVmIud8/gpa4B/cDQgjEdpyePM1wV+/+nh5EnOnL STrLYtbBeDH7a7QhEWx7fKoEJrjUeNEg+wIa+wyjXh9ZJ/8Jvv3j5N87N9Yw30APg1/doIc/eXA zQIUSxk0NgQWzANx2gg== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX/63cU50jrEfu yliWJ5nYfAQvSVHAr6S0hevsDGzA7daP4y/4gNA/SLFEdvK8fkAqBthjFLgyKghtFe1Xg1uBP2t kBVIGLIrYVt/hKfyPXAJhEUKTaIItbU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270140 Document the Global Clock Controller (GCC) binding and associated clock/reset IDs for the Qualcomm Kuno SoC. Signed-off-by: Hardeep Sharma --- .../devicetree/bindings/clock/qcom,kuno-gcc.yaml | 52 +++++++++++ include/dt-bindings/clock/qcom,kuno-gcc.h | 100 +++++++++++++++++= ++++ 2 files changed, 152 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml b/D= ocumentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml new file mode 100644 index 000000000000..7ae37033a1af --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kuno-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Kuno + +maintainers: + - Hardeep Sharma + +description: | + Qualcomm global clock control module provides the clocks and resets on K= uno. + + See also: include/dt-bindings/clock/qcom,kuno-gcc.h + +properties: + compatible: + const: qcom,kuno-gcc + + clocks: + items: + - description: Board XO source + - description: Board active-only XO source + - description: Sleep clock source + - description: PCIe pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible =3D "qcom,kuno-gcc"; + reg =3D <0x00080000 0x1f4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie_pipe_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,kuno-gcc.h b/include/dt-binding= s/clock/qcom,kuno-gcc.h new file mode 100644 index 000000000000..a237b25a061d --- /dev/null +++ b/include/dt-bindings/clock/qcom,kuno-gcc.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H +#define _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL2 2 +#define GPLL3 3 +#define GPLL4 4 +#define GPLL4_OUT_EVEN 5 +#define GCC_EMAC0_AXI_CLK 7 +#define GCC_EMAC0_PHY_AUX_CLK 8 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 9 +#define GCC_EMAC0_PTP_CLK 10 +#define GCC_EMAC0_PTP_CLK_SRC 11 +#define GCC_EMAC0_RGMII_CLK 12 +#define GCC_EMAC0_RGMII_CLK_SRC 13 +#define GCC_EMAC0_SLV_AHB_CLK 14 +#define GCC_EMAC_0_CLKREF_EN 15 +#define GCC_GP1_CLK 16 +#define GCC_GP1_CLK_SRC 17 +#define GCC_GP2_CLK 18 +#define GCC_GP2_CLK_SRC 19 +#define GCC_GP3_CLK 20 +#define GCC_GP3_CLK_SRC 21 +#define GCC_PCIE_0_CLKREF_EN 22 +#define GCC_PCIE_AUX_CLK 23 +#define GCC_PCIE_AUX_CLK_SRC 24 +#define GCC_PCIE_AUX_PHY_CLK_SRC 25 +#define GCC_PCIE_CFG_AHB_CLK 26 +#define GCC_PCIE_MSTR_AXI_CLK 27 +#define GCC_PCIE_PIPE_CLK 28 +#define GCC_PCIE_PIPE_CLK_SRC 29 +#define GCC_PCIE_RCHNG_PHY_CLK 30 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 31 +#define GCC_PCIE_SLEEP_CLK 32 +#define GCC_PCIE_SLV_AXI_CLK 33 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 34 +#define GCC_PDM2_CLK 35 +#define GCC_PDM2_CLK_SRC 36 +#define GCC_PDM_AHB_CLK 37 +#define GCC_PDM_XO4_CLK 38 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 39 +#define GCC_QUPV3_WRAP0_CORE_CLK 40 +#define GCC_QUPV3_WRAP0_S0_CLK 41 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 42 +#define GCC_QUPV3_WRAP0_S1_CLK 43 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 44 +#define GCC_QUPV3_WRAP0_S2_CLK 45 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 46 +#define GCC_QUPV3_WRAP0_S3_CLK 47 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 48 +#define GCC_QUPV3_WRAP0_S4_CLK 49 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 50 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 51 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 52 +#define GCC_SDCC4_AHB_CLK 53 +#define GCC_SDCC4_APPS_CLK 54 +#define GCC_SDCC4_APPS_CLK_SRC 55 +#define GCC_SNOC_CNOC_USB3_CLK 56 +#define GCC_SYS_NOC_USB_SF_AXI_CLK 57 +#define GCC_USB20_MASTER_CLK 58 +#define GCC_USB20_MASTER_CLK_SRC 59 +#define GCC_USB20_MOCK_UTMI_CLK 60 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 61 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 62 +#define GCC_USB20_SLEEP_CLK 63 +#define GCC_USB2_CLKREF_EN 64 +#define GCC_USB3_PRIM_CLKREF_EN 65 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 66 +#define GCC_BOOT_ROM_AHB_CLK 68 + +/* GCC power domains */ +#define GCC_EMAC0_GDSC 0 +#define GCC_PCIE_GDSC 1 +#define GCC_USB20_GDSC 2 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_PCIE_BCR 1 +#define GCC_PCIE_LINK_DOWN_BCR 2 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 3 +#define GCC_PCIE_PHY_BCR 4 +#define GCC_PCIE_PHY_CFG_AHB_BCR 5 +#define GCC_PCIE_PHY_COM_BCR 6 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PDM_BCR 8 +#define GCC_QUPV3_WRAPPER_0_BCR 9 +#define GCC_QUSB2PHY_BCR 10 +#define GCC_SDCC4_BCR 11 +#define GCC_TCSR_PCIE_BCR 12 +#define GCC_USB20_BCR 13 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 + +#endif --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAB7B48EBDF for ; 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Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-kuno.c | 1483 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1494 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index e609a7819e07..1f31bf09de0c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -212,6 +212,16 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config CLK_KUNO_GCC + tristate "Kuno Global Clock Controller" + depends on ARM || COMPILE_TEST + default ARCH_QCOM + help + Support for the global clock controller (GCC) on Kuno devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, SD, PCIe and Ethernet on the Kuno SoC. This clock + controller supplies the clocks and resets to those peripherals. + config CLK_NORD_DISPCC tristate "Nord Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b8590963736a..67f74898a582 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o +obj-$(CONFIG_CLK_KUNO_GCC) +=3D gcc-kuno.o obj-$(CONFIG_CLK_MAILI_VIDEOCC) +=3D videocc-maili.o obj-$(CONFIG_CLK_NORD_DISPCC) +=3D dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o diff --git a/drivers/clk/qcom/gcc-kuno.c b/drivers/clk/qcom/gcc-kuno.c new file mode 100644 index 000000000000..787111397df9 --- /dev/null +++ b/drivers/clk/qcom/gcc-kuno.c @@ -0,0 +1,1483 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, + DT_PCIE_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL2_OUT_MAIN, + P_GPLL3_OUT_MAIN, + P_GPLL4_OUT_EVEN, + P_GPLL4_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static struct clk_alpha_pll gpll2 =3D { + .offset =3D 0x2000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll3 =3D { + .offset =3D 0x3000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll4_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll4_out_even =3D { + .offset =3D 0x4000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpll4_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll4_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll4.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_out_even.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_out_even.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_GPLL4_OUT_MAIN, 3 }, + { P_GPLL2_OUT_MAIN, 4 }, + { P_GPLL3_OUT_MAIN, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_out_even.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, + { .hw =3D &gpll3.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_BI_TCXO, 2 }, +}; + +static struct clk_regmap_mux gcc_pcie_aux_clk_src =3D { + .reg =3D 0x5308c, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_6, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src =3D { + .reg =3D 0x53070, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x7102c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] =3D { + F(62500000, P_GPLL4_OUT_EVEN, 4, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(125000000, P_GPLL2_OUT_MAIN, 4, 0, 0), + F(230400000, P_GPLL3_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_ptp_clk_src =3D { + .cmd_rcgr =3D 0x71064, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_ptp_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] =3D { + F(41666667, P_GPLL4_OUT_EVEN, 6, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(125000000, P_GPLL2_OUT_MAIN, 4, 0, 0), + F(250000000, P_GPLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_rgmii_clk_src =3D { + .cmd_rcgr =3D 0x7104c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rgmii_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(41666667, P_GPLL4_OUT_EVEN, 6, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x47004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x48004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x49004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_aux_phy_clk_src =3D { + .cmd_rcgr =3D 0x53074, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_phy_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(83333333, P_GPLL4_OUT_EVEN, 3, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src =3D { + .cmd_rcgr =3D 0x53038, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie_rchng_phy_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rchng_phy_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x34010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(62500000, P_GPLL4_OUT_EVEN, 4, 0, 0), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x6c004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x6c13c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x6c274, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x6c3ac, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x6c4e4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 1, 1), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(83333333, P_GPLL4_OUT_EVEN, 3, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src =3D { + .cmd_rcgr =3D 0x6a01c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_apps_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] =3D { + F(50000000, P_GPLL4_OUT_EVEN, 5, 0, 0), + F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb20_master_clk_src =3D { + .cmd_rcgr =3D 0x27048, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb20_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2702c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x27044, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x37004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x37004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_axi_clk =3D { + .halt_reg =3D 0x71018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_phy_aux_clk =3D { + .halt_reg =3D 0x71028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_ptp_clk =3D { + .halt_reg =3D 0x71044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rgmii_clk =3D { + .halt_reg =3D 0x71048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_slv_ahb_clk =3D { + .halt_reg =3D 0x71024, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_slv_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac_0_clkref_en =3D { + .halt_reg =3D 0x94004, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x94004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x47000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x47000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x48000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x48000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x49000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_clkref_en =3D { + .halt_reg =3D 0x94000, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x94000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_aux_clk =3D { + .halt_reg =3D 0x53054, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x53054, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cfg_ahb_clk =3D { + .halt_reg =3D 0x53034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_mstr_axi_clk =3D { + .halt_reg =3D 0x53028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_pipe_clk =3D { + .halt_reg =3D 0x53064, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x53064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rchng_phy_clk =3D { + .halt_reg =3D 0x53050, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53050, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rchng_phy_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_rchng_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_sleep_clk =3D { + .halt_reg =3D 0x53060, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53060, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_axi_clk =3D { + .halt_reg =3D 0x5301c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x53018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3400c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x34004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x34004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x34008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x34008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x2d018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x2d008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x6c130, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x6c268, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x6c3a0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x6c4d8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x6c610, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x2d000, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d000, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x2d004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk =3D { + .halt_reg =3D 0x6a010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6a010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk =3D { + .halt_reg =3D 0x6a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_cnoc_usb3_clk =3D { + .halt_reg =3D 0x27060, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27060, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x27060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_cnoc_usb3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb_sf_axi_clk =3D { + .halt_reg =3D 0x27064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x27064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sys_noc_usb_sf_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk =3D { + .halt_reg =3D 0x27018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x27018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk =3D { + .halt_reg =3D 0x27028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x27028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk =3D { + .halt_reg =3D 0x27024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x27024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_clkref_en =3D { + .halt_reg =3D 0x94008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x94008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb2_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_en =3D { + .halt_reg =3D 0x9400c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x9400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk =3D { + .halt_reg =3D 0x29004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x29004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x29004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb_phy_cfg_ahb2phy_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct gdsc gcc_emac0_gdsc =3D { + .gdscr =3D 0x71004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_emac0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_gdsc =3D { + .gdscr =3D 0x53004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb20_gdsc =3D { + .gdscr =3D 0x27004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb20_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gcc_kuno_clocks[] =3D { + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_EMAC0_AXI_CLK] =3D &gcc_emac0_axi_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK] =3D &gcc_emac0_phy_aux_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK_SRC] =3D &gcc_emac0_phy_aux_clk_src.clkr, + [GCC_EMAC0_PTP_CLK] =3D &gcc_emac0_ptp_clk.clkr, + [GCC_EMAC0_PTP_CLK_SRC] =3D &gcc_emac0_ptp_clk_src.clkr, + [GCC_EMAC0_RGMII_CLK] =3D &gcc_emac0_rgmii_clk.clkr, + [GCC_EMAC0_RGMII_CLK_SRC] =3D &gcc_emac0_rgmii_clk_src.clkr, + [GCC_EMAC0_SLV_AHB_CLK] =3D &gcc_emac0_slv_ahb_clk.clkr, + [GCC_EMAC_0_CLKREF_EN] =3D &gcc_emac_0_clkref_en.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_PCIE_0_CLKREF_EN] =3D &gcc_pcie_0_clkref_en.clkr, + [GCC_PCIE_AUX_CLK] =3D &gcc_pcie_aux_clk.clkr, + [GCC_PCIE_AUX_CLK_SRC] =3D &gcc_pcie_aux_clk_src.clkr, + [GCC_PCIE_AUX_PHY_CLK_SRC] =3D &gcc_pcie_aux_phy_clk_src.clkr, + [GCC_PCIE_CFG_AHB_CLK] =3D &gcc_pcie_cfg_ahb_clk.clkr, + [GCC_PCIE_MSTR_AXI_CLK] =3D &gcc_pcie_mstr_axi_clk.clkr, + [GCC_PCIE_PIPE_CLK] =3D &gcc_pcie_pipe_clk.clkr, + [GCC_PCIE_PIPE_CLK_SRC] =3D &gcc_pcie_pipe_clk_src.clkr, + [GCC_PCIE_RCHNG_PHY_CLK] =3D &gcc_pcie_rchng_phy_clk.clkr, + [GCC_PCIE_RCHNG_PHY_CLK_SRC] =3D &gcc_pcie_rchng_phy_clk_src.clkr, + [GCC_PCIE_SLEEP_CLK] =3D &gcc_pcie_sleep_clk.clkr, + [GCC_PCIE_SLV_AXI_CLK] =3D &gcc_pcie_slv_axi_clk.clkr, + [GCC_PCIE_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_slv_q2a_axi_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_SDCC4_AHB_CLK] =3D &gcc_sdcc4_ahb_clk.clkr, + [GCC_SDCC4_APPS_CLK] =3D &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC4_APPS_CLK_SRC] =3D &gcc_sdcc4_apps_clk_src.clkr, + [GCC_SNOC_CNOC_USB3_CLK] =3D &gcc_snoc_cnoc_usb3_clk.clkr, + [GCC_SYS_NOC_USB_SF_AXI_CLK] =3D &gcc_sys_noc_usb_sf_axi_clk.clkr, + [GCC_USB20_MASTER_CLK] =3D &gcc_usb20_master_clk.clkr, + [GCC_USB20_MASTER_CLK_SRC] =3D &gcc_usb20_master_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_CLK] =3D &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK_SRC] =3D &gcc_usb20_mock_utmi_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb20_mock_utmi_postdiv_cl= k_src.clkr, + [GCC_USB20_SLEEP_CLK] =3D &gcc_usb20_sleep_clk.clkr, + [GCC_USB2_CLKREF_EN] =3D &gcc_usb2_clkref_en.clkr, + [GCC_USB3_PRIM_CLKREF_EN] =3D &gcc_usb3_prim_clkref_en.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] =3D &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL0_OUT_EVEN] =3D &gpll0_out_even.clkr, + [GPLL2] =3D &gpll2.clkr, + [GPLL3] =3D &gpll3.clkr, + [GPLL4] =3D &gpll4.clkr, + [GPLL4_OUT_EVEN] =3D &gpll4_out_even.clkr, +}; + +static const struct qcom_reset_map gcc_kuno_resets[] =3D { + [GCC_EMAC0_BCR] =3D { 0x71000 }, + [GCC_PCIE_BCR] =3D { 0x53000 }, + [GCC_PCIE_LINK_DOWN_BCR] =3D { 0x87000 }, + [GCC_PCIE_NOCSR_COM_PHY_BCR] =3D { 0x88008 }, + [GCC_PCIE_PHY_BCR] =3D { 0x54000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] =3D { 0x88000 }, + [GCC_PCIE_PHY_COM_BCR] =3D { 0x88004 }, + [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] =3D { 0x8800c }, + [GCC_PDM_BCR] =3D { 0x34000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x6c000 }, + [GCC_QUSB2PHY_BCR] =3D { 0x2a000 }, + [GCC_SDCC4_BCR] =3D { 0x6a000 }, + [GCC_TCSR_PCIE_BCR] =3D { 0x84000 }, + [GCC_USB20_BCR] =3D { 0x27000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x29000 }, +}; + +static struct gdsc *gcc_kuno_gdscs[] =3D { + [GCC_EMAC0_GDSC] =3D &gcc_emac0_gdsc, + [GCC_PCIE_GDSC] =3D &gcc_pcie_gdsc, + [GCC_USB20_GDSC] =3D &gcc_usb20_gdsc, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), +}; + +static const struct regmap_config gcc_kuno_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f41f0, + .fast_io =3D true, +}; + +static const u32 gcc_kuno_critical_cbcrs[] =3D { + 0x3e004, /* GCC_AHB_PCIE_LINK_CLK */ + 0x3e008, /* GCC_XO_PCIE_LINK_CLK */ +}; + +static const struct qcom_cc_driver_data gcc_kuno_driver_data =3D { + .dfs_rcgs =3D gcc_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(gcc_dfs_clocks), + .clk_cbcrs =3D gcc_kuno_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gcc_kuno_critical_cbcrs), +}; + +static const struct qcom_cc_desc gcc_kuno_desc =3D { + .config =3D &gcc_kuno_regmap_config, + .clks =3D gcc_kuno_clocks, + .num_clks =3D ARRAY_SIZE(gcc_kuno_clocks), + .resets =3D gcc_kuno_resets, + .num_resets =3D ARRAY_SIZE(gcc_kuno_resets), + .gdscs =3D gcc_kuno_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_kuno_gdscs), + .use_rpm =3D true, + .driver_data =3D &gcc_kuno_driver_data, +}; + +static const struct of_device_id gcc_kuno_match_table[] =3D { + { .compatible =3D "qcom,kuno-gcc" }, + { } +}; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index 8162a49d49a6..518fbf6b2761 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -30,6 +30,7 @@ properties: - qcom,glymur-pdc - qcom,hawi-pdc - qcom,kaanapali-pdc + - qcom,kuno-pdc - qcom,maili-pdc - qcom,milos-pdc - qcom,nord-pdc --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99C4946AA94 for ; Thu, 27 Aug 2026 16:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Bartosz Golaszewski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index 037d4ad8f718..ecee5aef65a7 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -37,6 +37,7 @@ properties: - qcom,scm-ipq9574 - qcom,scm-ipq9650 - qcom,scm-kaanapali + - qcom,scm-kuno - qcom,scm-maili - qcom,scm-mdm9607 - qcom,scm-milos --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2228248D868 for ; Thu, 27 Aug 2026 16:40:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bartosz Golaszewski Signed-off-by: Hardeep Sharma --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 4 ++-- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Document= ation/devicetree/bindings/arm/qcom-soc.yaml index e7160b63d814..179aadc86a9f 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -30,7 +30,7 @@ select: contains: oneOf: - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd= [amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|mil= os|nord|shikra).*$" + - pattern: "^qcom,.*(eliza|kaanapali|kuno|glymur|hawi|mahua|mail= i|milos|nord|shikra).*$" required: - compatible =20 @@ -42,7 +42,7 @@ properties: - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm= |x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" - - pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|n= ord|shikra)-.+$" + - pattern: "^qcom,(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|mi= los|nord|shikra)-.+$" =20 # Legacy namings - variations of existing patterns/compatibles are= OK, # but do not add completely new entries to these: diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index ff8a35df7862..ca02a2f0396f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -175,6 +175,11 @@ properties: - qcom,kaanapali-qrd - const: qcom,kaanapali =20 + - items: + - enum: + - qcom,kuno-idp + - const: qcom,kuno + - items: - enum: - qcom,mahua-crd --=20 2.43.0 From nobody Sun Sep 27 00:36:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DA804908A7 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6b1a24bce78sm4253171eaf.3.2026.08.27.09.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:40:35 -0700 (PDT) From: Hardeep Sharma Date: Thu, 27 Aug 2026 22:08:16 +0530 Subject: [PATCH v4 15/15] ARM: dts: qcom: Add initial device tree for Kuno SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260827-kuno-soc-support-v4-15-dd34f235fc1a@oss.qualcomm.com> References: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> In-Reply-To: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Dmitry Baryshkov , Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787848688; l=12320; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=VMPk8iPi43dEtmYkKXt01Gm+7aUp6TmVF3AL6pfOShE=; b=SPbz05t3R8boKbDajcmBt7Z66jqziTESt5X5RZnlljA91R+TkwG0nj3SOxGLNyD7pHFtzTe+y AZbRkSgMRSQBlNcf+1WEz/9RZpp8mj8iI7RVY+T2Vzb1gFRsNQzPeoB X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfXzJGpdOTON8/7 hjoX34w6B/uu/svBBE+qzEbVnW/OyWfs64cyPT0yndpS0gWbdOjtWirzWICOFxif5yaUALE+9cO tlRhrOwwJyGDF86H2XboXrZMYFkfM8M= X-Proofpoint-GUID: jgxuss6jGi2cGMevbD05JAaRIqNZih5E X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX+WsCTxFm6RWT slfDIZN8dAOHx28Z26RQaJx08tnUHLbzjVnldZihcwzl/RcxBOdRW08YC1MdZcm7NIwJCcxLWNA n6+LGH9jCsuHE8QX/mMhh9LT19fL5YUuwXdojGOB/08t1vuSvLGByMYCcZ6FczS7QnjMDcC3nVJ 4Au50xum2M0TTLEANRI+i5nN1nzcNX0y4ORkbtqr32dNhjfC+X2/CI3IvTl6DGspjL0Wj29vQkX PJgxsS+l5HC+PXHrk389CBq/Jao3HB1kxoy/UcpBn/YzWycZC4pwlVP2McVkg3xbsx2Jk1OfqsD G9CQVbFAMBp/6NrvkZ8sl3YNVWyDueRZxKZIJCNcqG++U6EOmAd5RiiLC4exJXgeT9K/sB0QgMO oo2YF31NhKGc5MxaVUcrJc2XiOfF6yi/SV+99YIowAp64Ob0833rwFuH0Zi1LC/dEeXuVa2Ighj 2cJOzJu8Bf74Jt21P3Q== X-Authority-Analysis: v=2.4 cv=eIgjSnp1 c=1 sm=1 tr=0 ts=6a906884 cx=c_pps a=zPxD6eHSjdtQ/OcAcrOFGw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=lKFnvmfiA1OmcLezn0cA:9 a=QEXdDO2ut3YA:10 a=y8BKWJGFn5sdPF1Y92-H:22 X-Proofpoint-ORIG-GUID: jgxuss6jGi2cGMevbD05JAaRIqNZih5E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270140 Add SoC-level DTSI (qcom-kuno.dtsi) and IDP board DTS (qcom-kuno-idp.dts) for the Qualcomm Kuno SoC. Peripherals included in this initial set: - Single Cortex-A7 CPU with PSCI idle states - RPMh RSC with clock controller, power domains, and BCM voter - GCC (Global Clock Controller) - TLMM pin controller (110 GPIOs) - Interconnect (aggre-noc, cnoc-main) - GENI UART console (QUP SE3) - SMEM, hardware spinlocks (TCSR mutex) Reviewed-by: Dmitry Baryshkov Reviewed-by: Linus Walleij Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- arch/arm/boot/dts/qcom/Makefile | 1 + arch/arm/boot/dts/qcom/qcom-kuno-idp.dts | 25 ++ arch/arm/boot/dts/qcom/qcom-kuno.dtsi | 423 +++++++++++++++++++++++++++= ++++ 3 files changed, 449 insertions(+) diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makef= ile index 026d5b682b2b..7327a7b8180e 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D \ qcom-ipq4019-ap.dk07.1-c2.dtb \ qcom-ipq8064-ap148.dtb \ qcom-ipq8064-rb3011.dtb \ + qcom-kuno-idp.dtb \ qcom-msm8226-microsoft-dempsey.dtb \ qcom-msm8226-microsoft-makepeace.dtb \ qcom-msm8226-microsoft-moneypenny.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts b/arch/arm/boot/dts/q= com/qcom-kuno-idp.dts new file mode 100644 index 000000000000..c2f6650d3fe6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "qcom-kuno.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Kuno IDP"; + compatible =3D "qcom,kuno-idp", "qcom,kuno"; + + aliases { + serial0 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart3 { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-kuno.dtsi b/arch/arm/boot/dts/qcom= /qcom-kuno.dtsi new file mode 100644 index 000000000000..d0c6e3f21a14 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&intc>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a7"; + reg =3D <0x0>; + enable-method =3D "psci"; + cpu-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "standalone-pc"; + entry-latency-us =3D <350>; + exit-latency-us =3D <450>; + min-residency-us =3D <1774>; + arm,psci-suspend-param =3D <0x40000003>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "pc"; + entry-latency-us =3D <550>; + exit-latency-us =3D <750>; + min-residency-us =3D <6700>; + arm,psci-suspend-param =3D <0x40000004>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + idle-state-name =3D "cx-min"; + entry-latency-us =3D <750>; + exit-latency-us =3D <2350>; + min-residency-us =3D <9144>; + arm,psci-suspend-param =3D <0x40000008>; + }; + }; + }; + + firmware { + scm { + compatible =3D "qcom,scm-kuno", "qcom,scm"; + }; + }; + + memory { + device_type =3D "memory"; + /* Bootloader will fill base and size */ + reg =3D <0x0 0x0>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0>; + }; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + quickboot@82100000 { + reg =3D <0x82100000 0x100000>; + no-map; + }; + + aop-image@82200000 { + reg =3D <0x82200000 0x20000>; + no-map; + }; + + aop-cmd-db@82220000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x82220000 0x20000>; + no-map; + }; + + aop-config@82240000 { + reg =3D <0x82240000 0x20000>; + no-map; + }; + + uefi-log@82260000 { + reg =3D <0x82260000 0x10000>; + no-map; + }; + + ipa-fw@82270000 { + reg =3D <0x82270000 0x10000>; + no-map; + }; + + smem@82280000 { + compatible =3D "qcom,smem"; + reg =3D <0x82280000 0xc0000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + tme-crashdump@82340000 { + reg =3D <0x82340000 0x40000>; + no-map; + }; + + tme-log@82380000 { + reg =3D <0x82380000 0x4000>; + no-map; + }; + + access-control-db@82384000 { + reg =3D <0x82384000 0x40000>; + no-map; + }; + + secdata@823c4000 { + reg =3D <0x823c4000 0x1000>; + no-map; + }; + + modem-efs@823c5000 { + reg =3D <0x823c5000 0x10000>; + no-map; + }; + + cpucp-fw@82400000 { + reg =3D <0x82400000 0x80000>; + no-map; + }; + + xbl-dt-log@824c0000 { + reg =3D <0x824c0000 0x20000>; + no-map; + }; + + qtee@82500000 { + reg =3D <0x82500000 0x180000>; + no-map; + }; + + trusted-apps@82680000 { + reg =3D <0x82680000 0x600000>; + no-map; + }; + + mpss-audio@82e00000 { + reg =3D <0x82e00000 0x5a00000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0xffffffff>; + + gcc: clock-controller@80000 { + compatible =3D "qcom,kuno-gcc"; + reg =3D <0x00080000 0x1f4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qup0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x009c0000 0x2000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x0 0x1000000>; + + uart3: serial@98c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&uart_console_active>; + pinctrl-1 =3D <&uart_console_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + }; + }; + + cnoc_main: interconnect@1580000 { + compatible =3D "qcom,kuno-cnoc-main"; + reg =3D <0x01580000 0x19200>; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@1640000 { + compatible =3D "qcom,kuno-aggre-noc"; + reg =3D <0x01640000 0x33400>; + clocks =3D <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + #interconnect-cells =3D <1>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01f40000 0x40000>; + #hwlock-cells =3D <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,kuno-pdc", "qcom,pdc"; + reg =3D <0x0b220000 0x10000>; + qcom,pdc-ranges =3D <1 148 6>, + <9 156 2>, + <17 164 7>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + restart@c264000 { + compatible =3D "qcom,pshold"; + reg =3D <0x0c264000 0x1000>; + }; + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,kuno-tlmm"; + reg =3D <0x0f000000 0x400000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 110>; + interrupt-controller; + #interrupt-cells =3D <2>; + + uart_console_active: uart-console-active-state { + pins =3D "gpio8", "gpio9"; + function =3D "qup0_se3_mira"; + drive-strength =3D <2>; + bias-disable; + }; + + uart_console_sleep: uart-console-sleep-state { + pins =3D "gpio8", "gpio9"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x17000000 0x1000>, + <0x17002000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + timer@17020000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x17020000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + frame@17021000 { + reg =3D <0x17021000 0x1000>, + <0x17022000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + }; + + apps_rsc: rsc@17040000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x17040000 0x10000>, + <0x17050000 0x10000>, + <0x17060000 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + /* drv-1: placeholder (unused) */ + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + power-domains =3D <&cluster_pd>; + + rpmhcc: clock-controller { + compatible =3D "qcom,kuno-rpmh-clk"; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,kuno-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + }; + }; + + timer { + compatible =3D "arm,armv7-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0