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Wed, 26 Aug 2026 10:48:58 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 01/13] drm: renesas: rzg2l_mipi_dsi: Add dphyctrl0_init_val to hw_info Date: Wed, 26 Aug 2026 18:48:35 +0100 Message-ID: <20260826174854.199139-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Move the DSIDPHYCTRL0 initialization value into the hw_info structure as dphyctrl0_init_val, allowing SoC-specific D-PHY control register initialization to be defined per compatible. This prepares the driver for supporting SoCs that require a different initial DSIDPHYCTRL0 value. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai --- v2->v3: * Collected tag. v1->v2: * No change. --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 0590ade96b91..2128fd16ebc9 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -56,6 +56,7 @@ struct rzg2l_mipi_dsi_hw_info { } cpg_plldsi; u32 phy_reg_offset; u32 link_reg_offset; + u32 dphyctrl0_init_val; unsigned long min_dclk; unsigned long max_dclk; u8 features; @@ -493,9 +494,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_d= si *dsi, } =20 /* Initializing DPHY before accessing LINK */ - dphyctrl0 =3D DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN | - DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR; - + dphyctrl0 =3D dsi->info->dphyctrl0_init_val; rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0); usleep_range(20, 30); =20 @@ -1531,6 +1530,8 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi= _dsi_info =3D { .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, .dphy_conf_clks =3D rzg2l_dphy_conf_clks, .link_reg_offset =3D 0x10000, + .dphyctrl0_init_val =3D DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_M= ASTER_EN | + DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR, .min_dclk =3D 5803, .max_dclk =3D 148500, }; --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C60A46EC61 for ; Wed, 26 Aug 2026 17:49:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787766556; cv=none; b=WjP6Lu3WLsLguzfoxfRzBGQq44J8Ux4/1K60qHC4EYFF1jXBqKct0MMDGlNjyhCJlW3X343VFmQeno1lSALs+chrJoDx1MIIk1grSQ+/OtPnAT4N5k3wu6J8CTE8MGrpHPFu4U47LcR5bGRwGpUqpcuj0mhvkixU9vayoM4LV2I= ARC-Message-Signature: i=1; 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charset="utf-8" From: Biju Das Move the post-reset activation delay into the hw_info structure as activation_dly, allowing SoC-specific values to be defined per compatible. This prepares the driver for supporting SoCs that require a different delay after reset deassertion. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai --- v2->v3: * Collected tag. v1->v2: * No change. --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 2128fd16ebc9..1538eeece2b5 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -59,6 +59,7 @@ struct rzg2l_mipi_dsi_hw_info { u32 dphyctrl0_init_val; unsigned long min_dclk; unsigned long max_dclk; + u16 activation_dly; u8 features; }; =20 @@ -806,7 +807,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, if (ret < 0) goto err_phy; =20 - fsleep(1000); + fsleep(dsi->info->activation_dly); } =20 return 0; @@ -1534,6 +1535,7 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi= _dsi_info =3D { DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR, .min_dclk =3D 5803, .max_dclk =3D 148500, + .activation_dly =3D 1000, }; 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Wed, 26 Aug 2026 10:49:00 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 03/13] drm: renesas: rzg2l_mipi_dsi: Move global timings into hardware info struct Date: Wed, 26 Aug 2026 18:48:37 +0100 Message-ID: <20260826174854.199139-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Move rzg2l_mipi_dsi_global_timings and its array size out of the hardcoded ARRAY_SIZE reference in rzg2l_mipi_dsi_dphy_init() and into the struct rzg2l_mipi_dsi_hw_info. This allows future hardware variants to supply their own timing tables rather than sharing a single global array, making the driver more extensible without code duplication. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai --- v2->v3: * Dropped .dsi_global_timings from rzv2h_mipi_dsi_info as it uses different path. v1->v2: * No change. --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 1538eeece2b5..d67e1230b70c 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -54,6 +54,8 @@ struct rzg2l_mipi_dsi_hw_info { const u8 *table; const u8 table_size; } cpg_plldsi; + const struct rzg2l_mipi_dsi_timings *dsi_global_timings; + unsigned int num_dsi_global_timings; u32 phy_reg_offset; u32 link_reg_offset; u32 dphyctrl0_init_val; @@ -488,8 +490,8 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_d= si *dsi, u32 dphytim3; =20 /* All DSI global operation timings are set with recommended setting */ - for (i =3D 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { - dphy_timings =3D &rzg2l_mipi_dsi_global_timings[i]; + for (i =3D 0; i < dsi->info->num_dsi_global_timings; ++i) { + dphy_timings =3D &dsi->info->dsi_global_timings[i]; if (hsfreq <=3D dphy_timings->hsfreq_max) break; } @@ -1530,6 +1532,8 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi= _dsi_info =3D { .dphy_init =3D rzg2l_mipi_dsi_dphy_init, .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, .dphy_conf_clks =3D rzg2l_dphy_conf_clks, + .dsi_global_timings =3D rzg2l_mipi_dsi_global_timings, + .num_dsi_global_timings =3D ARRAY_SIZE(rzg2l_mipi_dsi_global_timings), .link_reg_offset =3D 0x10000, .dphyctrl0_init_val =3D DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_M= ASTER_EN | DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR, --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED52D46AF3C for ; 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Wed, 26 Aug 2026 10:49:01 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:aa64:3da0:a259:ecd5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a88ac7fsm777752766b.30.2026.08.26.10.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 10:49:01 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 04/13] drm: renesas: rzg2l_mipi_dsi: Add support for DSI PWRRDY Date: Wed, 26 Aug 2026 18:48:38 +0100 Message-ID: <20260826174854.199139-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The register for controlling power to the DSI region is in the SYSC (System Controller) block. Add support for controlling the DSI PWRRDY signal so the driver can efficiently manage power to the DSI region. Signed-off-by: Biju Das --- v2->v3: * Updated powerseq API names. v1->v2: * Switched to power sequence for handling pwrrdy signal. * Dropped header file regmap.h and mfd/syscon.h * Added header file pwrseq/consumer.h --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index d67e1230b70c..7df5f4a4161b 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -63,6 +64,7 @@ struct rzg2l_mipi_dsi_hw_info { unsigned long max_dclk; u16 activation_dly; u8 features; + bool pwrrdy; }; =20 struct rzv2h_dsi_mode_calc { @@ -87,6 +89,8 @@ struct rzg2l_mipi_dsi { struct clk *vclk; struct clk *lpclk; =20 + struct pwrseq_desc *pwrseq; + enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; unsigned int lanes; @@ -1396,6 +1400,36 @@ static const struct dev_pm_ops rzg2l_mipi_pm_ops =3D= { * Probe & Remove */ =20 +static void rzg2l_mipi_dsi_pwrrdy_off(void *data) +{ + pwrseq_disable(data); +} + +static int rzg2l_mipi_dsi_pwrrdy_init(struct rzg2l_mipi_dsi *dsi) +{ + int ret; + + if (!dsi->info->pwrrdy) + return 0; + + dsi->pwrseq =3D devm_pwrseq_get(dsi->dev, "dsi-pwrrdy"); + if (IS_ERR(dsi->pwrseq)) { + /* + * This platform requires a sequencer. If we can't get it, we + * must return the error (including -EPROBE_DEFER to wait for + * the provider to appear) + */ + return dev_err_probe(dsi->dev, PTR_ERR(dsi->pwrseq), + "Failed to get required power sequencer\n"); + } + + ret =3D pwrseq_enable(dsi->pwrseq); + if (ret) + return ret; + + return devm_add_action_or_reset(dsi->dev, rzg2l_mipi_dsi_pwrrdy_off, dsi-= >pwrseq); +} + static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) { unsigned int num_data_lanes; @@ -1454,6 +1488,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_devi= ce *pdev) =20 platform_set_drvdata(pdev, dsi); =20 + ret =3D rzg2l_mipi_dsi_pwrrdy_init(dsi); + if (ret) + return ret; + pm_runtime_enable(dsi->dev); =20 ret =3D pm_runtime_resume_and_get(dsi->dev); --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BB5C45A2AE for ; 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charset="utf-8" From: Biju Das Add support for the MIPI DSI controller found on the Renesas RZ/G3L (R9A08G046) SoC. The D-PHY global timing table of RZ/G3L SoC different compared to the other SoCs. Introduce a dedicated D-PHY global timing table rzg3l_mipi_dsi_global_timings and wire it up via a new rzg3l_mipi_dsi_info hw_info variant for RZ/G3L SoC. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai --- v1->v2: * Moved set duty cycle to DU encoder. v1->v2: * Replaced syscon_field->pwrrdy in struct rzg3l_mipi_dsi_info. --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 117 ++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 7df5f4a4161b..88ec0612d529 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -226,6 +226,107 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi= _dsi_global_timings[] =3D { }, }; =20 +static const struct rzg2l_mipi_dsi_timings rzg3l_mipi_dsi_global_timings[]= =3D { + { + .hsfreq_max =3D 100000000, + .t_init =3D 79801, + .tclk_prepare =3D 10, + .ths_prepare =3D 18, + .tclk_zero =3D 35, + .tclk_pre =3D 13, + .tclk_post =3D 94, + .tclk_trail =3D 10, + .ths_zero =3D 16, + .ths_trail =3D 22, + .ths_exit =3D 15, + .tlpx =3D 9, + }, + { + .hsfreq_max =3D 150000000, + .t_init =3D 79801, + .tclk_prepare =3D 10, + .ths_prepare =3D 16, + .tclk_zero =3D 35, + .tclk_pre =3D 13, + .tclk_post =3D 94, + .tclk_trail =3D 10, + .ths_zero =3D 16, + .ths_trail =3D 15, + .ths_exit =3D 15, + .tlpx =3D 9, + }, + { + .hsfreq_max =3D 250000000, + .t_init =3D 79801, + .tclk_prepare =3D 10, + .ths_prepare =3D 13, + .tclk_zero =3D 35, + .tclk_pre =3D 13, + .tclk_post =3D 58, + .tclk_trail =3D 8, + .ths_zero =3D 16, + .ths_trail =3D 10, + .ths_exit =3D 15, + .tlpx =3D 9, + }, + { + .hsfreq_max =3D 400000000, + .t_init =3D 79801, + .tclk_prepare =3D 10, + .ths_prepare =3D 12, + .tclk_zero =3D 35, + .tclk_pre =3D 4, + .tclk_post =3D 58, + .tclk_trail =3D 7, + .ths_zero =3D 16, + .ths_trail =3D 9, + .ths_exit =3D 15, + .tlpx =3D 9, + }, + { + .hsfreq_max =3D 600000000, + .t_init =3D 79801, + .tclk_prepare =3D 10, + .ths_prepare =3D 11, + .tclk_zero =3D 35, + .tclk_pre =3D 4, + .tclk_post =3D 35, + .tclk_trail =3D 5, + .ths_zero =3D 16, + .ths_trail =3D 6, + .ths_exit =3D 15, + .tlpx =3D 9, + }, + { + .hsfreq_max =3D 1000000000, + .t_init =3D 79801, + .tclk_prepare =3D 10, + .ths_prepare =3D 11, + .tclk_zero =3D 35, + .tclk_pre =3D 4, + .tclk_post =3D 35, + .tclk_trail =3D 5, + .ths_zero =3D 16, + .ths_trail =3D 6, + .ths_exit =3D 15, + .tlpx =3D 9, + }, + { + .hsfreq_max =3D 1500000000, + .t_init =3D 79801, + .tclk_prepare =3D 10, + .ths_prepare =3D 11, + .tclk_zero =3D 35, + .tclk_pre =3D 4, + .tclk_post =3D 35, + .tclk_trail =3D 4, + .ths_zero =3D 16, + .ths_trail =3D 5, + .ths_exit =3D 15, + .tlpx =3D 9, + }, +}; + /** * struct rzv2h_mipi_dsi_timings - Timing parameter table structure * @@ -1580,7 +1681,23 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mip= i_dsi_info =3D { .activation_dly =3D 1000, }; =20 +static const struct rzg2l_mipi_dsi_hw_info rzg3l_mipi_dsi_info =3D { + .dphy_init =3D rzg2l_mipi_dsi_dphy_init, + .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, + .dphy_conf_clks =3D rzg2l_dphy_conf_clks, + .dsi_global_timings =3D rzg3l_mipi_dsi_global_timings, + .num_dsi_global_timings =3D ARRAY_SIZE(rzg3l_mipi_dsi_global_timings), + .link_reg_offset =3D 0x10000, + .dphyctrl0_init_val =3D DSIDPHYCTRL0_CMN_MASTER_EN | DSIDPHYCTRL0_EN_BGR, + .min_dclk =3D 5440, + .max_dclk =3D 187500, + .activation_dly =3D 100, + .features =3D RZ_MIPI_DSI_FEATURE_16BPP, + .pwrrdy =3D true, +}; + static const struct of_device_id rzg2l_mipi_dsi_of_table[] =3D { + { .compatible =3D "renesas,r9a08g046-mipi-dsi", .data =3D &rzg3l_mipi_dsi= _info, }, { .compatible =3D "renesas,r9a09g057-mipi-dsi", .data =3D &rzv2h_mipi_dsi= _info, }, { .compatible =3D "renesas,rzg2l-mipi-dsi", .data =3D &rzg2l_mipi_dsi_inf= o, }, { /* sentinel */ } --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59557470E99 for ; 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Wed, 26 Aug 2026 10:49:03 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:aa64:3da0:a259:ecd5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a88ac7fsm777752766b.30.2026.08.26.10.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 10:49:03 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 06/13] drm: renesas: rz-du: Add RZ/G3L (R9A08G046) DU support Date: Wed, 26 Aug 2026 18:48:40 +0100 Message-ID: <20260826174854.199139-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add Display Unit support for the Renesas RZ/G3L SoC (R9A08G046). It is similar to the one found on RZ/G2L, but has LVDS support. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai --- v2->v3: * Set duty cycle handling in DU encoder * Added min/max frequencies for DPI. v1->v2: * Dropped the macro RZG2L_DU_FEATURE_SMUX2_DSI_CLK and RZG2L_DU_MAX_LVDS. * Dropped the variable rcdu from struct rzg2l_du_encoder. * Dropped the variable lvds from struct rzg2l_du_device. --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 24 ++++++++++++++++++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 3 ++- .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 24 +++++++++++++++++++ 3 files changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.c index 3d13f61d3c97..6c2dc86abc7d 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -55,6 +55,26 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g= 044_info =3D { .mode_clock_max =3D 83500, }; =20 +static const struct rzg2l_du_device_info rzg2l_du_r9a08g046_info =3D { + .channels_mask =3D BIT(0), + .routes =3D { + [RZG2L_DU_OUTPUT_DSI0] =3D { + .possible_outputs =3D BIT(0), + .port =3D 0, + }, + [RZG2L_DU_OUTPUT_DPAD0] =3D { + .possible_outputs =3D BIT(0), + .port =3D 1, + }, + [RZG2L_DU_OUTPUT_LVDS0] =3D { + .possible_outputs =3D BIT(0), + .port =3D 2, + }, + }, + .mode_clock_min =3D 5440, + .mode_clock_max =3D 87000, +}; + static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info =3D { .channels_mask =3D BIT(0), .routes =3D { @@ -81,6 +101,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a09g= 077_info =3D { static const struct of_device_id rzg2l_du_of_table[] =3D { { .compatible =3D "renesas,r9a07g043u-du", .data =3D &rzg2l_du_r9a07g043u= _info }, { .compatible =3D "renesas,r9a07g044-du", .data =3D &rzg2l_du_r9a07g044_i= nfo }, + { .compatible =3D "renesas,r9a08g046-du", .data =3D &rzg2l_du_r9a08g046_i= nfo }, { .compatible =3D "renesas,r9a09g057-du", .data =3D &rzg2l_du_r9a09g057_i= nfo }, { .compatible =3D "renesas,r9a09g077-du", .data =3D &rzg2l_du_r9a09g077_i= nfo }, { /* sentinel */ } @@ -92,7 +113,8 @@ const char *rzg2l_du_output_name(enum rzg2l_du_output ou= tput) { static const char * const names[] =3D { [RZG2L_DU_OUTPUT_DSI0] =3D "DSI0", - [RZG2L_DU_OUTPUT_DPAD0] =3D "DPAD0" + [RZG2L_DU_OUTPUT_DPAD0] =3D "DPAD0", + [RZG2L_DU_OUTPUT_LVDS0] =3D "LVDS0" }; =20 if (output >=3D ARRAY_SIZE(names)) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.h index baf076d69cda..e9626ef37cde 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -25,6 +25,7 @@ struct drm_property; enum rzg2l_du_output { RZG2L_DU_OUTPUT_DSI0, RZG2L_DU_OUTPUT_DPAD0, + RZG2L_DU_OUTPUT_LVDS0, RZG2L_DU_OUTPUT_MAX, }; =20 @@ -33,7 +34,7 @@ enum rzg2l_du_output { * @possible_outputs: bitmask of possible outputs * @port: device tree port number corresponding to this output route * - * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data + * The DU has 3 possible outputs (DPAD0, DSI0, LVDS0). Output routing data * specify the valid SoC outputs, which CRTC can drive the output, and the= type * of in-SoC encoder for the output. */ diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu= /drm/renesas/rz-du/rzg2l_du_encoder.c index 3d0999e4fcfd..a1b48973aa8e 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c @@ -7,6 +7,7 @@ * Based on rcar_du_encoder.c */ =20 +#include #include #include =20 @@ -15,6 +16,7 @@ #include #include =20 +#include "rzg2l_du_crtc.h" #include "rzg2l_du_drv.h" #include "rzg2l_du_encoder.h" =20 @@ -64,8 +66,30 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder, return MODE_OK; } =20 +static void rzg2l_du_encoder_atomic_mode_set(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct rzg2l_du_encoder *renc =3D to_rzg2l_encoder(encoder); + struct rzg2l_du_crtc *rcrtc =3D to_rzg2l_crtc(crtc_state->crtc); + struct clk *clk_parent; + + clk_parent =3D clk_get_parent(rcrtc->rzg2l_clocks.dclk); + + /* + * Request appropriate duty cycle + * - LVDS path has DUTY H/L=3D4/3, 4/7 duty cycle. + * - DSI/RGB path has symmetric 50% duty cycle. + */ + if (renc->output =3D=3D RZG2L_DU_OUTPUT_LVDS0) + clk_set_duty_cycle(clk_parent, 4, 7); + else + clk_set_duty_cycle(clk_parent, 1, 2); +} + static const struct drm_encoder_helper_funcs rzg2l_du_encoder_helper_funcs= =3D { .mode_valid =3D rzg2l_du_encoder_mode_valid, + .atomic_mode_set =3D rzg2l_du_encoder_atomic_mode_set, }; =20 int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu, --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 506F344BCB5 for ; Wed, 26 Aug 2026 17:49:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 26 Aug 2026 10:49:04 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:aa64:3da0:a259:ecd5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a88ac7fsm777752766b.30.2026.08.26.10.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 10:49:04 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 07/13] drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder Date: Wed, 26 Aug 2026 18:48:41 +0100 Message-ID: <20260826174854.199139-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for the RZ/G3L LVDS encoder driver. It operates in single-link mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates from 25 to 87 MHz. The LVDS module cannot be used at the same time as MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock and the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS module. Signed-off-by: Tommaso Merciai Tested-by: Tommaso Merciai Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * Moved set duty cycle to DU encoder. v1->v2: * No change. v5[1]->v1: * Added clk.h as LVDS requires 4:7 duty clock and moved this handling to LVDS driver * Avoided accessing register in disable if clk is disabled. v5[1]: https://lore.kernel.org/all/20260625172359.292631-3-biju.das.jz@bp.r= enesas.com/ v4->v5: * Added Kconfig functional dependency for DRM_RZG2L_DU * Dropped DRM_PANEL from DRM_RZG3L_LVDS config * Dropped unused headers of_device.h,of_graph.h and drm_panel.h * Dropped the unused macro LVDS_CMN_RST_PHY0_SEL_CH0 * Used plain number for macro LVDS_0_PHY_CH_IO_EN0_MSK * Retained the tag as the above changes are trivial. v3->v4: * Dropped the header files clk.h and syscon.h * Dropped next_bridge check in attach(). * Dropped syscon for getting regmap. * Replaced the below macros to match with hardware manual: LVDS_0_CTL_FMT_SEL_MSK->LVDS_0_CTL_FMT_SEL0_MSK LVDS_0_PHY_CH_IO_EN_MSK->LVDS_0_PHY_CH_IO_EN0_MSK Replaced LVDS_0_PHY_CH_IO_EN->LVDS_0_PHY_CH_IO_EN0 * Replaced atomic_reset()->atomic_create_state() * Dropped the tags as there are new changes. v2->v3: * Collected tags. v2->v2[1]: * Replace drm_atomic_state with drm_atomic_commit in rzg3l_lvds_atomic_{en,dis}able(). * Drop local variable ret and dev_err() messages in rzg3l_lvds_atomic_enable(); use WARN_ON() instead to capture unexpected failures since atomic_enable should not fail. * Drop local variable next_bridge from rzg3l_lvds_probe(). [1] https://lore.kernel.org/all/20260524194457.479681-3-biju.das.jz@bp.rene= sas.com/ v1->v2: * Dropped unused function rzg3l_lvds_is_connected() and removed the=20 corresponding header file rzg3l_lvds.h * Dropped next_bridge from struct rzg3l_lvds instead using bridge's next_bridge. * Replaced pm_runtime_resume_and_get()->pm_runtime_get_sync() as atomic_enable doesn't fail and for each enable there always will be an atomic_disable() call. * Started using DEFINE_RUNTIME_DEV_PM_OPS for PM callback. * Replaced rzg3l_lvds_parse_dt() with devm_drm_of_get_bridge() in probe() * Started using reset_control_bulk_*() in rzg3l_lvds_pm_runtime_{suspend, resume}() --- drivers/gpu/drm/renesas/rz-du/Kconfig | 13 + drivers/gpu/drm/renesas/rz-du/Makefile | 1 + drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c | 295 ++++++++++++++++++ .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h | 25 ++ 4 files changed, 334 insertions(+) create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h diff --git a/drivers/gpu/drm/renesas/rz-du/Kconfig b/drivers/gpu/drm/renesa= s/rz-du/Kconfig index 7f2ef7137ae5..0dbe86bd65d0 100644 --- a/drivers/gpu/drm/renesas/rz-du/Kconfig +++ b/drivers/gpu/drm/renesas/rz-du/Kconfig @@ -26,3 +26,16 @@ config DRM_RZG2L_MIPI_DSI def_tristate DRM_RZG2L_DU depends on DRM_RZG2L_USE_MIPI_DSI select DRM_MIPI_DSI + +config DRM_RZG3L_USE_LVDS + bool "RZ/G3L DU LVDS Encoder Support" + depends on DRM_BRIDGE && OF + depends on DRM_RZG2L_DU || COMPILE_TEST + default DRM_RZG2L_DU + help + Enable support for the RZ/G3L Display Unit embedded LVDS encoder. + +config DRM_RZG3L_LVDS + def_tristate DRM_RZG2L_DU + depends on DRM_RZG3L_USE_LVDS + select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/renesas/rz-du/Makefile b/drivers/gpu/drm/renes= as/rz-du/Makefile index 2987900ea6b6..46decb7ac4f1 100644 --- a/drivers/gpu/drm/renesas/rz-du/Makefile +++ b/drivers/gpu/drm/renesas/rz-du/Makefile @@ -8,3 +8,4 @@ rzg2l-du-drm-$(CONFIG_VIDEO_RENESAS_VSP1) +=3D rzg2l_du_vsp= .o obj-$(CONFIG_DRM_RZG2L_DU) +=3D rzg2l-du-drm.o =20 obj-$(CONFIG_DRM_RZG2L_MIPI_DSI) +=3D rzg2l_mipi_dsi.o +obj-$(CONFIG_DRM_RZG3L_LVDS) +=3D rzg3l_lvds.o diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c b/drivers/gpu/drm/r= enesas/rz-du/rzg3l_lvds.c new file mode 100644 index 000000000000..2a7ae67ff08d --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3L LVDS Encoder Driver + * + * Copyright (C) 2026 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "rzg3l_lvds_regs.h" + +enum rzg3l_lvds_mode { + RZG3L_LVDS_MODE_JEIDA =3D 0, + RZG3L_LVDS_MODE_JEIDA_MIRROR =3D 1, + RZG3L_LVDS_MODE_MODE2 =3D 2, + RZG3L_LVDS_MODE_MODE2_MIRROR =3D 3, + RZG3L_LVDS_MODE_VESA =3D 4, + RZG3L_LVDS_MODE_VESA_MIRROR =3D 5, + RZG3L_LVDS_MODE_MODE6 =3D 6, + RZG3L_LVDS_MODE_MODE6_MIRROR =3D 7, +}; + +struct rzg3l_lvds { + struct device *dev; + struct clk *dotclk; + struct reset_control *prstc; + struct reset_control *lvd_rstc; + struct regmap *regmap; + struct drm_bridge bridge; +}; + +#define bridge_to_rzg3l_lvds(b) \ + container_of(b, struct rzg3l_lvds, bridge) + +static const struct regmap_config rzg3l_lvds_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D LVDS_0_CTL_OFFSET, +}; + +/* -----------------------------------------------------------------------= ------ + * Bridge + */ + +static void rzg3l_lvds_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_commit *state) +{ + struct rzg3l_lvds *lvds =3D bridge_to_rzg3l_lvds(bridge); + const struct drm_bridge_state *bridge_state; + u32 fmt; + + /* Get the LVDS format from the bridge state. */ + bridge_state =3D drm_atomic_get_new_bridge_state(state, bridge); + if (WARN_ON(!bridge_state)) + return; + + switch (bridge_state->output_bus_cfg.format) { + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + fmt =3D RZG3L_LVDS_MODE_JEIDA; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + fmt =3D RZG3L_LVDS_MODE_VESA; + break; + default: + fmt =3D RZG3L_LVDS_MODE_VESA; + dev_warn(lvds->dev, "Unsupported bus fmt 0x%04x\n", + bridge_state->output_bus_cfg.format); + break; + } + + if (WARN_ON(pm_runtime_get_sync(lvds->dev) < 0)) + return; + + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_BGR, LVDS_0_PHY_CH_EN_BGR); + fsleep(20); + + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_LDO, LVDS_0_PHY_CH_EN_LDO); + fsleep(10); + + regmap_write(lvds->regmap, LVDS_CMN, LVDS_CMN_RST_PHY0_SEL); + regmap_update_bits(lvds->regmap, LVDS_0_CTL_OFFSET, + LVDS_0_CTL_FMT_SEL0_MSK, + FIELD_PREP(LVDS_0_CTL_FMT_SEL0_MSK, fmt)); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_IO_EN0_MSK, LVDS_0_PHY_CH_IO_EN0); + regmap_write(lvds->regmap, LVDS_CMN, + LVDS_CMN_RST_PHY0_SEL | LVDS_CMN_PHY_RESET); + fsleep(100); +} + +static void rzg3l_lvds_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_commit *state) +{ + struct rzg3l_lvds *lvds =3D bridge_to_rzg3l_lvds(bridge); + int ret; + + PM_RUNTIME_ACQUIRE_IF_ENABLED(lvds->dev, pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret < 0) + goto pm_put_sync; + + regmap_update_bits(lvds->regmap, LVDS_CMN, LVDS_CMN_PHY_RESET, 0); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_IO_EN0_MSK, 0); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_LDO, 0); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_BGR, 0); + +pm_put_sync: + pm_runtime_put_sync(lvds->dev); +} + +static int rzg3l_lvds_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct rzg3l_lvds *lvds =3D bridge_to_rzg3l_lvds(bridge); + + return drm_bridge_attach(encoder, lvds->bridge.next_bridge, bridge, flags= ); +} + +static enum drm_mode_status +rzg3l_lvds_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->clock > 87000) + return MODE_CLOCK_HIGH; + + if (mode->clock < 25000) + return MODE_CLOCK_LOW; + + return MODE_OK; +} + +static const struct drm_bridge_funcs rzg3l_lvds_bridge_ops =3D { + .attach =3D rzg3l_lvds_attach, + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_create_state =3D drm_atomic_helper_bridge_create_state, + .atomic_enable =3D rzg3l_lvds_atomic_enable, + .atomic_disable =3D rzg3l_lvds_atomic_disable, + .mode_valid =3D rzg3l_lvds_bridge_mode_valid, +}; + +/* -----------------------------------------------------------------------= ------ + * Power Management + */ + +static int rzg3l_lvds_pm_runtime_suspend(struct device *dev) +{ + struct rzg3l_lvds *lvds =3D dev_get_drvdata(dev); + struct reset_control_bulk_data resets[] =3D { + { .rstc =3D lvds->lvd_rstc }, + { .rstc =3D lvds->prstc }, + }; + + return reset_control_bulk_assert(ARRAY_SIZE(resets), resets); +} + +static int rzg3l_lvds_pm_runtime_resume(struct device *dev) +{ + struct rzg3l_lvds *lvds =3D dev_get_drvdata(dev); + struct reset_control_bulk_data resets[] =3D { + { .rstc =3D lvds->lvd_rstc }, + { .rstc =3D lvds->prstc }, + }; + + return reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); +} + +static DEFINE_RUNTIME_DEV_PM_OPS(rzg3l_lvds_pm_ops, + rzg3l_lvds_pm_runtime_suspend, + rzg3l_lvds_pm_runtime_resume, NULL); + +/* -----------------------------------------------------------------------= ------ + * Probe & Remove + */ + +static int rzg3l_lvds_probe(struct platform_device *pdev) +{ + struct reset_control *rstc, *arstc; + struct device *dev =3D &pdev->dev; + struct rzg3l_lvds *lvds; + void __iomem *base; + int ret; + + lvds =3D devm_drm_bridge_alloc(dev, struct rzg3l_lvds, bridge, + &rzg3l_lvds_bridge_ops); + if (IS_ERR(lvds)) + return PTR_ERR(lvds); + + lvds->dev =3D dev; + lvds->bridge.of_node =3D pdev->dev.of_node; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + lvds->regmap =3D devm_regmap_init_mmio(dev, base, &rzg3l_lvds_regmap_conf= ig); + if (IS_ERR(lvds->regmap)) + return dev_err_probe(dev, PTR_ERR(lvds->regmap), + "failed to init regmap\n"); + + lvds->dotclk =3D devm_clk_get(dev, "dotclk"); + if (IS_ERR(lvds->dotclk)) + return PTR_ERR(lvds->dotclk); + + rstc =3D devm_reset_control_get_exclusive(dev, "rst"); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), "failed to get rst\n"); + + arstc =3D devm_reset_control_get_exclusive(dev, "arst"); + if (IS_ERR(arstc)) + return dev_err_probe(dev, PTR_ERR(arstc), + "failed to get arst\n"); + + lvds->prstc =3D devm_reset_control_get_exclusive(dev, "prst"); + if (IS_ERR(lvds->prstc)) + return dev_err_probe(dev, PTR_ERR(lvds->prstc), + "failed to get prst\n"); + + lvds->lvd_rstc =3D devm_reset_control_get_exclusive(dev, "lvdrst"); + if (IS_ERR(lvds->lvd_rstc)) + return dev_err_probe(dev, PTR_ERR(lvds->lvd_rstc), + "failed to get core reset\n"); + + platform_set_drvdata(pdev, lvds); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable Runtime PM\n"); + + lvds->bridge.next_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, 1,= 0); + if (IS_ERR(lvds->bridge.next_bridge)) + return dev_err_probe(dev, PTR_ERR(lvds->bridge.next_bridge), + "failed to get next bridge\n"); + + ret =3D reset_control_assert(rstc); + if (ret < 0) + return ret; + + ret =3D reset_control_assert(arstc); + if (ret < 0) + return ret; + + ret =3D devm_drm_bridge_add(dev, &lvds->bridge); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register drm bridge\n"); + + return ret; +} + +static const struct of_device_id rzg3l_lvds_of_table[] =3D { + { .compatible =3D "renesas,r9a08g046-lvds" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, rzg3l_lvds_of_table); + +static struct platform_driver rzg3l_lvds_platform_driver =3D { + .probe =3D rzg3l_lvds_probe, + .driver =3D { + .name =3D "rzg3l-lvds", + .pm =3D pm_ptr(&rzg3l_lvds_pm_ops), + .of_match_table =3D rzg3l_lvds_of_table, + }, +}; + +module_platform_driver(rzg3l_lvds_platform_driver); + +MODULE_AUTHOR("Biju Das "); +MODULE_AUTHOR("Tommaso Merciai "); +MODULE_DESCRIPTION("Renesas RZ/G3L LVDS Encoder Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h b/drivers/gpu/= drm/renesas/rz-du/rzg3l_lvds_regs.h new file mode 100644 index 000000000000..5b276cca9a5d --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/G3L LVDS Interface Registers Definitions + * + * Copyright (C) 2026 Renesas Electronics Corporation + * + */ + +#ifndef __RZG3L_LVDS_REGS_H__ +#define __RZG3L_LVDS_REGS_H__ + +#define LVDS_CMN 0x00 +#define LVDS_CMN_RST_PHY0_SEL BIT(24) +#define LVDS_CMN_PHY_RESET BIT(0) + +#define LVDS_0_PHY_OFFSET 0x10 +#define LVDS_0_PHY_CH_IO_EN0_MSK 0x1f +#define LVDS_0_PHY_CH_IO_EN0 (LVDS_0_PHY_CH_IO_EN0_MSK << 0) +#define LVDS_0_PHY_CH_EN_BGR BIT(8) +#define LVDS_0_PHY_CH_EN_LDO BIT(9) + +#define LVDS_0_CTL_OFFSET 0x14 +#define LVDS_0_CTL_FMT_SEL0_MSK GENMASK(23, 20) + +#endif /* __RZG3L_LVDS_REGS_H__ */ --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 400F6466B09 for ; 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charset="utf-8" From: Biju Das Add fcpvd node to RZ/G3L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Tommaso Merciai --- v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index 9f5ea62efc2c..ad38aee2efb3 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -696,6 +696,17 @@ ssi3: ssi@100e4c00 { status =3D "disabled"; }; =20 + fcpvd: fcp@10880000 { + compatible =3D "renesas,r9a08g046-fcpvd", "renesas,fcpv"; + reg =3D <0 0x10880000 0 0x10000>; + clocks =3D <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>; + clock-names =3D "aclk", "pclk", "vclk"; + resets =3D <&cpg R9A08G046_LCDC_RESET_N>; + power-domains =3D <&cpg>; + }; + gpu: gpu@108b0000 { compatible =3D "renesas,r9a08g046-mali", "arm,mali-bifrost"; --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 762F247125F for ; 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Wed, 26 Aug 2026 10:49:06 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:aa64:3da0:a259:ecd5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a88ac7fsm777752766b.30.2026.08.26.10.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 10:49:06 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 09/13] arm64: dts: renesas: r9a08g046: Add vspd node Date: Wed, 26 Aug 2026 18:48:43 +0100 Message-ID: <20260826174854.199139-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add vspd node to RZ/G3L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Tommaso Merciai --- v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index ad38aee2efb3..6ff145dc81fa 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -696,6 +696,20 @@ ssi3: ssi@100e4c00 { status =3D "disabled"; }; =20 + vspd: vsp@10870000 { + compatible =3D "renesas,r9a08g046-vsp2", + "renesas,r9a07g044-vsp2"; + reg =3D <0 0x10870000 0 0x10000>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>; + clock-names =3D "aclk", "pclk", "vclk"; + resets =3D <&cpg R9A08G046_LCDC_RESET_N>; + power-domains =3D <&cpg>; + renesas,fcp =3D <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible =3D "renesas,r9a08g046-fcpvd", "renesas,fcpv"; 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Wed, 26 Aug 2026 10:49:07 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 10/13] arm64: dts: renesas: r9a08g046: Add DU and DSI nodes Date: Wed, 26 Aug 2026 18:48:44 +0100 Message-ID: <20260826174854.199139-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add DU and DSI nodes to RZ/G3L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Tommaso Merciai --- v2->v3: * No change. v1->v2: * Dropped renesas,sysc-pwrrdy from dsi node. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index 6ff145dc81fa..cc8bfb24da87 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -696,6 +696,49 @@ ssi3: ssi@100e4c00 { status =3D "disabled"; }; =20 + dsi: dsi@10850000 { + compatible =3D "renesas,r9a08g046-mipi-dsi"; + reg =3D <0 0x10850000 0 0x20000>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks =3D <&cpg CPG_CORE R9A08G046_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A08G046_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A08G046_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A08G046_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A08G046_MIPI_DSI_LPCLK>; + clock-names =3D "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets =3D <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>, + <&cpg R9A08G046_MIPI_DSI_ARESET_N>, + <&cpg R9A08G046_MIPI_DSI_PRESET_N>; + reset-names =3D "rst", "arst", "prst"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi_in: endpoint { + remote-endpoint =3D <&du_out_dsi>; + }; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; + vspd: vsp@10870000 { compatible =3D "renesas,r9a08g046-vsp2", "renesas,r9a07g044-vsp2"; @@ -721,6 +764,40 @@ fcpvd: fcp@10880000 { power-domains =3D <&cpg>; }; =20 + du: display@10890000 { + compatible =3D "renesas,r9a08g046-du"; + reg =3D <0 0x10890000 0 0x10000>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>, + <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>; + clock-names =3D "aclk", "pclk", "vclk"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_LCDC_RESET_N>; + renesas,vsps =3D <&vspd 0>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + du_out_dsi: endpoint { + remote-endpoint =3D <&dsi_in>; + }; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + }; + }; + gpu: gpu@108b0000 { compatible =3D "renesas,r9a08g046-mali", "arm,mali-bifrost"; --=20 2.43.0 From nobody Mon Sep 28 04:10:50 2026 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5240246AA94 for ; Wed, 26 Aug 2026 17:49:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787766567; cv=none; b=WmLRfNxaKvZxHW7li8xb4u3ePPJ+msx2piak0AsMOe1Z1B7xIrHiW4L8zxBkaSm6e/0yHfPB7y5G8UIpabqF9qH5qbzSgKQELqqy6pejeyFQuXuh9XOpDmTqK/9bYBBAlQjOPn28FiYRFoEuNcVbaiTXJvs6dNw5fAcEJTFyEZs= ARC-Message-Signature: i=1; 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Wed, 26 Aug 2026 10:49:09 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:aa64:3da0:a259:ecd5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a88ac7fsm777752766b.30.2026.08.26.10.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 10:49:08 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 11/13] arm64: dts: renesas: r9a08g046: Add LVDS node Date: Wed, 26 Aug 2026 18:48:45 +0100 Message-ID: <20260826174854.199139-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add LVDS node to RZ/G3L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Tommaso Merciai --- v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index cc8bfb24da87..f652ad3f1d1a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -794,6 +794,43 @@ port@1 { =20 port@2 { reg =3D <2>; + du_out_lvds: endpoint { + remote-endpoint =3D <&lvds_in>; + }; + }; + }; + }; + + lvds: lvds@108a0000 { + compatible =3D "renesas,r9a08g046-lvds"; + reg =3D <0 0x108a0000 0 0x10000>; + clocks =3D <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>, + <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>; + clock-names =3D "pclk", "phyclk", "dotclk"; + resets =3D <&cpg R9A08G046_LVDS_RESET_N>, + <&cpg R9A08G046_MIPI_DSI_PRESET_N>, + <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>, + <&cpg R9A08G046_MIPI_DSI_ARESET_N>; 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charset="utf-8" From: Biju Das Add a Device Tree overlay (r9a08g046l48-smarc-dsi-adv7535.dtso) for the RZ/G3L (R9A08G046) SMARC EVK board to support DSI-to-HDMI output via the Analog Devices ADV7535 HDMI transmitter. The overlay enables the DSI controller with a 4-lane data path and the display unit (DU/LCDC), and configures the ADV7535 on I2C2. Update the Makefile to build the overlay as both a standalone .dtbo and a composite .dtb (base DTB + overlay). Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/Makefile | 3 + .../r9a08g046l48-smarc-dsi-adv7535.dtso | 95 +++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7= 535.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 8bf155badd11..8c6a44890715 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -187,6 +187,9 @@ r9a08g045s33-smarc-pmod1-type-3a-dtbs :=3D r9a08g045s33= -smarc.dtb r9a08g045s33-sma dtb-$(CONFIG_ARCH_R9A08G045) +=3D r9a08g045s33-smarc-pmod1-type-3a.dtb =20 dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc.dtb +dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc-dsi-adv7535.dtbo +r9a08g046l48-smarc-dsi-adv7535-dtbs :=3D r9a08g046l48-smarc.dtb r9a08g046l= 48-smarc-dsi-adv7535.dtbo +dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc-dsi-adv7535.dtb =20 dtb-$(CONFIG_ARCH_R9A09G011) +=3D r9a09g011-v2mevk2.dtb =20 diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dts= o b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso new file mode 100644 index 000000000000..cede3b4ba318 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G3L SMARC EVK with ADV7535 + * connected to DSI and LCDC enabled. + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + osc1: cec-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <12000000>; + }; + + dsi-to-hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "d"; + + port { + dsi_to_hdmi_con_out: endpoint { + remote-endpoint =3D <&adv7535_out>; + }; + }; + }; +}; + +&dsi { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + dsi_out: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&adv7535_in>; + }; + }; + }; +}; + +&du { + status =3D "okay"; +}; + +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adv7535: hdmi@3d { + compatible =3D "adi,adv7535"; + reg =3D <0x3d>; + + interrupts-extended =3D <&pinctrl RZG3L_GPIO(K, 3) IRQ_TYPE_EDGE_FALLING= >; + clocks =3D <&osc1>; + clock-names =3D "cec"; + avdd-supply =3D <®_1p8v>; + dvdd-supply =3D <®_1p8v>; + pvdd-supply =3D <®_1p8v>; + a2vdd-supply =3D <®_1p8v>; + v3p3-supply =3D <®_3p3v>; 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Wed, 26 Aug 2026 10:49:10 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:aa64:3da0:a259:ecd5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a88ac7fsm777752766b.30.2026.08.26.10.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 10:49:10 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263 Date: Wed, 26 Aug 2026 18:48:47 +0100 Message-ID: <20260826174854.199139-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add a Device Tree overlay (r9a08g046l48-smarc-lvds-ite6263.dtso) for the RZ/G3L (R9A08G046) SMARC EVK board to support LVDS-to-HDMI output via the ITE 6263 HDMI transmitter. The overlay enables the LVDS controller and the display unit (DU/LCDC), and configures the ITE6263 on I2C2. Update the Makefile to build the overlay as both a standalone .dtbo and a composite .dtb (base DTB + overlay). Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/Makefile | 3 + .../r9a08g046l48-smarc-lvds-ite6263.dtso | 104 ++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite= 6263.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 8c6a44890715..3cecc40204e9 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -190,6 +190,9 @@ dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc.dtb dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc-dsi-adv7535.dtbo r9a08g046l48-smarc-dsi-adv7535-dtbs :=3D r9a08g046l48-smarc.dtb r9a08g046l= 48-smarc-dsi-adv7535.dtbo dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc-dsi-adv7535.dtb +dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc-lvds-ite6263.dtbo +r9a08g046l48-smarc-lvds-ite6263-dtbs :=3D r9a08g046l48-smarc.dtb r9a08g046= l48-smarc-lvds-ite6263.dtbo +dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc-lvds-ite6263.dtb =20 dtb-$(CONFIG_ARCH_R9A09G011) +=3D r9a09g011-v2mevk2.dtb =20 diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dt= so b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso new file mode 100644 index 000000000000..95e1f411fa04 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G3L SMARC EVK with ITE6263 + * connected to LVDS and LCDC enabled. + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + lvds-to-hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "d"; + + port { + lvds_to_hdmi_con_out: endpoint { + remote-endpoint =3D <&it6263_out>; + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-1.8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-3.3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&du { + status =3D "okay"; +}; + +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + it6263: it6263@4c { + compatible =3D "ite,it6263"; + reg =3D <0x4c>; + data-mapping =3D "vesa-24"; + ivdd-supply =3D <®_1v8>; + ovdd-supply =3D <®_3v3>; + txavcc18-supply =3D <®_1v8>; + txavcc33-supply =3D <®_3v3>; + pvcc1-supply =3D <®_1v8>; + pvcc2-supply =3D <®_1v8>; + avcc-supply =3D <®_3v3>; + anvdd-supply =3D <®_1v8>; + apvdd-supply =3D <®_1v8>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + bridge_in: endpoint { + remote-endpoint =3D <&lvds_out>; + }; + }; + + port@2 { + reg =3D <2>; + it6263_out: endpoint { + remote-endpoint =3D <&lvds_to_hdmi_con_out>; + }; + }; + }; + }; +}; + +&lvds { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + lvds_out: endpoint { + remote-endpoint =3D <&bridge_in>; + }; + }; + }; +}; --=20 2.43.0