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Tue, 25 Aug 2026 18:30:23 -0700 (PDT) From: Yuanshen Cao Date: Wed, 26 Aug 2026 01:30:03 +0000 Subject: [PATCH v4 1/5] dmaengine: sun6i-dma: Refactor to support A733 interrupt and register handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-sun60i-a733-dma-v4-1-dc2f745f40dc@gmail.com> References: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> In-Reply-To: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.16.0 The `sun6i-dma` driver currently uses hardcoded logic for interrupt handling (reading/writing interrupt enable and status registers) and register dumping. To support the Allwinner A733, which has a different register layout and interrupt handling logic, add `irq_stride`, `irq_en_offset`, and `irq_stat_offset` to `struct sun6i_dma_config`. Implement generic `sun6i_read/write_irq_*` functions using these new configuration fields to accommodate different hardware revisions. Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 87 +++++++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 67 insertions(+), 20 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index f47a326dd7ff..f305fbfb3545 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -27,7 +27,6 @@ /* * Common registers */ -#define DMA_IRQ_EN(x) ((x) * 0x04) #define DMA_IRQ_HALF BIT(0) #define DMA_IRQ_PKG BIT(1) #define DMA_IRQ_QUEUE BIT(2) @@ -36,8 +35,6 @@ #define DMA_IRQ_CHAN_WIDTH 4 =20 =20 -#define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10) - #define DMA_STAT 0x30 =20 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ @@ -52,6 +49,14 @@ #define SUNXI_H3_SECURE_REG 0x20 #define SUNXI_H3_DMA_GATE 0x28 #define SUNXI_H3_DMA_GATE_ENABLE 0x4 + +/* + * Interrupts specific registers + */ +#define DMA_IRQ_STRIDE_A31 0x04 +#define DMA_IRQ_EN_OFFSET_A31 0x00 +#define DMA_IRQ_STAT_OFFSET_A31 0x10 + /* * Channels specific registers */ @@ -144,6 +149,9 @@ struct sun6i_dma_config { u32 dst_addr_widths; bool has_high_addr; bool has_mbus_clk; + u32 irq_stride; + u32 irq_en_offset; + u32 irq_stat_offset; }; =20 /* @@ -234,19 +242,43 @@ to_sun6i_desc(struct dma_async_tx_descriptor *tx) return container_of(tx, struct sun6i_desc, vd.tx); } =20 +static u32 sun6i_read_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg->ir= q_en_offset); +} + +static void sun6i_write_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg, u3= 2 irq_val) +{ + writel(irq_val, sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg-= >irq_en_offset); +} + +static u32 sun6i_read_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg->ir= q_stat_offset); +} + +static void sun6i_write_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg, = u32 status) +{ + writel(status, sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg->= irq_stat_offset); +} + static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) { - dev_dbg(sdev->slave.dev, "Common register:\n" - "\tmask0(%04x): 0x%08x\n" - "\tmask1(%04x): 0x%08x\n" - "\tpend0(%04x): 0x%08x\n" - "\tpend1(%04x): 0x%08x\n" - "\tstats(%04x): 0x%08x\n", - DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), - DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), - DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), - DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), - DMA_STAT, readl(sdev->base + DMA_STAT)); + int i; + + for (i =3D 0; i < 2; i++) { + dev_dbg(sdev->slave.dev, "Common register:\n" + "chan num %d\n" + "\tmask(%04x): 0x%08x\n" + "\tpend(%04x): 0x%08x\n" + "\tstats(%04x): 0x%08x\n", + i, + i * sdev->cfg->irq_stride + sdev->cfg->irq_en_offset, + sun6i_read_irq_en(sdev, i), + i * sdev->cfg->irq_stride + sdev->cfg->irq_stat_offset, + sun6i_read_irq_stat(sdev, i), + DMA_STAT, readl(sdev->base + DMA_STAT)); + } } =20 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, @@ -460,11 +492,11 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *v= chan) =20 vchan->irq_type =3D vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; =20 - irq_val =3D readl(sdev->base + DMA_IRQ_EN(irq_reg)); + irq_val =3D sun6i_read_irq_en(sdev, irq_reg); irq_val &=3D ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) << (irq_offset * DMA_IRQ_CHAN_WIDTH)); irq_val |=3D vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH); - writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); + sun6i_write_irq_en(sdev, irq_reg, irq_val); =20 writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); @@ -549,14 +581,14 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void = *dev_id) u32 status; =20 for (i =3D 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { - status =3D readl(sdev->base + DMA_IRQ_STAT(i)); + status =3D sun6i_read_irq_stat(sdev, i); if (!status) continue; =20 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", str_high_low(i), status); =20 - writel(status, sdev->base + DMA_IRQ_STAT(i)); + sun6i_write_irq_stat(sdev, i, status); =20 for (j =3D 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { pchan =3D sdev->pchans + j; @@ -1072,9 +1104,11 @@ static struct dma_chan *sun6i_dma_of_xlate(struct of= _phandle_args *dma_spec, =20 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) { + int i; + /* Disable all interrupts from DMA */ - writel(0, sdev->base + DMA_IRQ_EN(0)); - writel(0, sdev->base + DMA_IRQ_EN(1)); + for (i =3D 0; i < 2; i++) + sun6i_write_irq_en(sdev, i, 0); =20 /* Prevent spurious interrupts from scheduling the tasklet */ atomic_inc(&sdev->tasklet_shutdown); @@ -1098,6 +1132,11 @@ static inline void sun6i_dma_free(struct sun6i_dma_d= ev *sdev) } } =20 +#define SUN6I_DMA_IRQ_A31_COMMON_CFG \ + .irq_stride =3D DMA_IRQ_STRIDE_A31, \ + .irq_en_offset =3D DMA_IRQ_EN_OFFSET_A31, \ + .irq_stat_offset =3D DMA_IRQ_STAT_OFFSET_A31, + /* * For A31: * @@ -1129,6 +1168,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg =3D { .dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; =20 /* @@ -1152,6 +1192,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg =3D { .dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; =20 static struct sun6i_dma_config sun8i_a83t_dma_cfg =3D { @@ -1170,6 +1211,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg =3D= { .dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; =20 /* @@ -1197,6 +1239,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg =3D { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; =20 /* @@ -1218,6 +1261,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg =3D= { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; =20 /* @@ -1241,6 +1285,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = =3D { BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), .has_high_addr =3D true, .has_mbus_clk =3D true, + SUN6I_DMA_IRQ_A31_COMMON_CFG }; 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Tue, 25 Aug 2026 18:30:25 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9377e67c52csm102398585a.38.2026.08.25.18.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 18:30:25 -0700 (PDT) From: Yuanshen Cao Date: Wed, 26 Aug 2026 01:30:04 +0000 Subject: [PATCH v4 2/5] dmaengine: sun6i-dma: Support variable address widths using masks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-sun60i-a733-dma-v4-2-dc2f745f40dc@gmail.com> References: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> In-Reply-To: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.16.0 The Allwinner A733 DMA controller supports higher addresses (up to 32G) compared to previous generations. The existing `sun6i_dma_set_addr` function uses hardcoded logic for setting the high-address bits in the LLI parameters. Add `src_high_addr_mask` and `dst_high_addr_mask` to `struct sun6i_dma_config` to handle different high-address bitfield mappings. Update `sun6i_dma_set_addr` to use these masks via `field_prep()`, allowing the driver to support variable address widths. Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index f305fbfb3545..53c54161e32a 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -24,6 +24,10 @@ =20 #include "virt-dma.h" =20 +/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + /* * Common registers */ @@ -103,8 +107,8 @@ * The LLI link physical address is also mangled, but we avoid dealing * with that by allocating LLIs from the DMA32 zone. */ -#define SRC_HIGH_ADDR(x) (((x) & 0x3U) << 16) -#define DST_HIGH_ADDR(x) (((x) & 0x3U) << 18) +#define SRC_HIGH_ADDR_MASK GENMASK(17, 16) +#define DST_HIGH_ADDR_MASK GENMASK(19, 18) =20 /* * Various hardware related defines @@ -147,7 +151,8 @@ struct sun6i_dma_config { u32 dst_burst_lengths; u32 src_addr_widths; u32 dst_addr_widths; - bool has_high_addr; + u32 src_high_addr_mask; + u32 dst_high_addr_mask; bool has_mbus_clk; u32 irq_stride; u32 irq_en_offset; @@ -687,9 +692,10 @@ static inline void sun6i_dma_set_addr(struct sun6i_dma= _dev *sdev, v_lli->src =3D lower_32_bits(src); v_lli->dst =3D lower_32_bits(dst); =20 - if (sdev->cfg->has_high_addr) - v_lli->para |=3D SRC_HIGH_ADDR(upper_32_bits(src)) | - DST_HIGH_ADDR(upper_32_bits(dst)); + if (sdev->cfg->src_high_addr_mask) + v_lli->para |=3D + field_prep(sdev->cfg->src_high_addr_mask, upper_32_bits(src)) | + field_prep(sdev->cfg->dst_high_addr_mask, upper_32_bits(dst)); } =20 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( @@ -1283,7 +1289,8 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = =3D { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), - .has_high_addr =3D true, + .src_high_addr_mask =3D SRC_HIGH_ADDR_MASK, + .dst_high_addr_mask =3D DST_HIGH_ADDR_MASK, .has_mbus_clk =3D true, SUN6I_DMA_IRQ_A31_COMMON_CFG }; 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Tue, 25 Aug 2026 18:30:26 -0700 (PDT) From: Yuanshen Cao Date: Wed, 26 Aug 2026 01:30:05 +0000 Subject: [PATCH v4 3/5] dmaengine: sun6i-dma: Add num_channels_per_reg for flexible interrupt mapping Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-sun60i-a733-dma-v4-3-dc2f745f40dc@gmail.com> References: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> In-Reply-To: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.16.0 The `sun6i-dma` driver previously assumed a fixed number of channels per interrupt register. For example, `sun6i_kill_tasklet` was hardcoded to disable interrupts only for registers 0 and 1. `DMA_MAX_CHANNELS` was also not in used previously, and the old SoCs never has more than 16 channels. The A733 has a different interrupt structure where the number of channels per register may differ. Add `num_channels_per_reg` to `struct sun6i_dma_config` to make the interrupt handling logic handware-agnostic Update `sun6i_dma_interrupt`, `sun6i_dma_start_desc`, and `sun6i_kill_tasklet` to use this value. Additionally, set `DMA_MAX_CHANNELS` to 16 to ensure loops over interrupts are correctly bounded, aligning with the hardware specifications. Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 53c54161e32a..b96d7d90f6b5 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -35,14 +35,13 @@ #define DMA_IRQ_PKG BIT(1) #define DMA_IRQ_QUEUE BIT(2) =20 -#define DMA_IRQ_CHAN_NR 8 #define DMA_IRQ_CHAN_WIDTH 4 =20 =20 #define DMA_STAT 0x30 =20 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ -#define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4) +#define DMA_MAX_CHANNELS 16 =20 /* * sun8i specific registers @@ -61,6 +60,8 @@ #define DMA_IRQ_EN_OFFSET_A31 0x00 #define DMA_IRQ_STAT_OFFSET_A31 0x10 =20 +#define DMA_IRQ_CHAN_NR_A31 8 + /* * Channels specific registers */ @@ -157,6 +158,7 @@ struct sun6i_dma_config { u32 irq_stride; u32 irq_en_offset; u32 irq_stat_offset; + u32 num_channels_per_reg; }; =20 /* @@ -271,7 +273,7 @@ static inline void sun6i_dma_dump_com_regs(struct sun6i= _dma_dev *sdev) { int i; =20 - for (i =3D 0; i < 2; i++) { + for (i =3D 0; i < DIV_ROUND_UP(sdev->num_pchans, sdev->cfg->num_channels_= per_reg); i++) { dev_dbg(sdev->slave.dev, "Common register:\n" "chan num %d\n" "\tmask(%04x): 0x%08x\n" @@ -492,8 +494,8 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vch= an) =20 sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli); =20 - irq_reg =3D pchan->idx / DMA_IRQ_CHAN_NR; - irq_offset =3D pchan->idx % DMA_IRQ_CHAN_NR; + irq_reg =3D pchan->idx / sdev->cfg->num_channels_per_reg; + irq_offset =3D pchan->idx % sdev->cfg->num_channels_per_reg; =20 vchan->irq_type =3D vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; =20 @@ -585,7 +587,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *d= ev_id) int i, j, ret =3D IRQ_NONE; u32 status; =20 - for (i =3D 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { + for (i =3D 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++= ) { status =3D sun6i_read_irq_stat(sdev, i); if (!status) continue; @@ -595,7 +597,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *d= ev_id) =20 sun6i_write_irq_stat(sdev, i, status); =20 - for (j =3D 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { + for (j =3D 0; (j < sdev->cfg->num_channels_per_reg) && status; j++) { pchan =3D sdev->pchans + j; vchan =3D pchan->vchan; if (vchan && (status & vchan->irq_type)) { @@ -1113,7 +1115,7 @@ static inline void sun6i_kill_tasklet(struct sun6i_dm= a_dev *sdev) int i; =20 /* Disable all interrupts from DMA */ - for (i =3D 0; i < 2; i++) + for (i =3D 0; i < DMA_MAX_CHANNELS / sdev->cfg->num_channels_per_reg; i++) sun6i_write_irq_en(sdev, i, 0); =20 /* Prevent spurious interrupts from scheduling the tasklet */ @@ -1141,7 +1143,8 @@ static inline void sun6i_dma_free(struct sun6i_dma_de= v *sdev) #define SUN6I_DMA_IRQ_A31_COMMON_CFG \ .irq_stride =3D DMA_IRQ_STRIDE_A31, \ .irq_en_offset =3D DMA_IRQ_EN_OFFSET_A31, \ - .irq_stat_offset =3D DMA_IRQ_STAT_OFFSET_A31, + .irq_stat_offset =3D DMA_IRQ_STAT_OFFSET_A31, \ + .num_channels_per_reg =3D DMA_IRQ_CHAN_NR_A31, =20 /* * For A31: --=20 2.55.0 From nobody Mon Sep 28 05:48:44 2026 Received: from mail-qk1-f181.google.com (mail-qk1-f181.google.com [209.85.222.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C99FA279DCC for ; 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Tue, 25 Aug 2026 18:30:28 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9377e67c52csm102398585a.38.2026.08.25.18.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 18:30:28 -0700 (PDT) From: Yuanshen Cao Date: Wed, 26 Aug 2026 01:30:06 +0000 Subject: [PATCH v4 4/5] dt-bindings: dmaengine: sun50i-a64-dma: Add allwinner,sun60i-a733-dma compatible string Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-sun60i-a733-dma-v4-4-dc2f745f40dc@gmail.com> References: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> In-Reply-To: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Frank Li , Krzysztof Kozlowski X-Mailer: b4 0.16.0 Add `allwinner,sun60i-a733-dma` to the list of compatible strings for the `sun50i-a64-dma` dtbinding documentation. While the A733 DMA controller shares many similarities with the sun50i-a64 DMA controller, it requires a specific configuration due to differences in: - Interrupt register layout and mapping. - Number of channels per interrupt register. - Support for higher (32G) address widths in LLI parameters. Reviewed-by: Frank Li Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yuanshen Cao --- Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma= .yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index c3e14eb6cfff..1cc3304b7414 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -25,6 +25,7 @@ properties: - allwinner,sun50i-a64-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma @@ -70,6 +71,7 @@ if: - allwinner,sun20i-d1-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma =20 then: properties: --=20 2.55.0 From nobody Mon Sep 28 05:48:44 2026 Received: from mail-qv1-f44.google.com (mail-qv1-f44.google.com [209.85.219.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 862F727A916 for ; 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Tue, 25 Aug 2026 18:30:30 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9377e67c52csm102398585a.38.2026.08.25.18.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 18:30:29 -0700 (PDT) From: Yuanshen Cao Date: Wed, 26 Aug 2026 01:30:07 +0000 Subject: [PATCH v4 5/5] dmaengine: sun6i-dma: Add support for Allwinner A733 DMA controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-sun60i-a733-dma-v4-5-dc2f745f40dc@gmail.com> References: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> In-Reply-To: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.16.0 Implement support for the Allwinner A733 DMA controller by defining A733-specific register offsets, bitfield masks, and the `sun60i_a733_dma_cfg` configuration structure. This includes the IRQ stride, offsets, and channel counts specific to the A733, as well as the 32G mask for high-address fields in the LLI. Add `sun60i_a733_dma_cfg`, which ties all the refactored functionality together for A733. Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index b96d7d90f6b5..fb371b57d792 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -57,10 +57,14 @@ * Interrupts specific registers */ #define DMA_IRQ_STRIDE_A31 0x04 +#define DMA_IRQ_STRIDE_A733 0x40 #define DMA_IRQ_EN_OFFSET_A31 0x00 +#define DMA_IRQ_EN_OFFSET_A733 0x134 #define DMA_IRQ_STAT_OFFSET_A31 0x10 +#define DMA_IRQ_STAT_OFFSET_A733 0x138 =20 #define DMA_IRQ_CHAN_NR_A31 8 +#define DMA_IRQ_CHAN_NR_A733 1 =20 /* * Channels specific registers @@ -110,6 +114,8 @@ */ #define SRC_HIGH_ADDR_MASK GENMASK(17, 16) #define DST_HIGH_ADDR_MASK GENMASK(19, 18) +#define SRC_HIGH_ADDR_32G_MASK GENMASK(13, 11) +#define DST_HIGH_ADDR_32G_MASK GENMASK(17, 15) =20 /* * Various hardware related defines @@ -1321,6 +1327,29 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg =3D= { SUN6I_DMA_IRQ_A31_COMMON_CFG }; =20 +/* + * The A733 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun60i_a733_dma_cfg =3D { + .clock_autogate_enable =3D sun6i_enable_clock_autogate_h3, + .src_burst_lengths =3D BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths =3D BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .src_high_addr_mask =3D SRC_HIGH_ADDR_32G_MASK, + .dst_high_addr_mask =3D DST_HIGH_ADDR_32G_MASK, + .has_mbus_clk =3D true, + .irq_stride =3D DMA_IRQ_STRIDE_A733, + .irq_en_offset =3D DMA_IRQ_EN_OFFSET_A733, + .irq_stat_offset =3D DMA_IRQ_STAT_OFFSET_A733, + .num_channels_per_reg =3D DMA_IRQ_CHAN_NR_A733, +}; + /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. @@ -1355,6 +1384,7 @@ static const struct of_device_id sun6i_dma_match[] = =3D { { .compatible =3D "allwinner,sun50i-a64-dma", .data =3D &sun50i_a64_dma_c= fg }, { .compatible =3D "allwinner,sun50i-a100-dma", .data =3D &sun50i_a100_dma= _cfg }, { .compatible =3D "allwinner,sun50i-h6-dma", .data =3D &sun50i_h6_dma_cfg= }, + { .compatible =3D "allwinner,sun60i-a733-dma", .data =3D &sun60i_a733_dma= _cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match); --=20 2.55.0