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a=ed25519-sha256; t=1787737891; l=3434; i=aniket.randive@oss.qualcomm.com; s=20260325; h=from:subject:message-id; bh=q6lnsY3bEIeljUOjeWLcxQADTc6XmvxdsLsC9iNl46Q=; b=5w6OCYdxBkdnA/Vfk6+SF0rNAOMSGJ7ci5lTeen32UHILV4bOZD6Ou9Wrwq2mxwPaq4Qp5Tks eOIaDGWrWbfD0zmdIX82fCBLN0RZ0TOmnlNDvD99I3ssCe6xRiLXdBt X-Developer-Key: i=aniket.randive@oss.qualcomm.com; a=ed25519; pk=4o37X1ZqGbCO/T2SR8kq/HnWvq0yb1RUlFuNukovbQk= X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDA4MSBTYWx0ZWRfXxCV/JqHNAJnB dLmdF1W/Za9ECDs+7xaqAZj0hTnYuzIkei/br1rFs0ZGx427mZD2/ZKaqVNROeisclfv2u1bn17 FdtNI4Y9VukKxIPweAHlH08YccehqP0= X-Proofpoint-ORIG-GUID: K6XP5UCJpDfyx0-WrfGUrf5AyVSwOrky X-Authority-Analysis: v=2.4 cv=eYgNubEH c=1 sm=1 tr=0 ts=6a8eb72d cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=CbeJ011b9i7gwIzP_X4A:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDA4MSBTYWx0ZWRfX+3Y/qc+jwRD3 UahzEQA/bF6KSqZwEZwO4UZ0Q8BK70dGwntTX2J5XgeKjZ6QUvmyArDADSzo/RjSrFRFr59o2AV 0fA5WN8KHf0nkSktOiSj16ZrExa6pdNRPgadKQ+VQ5DXrbko/DViUW6HE7UzPMNanOW5szFkTGE FQ6eQlFHGObIEchUQd29yfNeNOqk56s8iyFVtL554yYeeJcauQGljZ1sXrhYgFs9mjadunMjT7N /y+9KAc0Qzvty2RaW9+Yncwyyoai6RocvZE/WuK8jm0M1ZGRqrYuDx1I+RGL0h2hFMPBNwtENtd uEcevmlcx1Xdh1wi0uMnNVVv+vUVcL90ayri+6OmADfuteV6diqMDF5G6NpglQLk9hIIhkq+11F va9iAJkiUzz4s0leNYIUKj6grfPyudhWHevH3SDl1nNCpAvsSQCP3gpedo9yeg1RmhGpNfVX5ss iiRmFmVeDbQ5bgnjL0A== X-Proofpoint-GUID: K6XP5UCJpDfyx0-WrfGUrf5AyVSwOrky X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-26_02,2026-08-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 phishscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260081 The I2C_BUS_CLEAR and I2C_STOP_ON_BUS GENI sequencer opcodes release a stuck I2C bus, but the GPI DMA driver has no way to emit these zero-payload control commands, so an I2C controller using GPI DMA cannot recover the bus. Add I2C_BUS_CLEAR and I2C_STOP_ON_BUS to enum i2c_op so I2C drivers can request them through gpi_i2c_config.op. Handle them in gpi_create_i2c_tre() by emitting a CONFIG TRE (when set_config is set) followed by a GO TRE with IEOT set and no DMA TRE, and reserve the matching number of ring entries in gpi_prep_slave_sg(). Signed-off-by: Aniket Randive --- drivers/dma/qcom/gpi.c | 30 ++++++++++++++++++++++++++++++ include/linux/dma/qcom-gpi-dma.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index a5055a6273af..14a74f0a602d 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1620,6 +1620,17 @@ gpi_peripheral_config(struct dma_chan *chan, struct = dma_slave_config *config) return 0; } =20 +static void gpi_create_i2c_go_recovery_tre(struct gpi_i2c_config *i2c, + struct gpi_tre *tre) +{ + tre->dword[0] =3D u32_encode_bits(i2c->op, TRE_I2C_GO_CMD); + tre->dword[1] =3D 0; + tre->dword[2] =3D 0; + + tre->dword[3] =3D u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE); + tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_IEOT); +} + static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, struct scatterlist *sgl, enum dma_transfer_direction direction, unsigned long flags) @@ -1650,6 +1661,12 @@ static int gpi_create_i2c_tre(struct gchan *chan, st= ruct gpi_desc *desc, tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_CHAIN); } =20 + if (i2c->op =3D=3D I2C_BUS_CLEAR || i2c->op =3D=3D I2C_STOP_ON_BUS) { + gpi_create_i2c_go_recovery_tre(i2c, &desc->tre[tre_idx]); + tre_idx++; + goto log_tre; + } + /* create the GO tre for Tx */ if (i2c->op =3D=3D I2C_WRITE) { tre =3D &desc->tre[tre_idx]; @@ -1692,6 +1709,7 @@ static int gpi_create_i2c_tre(struct gchan *chan, str= uct gpi_desc *desc, tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_BEI); } =20 +log_tre: for (i =3D 0; i < tre_idx; i++) dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); @@ -1825,6 +1843,18 @@ gpi_prep_slave_sg(struct dma_chan *chan, struct scat= terlist *sgl, nr_tre =3D 2; if (direction =3D=3D DMA_DEV_TO_MEM) /* rx */ nr_tre =3D 1; + /* + * Recovery opcodes do not require DMA data TREs, only CONFIG + * (for set_config) and GO TREs. Since gpi_prep_slave_sg() is + * shared with SPI, verify the channel is I2C before accessing + * the configuration data. + */ + if (gchan->protocol =3D=3D QCOM_GPI_I2C) { + struct gpi_i2c_config *i2c =3D gchan->config; + + if (i2c->op =3D=3D I2C_BUS_CLEAR || i2c->op =3D=3D I2C_STOP_ON_BUS) + nr_tre =3D set_config ? 2 : 1; + } =20 /* calculate # of elements required & available */ nr =3D gpi_ring_num_elements_avail(ch_ring); diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-= dma.h index 332be28427e4..b9b75c302825 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -52,6 +52,8 @@ struct gpi_spi_config { enum i2c_op { I2C_WRITE =3D 1, I2C_READ, + I2C_BUS_CLEAR =3D 6, + I2C_STOP_ON_BUS, }; =20 /** --=20 2.34.1 From nobody Mon Sep 28 04:54:26 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B04A3D75D7 for ; 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Add bus recovery support using the I2C_BUS_CLEAR and I2C_STOP_ON_BUS hardware opcodes to restore the bus to an idle state. Check the SDA line state through SE_GENI_IOS.RX_DATA_IN and skip recovery when the bus is already free. Trigger recovery automatically from geni_i2c_xfer() on -EPROTO, -ETIMEDOUT and -EAGAIN (arbitration-lost) errors, and register the recovery callback through i2c_bus_recovery_info to allow recovery via i2c_recover_bus(). This adds bus recovery support for FIFO mode only. Signed-off-by: Aniket Randive --- drivers/i2c/busses/i2c-qcom-geni.c | 109 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 109 insertions(+) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 658636c1ee0e..9fa1a8ac400c 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -138,6 +138,7 @@ struct geni_i2c_dev { u32 num_msgs; struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config; const struct geni_i2c_desc *dev_data; + struct i2c_bus_recovery_info rinfo; }; =20 struct geni_i2c_err_log { @@ -956,6 +957,90 @@ static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2= c, return num; } =20 +static int geni_i2c_fifo_bus_cmd(struct geni_i2c_dev *gi2c, u32 cmd) +{ + unsigned long time_left; + unsigned long flags; + + /* + * Clear cur so the IRQ handler does not attempt FIFO watermark + * filling or draining while the recovery opcode is in flight. + * cur and err are shared with geni_i2c_irq(), which reads cur and + * writes err under gi2c->lock, so take the lock around this reset. + */ + spin_lock_irqsave(&gi2c->lock, flags); + gi2c->cur =3D NULL; + gi2c->err =3D 0; + spin_unlock_irqrestore(&gi2c->lock, flags); + geni_se_select_mode(&gi2c->se, GENI_SE_FIFO); + reinit_completion(&gi2c->done); + + geni_se_setup_m_cmd(&gi2c->se, cmd, 0); + time_left =3D wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); + if (!time_left) { + dev_err(gi2c->se.dev, "timeout waiting for bus cmd %u\n", cmd); + gi2c->abort_done =3D false; + geni_se_abort_m_cmd(&gi2c->se); + time_left =3D ABORT_TIMEOUT; + do { + time_left =3D wait_for_completion_timeout(&gi2c->done, time_left); + } while (!gi2c->abort_done && time_left); + + if (!time_left) + dev_err(gi2c->se.dev, "abort timed out for bus cmd %u\n", cmd); + + return -ETIMEDOUT; + } + + /* + * ARB_LOST and BUS_PROTO interrupts may be reported while the bus + * transitions from stuck to idle during the recovery sequence. + * The opcode completed successfully so treat these as success. + */ + if (gi2c->err =3D=3D -EAGAIN || gi2c->err =3D=3D -EPROTO) + return 0; + + return gi2c->err; +} + +static int geni_i2c_recover_bus(struct i2c_adapter *adap) +{ + struct geni_i2c_dev *gi2c =3D i2c_get_adapdata(adap); + int ret; + + ret =3D pm_runtime_get_sync(gi2c->se.dev); + if (ret < 0) { + dev_err(gi2c->se.dev, "bus recovery failed, error turning SE resources:%= d\n", ret); + pm_runtime_put_noidle(gi2c->se.dev); + return ret; + } + + /* SDA is high means bus is free */ + if (readl_relaxed(gi2c->se.base + SE_GENI_IOS) & RX_DATA_IN) { + pm_runtime_put_autosuspend(gi2c->se.dev); + return 0; + } + + ret =3D geni_i2c_fifo_bus_cmd(gi2c, I2C_BUS_CLEAR); + if (!ret) + ret =3D geni_i2c_fifo_bus_cmd(gi2c, I2C_STOP_ON_BUS); + + /* + * Recovery succeeds only once the slave releases SDA, so the bus + * state is the authority: RX_DATA_IN high means the bus is free, + * while a clean opcode status with SDA still low is a failed + * recovery. + */ + if (readl_relaxed(gi2c->se.base + SE_GENI_IOS) & RX_DATA_IN) + ret =3D 0; + else if (!ret) + ret =3D -EBUSY; + + pm_runtime_put_autosuspend(gi2c->se.dev); + + return ret; +} + static int geni_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) @@ -981,6 +1066,25 @@ static int geni_i2c_xfer(struct i2c_adapter *adap, else ret =3D geni_i2c_fifo_xfer(gi2c, msgs, num); =20 + if (!gi2c->gpi_mode && + (ret =3D=3D -EPROTO || ret =3D=3D -ETIMEDOUT || ret =3D=3D -EAGAIN)) { + /* + * Only attempt recovery if SDA is stuck low. -EPROTO and + * -ETIMEDOUT indicate bus errors where the target may be + * holding SDA low. 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Wed, 26 Aug 2026 02:51:47 -0700 (PDT) Received: from hu-arandive-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d8d208csm7249738eec.23.2026.08.26.02.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 02:51:46 -0700 (PDT) From: Aniket Randive Date: Wed, 26 Aug 2026 15:21:24 +0530 Subject: [PATCH v1 3/3] i2c: qcom-geni: Add bus recovery support for GPI DMA mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-i2c_bus_recovery-v1-3-203f0ec76f84@oss.qualcomm.com> References: <20260826-i2c_bus_recovery-v1-0-203f0ec76f84@oss.qualcomm.com> In-Reply-To: <20260826-i2c_bus_recovery-v1-0-203f0ec76f84@oss.qualcomm.com> To: Vinod Koul , Frank Li , Mukesh Kumar Savaliya , Viken Dadhaniya , Andi Shyti Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Aniket Randive X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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The GPI completion callback reports a NACK and a genuine bus error alike as -EIO, and the existing recovery path switches the SE to FIFO mode which is not valid in GPI DMA mode. Add bus recovery support using the I2C_BUS_CLEAR and I2C_STOP_ON_BUS opcodes issued via the GPI TX DMA channel. Guard the -EIO recovery trigger with a SE_GENI_IOS RX_DATA_IN check to skip recovery when SDA is already released. Extend the recovery callback to dispatch through the GPI DMA path when gi2c->gpi_mode is set. Signed-off-by: Aniket Randive --- drivers/i2c/busses/i2c-qcom-geni.c | 104 +++++++++++++++++++++++++++++++--= ---- 1 file changed, 88 insertions(+), 16 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 9fa1a8ac400c..85cb1367958c 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -34,8 +34,6 @@ #define I2C_READ 0x2 #define I2C_WRITE_READ 0x3 #define I2C_ADDR_ONLY 0x4 -#define I2C_BUS_CLEAR 0x6 -#define I2C_STOP_ON_BUS 0x7 /* M_CMD params for I2C */ #define PRE_CMD_DELAY BIT(0) #define TIMESTAMP_BEFORE BIT(1) @@ -1003,6 +1001,70 @@ static int geni_i2c_fifo_bus_cmd(struct geni_i2c_dev= *gi2c, u32 cmd) return gi2c->err; } =20 +static int geni_i2c_gpi_bus_cmd(struct geni_i2c_dev *gi2c, enum i2c_op cmd) +{ + const struct geni_i2c_clk_fld *itr =3D gi2c->clk_fld; + struct dma_async_tx_descriptor *desc; + struct gpi_i2c_config peripheral =3D {}; + struct dma_slave_config config =3D {}; + unsigned long time_left; + unsigned long flags; + dma_cookie_t cookie; + + config.peripheral_config =3D &peripheral; + config.peripheral_size =3D sizeof(peripheral); + + peripheral.set_config =3D 1; + peripheral.pack_enable =3D I2C_PACK_TX | I2C_PACK_RX; + peripheral.cycle_count =3D itr->t_cycle_cnt; + peripheral.high_count =3D itr->t_high_cnt; + peripheral.low_count =3D itr->t_low_cnt; + peripheral.clk_div =3D itr->clk_div; + peripheral.op =3D cmd; + + if (dmaengine_slave_config(gi2c->tx_c, &config)) { + dev_err(gi2c->se.dev, "dma config error for bus cmd %u\n", cmd); + return -EIO; + } + + desc =3D dmaengine_prep_slave_single(gi2c->tx_c, 0, 0, DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc) + return -EIO; + + desc->callback_result =3D i2c_gpi_cb_result; + desc->callback_param =3D gi2c; + + cookie =3D dmaengine_submit(desc); + if (dma_submit_error(cookie)) + return -EIO; + + /* + * cur and err are shared with geni_i2c_irq() and the GPI callback + * i2c_gpi_cb_result(); both write err (the IRQ handler under + * gi2c->lock). Reset them under the lock before issuing the transfer. + */ + spin_lock_irqsave(&gi2c->lock, flags); + gi2c->cur =3D NULL; + gi2c->err =3D 0; + spin_unlock_irqrestore(&gi2c->lock, flags); + reinit_completion(&gi2c->done); + dma_async_issue_pending(gi2c->tx_c); + + time_left =3D wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); + if (!time_left) { + dev_err(gi2c->se.dev, "timeout waiting for GPI bus cmd %u\n", cmd); + dmaengine_terminate_sync(gi2c->tx_c); + return -ETIMEDOUT; + } + + /* ARB_LOST and BUS_PROTO may be expected during recovery; treat as succe= ss */ + if (gi2c->err =3D=3D -EAGAIN || gi2c->err =3D=3D -EPROTO) + return 0; + + return gi2c->err; +} + static int geni_i2c_recover_bus(struct i2c_adapter *adap) { struct geni_i2c_dev *gi2c =3D i2c_get_adapdata(adap); @@ -1021,15 +1083,23 @@ static int geni_i2c_recover_bus(struct i2c_adapter = *adap) return 0; } =20 - ret =3D geni_i2c_fifo_bus_cmd(gi2c, I2C_BUS_CLEAR); - if (!ret) - ret =3D geni_i2c_fifo_bus_cmd(gi2c, I2C_STOP_ON_BUS); + if (gi2c->gpi_mode) { + ret =3D geni_i2c_gpi_bus_cmd(gi2c, I2C_BUS_CLEAR); + if (ret) + dev_dbg(gi2c->se.dev, "GPI bus clear returned %d, issuing stop anyway\n= ", + ret); + + ret =3D geni_i2c_gpi_bus_cmd(gi2c, I2C_STOP_ON_BUS); + } else { + ret =3D geni_i2c_fifo_bus_cmd(gi2c, I2C_BUS_CLEAR); + if (!ret) + ret =3D geni_i2c_fifo_bus_cmd(gi2c, I2C_STOP_ON_BUS); + } =20 /* - * Recovery succeeds only once the slave releases SDA, so the bus - * state is the authority: RX_DATA_IN high means the bus is free, - * while a clean opcode status with SDA still low is a failed - * recovery. + * Recovery succeeds when SDA is released. RX_DATA_IN high means the + * bus is free; trust this over the opcode return path, which cannot + * flag a benign recovery event in GPI mode. */ if (readl_relaxed(gi2c->se.base + SE_GENI_IOS) & RX_DATA_IN) ret =3D 0; @@ -1066,14 +1136,18 @@ static int geni_i2c_xfer(struct i2c_adapter *adap, else ret =3D geni_i2c_fifo_xfer(gi2c, msgs, num); =20 - if (!gi2c->gpi_mode && - (ret =3D=3D -EPROTO || ret =3D=3D -ETIMEDOUT || ret =3D=3D -EAGAIN)) { + if (ret =3D=3D -EPROTO || ret =3D=3D -ETIMEDOUT || ret =3D=3D -EAGAIN || + (gi2c->gpi_mode && ret =3D=3D -EIO)) { /* * Only attempt recovery if SDA is stuck low. -EPROTO and * -ETIMEDOUT indicate bus errors where the target may be * holding SDA low. ARB_LOST (-EAGAIN) on a single-controller * bus indicates a stuck target, not a real arbitration loss. - * GPI DMA mode extends this trigger separately. + * In GPI DMA mode the completion callback reports NACK, + * BUS_PROTO and ARB_LOST alike as -EIO, so the SE_GENI_IOS + * RX_DATA_IN check below is what distinguishes a genuinely + * stuck bus from a benign NACK: a NACK leaves SDA released + * (high) after the STOP, so recovery is skipped. */ if (!(readl_relaxed(gi2c->se.base + SE_GENI_IOS) & RX_DATA_IN)) { int recovery_ret =3D i2c_recover_bus(adap); @@ -1292,10 +1366,8 @@ static int geni_i2c_probe(struct platform_device *pd= ev) if (ret < 0) return ret; =20 - if (!gi2c->gpi_mode) { - gi2c->rinfo.recover_bus =3D geni_i2c_recover_bus; - gi2c->adap.bus_recovery_info =3D &gi2c->rinfo; - } + gi2c->rinfo.recover_bus =3D geni_i2c_recover_bus; + gi2c->adap.bus_recovery_info =3D &gi2c->rinfo; =20 ret =3D i2c_add_adapter(&gi2c->adap); if (ret) --=20 2.34.1