From nobody Mon Sep 28 05:51:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65682231C91; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787701498; cv=none; b=JGg2JkseC7l/e6VDWjP5YfXIsEuq0KF9VIOFU2fW8FgV4iVOEws+LQG6Tcsvofu6bkp/xZYVo17oU+v70ewv3vZrd2jtrk8CKly6hliCU6+xbW0/pqlHAl9+MikMzMQ7ID14ckIiIfpS2edfXXrXNo8ddExLDiOKNWj72khVmKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787701498; c=relaxed/simple; bh=D3bIYSjqgfPZznmN5ArMF1O8eQyv1W/Tut4eY/ZuxD8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fwTIYR1yx+bhr25ekg/kPr7aFUv6vUnE2Su772fXvAf7d0/cjIIuKMqriq0U3RvcLctV2gF7nBlWl73Jh/mXt3sreLbQsdr1pL0cYxdiGOTWnDQj2jyHFUSyOyCZeWZVx0Pv21Ek01MlDJZtsQT7XMq64aKJbo+3gIvSZDeqH8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LvCZqh84; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LvCZqh84" Received: by smtp.kernel.org (Postfix) with ESMTPS id 09A8AC2BCC7; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787701498; bh=D3bIYSjqgfPZznmN5ArMF1O8eQyv1W/Tut4eY/ZuxD8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=LvCZqh843FXSlb8d28w0Kcd06hVoO+M5vtBaZmQN5aP6u20mN/ClQuHw3M16m1xKO ePEtuxybWfqr4FaBJmQV6Eyyxx1QdgbcQ6JqvSnf7K32k+DNOGwWcmtl78/OBRq6Mp RaHywVvoHUqD83pw2eZ3uZm2CgHhMzq6pHBmUuqqZC54cMTXgAKx+eWnynUh8n238V hGKOc07BUi4b8mVanepwgFMqWyyLOdAnMrKKH3waJje/hmuLnARZKpGPHJqKnAcvxM ucGPesm+jPTumCmzhpvgK1ijakYhM1zyx/RwHH3Fossx8ouySycPj2eGiVO4W47lLW d1B3QIBv+mwqQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9818C61DBD; Tue, 25 Aug 2026 23:44:57 +0000 (UTC) From: Antonin Malzieu Ridolfi via B4 Relay Date: Wed, 26 Aug 2026 01:44:18 +0200 Subject: [PATCH 1/4] gpu: nova-core: Extract PFSP register definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-1-38351df09084@nanonej.com> References: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-0-38351df09084@nanonej.com> In-Reply-To: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-0-38351df09084@nanonej.com> To: Danilo Krummrich , Alice Ryhl , Alexandre Courbot , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, Antonin Malzieu Ridolfi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4995; i=dev@nanonej.com; h=from:subject:message-id; bh=wqNRbUL7XMnvvIqxJx4lZ57luQxlOACegl3jQUnJo0o=; b=owEBbQKS/ZANAwAKAWaH8SMKFRX9AcsmYgBqjij3/dpP0vSUEuzwVXkj3C1sJoZi6XZeb/ZGM OCfZJkiOaGJAjMEAAEKAB0WIQSDtk+wfJEhL1KFIn1mh/EjChUV/QUCao4o9wAKCRBmh/EjChUV /QujEACUpjPN4T/0y6QabTddhhrPY3GIQtRQpv0+HN4RPeq16VPwC4JLyL45LFZ2Tf+mPfpVfcO mpQ/fGGXe0UE+C5OtAU1hYuGyARph/n1h5xBJIRlnP91ljwV3NkvblH1ZWq3WFozKLJkkTRmg0K 3NrELsRpSo3V4gLPQqSbAn8PDKm5FLwz0f6XC8ZbkhvudLuZL4o6W3RxFEUVNaDC3oez9yh5VY7 +xathCm9aKa4y2nOkIRkX00HqOc/V2xLTzJX5H7Vp35iSLlOna5q32IMzvHFEK0uW8KACt6BC5Y LJjU9gkkqiQ3uDvqZqPbTAh8y0NzrJUSf2TxuW//0NGWrWnITkmqDweKv924Q53SkaNHI0VcbA9 Vo8PqGCtff23ER8NbhbywV0DBPdmEVfwxiomAoMGAqq6eox9GFjG540U5l5neTpfOCepQDM/Eih AZughzwPP2XqgjUGhExIA9uxxtvxIHXuHxI44gc6b8rTocAr1LZrBuGYuXLte/3xAiEB8sl8AcW 8S0+kRccxjLppHaPhzm8k7XrYCqBJ82jDmi0maMZDbFlB6HpP7vvCL1l/hJnve5WCd9HzKzEsYx Ny8Lp3s9tySKp/Skfi8FIV+4tvHB0T346DV2QMiVTX5gxPh1IxflowskziXLmunxExRlIx2QpYh qiQBUR0HPYKiYIQ== X-Developer-Key: i=dev@nanonej.com; a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Move PFSP register definitions from the root regs.rs file into the falcon module that own them, in the new falcon/regs.rs file. This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS and PMC registers: register definitions move to the module that interprets their service, visibility changes to pub(super). Since PFALCON registers are defined in the root regs.rs but are also part of the falcon interface, accessed by the whole falcon module. They are re-exported in falcon/regs.rs so falcon code can use a single regs:: prefix. Once the PFALCON family moves out of the root module, these re-exports will become plain definitions. Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon.rs | 4 ++-- drivers/gpu/nova-core/falcon/fsp.rs | 6 +++--- drivers/gpu/nova-core/falcon/regs.rs | 39 ++++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/regs.rs | 21 ------------------- 4 files changed, 44 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 11c1008b7d1e..68658a6e666c 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -32,13 +32,13 @@ num::{ self, FromSafeCast, // - }, - regs, + }, // }; =20 pub(crate) mod fsp; pub(crate) mod gsp; mod hal; +mod regs; pub(crate) mod sec2; =20 /// Alignment (in bytes) of falcon memory blocks. diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index 0437180b8829..c2bc61ecc07c 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -23,13 +23,13 @@ =20 use crate::{ falcon::{ + regs, // Falcon, FalconEngine, PFalcon2Base, - PFalconBase, // + PFalconBase, }, - num, - regs, // + num, // }; =20 /// FSP message timeout in milliseconds. diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs new file mode 100644 index 000000000000..96e1f0f1df5a --- /dev/null +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::io::register; + +// FSP (Foundation Security Processor) queue registers for Hopper/Blackwel= l Chain of Trust. +// These registers manage falcon EMEM communication queues. + +register! { + pub(super) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { + 31:0 address =3D> u32; + } + + pub(super) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { + 31:0 address =3D> u32; + } + + pub(super) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { + 31:0 val =3D> u32; + } + + pub(super) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { + 31:0 val =3D> u32; + } +} + +// PFALCON registers are defined in the root `regs.rs` but are part of the= falcon +// interface, accessed by the whole falcon module. They are re-exported he= re so +// falcon code can use a single `regs::` prefix. +// Once the PFALCON family moves out of the root module, these re-exports = become +// plain definitions. +pub(super) use crate::regs::{ + NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON= _CPUCTL_ALIAS, + NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FAL= CON_DMATRFBASE1, + NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCO= N_FALCON_DMATRFMOFFS, + NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EM= EMC, + NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IM= EMD, + NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON= _MAILBOX1, + NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PF= ALCON_FBIF_TRANSCFG, +}; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 3422b49df7a7..0404fb82aa7e 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -359,27 +359,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 -// FSP (Foundation Security Processor) queue registers for Hopper/Blackwel= l Chain of Trust. -// These registers manage falcon EMEM communication queues. - -register! { - pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { - 31:0 address =3D> u32; - } - - pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { - 31:0 address =3D> u32; - } - - pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { - 31:0 val =3D> u32; - } - - pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { - 31:0 val =3D> u32; - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.55.0 From nobody Mon Sep 28 05:51:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 657183F20F4; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787701498; cv=none; b=cF4OD49VND7ojZca56z/FDAMRjGK3j4oi4K02NOZ2ExJHLQH7fxkRwZkUT3HEbs5shMrwLrpyGvK+RA5E5/0GtU5psczz7JYbBkaxEb0in8zkTO3/hq9oQ9yv3XAxeoep6pxT826gemY49p79kslsSwescci5Deg3GMQZ1V66Zw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787701498; c=relaxed/simple; bh=+SG7MQ6dj2q9A59lleV8xmfVK6vHOA9hYyn78jLb98I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bAeQG4d5SBMfMP1lSO0yF9pu4ct7tTTqrglU0VqapdWlI5imtsGKaZMqTTbeqfdNLnhvH4zztUDVNv5kjc3qcpwmrRA8SHKHZlcUPQ4nH9JtLVSI/zUAD85lHHdwBNcpBkM2uJqrnvkCiWFf01r5rGVfnWvaeKf6UAGevdSbGIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EHxnvV3f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EHxnvV3f" Received: by smtp.kernel.org (Postfix) with ESMTPS id 24607C2BCF6; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787701498; bh=+SG7MQ6dj2q9A59lleV8xmfVK6vHOA9hYyn78jLb98I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EHxnvV3f4vvI4h4iiIbASHVQiLamRo7ZNlEXyJzdSz6qVSVj/w1dD+0Da+jBrXKPl GuXQfOMrubwzgkU6ibifvLO8DWnBInjTz7+jciNZtxqCv9xoYBsjOzYd0i9nOuBeBH O1foV7qgO1xpjjOXUoMBCXhvXrcA6njag3resjjdae2L/+cKeZFSmsXEhpkaWr+X44 NfyNDUDLyOJH+AMkkZX6oUo6WnCGrZIU+ZJaTjfVvgE7O2Do4uj3Y4K/Jfsw3oCiXR YFoYBx79HOZ7MMFtQXevVQU1oAX9PmDhXkgmitzkEkf0fUaHHT8chj8m5QIM9owuhO Ieku/7ZMIp+0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03AC8C61DB9; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) From: Antonin Malzieu Ridolfi via B4 Relay Date: Wed, 26 Aug 2026 01:44:19 +0200 Subject: [PATCH 2/4] gpu: nova-core: falcon: Extract PRISCV register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-2-38351df09084@nanonej.com> References: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-0-38351df09084@nanonej.com> In-Reply-To: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-0-38351df09084@nanonej.com> To: Danilo Krummrich , Alice Ryhl , Alexandre Courbot , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, Antonin Malzieu Ridolfi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7318; i=dev@nanonej.com; h=from:subject:message-id; bh=bX0B3Voxms/whW42qQyonw4PJ52AO9nzIiHe/Qc+KFY=; b=owEBbQKS/ZANAwAKAWaH8SMKFRX9AcsmYgBqjij4TocfUQf7uDpWfkaD9KGQetyuehQkIzWLZ Z9xRYBZ/y2JAjMEAAEKAB0WIQSDtk+wfJEhL1KFIn1mh/EjChUV/QUCao4o+AAKCRBmh/EjChUV /VfjD/9FvSjEirtIPPEje0SBiUKJpDtcs70n754oeVdCXT6YiVTQ0MhpKr4TbcedDXvXDCYVYG2 6xDMAcSwAwyixCveysiCGKLFRvQxLSaFSBiw2te1uMWE6tUcMR+i3okTNssRljAVLHZkpgvLHSP O7oy4Rs26o0+eVRS5g1my2zOxEK6zU+Hv6e8RGjB9vRTSMZMx8VV6NtU8vm+JjCpfdVFKlDpzX7 fPovjo1QmHfJDsZGNrDbXPzazpUMN3/if6nerepWQ2xCl09Zaw8Rzlr+1o+4FyK4+axsBPO3XZS +cZdvERcygtF0Hv00ifA/qkTQl4pjrL5YI1V4GrN1UOANzgJQFzRo0UDZOOOt9PwDGX8xAS+Im8 9t+Yfa7i2rKI+cGTZIstKcLM9C/Xd29tSdIIaKJQgwyXLTQfqd95XtDXa0OCC4jw7ZRWdab1VYA 6gizyCXJHZ70zfQ771Zqre7E0PfvkFRVCWSh/HLOrmOCuCQiyEQteU1VIalP9NkGeBhUqdPcaJp G7QYThoku0FGZHqt9JF9fvEa1IfBKyl1Yz0eiQ5ywxRucdrl5SgkZl5xkBuQs28EFbMU41zdYH0 BMf/BMnO6WKYN6nUMBF9ldVvhRar7peTeFGU0RjXhXmAHIMgxcAagZ1VHLgQbOHjG+aIzLWcZOM uDzvXxsZqPKPLZg== X-Developer-Key: i=dev@nanonej.com; a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Move PRISCV register definitions from the root regs.rs file into the falcon module that own them, in the existing falcon/regs.rs file. This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS, PMC and PFSP registers: register definitions move to the module that interprets their service, visibility changes to pub(super). Since PFALCON, PFALCON2 and FUSE registers are defined in the root regs.rs but are also part of the falcon interface, accessed by the whole falcon module. They are re-exported in falcon/regs.rs so falcon code can use a single regs:: prefix. Once these families moves out of the root module, these re-exports will become plain definitions. Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon/hal/ga102.rs | 4 +-- drivers/gpu/nova-core/falcon/hal/tu102.rs | 12 +++---- drivers/gpu/nova-core/falcon/regs.rs | 56 +++++++++++++++++++++++++--= ---- drivers/gpu/nova-core/regs.rs | 27 +-------------- 4 files changed, 53 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-c= ore/falcon/hal/ga102.rs index 7600ee07ca2e..7586f80388b0 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -20,13 +20,13 @@ driver::Bar0, falcon::{ hal::LoadMethod, + regs, // Falcon, FalconBromParams, FalconEngine, FalconModSelAlgo, - PeregrineCoreSelect, // + PeregrineCoreSelect, }, - regs, }; =20 use super::FalconHal; diff --git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-c= ore/falcon/hal/tu102.rs index 5291598fedf7..fb624b925f49 100644 --- a/drivers/gpu/nova-core/falcon/hal/tu102.rs +++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs @@ -12,14 +12,12 @@ time::Delta, // }; =20 -use crate::{ - falcon::{ - hal::LoadMethod, - Falcon, - FalconBromParams, - FalconEngine, // - }, +use crate::falcon::{ + hal::LoadMethod, regs, // + Falcon, + FalconBromParams, + FalconEngine, }; =20 use super::FalconHal; diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs index 96e1f0f1df5a..a9e1f75598dd 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -2,6 +2,35 @@ =20 use kernel::io::register; =20 +use crate::falcon::{ + PFalcon2Base, + PeregrineCoreSelect, // +}; + +// PRISCV + +register! { + /// RISC-V status register for debug (Turing and GA100 only). + /// Reflects current RISC-V core status. + pub(super) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Bas= e + 0x00000240 { + /// RISC-V core active/inactive status. + 0:0 active_stat =3D> bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { + 7:7 active_stat =3D> bool; + 4:4 halted =3D> bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { + 8:8 br_fetch =3D> bool; + 4:4 core_select =3D> PeregrineCoreSelect; + 0:0 valid =3D> bool; + } +} + // FSP (Foundation Security Processor) queue registers for Hopper/Blackwel= l Chain of Trust. // These registers manage falcon EMEM communication queues. =20 @@ -23,17 +52,22 @@ } } =20 -// PFALCON registers are defined in the root `regs.rs` but are part of the= falcon -// interface, accessed by the whole falcon module. They are re-exported he= re so -// falcon code can use a single `regs::` prefix. -// Once the PFALCON family moves out of the root module, these re-exports = become +// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` = but +// are part of the falcon interface, accessed by the whole falcon module. = They +// are re-exported here so falcon code can use a single `regs::` prefix. +// Once these families move out of the root module, these re-exports become // plain definitions. pub(super) use crate::regs::{ - NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON= _CPUCTL_ALIAS, - NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FAL= CON_DMATRFBASE1, - NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCO= N_FALCON_DMATRFMOFFS, - NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EM= EMC, - NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IM= EMD, - NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON= _MAILBOX1, - NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PF= ALCON_FBIF_TRANSCFG, + NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSI= ON, + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, + NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMA= SK, + NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALC= ON_FALCON_BOOTVEC, + NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_F= ALCON_DMACTL, + NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCO= N_FALCON_DMATRFCMD, + NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFAL= CON_FALCON_DMEMC, + NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EM= EMD, + NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_= IMEMC, + NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MA= ILBOX0, + NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM= , NV_PFALCON_FBIF_CTL, + NV_PFALCON_FBIF_TRANSCFG, }; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0404fb82aa7e..5c1cef1c66a1 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -24,8 +24,7 @@ FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, - PFalconBase, - PeregrineCoreSelect, // + PFalconBase, // }, }; =20 @@ -335,30 +334,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 -// PRISCV - -register! { - /// RISC-V status register for debug (Turing and GA100 only). - /// Reflects current RISC-V core status. - pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Bas= e + 0x00000240 { - /// RISC-V core active/inactive status. - 0:0 active_stat =3D> bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { - 7:7 active_stat =3D> bool; - 4:4 halted =3D> bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { - 8:8 br_fetch =3D> bool; - 4:4 core_select =3D> PeregrineCoreSelect; - 0:0 valid =3D> bool; - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.55.0 From nobody Mon Sep 28 05:51:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 657B0488210; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787701498; cv=none; b=BetMCXewiBcCBtmmSpTTm37mXoKbvu9A6Vyq2ZYbAbSKQPjn4o2GiCCubmJX5bJh6Z5tFALVaTLVVt0Tr/xKfGaUd/bMENYfcqojp67ByxLklfrECLQLejseutPmXp6xBPWqcn4DeG9vyIlfofF/9PHF9xEFCDaPABADxOpKVWg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787701498; c=relaxed/simple; bh=t1t28+oq4vInabn8KtnubXPRvys01xfCsPHSy8FPoPU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=P71nN3ArAid8eCy+0VQD4adimPC//X1rgZvF8u3EVUP3I+W9De1jYP8c9ykFU+Ovcy+o9BNs63KYtjzvX6mosY6AlnDr9PLzS/f54TLSdgelK3n/sRvBwAwUU37zJZamSdFbH9AVlbmmB6enoUcdeZByboW12IGxTtOtIUbtE+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OF/MnDcv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OF/MnDcv" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2D178C2BCFB; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787701498; bh=t1t28+oq4vInabn8KtnubXPRvys01xfCsPHSy8FPoPU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OF/MnDcvb44kN1XUMBcSgsH+6orrOdON8YwtcHYyAskbgmVDsizDnhHXBEfD3Rr3J zIofpV8mvHuwedJKOBVCr/blBeRh1WSQVuNNTg0m3Ptavteb/6NjHEE9/YzxxGwL4u uM4y6w3BKtCWyplVPxYBwukQGiPdcCqKEDep+wxnyfJcdY+VKgYm5eAZEsy6vgzy8N f8tr1243jfgkSeKNYn+/p/RbsqVsRHv8SD7SPXfpx5B0OZPlPdlijPX3rW5xlEJKYr edg4busIcmBdVZwjlYxZnUK8DItXPjv7QlI7qbVl8NQ1SmmXUSauE51VQD5WXc1VwV XNWCv48d7Pz2g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A1F4C61DC7; Tue, 25 Aug 2026 23:44:58 +0000 (UTC) From: Antonin Malzieu Ridolfi via B4 Relay Date: Wed, 26 Aug 2026 01:44:20 +0200 Subject: [PATCH 3/4] gpu: nova-core: falcon: Extract PFALCON2 register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-3-38351df09084@nanonej.com> References: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-0-38351df09084@nanonej.com> In-Reply-To: <20260826-b4-extract-pfsp-registers-to-falcon-mod-v1-0-38351df09084@nanonej.com> To: Danilo Krummrich , Alice Ryhl , Alexandre Courbot , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, Antonin Malzieu Ridolfi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5391; i=dev@nanonej.com; h=from:subject:message-id; bh=+5srcIuDrPHxo7RqYT2/oVgDi4LJMOur/dkzKD5zi7M=; b=kA0DAAoBZofxIwoVFf0ByyZiAGqOKPigEFX4gzYbkVNU+kiYbYKv5cNg0JbSBYH7AAanev+ut okCMwQAAQoAHRYhBIO2T7B8kSEvUoUifWaH8SMKFRX9BQJqjij4AAoJEGaH8SMKFRX9zRMP/1Oq 7PlxuHne//KCaYihnEfDK1WssNGU3vxB8hN0vsxVW3GgZUEcIEQWiENMppW5RZQDVWSl3iCzSJN kYEM+dy1hWVkC3l9siEh8oaRVK8pzBuCkijWCgPhSl2ga0TeqQn28/gPNixfd4F3BSd8VClJ677 4zMI3PSLi7yyxFsDuu+HEWLVOi3JmzhtAJYdjcK9c8I7LQela5nWRzW4PmOQF2Z5pzHUj1qsZlL wmxmkDrrM2z9xTkhRONAufvIi7qRb70fFYeOURtqzvTbVQ9o2rStDH7+1yY6tck0JDEV+A0FThy lGS8bXJhUhl/SdT7ZmhxJkIvc8SMv1AVSGs/kr0CC8a4+7DFUZIEHxntA6BoGhoxlSopyY6o65D hHwzuGBV2V+a7sBQEMArY/UqQ6chSrRfDAVHJpxlJ+8yR3gIDipaLEHdlkUOkilFXWVSoiOQZ0B 0eiGTbqanMlS0wudrUUKZh5j31NPdJMOPF+MESBgbL/FXPQkajeS8cMQp2IJs38aFS1uYZYCo2L JNix5UPxrXXABiDWsEcDazYhJ34/2AStRbYfVn01QP4A2qvYx+4XcewsQpkYtPwr/dbxfWTsgz8 sIfNvwyBekDPMlil1pZ7uA9D17hKt5hK/oSbgRAmq+GUzk1BdYrHma6d4iDXNJdJED6Wt3BrN5m XRhO+ X-Developer-Key: i=dev@nanonej.com; a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Move PFALCON2 register definitions from the root regs.rs file into the falcon module that own them, in the existing falcon/regs.rs file. This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS, PMC, PFSP and PRISCV registers: register definitions move to the module that interprets their service, visibility changes to pub(super). Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon.rs | 4 ++-- drivers/gpu/nova-core/falcon/regs.rs | 31 ++++++++++++++++++++++++++----- drivers/gpu/nova-core/regs.rs | 24 ------------------------ 3 files changed, 28 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 68658a6e666c..11613a2ccb69 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -95,8 +95,8 @@ pub(crate) enum FalconSecurityModel with TryFrom> { =20 bounded_enum! { /// Signing algorithm for a given firmware, used in the - /// [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed= to the Falcon Boot ROM - /// (BROM) as a parameter. + /// [`crate::falcon::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It i= s passed to the Falcon + /// Boot ROM (BROM) as a parameter. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconModSelAlgo with TryFrom> { /// AES. diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs index a9e1f75598dd..446a67bdf3dd 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -3,10 +3,33 @@ use kernel::io::register; =20 use crate::falcon::{ + FalconModSelAlgo, PFalcon2Base, PeregrineCoreSelect, // }; =20 +// PFALCON2 + +register! { + pub(super) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180= { + 7:0 algo ?=3D> FalconModSelAlgo; + } + + pub(super) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base += 0x00000198 { + 7:0 ucode_id =3D> u8; + } + + pub(super) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0= 000019c { + 31:0 value =3D> u32; + } + + /// OpenRM defines this as a register array, but doesn't specify its s= ize and only uses its + /// first element. Be conservative until we know the actual size or ne= ed to use more registers. + pub(super) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0= x00000210 { + 31:0 value =3D> u32; + } +} + // PRISCV =20 register! { @@ -52,16 +75,14 @@ } } =20 -// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` = but -// are part of the falcon interface, accessed by the whole falcon module. = They +// PFALCON and FUSE registers are defined in the root `regs.rs` but are +// part of the falcon interface, accessed by the whole falcon module. They // are re-exported here so falcon code can use a single `regs::` prefix. // Once these families move out of the root module, these re-exports become // plain definitions. pub(super) use crate::regs::{ NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSI= ON, - NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, - NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMA= SK, - NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALC= ON_FALCON_BOOTVEC, + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, NV_PFALCON_= FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_F= ALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCO= N_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFAL= CON_FALCON_DMEMC, diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 5c1cef1c66a1..c9eca3ff911f 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -21,9 +21,7 @@ FalconFbifMemType, FalconFbifTarget, FalconMem, - FalconModSelAlgo, FalconSecurityModel, - PFalcon2Base, PFalconBase, // }, }; @@ -312,28 +310,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 -/* PFALCON2 */ - -register! { - pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180= { - 7:0 algo ?=3D> FalconModSelAlgo; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base += 0x00000198 { - 7:0 ucode_id =3D> u8; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0= 000019c { - 31:0 value =3D> u32; - } - - /// OpenRM defines this as a register array, but doesn't specify its s= ize and only uses its - /// first element. Be conservative until we know the actual size or ne= ed to use more registers. - pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0= x00000210 { - 31:0 value =3D> u32; - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. 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This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS, PMC, PFSP, PRISCV and PFALCON2 registers: register definitions move to the module that interprets their service, visibility changes to pub(super). The firmware module still needs to configure the FBIF DMA index used by the bootloader to fetch the FWSEC firmware from system memory, so the falcon module now exposes a `set_fbif_transcfg_regs_at()` helper to access the `NV_PFALCON_FBIF_TRANSCFG` register. Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon.rs | 30 ++- drivers/gpu/nova-core/falcon/gsp.rs | 16 +- drivers/gpu/nova-core/falcon/regs.rs | 248 +++++++++++++++++= ++-- drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 22 +- drivers/gpu/nova-core/gsp/hal/tu102.rs | 7 +- drivers/gpu/nova-core/regs.rs | 225 +----------------= -- 6 files changed, 263 insertions(+), 285 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 11613a2ccb69..d2ee9876bafb 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -45,8 +45,8 @@ pub(crate) const MEM_BLOCK_ALIGNMENT: usize =3D 256; =20 bounded_enum! { - /// Revision number of a falcon core, used in the [`crate::regs::NV_PF= ALCON_FALCON_HWCFG1`] - /// register. + /// Revision number of a falcon core, used in the + /// [`crate::falcon::regs::NV_PFALCON_FALCON_HWCFG1`] register. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconCoreRev with TryFrom> { Rev1 =3D 1, @@ -61,7 +61,7 @@ pub(crate) enum FalconCoreRev with TryFrom> { =20 bounded_enum! { /// Revision subversion number of a falcon core, used in the - /// [`crate::regs::NV_PFALCON_FALCON_HWCFG1`] register. + /// [`crate::falcon::regs::NV_PFALCON_FALCON_HWCFG1`] register. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconCoreRevSubversion with From> { Subversion0 =3D 0, @@ -107,8 +107,8 @@ pub(crate) enum FalconModSelAlgo with TryFrom> { } =20 bounded_enum! { - /// Valid values for the `size` field of the [`crate::regs::NV_PFALCON= _FALCON_DMATRFCMD`] - /// register. + /// Valid values for the `size` field of the + /// [`crate::falcon::regs::NV_PFALCON_FALCON_DMATRFCMD`] register. #[derive(Debug, Copy, Clone)] pub(crate) enum DmaTrfCmdSize with TryFrom> { /// 256 bytes transfer. @@ -592,6 +592,20 @@ fn dma_wr( Ok(()) } =20 + // Configure DMA index for the bootloader to fetch the FWSEC firmware = from system memory. + pub(crate) fn set_fbif_transcfg_regs_at(&self, ctx_dma: u32) -> Result= { + self.bar.update( + regs::NV_PFALCON_FBIF_TRANSCFG::of::() + .try_at(usize::from_safe_cast(ctx_dma)) + .ok_or(EINVAL)?, + |v| { + v.with_target(FalconFbifTarget::CoherentSysmem) + .with_mem_type(FalconFbifMemType::Physical) + }, + ); + Ok(()) + } + /// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the= falcon to run it. fn dma_load + FalconDmaLoadable>(&self= , fw: &F) -> Result { // DMA object with firmware content as the source of the DMA engin= e. @@ -614,11 +628,7 @@ fn dma_load + FalconDm= aLoadable>(&self, fw: &F) -> }; =20 self.dma_reset(); - self.bar - .update(regs::NV_PFALCON_FBIF_TRANSCFG::of::().at(0), |v| { - v.with_target(FalconFbifTarget::CoherentSysmem) - .with_mem_type(FalconFbifMemType::Physical) - }); + self.set_fbif_transcfg_regs_at(0)?; =20 self.dma_wr(&dma_obj, FalconMem::ImemSecure, fw.imem_sec_load_para= ms())?; self.dma_wr(&dma_obj, FalconMem::Dmem, fw.dmem_load_params())?; diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/fa= lcon/gsp.rs index ae32f401aeb0..fec13f5e99f4 100644 --- a/drivers/gpu/nova-core/falcon/gsp.rs +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -7,20 +7,18 @@ RegisterBase, WithBase, // }, - Io, + Io, // }, prelude::*, time::Delta, // }; =20 -use crate::{ - falcon::{ - Falcon, - FalconEngine, - PFalcon2Base, - PFalconBase, // - }, +use crate::falcon::{ regs, + Falcon, + FalconEngine, + PFalcon2Base, + PFalconBase, // }; =20 /// Type specifying the `Gsp` falcon engine. Cannot be instantiated. @@ -49,7 +47,7 @@ pub(crate) fn clear_swgen0_intr(&self) { /// Checks if GSP reload/resume has completed during the boot process. pub(crate) fn check_reload_completed(&self, timeout: Delta) -> Result<= bool> { read_poll_timeout( - || Ok(self.bar.read(regs::NV_PGC6_BSI_SECURE_SCRATCH_14)), + || Ok(self.bar.read(crate::regs::NV_PGC6_BSI_SECURE_SCRATCH_14= )), |val| val.boot_stage_3_handoff(), Delta::ZERO, timeout, diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs index 446a67bdf3dd..8e82d9f439a9 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -1,13 +1,233 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use kernel::io::register; +use kernel::{ + io::{ + register, + register::WithBase, + Io, // + }, + time, // +}; =20 -use crate::falcon::{ - FalconModSelAlgo, - PFalcon2Base, - PeregrineCoreSelect, // +use crate::{ + driver::Bar0, + falcon::{ + DmaTrfCmdSize, + FalconCoreRev, + FalconCoreRevSubversion, + FalconEngine, + FalconFbifMemType, + FalconFbifTarget, + FalconMem, + FalconModSelAlgo, + FalconSecurityModel, + PFalcon2Base, + PFalconBase, + PeregrineCoreSelect, // + }, }; =20 +// PFALCON + +register! { + pub(super) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 { + 6:6 swgen0 =3D> bool; + 4:4 halt =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_MAILBOX1(u32) @ PFalconBase + 0x00000044 { + 31:0 value =3D> u32; + } + + /// Used to store version information about the firmware running + /// on the Falcon processor. + pub(super) NV_PFALCON_FALCON_OS(u32) @ PFalconBase + 0x00000080 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_RM(u32) @ PFalconBase + 0x00000084 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 { + /// Signal indicating that reset is completed (GA102+). + 31:31 reset_ready =3D> bool; + /// RISC-V branch privilege lockdown bit. + 13:13 riscv_br_priv_lockdown =3D> bool; + /// Set to 0 after memory scrubbing is completed. + 12:12 mem_scrubbing =3D> bool; + 10:10 riscv =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_CPUCTL(u32) @ PFalconBase + 0x00000100 { + 6:6 alias_en =3D> bool; + 4:4 halted =3D> bool; + 1:1 startcpu =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_BOOTVEC(u32) @ PFalconBase + 0x00000104 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_DMACTL(u32) @ PFalconBase + 0x0000010c { + 7:7 secure_stat =3D> bool; + 6:3 dmaq_num; + 2:2 imem_scrubbing =3D> bool; + 1:1 dmem_scrubbing =3D> bool; + 0:0 require_ctx =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_DMATRFBASE(u32) @ PFalconBase + 0x0000011= 0 { + 31:0 base =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ PFalconBase + 0x000001= 14 { + 23:0 offs; + } + + pub(super) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase + 0x00000118= { + 16:16 set_dmtag; + 14:12 ctxdma; + 10:8 size ?=3D> DmaTrfCmdSize; + 5:5 is_write =3D> bool; + 4:4 imem =3D> bool; + 3:2 sec; + 1:1 idle =3D> bool; + 0:0 full =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ PFalconBase + 0x00000= 11c { + 31:0 offs =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ PFalconBase + 0x000001= 28 { + 8:0 base; + } + + pub(super) NV_PFALCON_FALCON_HWCFG1(u32) @ PFalconBase + 0x0000012c { + /// Core revision subversion. + 7:6 core_rev_subversion =3D> FalconCoreRevSubversion; + /// Security model. + 5:4 security_model ?=3D> FalconSecurityModel; + /// Core revision. + 3:0 core_rev ?=3D> FalconCoreRev; + } + + pub(super) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ PFalconBase + 0x00000= 130 { + 1:1 startcpu =3D> bool; + } + + /// IMEM access control register. Up to 4 ports are available for IMEM= access. + pub(super) NV_PFALCON_FALCON_IMEMC(u32)[4, stride =3D 16] @ PFalconBas= e + 0x00000180 { + /// Access secure IMEM. + 28:28 secure =3D> bool; + /// Auto-increment on write. + 24:24 aincw =3D> bool; + /// IMEM block and word offset. + 15:0 offs; + } + + /// IMEM data register. Reading/writing this register accesses IMEM at= the address + /// specified by the corresponding IMEMC register. + pub(super) NV_PFALCON_FALCON_IMEMD(u32)[4, stride =3D 16] @ PFalconBas= e + 0x00000184 { + 31:0 data; + } + + /// IMEM tag register. Used to set the tag for the current IMEM block. + pub(super) NV_PFALCON_FALCON_IMEMT(u32)[4, stride =3D 16] @ PFalconBas= e + 0x00000188 { + 15:0 tag; + } + + /// DMEM access control register. Up to 8 ports are available for DMEM= access. + pub(super) NV_PFALCON_FALCON_DMEMC(u32)[8, stride =3D 8] @ PFalconBase= + 0x000001c0 { + /// Auto-increment on write. + 24:24 aincw =3D> bool; + /// DMEM block and word offset. + 15:0 offs; + } + + /// DMEM data register. Reading/writing this register accesses DMEM at= the address + /// specified by the corresponding DMEMC register. + pub(super) NV_PFALCON_FALCON_DMEMD(u32)[8, stride =3D 8] @ PFalconBase= + 0x000001c4 { + 31:0 data; + } + + /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGI= NE` depending on the + /// falcon instance. + pub(super) NV_PFALCON_FALCON_ENGINE(u32) @ PFalconBase + 0x000003c0 { + 0:0 reset =3D> bool; + } + + pub(super) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600= { + 2:2 mem_type =3D> FalconFbifMemType; + 1:0 target ?=3D> FalconFbifTarget; + } + + pub(super) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 { + 7:7 allow_phys_no_ctx =3D> bool; + } + + // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). + // These provide the falcon external memory communication interface. + + pub(super) NV_PFALCON_FALCON_EMEMC(u32) @ PFalconBase + 0x00000ac0 { + /// EMEM byte offset (4-byte aligned) within the block. + 7:2 offs; + /// EMEM block to access. + 15:8 blk; + /// Auto-increment the offset after each write. + 24:24 aincw =3D> bool; + /// Auto-increment the offset after each read. + 25:25 aincr =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_EMEMD(u32) @ PFalconBase + 0x00000ac4 { + 31:0 data =3D> u32; + } +} + +impl NV_PFALCON_FALCON_DMACTL { + /// Returns `true` if memory scrubbing is completed. + pub(super) fn mem_scrubbing_done(self) -> bool { + !self.dmem_scrubbing() && !self.imem_scrubbing() + } +} + +impl NV_PFALCON_FALCON_DMATRFCMD { + /// Programs the `imem` and `sec` fields for the given FalconMem + pub(super) fn with_falcon_mem(self, mem: FalconMem) -> Self { + let this =3D self.with_imem(mem !=3D FalconMem::Dmem); + + match mem { + FalconMem::ImemSecure =3D> this.with_const_sec::<1>(), + _ =3D> this.with_const_sec::<0>(), + } + } +} + +impl NV_PFALCON_FALCON_ENGINE { + /// Resets the falcon + pub(super) fn reset_engine(bar: Bar0<'_>) { + bar.update(Self::of::(), |r| r.with_reset(true)); + + // TIMEOUT: falcon engine should not take more than 10us to reset. + time::delay::fsleep(time::Delta::from_micros(10)); + + bar.update(Self::of::(), |r| r.with_reset(false)); + } +} + +impl NV_PFALCON_FALCON_HWCFG2 { + /// Returns `true` if memory scrubbing is completed. + pub(super) fn mem_scrubbing_done(self) -> bool { + !self.mem_scrubbing() + } +} + // PFALCON2 =20 register! { @@ -75,20 +295,10 @@ } } =20 -// PFALCON and FUSE registers are defined in the root `regs.rs` but are -// part of the falcon interface, accessed by the whole falcon module. They -// are re-exported here so falcon code can use a single `regs::` prefix. -// Once these families move out of the root module, these re-exports become -// plain definitions. +// FUSE registers are defined in the root `regs.rs` but are part of the +// falcon interface, accessed by the whole falcon module. They are +// re-exported here so falcon code can use a single `regs::` prefix. pub(super) use crate::regs::{ NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSI= ON, - NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, NV_PFALCON_= FALCON_BOOTVEC, - NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_F= ALCON_DMACTL, - NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCO= N_FALCON_DMATRFCMD, - NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFAL= CON_FALCON_DMEMC, - NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EM= EMD, - NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_= IMEMC, - NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MA= ILBOX0, - NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM= , NV_PFALCON_FBIF_CTL, - NV_PFALCON_FBIF_TRANSCFG, + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, }; diff --git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers/g= pu/nova-core/firmware/fwsec/bootloader.rs index ec4d92317a93..6777e041c879 100644 --- a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs +++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs @@ -12,7 +12,6 @@ Device, // }, dma::Coherent, - io::{register::WithBase, Io}, prelude::*, ptr::{ Alignable, @@ -23,15 +22,12 @@ }; =20 use crate::{ - driver::Bar0, falcon::{ self, gsp::Gsp, Falcon, FalconBromParams, FalconDmaLoadable, - FalconFbifMemType, - FalconFbifTarget, FalconFirmware, FalconPioDmemLoadTarget, FalconPioImemLoadTarget, @@ -46,7 +42,6 @@ }, gpu::Chipset, num::FromSafeCast, // - regs, }; =20 /// Structure used by the boot-loader to load the rest of the code. @@ -235,12 +230,7 @@ pub(crate) fn new( /// /// The bootloader will load the FWSEC firmware and then execute it. T= his function returns /// after FWSEC has reached completion. - pub(crate) fn run( - &self, - dev: &Device, - falcon: &Falcon<'_, Gsp>, - bar: Bar0<'_>, - ) -> Result<()> { + pub(crate) fn run(&self, dev: &Device, falcon: &Falcon<= '_, Gsp>) -> Result<()> { // Reset falcon, load the firmware, and run it. falcon .reset() @@ -250,15 +240,7 @@ pub(crate) fn run( .inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware:= {:?}\n", e))?; =20 // Configure DMA index for the bootloader to fetch the FWSEC firmw= are from system memory. - bar.update( - regs::NV_PFALCON_FBIF_TRANSCFG::of::() - .try_at(usize::from_safe_cast(self.dmem_desc.ctx_dma)) - .ok_or(EINVAL)?, - |v| { - v.with_target(FalconFbifTarget::CoherentSysmem) - .with_mem_type(FalconFbifMemType::Physical) - }, - ); + falcon.set_fbif_transcfg_regs_at(self.dmem_desc.ctx_dma)?; =20 let (mbox0, _) =3D falcon .boot(Some(0), None) diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core= /gsp/hal/tu102.rs index a5c0ca355493..d2ef35080689 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -62,12 +62,11 @@ impl FwsecUnloadFirmware { fn run( &self, dev: &device::Device, - bar: Bar0<'_>, gsp_falcon: &Falcon<'_, GspEngine>, ) -> Result { match self { Self::WithoutBl(fw) =3D> fw.run(dev, gsp_falcon), - Self::WithBl(fw) =3D> fw.run(dev, gsp_falcon, bar), + Self::WithBl(fw) =3D> fw.run(dev, gsp_falcon), } } } @@ -88,7 +87,7 @@ fn run(&self, ctx: &mut GspBootContext<'_, '_>) -> Result= { // Log errors but keep going if it fails. let fwsec_sb_res =3D self .fwsec_sb - .run(dev, bar, ctx.gsp_falcon) + .run(dev, ctx.gsp_falcon) .inspect_err(|e| dev_err!(dev, "FWSEC-SB failed to run: {:?}\n= ", e)); =20 // Remove WPR2 region if set. @@ -168,7 +167,7 @@ fn run_fwsec_frts( if self.needs_fwsec_bootloader { let fwsec_frts_bl =3D FwsecFirmwareWithBl::new(fwsec_frts, dev= , chipset)?; // Load and run the bootloader, which will load FWSEC-FRTS and= run it. - fwsec_frts_bl.run(dev, falcon, bar)?; + fwsec_frts_bl.run(dev, falcon)?; } else { // Load and run FWSEC-FRTS directly. fwsec_frts.run(dev, falcon)?; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index c9eca3ff911f..842664428b0d 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -2,28 +2,8 @@ // SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::{ - io::{ - register, - register::WithBase, - Io, // - }, - sizes::SizeConstants, - time, // -}; - -use crate::{ - driver::Bar0, - falcon::{ - DmaTrfCmdSize, - FalconCoreRev, - FalconCoreRevSubversion, - FalconEngine, - FalconFbifMemType, - FalconFbifTarget, - FalconMem, - FalconSecurityModel, - PFalconBase, // - }, + io::register, + sizes::SizeConstants, // }; =20 // PBUS @@ -109,207 +89,6 @@ pub(crate) fn usable_fb_size(self) -> u64 { } } =20 -// PFALCON - -register! { - pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 { - 6:6 swgen0 =3D> bool; - 4:4 halt =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_MAILBOX1(u32) @ PFalconBase + 0x00000044 { - 31:0 value =3D> u32; - } - - /// Used to store version information about the firmware running - /// on the Falcon processor. - pub(crate) NV_PFALCON_FALCON_OS(u32) @ PFalconBase + 0x00000080 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_RM(u32) @ PFalconBase + 0x00000084 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 { - /// Signal indicating that reset is completed (GA102+). - 31:31 reset_ready =3D> bool; - /// RISC-V branch privilege lockdown bit. - 13:13 riscv_br_priv_lockdown =3D> bool; - /// Set to 0 after memory scrubbing is completed. - 12:12 mem_scrubbing =3D> bool; - 10:10 riscv =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_CPUCTL(u32) @ PFalconBase + 0x00000100 { - 6:6 alias_en =3D> bool; - 4:4 halted =3D> bool; - 1:1 startcpu =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_BOOTVEC(u32) @ PFalconBase + 0x00000104 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ PFalconBase + 0x0000010c { - 7:7 secure_stat =3D> bool; - 6:3 dmaq_num; - 2:2 imem_scrubbing =3D> bool; - 1:1 dmem_scrubbing =3D> bool; - 0:0 require_ctx =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFBASE(u32) @ PFalconBase + 0x0000011= 0 { - 31:0 base =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ PFalconBase + 0x000001= 14 { - 23:0 offs; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase + 0x00000118= { - 16:16 set_dmtag; - 14:12 ctxdma; - 10:8 size ?=3D> DmaTrfCmdSize; - 5:5 is_write =3D> bool; - 4:4 imem =3D> bool; - 3:2 sec; - 1:1 idle =3D> bool; - 0:0 full =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ PFalconBase + 0x00000= 11c { - 31:0 offs =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ PFalconBase + 0x000001= 28 { - 8:0 base; - } - - pub(crate) NV_PFALCON_FALCON_HWCFG1(u32) @ PFalconBase + 0x0000012c { - /// Core revision subversion. - 7:6 core_rev_subversion =3D> FalconCoreRevSubversion; - /// Security model. - 5:4 security_model ?=3D> FalconSecurityModel; - /// Core revision. - 3:0 core_rev ?=3D> FalconCoreRev; - } - - pub(crate) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ PFalconBase + 0x00000= 130 { - 1:1 startcpu =3D> bool; - } - - /// IMEM access control register. Up to 4 ports are available for IMEM= access. - pub(crate) NV_PFALCON_FALCON_IMEMC(u32)[4, stride =3D 16] @ PFalconBas= e + 0x00000180 { - /// Access secure IMEM. - 28:28 secure =3D> bool; - /// Auto-increment on write. - 24:24 aincw =3D> bool; - /// IMEM block and word offset. - 15:0 offs; - } - - /// IMEM data register. Reading/writing this register accesses IMEM at= the address - /// specified by the corresponding IMEMC register. - pub(crate) NV_PFALCON_FALCON_IMEMD(u32)[4, stride =3D 16] @ PFalconBas= e + 0x00000184 { - 31:0 data; - } - - /// IMEM tag register. Used to set the tag for the current IMEM block. - pub(crate) NV_PFALCON_FALCON_IMEMT(u32)[4, stride =3D 16] @ PFalconBas= e + 0x00000188 { - 15:0 tag; - } - - /// DMEM access control register. Up to 8 ports are available for DMEM= access. - pub(crate) NV_PFALCON_FALCON_DMEMC(u32)[8, stride =3D 8] @ PFalconBase= + 0x000001c0 { - /// Auto-increment on write. - 24:24 aincw =3D> bool; - /// DMEM block and word offset. - 15:0 offs; - } - - /// DMEM data register. Reading/writing this register accesses DMEM at= the address - /// specified by the corresponding DMEMC register. - pub(crate) NV_PFALCON_FALCON_DMEMD(u32)[8, stride =3D 8] @ PFalconBase= + 0x000001c4 { - 31:0 data; - } - - /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGI= NE` depending on the - /// falcon instance. - pub(crate) NV_PFALCON_FALCON_ENGINE(u32) @ PFalconBase + 0x000003c0 { - 0:0 reset =3D> bool; - } - - pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600= { - 2:2 mem_type =3D> FalconFbifMemType; - 1:0 target ?=3D> FalconFbifTarget; - } - - pub(crate) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 { - 7:7 allow_phys_no_ctx =3D> bool; - } - - // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). - // These provide the falcon external memory communication interface. - - pub(crate) NV_PFALCON_FALCON_EMEMC(u32) @ PFalconBase + 0x00000ac0 { - /// EMEM byte offset (4-byte aligned) within the block. - 7:2 offs; - /// EMEM block to access. - 15:8 blk; - /// Auto-increment the offset after each write. - 24:24 aincw =3D> bool; - /// Auto-increment the offset after each read. - 25:25 aincr =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_EMEMD(u32) @ PFalconBase + 0x00000ac4 { - 31:0 data =3D> u32; - } -} - -impl NV_PFALCON_FALCON_DMACTL { - /// Returns `true` if memory scrubbing is completed. - pub(crate) fn mem_scrubbing_done(self) -> bool { - !self.dmem_scrubbing() && !self.imem_scrubbing() - } -} - -impl NV_PFALCON_FALCON_DMATRFCMD { - /// Programs the `imem` and `sec` fields for the given FalconMem - pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { - let this =3D self.with_imem(mem !=3D FalconMem::Dmem); - - match mem { - FalconMem::ImemSecure =3D> this.with_const_sec::<1>(), - _ =3D> this.with_const_sec::<0>(), - } - } -} - -impl NV_PFALCON_FALCON_ENGINE { - /// Resets the falcon - pub(crate) fn reset_engine(bar: Bar0<'_>) { - bar.update(Self::of::(), |r| r.with_reset(true)); - - // TIMEOUT: falcon engine should not take more than 10us to reset. - time::delay::fsleep(time::Delta::from_micros(10)); - - bar.update(Self::of::(), |r| r.with_reset(false)); - } -} - -impl NV_PFALCON_FALCON_HWCFG2 { - /// Returns `true` if memory scrubbing is completed. - pub(crate) fn mem_scrubbing_done(self) -> bool { - !self.mem_scrubbing() - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.55.0