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This binding will be used for the board-level DTS files that support the AX3005 platforms. Acked-by: Conor Dooley Acked-by: Tzu-Hao Wei Signed-off-by: Swark Yang --- Documentation/devicetree/bindings/arm/axiado.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/axiado.yaml b/Documentat= ion/devicetree/bindings/arm/axiado.yaml index bfabe7b32e65..008d2b1d4e62 100644 --- a/Documentation/devicetree/bindings/arm/axiado.yaml +++ b/Documentation/devicetree/bindings/arm/axiado.yaml @@ -20,4 +20,10 @@ properties: - axiado,ax3000-evk # Axiado AX3000 Evaluation Board - const: axiado,ax3000 # Axiado AX3000 SoC =20 + - description: AX3005 based boards + items: + - enum: + - axiado,ax3005-evk # Axiado AX3005 Evaluation Board + - const: axiado,ax3005 # Axiado AX3005 SoC + additionalProperties: true --=20 2.34.1 From nobody Mon Sep 28 04:53:54 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11023097.outbound.protection.outlook.com [40.93.196.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 231B0231842; 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Wed, 26 Aug 2026 03:10:11 -0700 (PDT) From: Swark Yang Date: Wed, 26 Aug 2026 03:10:07 -0700 Subject: [PATCH v4 2/2] arm64: dts: axiado: Add initial support for AX3005 SoC and eval board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-ax3005-dts-v4-v4-2-a7702a3ace0e@axiado.com> References: <20260826-ax3005-dts-v4-v4-0-a7702a3ace0e@axiado.com> In-Reply-To: <20260826-ax3005-dts-v4-v4-0-a7702a3ace0e@axiado.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prasad Bolisetty , Tzu-Hao Wei , Karthikeyan Mitran , Harshit Shah Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Marc Zyngier , Swark Yang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=30221; i=syang@axiado.com; h=from:subject:message-id; bh=e55Y2Oq6pW+pF0+mOoB800iernZWOUvha17gYM2W5Uw=; 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The AX3005 is a multi-core SoC featuring 4 Cortex-A53 cores, and this adds the CPUs, timer, GPIO, UART, I2C, I3C, SPI and USB controllers. Note that all secondary CPUs share a single cpu-release-addr for SMP bring-up per the AX3005 platform specification. The AX3005 groups its low-speed controllers into four Slow Peripheral (SP) blocks (SP0-SP3), each exposing its own I2C/I3C, SPI and UART instances. The controllers are numbered by their per-SP hardware instance ID, so the i2cN/spiN/uartN labels and their aliases are intentionally non-contiguous and do not increase monotonically with the register address. Signed-off-by: Swark Yang Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/axiado/Makefile | 1 + arch/arm64/boot/dts/axiado/ax3005-evk.dts | 327 ++++++++++++ arch/arm64/boot/dts/axiado/ax3005.dtsi | 844 ++++++++++++++++++++++++++= ++++ 3 files changed, 1172 insertions(+) diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axia= do/Makefile index 6676ad07db61..e71a0850a451 100644 --- a/arch/arm64/boot/dts/axiado/Makefile +++ b/arch/arm64/boot/dts/axiado/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_AXIADO) +=3D ax3000-evk.dtb +dtb-$(CONFIG_ARCH_AXIADO) +=3D ax3005-evk.dtb diff --git a/arch/arm64/boot/dts/axiado/ax3005-evk.dts b/arch/arm64/boot/dt= s/axiado/ax3005-evk.dts new file mode 100644 index 000000000000..f6705504679e --- /dev/null +++ b/arch/arm64/boot/dts/axiado/ax3005-evk.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DTS file for Axiado AX3005 SoC based EVK + * Copyright (c) 2026 Axiado Corporation. + */ + +/dts-v1/; + +#include "ax3005.dtsi" + +/ { + model =3D "Axiado AX3005 EVK"; + compatible =3D "axiado,ax3005-evk", "axiado,ax3005"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + serial6 =3D &uart6; + serial7 =3D &uart7; + serial8 =3D &uart8; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c8 =3D &i2c8; + i2c9 =3D &i2c9; + i2c10 =3D &i2c10; + i2c11 =3D &i2c11; + i2c12 =3D &i3c12; + i2c13 =3D &i3c13; + i2c14 =3D &i2c14; + i2c15 =3D &i2c15; + i2c16 =3D &i2c16; + i2c17 =3D &i2c17; + i2c18 =3D &i2c18; + i2c19 =3D &i2c19; + i2c20 =3D &i2c20; + i2c21 =3D &i2c21; + i2c22 =3D &i2c22; + i2c23 =3D &i2c23; + i2c24 =3D &i2c24; + i2c25 =3D &i2c25; + i2c26 =3D &i2c26; + i2c27 =3D &i2c27; + i2c28 =3D &i2c28; + i2c29 =3D &i2c29; + i2c30 =3D &i2c30; + i2c31 =3D &i2c31; + i2c32 =3D &i2c32; + i2c33 =3D &i2c33; + i2c34 =3D &i2c34; + i2c35 =3D &i2c35; + i2c36 =3D &i2c36; + spi0 =3D &spi0; + spi1 =3D &spi1; + spi2 =3D &spi2; + spi3 =3D &spi3; + spi5 =3D &spi5; + spi6 =3D &spi6; + }; + + chosen { + stdout-path =3D "serial3:115200"; + }; + + memory@81000000 { + device_type =3D "memory"; + /* Cortex-A53 will use following memory map */ + reg =3D <0x0 0x81000000 0x0 0x7f000000>; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gpio2 { + status =3D "okay"; +}; + +&gpio3 { + status =3D "okay"; +}; + +&gpio4 { + status =3D "okay"; +}; + +&gpio5 { + status =3D "okay"; +}; + +&gpio6 { + status =3D "okay"; +}; + +&gpio7 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c3 { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2c9 { + status =3D "okay"; +}; + +&i2c10 { + status =3D "okay"; +}; + +&i2c11 { + status =3D "okay"; +}; + +&i3c12 { + status =3D "okay"; +}; + +&i3c13 { + status =3D "okay"; +}; + +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&i2c16 { + status =3D "okay"; +}; + +&i2c17 { + status =3D "okay"; +}; + +&i2c18 { + status =3D "okay"; +}; + +&i2c19 { + status =3D "okay"; +}; + +&i2c20 { + status =3D "okay"; +}; + +&i2c21 { + status =3D "okay"; +}; + +&i2c22 { + status =3D "okay"; +}; + +&i2c23 { + status =3D "okay"; +}; + +&i2c24 { + status =3D "okay"; +}; + +&i2c25 { + status =3D "okay"; +}; + +&i2c26 { + status =3D "okay"; +}; + +&i2c27 { + status =3D "okay"; +}; + +&i2c28 { + status =3D "okay"; +}; + +&i2c29 { + status =3D "okay"; +}; + +&i2c30 { + status =3D "okay"; +}; + +&i2c31 { + status =3D "okay"; +}; + +&i2c32 { + status =3D "okay"; +}; + +&i2c33 { + status =3D "okay"; +}; + +&i2c34 { + status =3D "okay"; +}; + +&i2c35 { + status =3D "okay"; +}; + +&i2c36 { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&spi2 { + status =3D "okay"; +}; + +&spi3 { + status =3D "okay"; +}; + +&spi5 { + status =3D "okay"; +}; + +&spi6 { + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +&uart5 { + status =3D "okay"; +}; + +&uart6 { + status =3D "okay"; +}; + +&uart7 { + status =3D "okay"; +}; + +&uart8 { + status =3D "okay"; +}; + +&usb2_0 { + status =3D "okay"; +}; + +&usb2_1 { + status =3D "okay"; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/axiado/ax3005.dtsi b/arch/arm64/boot/dts/a= xiado/ax3005.dtsi new file mode 100644 index 000000000000..5636531f173d --- /dev/null +++ b/arch/arm64/boot/dts/axiado/ax3005.dtsi @@ -0,0 +1,844 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2026 Axiado Corporation. + */ + +/dts-v1/; + +#include +#include +/memreserve/ 0x80002fa0 0x00000008; +/ { + model =3D "Axiado AX3005"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + pclk: clock-100000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + + refclk: clock-125000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + sysclk: clock-200000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + }; + + spiclk: clock-400000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <400000000>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80002fa0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80002fa0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x2>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80002fa0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x3>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80002fa0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + ranges; + + gic500: interrupt-controller@40400000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x40400000 0x0 0x10000>, + <0x0 0x40500000 0x0 0xc0000>, + <0x60 0x00000000 0x0 0x2000>, + <0x60 0x00010000 0x0 0x1000>, + <0x60 0x00020000 0x0 0x2000>; + ranges; + #interrupt-cells =3D <3>; + interrupt-controller; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupts =3D ; + }; + + /* GPIO Controller banks 0 - 7 */ + gpio0: gpio-controller@33000000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33000000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + gpio1: gpio-controller@33080000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33080000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + gpio2: gpio-controller@33100000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33100000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + gpio3: gpio-controller@33180000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33180000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + gpio4: gpio-controller@33200000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33200000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + gpio5: gpio-controller@33280000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33280000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + gpio6: gpio-controller@33300000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33300000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + gpio7: gpio-controller@33380000 { + compatible =3D "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r= 1p02"; + reg =3D <0x0 0x33380000 0x0 0x100>; + clocks =3D <&pclk>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + i2c0: i2c@33000400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33000400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@33000800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33000800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@33080400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33080400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@33080800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33080800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@33100400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33100400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@33100800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33100800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@33200400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33200400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c9: i2c@33200800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33200800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c10: i2c@33280400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33280400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c11: i2c@33280800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33280800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i3c12: i3c@33300400 { + compatible =3D "axiado,ax3005-i3c", "cdns,i3c-master"; + reg =3D <0x0 0x33300400 0x0 0x400>; + clock-names =3D "pclk", "sysclk"; + clocks =3D <&pclk &sysclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i3c13: i3c@33300800 { + compatible =3D "axiado,ax3005-i3c", "cdns,i3c-master"; + reg =3D <0x0 0x33300800 0x0 0x400>; + clock-names =3D "pclk", "sysclk"; + clocks =3D <&pclk &sysclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c14: i2c@33380400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33380400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c15: i2c@33380800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33380800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c16: i2c@33120400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33120400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c17: i2c@33021400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33021400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c18: i2c@33021800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33021800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c19: i2c@330c0400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x330c0400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c20: i2c@330c0800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x330c0800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c21: i2c@330c0c00 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x330c0c00 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c22: i2c@331a0800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x331a0800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c23: i2c@33302800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33302800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c24: i2c@33302c00 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33302c00 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c25: i2c@33303000 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33303000 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c26: i2c@33382000 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33382000 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c27: i2c@33382400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33382400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c28: i2c@33382800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33382800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c29: i2c@33382c00 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33382c00 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c30: i2c@33383000 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33383000 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c31: i2c@33383400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33383400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c32: i2c@33383800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33383800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c33: i2c@33282400 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33282400 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c34: i2c@33282800 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33282800 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c35: i2c@33282c00 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33282c00 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c36: i2c@33283000 { + compatible =3D "axiado,ax3005-i2c", "cdns,i2c-r1p14"; + reg =3D <0x0 0x33283000 0x0 0x400>; + clocks =3D <&pclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@33010000 { + compatible =3D "axiado,ax3005-spi", "snps,dwc-ssi-1.01a"; + reg =3D <0x0 0x33010000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clocks =3D <&spiclk>; + num-cs =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + spi1: spi@33090000 { + compatible =3D "axiado,ax3005-spi", "snps,dwc-ssi-1.01a"; + reg =3D <0x0 0x33090000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clocks =3D <&spiclk>; + num-cs =3D <1>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + spi2: spi@333c0000 { + compatible =3D "axiado,ax3005-spi", "snps,dwc-ssi-1.01a"; + reg =3D <0x0 0x333c0000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clocks =3D <&spiclk>; + num-cs =3D <1>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + spi3: spi@330e0000 { + compatible =3D "axiado,ax3005-spi", "snps,dwc-ssi-1.01a"; + reg =3D <0x0 0x330e0000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clocks =3D <&spiclk>; + num-cs =3D <1>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + spi5: spi@33390000 { + compatible =3D "axiado,ax3005-spi", "snps,dwc-ssi-1.01a"; + reg =3D <0x0 0x33390000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clocks =3D <&spiclk>; + num-cs =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + spi6: spi@333a0000 { + compatible =3D "axiado,ax3005-spi", "snps,dwc-ssi-1.01a"; + reg =3D <0x0 0x333a0000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clocks =3D <&spiclk>; + num-cs =3D <1>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart0: serial@33020000 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x33020000 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart1: serial@330a0000 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x330a0000 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart2: serial@33120000 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x33120000 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart3: serial@33020800 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x33020800 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart4: serial@331a0400 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x331a0400 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart5: serial@33381d00 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x33381d00 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart6: serial@33381e00 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x33381e00 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart7: serial@33381f00 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x33381f00 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + uart8: serial@330c0000 { + compatible =3D "axiado,ax3005-uart", "cdns,uart-r1p12"; + reg =3D <0x0 0x330c0000 0x0 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &pclk>; + status =3D "disabled"; + }; + + usb2_0: usb@41000000 { + compatible =3D "axiado,ax3005-xhci", "generic-xhci"; + reg =3D <0x0 0x41000000 0x0 0x100000>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + status =3D "disabled"; + }; + + usb2_1: usb@41100000 { + compatible =3D "axiado,ax3005-xhci", "generic-xhci"; + reg =3D <0x0 0x41100000 0x0 0x100000>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + status =3D "disabled"; + }; + + usb3_0: usb@41400000 { + compatible =3D "axiado,ax3005-xhci", "generic-xhci"; + reg =3D <0x0 0x41400000 0x0 0x100000>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + status =3D "disabled"; + }; + + usb3_1: usb@41500000 { + compatible =3D "axiado,ax3005-xhci", "generic-xhci"; + reg =3D <0x0 0x41500000 0x0 0x100000>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.34.1